| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 4 | * Copyright 2011 Linaro Ltd. |
| 5 | */ |
| 6 | |
| 7 | #include <linux/io.h> |
| 8 | #include <linux/of.h> |
| 9 | #include <linux/of_address.h> |
| 10 | #include <asm/mach/arch.h> |
| 11 | |
| 12 | #include "common.h" |
| 13 | #include "hardware.h" |
| 14 | |
| 15 | static void __init imx51_init_early(void) |
| 16 | { |
| 17 | mxc_set_cpu_type(MXC_CPU_MX51); |
| 18 | } |
| 19 | |
| 20 | /* |
| 21 | * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by |
| 22 | * the Freescale marketing division. However this did not remove the |
| 23 | * hardware from the chip which still needs to be configured for proper |
| 24 | * IPU support. |
| 25 | */ |
| 26 | #define MX51_MIPI_HSC_BASE 0x83fdc000 |
| 27 | static void __init imx51_ipu_mipi_setup(void) |
| 28 | { |
| 29 | void __iomem *hsc_addr; |
| 30 | |
| 31 | hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K); |
| 32 | WARN_ON(!hsc_addr); |
| 33 | |
| 34 | /* setup MIPI module to legacy mode */ |
| 35 | imx_writel(0xf00, hsc_addr); |
| 36 | |
| 37 | /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ |
| 38 | imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); |
| 39 | |
| 40 | iounmap(addr: hsc_addr); |
| 41 | } |
| 42 | |
| 43 | static void __init imx51_m4if_setup(void) |
| 44 | { |
| 45 | void __iomem *m4if_base; |
| 46 | struct device_node *np; |
| 47 | |
| 48 | np = of_find_compatible_node(NULL, NULL, compat: "fsl,imx51-m4if" ); |
| 49 | if (!np) |
| 50 | return; |
| 51 | |
| 52 | m4if_base = of_iomap(node: np, index: 0); |
| 53 | of_node_put(node: np); |
| 54 | if (!m4if_base) { |
| 55 | pr_err("Unable to map M4IF registers\n" ); |
| 56 | return; |
| 57 | } |
| 58 | |
| 59 | /* |
| 60 | * Configure VPU and IPU with higher priorities |
| 61 | * in order to avoid artifacts during video playback |
| 62 | */ |
| 63 | writel_relaxed(0x00000203, m4if_base + 0x40); |
| 64 | writel_relaxed(0x00000000, m4if_base + 0x44); |
| 65 | writel_relaxed(0x00120125, m4if_base + 0x9c); |
| 66 | writel_relaxed(0x001901A3, m4if_base + 0x48); |
| 67 | iounmap(addr: m4if_base); |
| 68 | } |
| 69 | |
| 70 | static void __init imx51_dt_init(void) |
| 71 | { |
| 72 | imx51_ipu_mipi_setup(); |
| 73 | imx_src_init(); |
| 74 | imx51_m4if_setup(); |
| 75 | imx5_pmu_init(); |
| 76 | imx_aips_allow_unprivileged_access(compat: "fsl,imx51-aipstz" ); |
| 77 | } |
| 78 | |
| 79 | static void __init imx51_init_late(void) |
| 80 | { |
| 81 | mx51_neon_fixup(); |
| 82 | imx51_pm_init(); |
| 83 | } |
| 84 | |
| 85 | static const char * const imx51_dt_board_compat[] __initconst = { |
| 86 | "fsl,imx51" , |
| 87 | NULL |
| 88 | }; |
| 89 | |
| 90 | DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)" ) |
| 91 | .init_early = imx51_init_early, |
| 92 | .init_machine = imx51_dt_init, |
| 93 | .init_late = imx51_init_late, |
| 94 | .dt_compat = imx51_dt_board_compat, |
| 95 | MACHINE_END |
| 96 | |