1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * arch/m68k/q40/config.c |
4 | * |
5 | * Copyright (C) 1999 Richard Zidlicky |
6 | * |
7 | * originally based on: |
8 | * |
9 | * linux/bvme/config.c |
10 | */ |
11 | |
12 | #include <linux/errno.h> |
13 | #include <linux/types.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/mm.h> |
16 | #include <linux/tty.h> |
17 | #include <linux/console.h> |
18 | #include <linux/linkage.h> |
19 | #include <linux/init.h> |
20 | #include <linux/major.h> |
21 | #include <linux/serial_reg.h> |
22 | #include <linux/rtc.h> |
23 | #include <linux/vt_kern.h> |
24 | #include <linux/bcd.h> |
25 | #include <linux/platform_device.h> |
26 | |
27 | #include <asm/io.h> |
28 | #include <asm/bootinfo.h> |
29 | #include <asm/setup.h> |
30 | #include <asm/irq.h> |
31 | #include <asm/traps.h> |
32 | #include <asm/machdep.h> |
33 | #include <asm/q40_master.h> |
34 | #include <asm/config.h> |
35 | |
36 | #include "q40.h" |
37 | |
38 | static void q40_get_model(char *model); |
39 | |
40 | static int q40_hwclk(int, struct rtc_time *); |
41 | static int q40_get_rtc_pll(struct rtc_pll_info *pll); |
42 | static int q40_set_rtc_pll(struct rtc_pll_info *pll); |
43 | |
44 | static void q40_mem_console_write(struct console *co, const char *b, |
45 | unsigned int count); |
46 | |
47 | extern int ql_ticks; |
48 | |
49 | static struct console q40_console_driver = { |
50 | .name = "debug" , |
51 | .write = q40_mem_console_write, |
52 | .flags = CON_PRINTBUFFER, |
53 | .index = -1, |
54 | }; |
55 | |
56 | |
57 | /* early debugging function:*/ |
58 | extern char *q40_mem_cptr; /*=(char *)0xff020000;*/ |
59 | static int _cpleft; |
60 | |
61 | static void q40_mem_console_write(struct console *co, const char *s, |
62 | unsigned int count) |
63 | { |
64 | const char *p = s; |
65 | |
66 | if (count < _cpleft) { |
67 | while (count-- > 0) { |
68 | *q40_mem_cptr = *p++; |
69 | q40_mem_cptr += 4; |
70 | _cpleft--; |
71 | } |
72 | } |
73 | } |
74 | |
75 | static int __init q40_debug_setup(char *arg) |
76 | { |
77 | /* useful for early debugging stages - writes kernel messages into SRAM */ |
78 | if (MACH_IS_Q40 && !strncmp(arg, "mem" , 3)) { |
79 | /*pr_info("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/ |
80 | _cpleft = 2000 - ((long)q40_mem_cptr-0xff020000) / 4; |
81 | register_console(&q40_console_driver); |
82 | } |
83 | return 0; |
84 | } |
85 | |
86 | early_param("debug" , q40_debug_setup); |
87 | |
88 | #if 0 |
89 | void printq40(char *str) |
90 | { |
91 | int l = strlen(str); |
92 | char *p = q40_mem_cptr; |
93 | |
94 | while (l-- > 0 && _cpleft-- > 0) { |
95 | *p = *str++; |
96 | p += 4; |
97 | } |
98 | q40_mem_cptr = p; |
99 | } |
100 | #endif |
101 | |
102 | static int halted; |
103 | |
104 | #ifdef CONFIG_HEARTBEAT |
105 | static void q40_heartbeat(int on) |
106 | { |
107 | if (halted) |
108 | return; |
109 | |
110 | if (on) |
111 | Q40_LED_ON(); |
112 | else |
113 | Q40_LED_OFF(); |
114 | } |
115 | #endif |
116 | |
117 | static void q40_reset(void) |
118 | { |
119 | halted = 1; |
120 | pr_info("*******************************************\n" |
121 | "Called q40_reset : press the RESET button!!\n" |
122 | "*******************************************\n" ); |
123 | Q40_LED_ON(); |
124 | while (1) |
125 | ; |
126 | } |
127 | |
128 | static void q40_halt(void) |
129 | { |
130 | halted = 1; |
131 | pr_info("*******************\n" |
132 | " Called q40_halt\n" |
133 | "*******************\n" ); |
134 | Q40_LED_ON(); |
135 | while (1) |
136 | ; |
137 | } |
138 | |
139 | static void q40_get_model(char *model) |
140 | { |
141 | sprintf(buf: model, fmt: "Q40" ); |
142 | } |
143 | |
144 | static unsigned int serports[] = |
145 | { |
146 | 0x3f8,0x2f8,0x3e8,0x2e8,0 |
147 | }; |
148 | |
149 | static void __init q40_disable_irqs(void) |
150 | { |
151 | unsigned i, j; |
152 | |
153 | j = 0; |
154 | while ((i = serports[j++])) |
155 | outb(value: 0, port: i + UART_IER); |
156 | master_outb(0, EXT_ENABLE_REG); |
157 | master_outb(0, KEY_IRQ_ENABLE_REG); |
158 | } |
159 | |
160 | void __init config_q40(void) |
161 | { |
162 | mach_sched_init = q40_sched_init; |
163 | |
164 | mach_init_IRQ = q40_init_IRQ; |
165 | mach_hwclk = q40_hwclk; |
166 | mach_get_rtc_pll = q40_get_rtc_pll; |
167 | mach_set_rtc_pll = q40_set_rtc_pll; |
168 | |
169 | mach_reset = q40_reset; |
170 | mach_get_model = q40_get_model; |
171 | |
172 | #if IS_ENABLED(CONFIG_INPUT_M68K_BEEP) |
173 | mach_beep = q40_mksound; |
174 | #endif |
175 | #ifdef CONFIG_HEARTBEAT |
176 | mach_heartbeat = q40_heartbeat; |
177 | #endif |
178 | mach_halt = q40_halt; |
179 | |
180 | /* disable a few things that SMSQ might have left enabled */ |
181 | q40_disable_irqs(); |
182 | } |
183 | |
184 | |
185 | int __init q40_parse_bootinfo(const struct bi_record *rec) |
186 | { |
187 | return 1; |
188 | } |
189 | |
190 | /* |
191 | * Looks like op is non-zero for setting the clock, and zero for |
192 | * reading the clock. |
193 | * |
194 | * struct hwclk_time { |
195 | * unsigned sec; 0..59 |
196 | * unsigned min; 0..59 |
197 | * unsigned hour; 0..23 |
198 | * unsigned day; 1..31 |
199 | * unsigned mon; 0..11 |
200 | * unsigned year; 00... |
201 | * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set |
202 | * }; |
203 | */ |
204 | |
205 | static int q40_hwclk(int op, struct rtc_time *t) |
206 | { |
207 | if (op) { |
208 | /* Write.... */ |
209 | Q40_RTC_CTRL |= Q40_RTC_WRITE; |
210 | |
211 | Q40_RTC_SECS = bin2bcd(t->tm_sec); |
212 | Q40_RTC_MINS = bin2bcd(t->tm_min); |
213 | Q40_RTC_HOUR = bin2bcd(t->tm_hour); |
214 | Q40_RTC_DATE = bin2bcd(t->tm_mday); |
215 | Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1); |
216 | Q40_RTC_YEAR = bin2bcd(t->tm_year%100); |
217 | if (t->tm_wday >= 0) |
218 | Q40_RTC_DOW = bin2bcd(t->tm_wday+1); |
219 | |
220 | Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); |
221 | } else { |
222 | /* Read.... */ |
223 | Q40_RTC_CTRL |= Q40_RTC_READ; |
224 | |
225 | t->tm_year = bcd2bin (Q40_RTC_YEAR); |
226 | t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1; |
227 | t->tm_mday = bcd2bin (Q40_RTC_DATE); |
228 | t->tm_hour = bcd2bin (Q40_RTC_HOUR); |
229 | t->tm_min = bcd2bin (Q40_RTC_MINS); |
230 | t->tm_sec = bcd2bin (Q40_RTC_SECS); |
231 | |
232 | Q40_RTC_CTRL &= ~(Q40_RTC_READ); |
233 | |
234 | if (t->tm_year < 70) |
235 | t->tm_year += 100; |
236 | t->tm_wday = bcd2bin(Q40_RTC_DOW)-1; |
237 | } |
238 | |
239 | return 0; |
240 | } |
241 | |
242 | /* get and set PLL calibration of RTC clock */ |
243 | #define Q40_RTC_PLL_MASK ((1<<5)-1) |
244 | #define Q40_RTC_PLL_SIGN (1<<5) |
245 | |
246 | static int q40_get_rtc_pll(struct rtc_pll_info *pll) |
247 | { |
248 | int tmp = Q40_RTC_CTRL; |
249 | |
250 | pll->pll_ctrl = 0; |
251 | pll->pll_value = tmp & Q40_RTC_PLL_MASK; |
252 | if (tmp & Q40_RTC_PLL_SIGN) |
253 | pll->pll_value = -pll->pll_value; |
254 | pll->pll_max = 31; |
255 | pll->pll_min = -31; |
256 | pll->pll_posmult = 512; |
257 | pll->pll_negmult = 256; |
258 | pll->pll_clock = 125829120; |
259 | |
260 | return 0; |
261 | } |
262 | |
263 | static int q40_set_rtc_pll(struct rtc_pll_info *pll) |
264 | { |
265 | if (!pll->pll_ctrl) { |
266 | /* the docs are a bit unclear so I am doublesetting */ |
267 | /* RTC_WRITE here ... */ |
268 | int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | |
269 | Q40_RTC_WRITE; |
270 | Q40_RTC_CTRL |= Q40_RTC_WRITE; |
271 | Q40_RTC_CTRL = tmp; |
272 | Q40_RTC_CTRL &= ~(Q40_RTC_WRITE); |
273 | return 0; |
274 | } else |
275 | return -EINVAL; |
276 | } |
277 | |
278 | #define PCIDE_BASE1 0x1f0 |
279 | #define PCIDE_BASE2 0x170 |
280 | #define PCIDE_CTL 0x206 |
281 | |
282 | static const struct resource q40_pata_rsrc_0[] __initconst = { |
283 | DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE1 * 4, 0x38), |
284 | DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE1 + PCIDE_CTL) * 4, 2), |
285 | DEFINE_RES_IO(PCIDE_BASE1, 8), |
286 | DEFINE_RES_IO(PCIDE_BASE1 + PCIDE_CTL, 1), |
287 | DEFINE_RES_IRQ(14), |
288 | }; |
289 | |
290 | static const struct resource q40_pata_rsrc_1[] __initconst = { |
291 | DEFINE_RES_MEM(q40_isa_io_base + PCIDE_BASE2 * 4, 0x38), |
292 | DEFINE_RES_MEM(q40_isa_io_base + (PCIDE_BASE2 + PCIDE_CTL) * 4, 2), |
293 | DEFINE_RES_IO(PCIDE_BASE2, 8), |
294 | DEFINE_RES_IO(PCIDE_BASE2 + PCIDE_CTL, 1), |
295 | DEFINE_RES_IRQ(15), |
296 | }; |
297 | |
298 | static __init int q40_platform_init(void) |
299 | { |
300 | if (!MACH_IS_Q40) |
301 | return -ENODEV; |
302 | |
303 | platform_device_register_simple(name: "q40kbd" , id: -1, NULL, num: 0); |
304 | |
305 | platform_device_register_simple("atari-falcon-ide" , 0, q40_pata_rsrc_0, |
306 | ARRAY_SIZE(q40_pata_rsrc_0)); |
307 | |
308 | platform_device_register_simple("atari-falcon-ide" , 1, q40_pata_rsrc_1, |
309 | ARRAY_SIZE(q40_pata_rsrc_1)); |
310 | |
311 | return 0; |
312 | } |
313 | arch_initcall(q40_platform_init); |
314 | |