1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 *
5 * Author: John Rigby <jrigby@freescale.com>
6 *
7 * Description:
8 * MPC512x Shared code
9 */
10
11#include <linux/clk.h>
12#include <linux/kernel.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/of_address.h>
16#include <linux/of_platform.h>
17#include <linux/fsl-diu-fb.h>
18#include <linux/memblock.h>
19#include <sysdev/fsl_soc.h>
20
21#include <asm/cacheflush.h>
22#include <asm/machdep.h>
23#include <asm/ipic.h>
24#include <asm/time.h>
25#include <asm/mpc5121.h>
26#include <asm/mpc52xx_psc.h>
27
28#include "mpc512x.h"
29
30static struct mpc512x_reset_module __iomem *reset_module_base;
31
32void __noreturn mpc512x_restart(char *cmd)
33{
34 if (reset_module_base) {
35 /* Enable software reset "RSTE" */
36 out_be32(&reset_module_base->rpr, 0x52535445);
37 /* Set software hard reset */
38 out_be32(&reset_module_base->rcr, 0x2);
39 } else {
40 pr_err("Restart module not mapped.\n");
41 }
42 for (;;)
43 ;
44}
45
46struct fsl_diu_shared_fb {
47 u8 gamma[0x300]; /* 32-bit aligned! */
48 struct diu_ad ad0; /* 32-bit aligned! */
49 phys_addr_t fb_phys;
50 size_t fb_len;
51 bool in_use;
52};
53
54/* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
55static void mpc512x_set_pixel_clock(unsigned int pixclock)
56{
57 struct device_node *np;
58 struct clk *clk_diu;
59 unsigned long epsilon, minpixclock, maxpixclock;
60 unsigned long offset, want, got, delta;
61
62 /* lookup and enable the DIU clock */
63 np = of_find_compatible_node(NULL, NULL, compat: "fsl,mpc5121-diu");
64 if (!np) {
65 pr_err("Could not find DIU device tree node.\n");
66 return;
67 }
68 clk_diu = of_clk_get(np, index: 0);
69 if (IS_ERR(ptr: clk_diu)) {
70 /* backwards compat with device trees that lack clock specs */
71 clk_diu = clk_get_sys(dev_id: np->name, con_id: "ipg");
72 }
73 of_node_put(node: np);
74 if (IS_ERR(ptr: clk_diu)) {
75 pr_err("Could not lookup DIU clock.\n");
76 return;
77 }
78 if (clk_prepare_enable(clk: clk_diu)) {
79 pr_err("Could not enable DIU clock.\n");
80 return;
81 }
82
83 /*
84 * convert the picoseconds spec into the desired clock rate,
85 * determine the acceptable clock range for the monitor (+/- 5%),
86 * do the calculation in steps to avoid integer overflow
87 */
88 pr_debug("DIU pixclock in ps - %u\n", pixclock);
89 pixclock = (1000000000 / pixclock) * 1000;
90 pr_debug("DIU pixclock freq - %u\n", pixclock);
91 epsilon = pixclock / 20; /* pixclock * 0.05 */
92 pr_debug("DIU deviation - %lu\n", epsilon);
93 minpixclock = pixclock - epsilon;
94 maxpixclock = pixclock + epsilon;
95 pr_debug("DIU minpixclock - %lu\n", minpixclock);
96 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
97
98 /*
99 * check whether the DIU supports the desired pixel clock
100 *
101 * - simply request the desired clock and see what the
102 * platform's clock driver will make of it, assuming that it
103 * will setup the best approximation of the requested value
104 * - try other candidate frequencies in the order of decreasing
105 * preference (i.e. with increasing distance from the desired
106 * pixel clock, and checking the lower frequency before the
107 * higher frequency to not overload the hardware) until the
108 * first match is found -- any potential subsequent match
109 * would only be as good as the former match or typically
110 * would be less preferrable
111 *
112 * the offset increment of pixelclock divided by 64 is an
113 * arbitrary choice -- it's simple to calculate, in the typical
114 * case we expect the first check to succeed already, in the
115 * worst case seven frequencies get tested (the exact center and
116 * three more values each to the left and to the right) before
117 * the 5% tolerance window is exceeded, resulting in fast enough
118 * execution yet high enough probability of finding a suitable
119 * value, while the error rate will be in the order of single
120 * percents
121 */
122 for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
123 want = pixclock - offset;
124 pr_debug("DIU checking clock - %lu\n", want);
125 clk_set_rate(clk: clk_diu, rate: want);
126 got = clk_get_rate(clk: clk_diu);
127 delta = abs(pixclock - got);
128 if (delta < epsilon)
129 break;
130 if (!offset)
131 continue;
132 want = pixclock + offset;
133 pr_debug("DIU checking clock - %lu\n", want);
134 clk_set_rate(clk: clk_diu, rate: want);
135 got = clk_get_rate(clk: clk_diu);
136 delta = abs(pixclock - got);
137 if (delta < epsilon)
138 break;
139 }
140 if (offset <= epsilon) {
141 pr_debug("DIU clock accepted - %lu\n", want);
142 pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
143 pixclock, got, delta, epsilon);
144 return;
145 }
146 pr_warn("DIU pixclock auto search unsuccessful\n");
147
148 /*
149 * what is the most appropriate action to take when the search
150 * for an available pixel clock which is acceptable to the
151 * monitor has failed? disable the DIU (clock) or just provide
152 * a "best effort"? we go with the latter
153 */
154 pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
155 clk_set_rate(clk: clk_diu, rate: pixclock);
156 got = clk_get_rate(clk: clk_diu);
157 delta = abs(pixclock - got);
158 pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
159 pixclock, got, delta, epsilon);
160}
161
162static enum fsl_diu_monitor_port
163mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port)
164{
165 return FSL_DIU_PORT_DVI;
166}
167
168static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
169
170static inline void mpc512x_free_bootmem(struct page *page)
171{
172 BUG_ON(PageTail(page));
173 BUG_ON(page_ref_count(page) > 1);
174 free_reserved_page(page);
175}
176
177static void mpc512x_release_bootmem(void)
178{
179 unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK;
180 unsigned long size = diu_shared_fb.fb_len;
181 unsigned long start, end;
182
183 if (diu_shared_fb.in_use) {
184 start = PFN_UP(addr);
185 end = PFN_DOWN(addr + size);
186
187 for (; start < end; start++)
188 mpc512x_free_bootmem(pfn_to_page(start));
189
190 diu_shared_fb.in_use = false;
191 }
192 diu_ops.release_bootmem = NULL;
193}
194
195/*
196 * Check if DIU was pre-initialized. If so, perform steps
197 * needed to continue displaying through the whole boot process.
198 * Move area descriptor and gamma table elsewhere, they are
199 * destroyed by bootmem allocator otherwise. The frame buffer
200 * address range will be reserved in setup_arch() after bootmem
201 * allocator is up.
202 */
203static void __init mpc512x_init_diu(void)
204{
205 struct device_node *np;
206 struct diu __iomem *diu_reg;
207 phys_addr_t desc;
208 void __iomem *vaddr;
209 unsigned long mode, pix_fmt, res, bpp;
210 unsigned long dst;
211
212 np = of_find_compatible_node(NULL, NULL, compat: "fsl,mpc5121-diu");
213 if (!np) {
214 pr_err("No DIU node\n");
215 return;
216 }
217
218 diu_reg = of_iomap(node: np, index: 0);
219 of_node_put(node: np);
220 if (!diu_reg) {
221 pr_err("Can't map DIU\n");
222 return;
223 }
224
225 mode = in_be32(&diu_reg->diu_mode);
226 if (mode == MFB_MODE0) {
227 pr_info("%s: DIU OFF\n", __func__);
228 goto out;
229 }
230
231 desc = in_be32(&diu_reg->desc[0]);
232 vaddr = ioremap(offset: desc, size: sizeof(struct diu_ad));
233 if (!vaddr) {
234 pr_err("Can't map DIU area desc.\n");
235 goto out;
236 }
237 memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad));
238 /* flush fb area descriptor */
239 dst = (unsigned long)&diu_shared_fb.ad0;
240 flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1);
241
242 res = in_be32(&diu_reg->disp_size);
243 pix_fmt = in_le32(vaddr);
244 bpp = ((pix_fmt >> 16) & 0x3) + 1;
245 diu_shared_fb.fb_phys = in_le32(vaddr + 4);
246 diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp;
247 diu_shared_fb.in_use = true;
248 iounmap(addr: vaddr);
249
250 desc = in_be32(&diu_reg->gamma);
251 vaddr = ioremap(offset: desc, size: sizeof(diu_shared_fb.gamma));
252 if (!vaddr) {
253 pr_err("Can't map DIU area desc.\n");
254 diu_shared_fb.in_use = false;
255 goto out;
256 }
257 memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma));
258 /* flush gamma table */
259 dst = (unsigned long)&diu_shared_fb.gamma;
260 flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1);
261
262 iounmap(addr: vaddr);
263 out_be32(&diu_reg->gamma, virt_to_phys(address: &diu_shared_fb.gamma));
264 out_be32(&diu_reg->desc[1], 0);
265 out_be32(&diu_reg->desc[2], 0);
266 out_be32(&diu_reg->desc[0], virt_to_phys(address: &diu_shared_fb.ad0));
267
268out:
269 iounmap(addr: diu_reg);
270}
271
272static void __init mpc512x_setup_diu(void)
273{
274 int ret;
275
276 /*
277 * We do not allocate and configure new area for bitmap buffer
278 * because it would require copying bitmap data (splash image)
279 * and so negatively affect boot time. Instead we reserve the
280 * already configured frame buffer area so that it won't be
281 * destroyed. The starting address of the area to reserve and
282 * also its length is passed to memblock_reserve(). It will be
283 * freed later on first open of fbdev, when splash image is not
284 * needed any more.
285 */
286 if (diu_shared_fb.in_use) {
287 ret = memblock_reserve(base: diu_shared_fb.fb_phys,
288 size: diu_shared_fb.fb_len);
289 if (ret) {
290 pr_err("%s: reserve bootmem failed\n", __func__);
291 diu_shared_fb.in_use = false;
292 }
293 }
294
295 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock;
296 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port;
297 diu_ops.release_bootmem = mpc512x_release_bootmem;
298}
299
300void __init mpc512x_init_IRQ(void)
301{
302 struct device_node *np;
303
304 np = of_find_compatible_node(NULL, NULL, compat: "fsl,mpc5121-ipic");
305 if (!np)
306 return;
307
308 ipic_init(np, 0);
309 of_node_put(node: np);
310
311 /*
312 * Initialize the default interrupt mapping priorities,
313 * in case the boot rom changed something on us.
314 */
315 ipic_set_default_priority();
316}
317
318/*
319 * Nodes to do bus probe on, soc and localbus
320 */
321static const struct of_device_id of_bus_ids[] __initconst = {
322 { .compatible = "fsl,mpc5121-immr", },
323 { .compatible = "fsl,mpc5121-localbus", },
324 { .compatible = "fsl,mpc5121-mbx", },
325 { .compatible = "fsl,mpc5121-nfc", },
326 { .compatible = "fsl,mpc5121-sram", },
327 { .compatible = "fsl,mpc5121-pci", },
328 { .compatible = "gpio-leds", },
329 {},
330};
331
332static void __init mpc512x_declare_of_platform_devices(void)
333{
334 if (of_platform_bus_probe(NULL, matches: of_bus_ids, NULL))
335 printk(KERN_ERR __FILE__ ": "
336 "Error while probing of_platform bus\n");
337}
338
339#define DEFAULT_FIFO_SIZE 16
340
341const char *__init mpc512x_select_psc_compat(void)
342{
343 if (of_machine_is_compatible(compat: "fsl,mpc5121"))
344 return "fsl,mpc5121-psc";
345
346 if (of_machine_is_compatible(compat: "fsl,mpc5125"))
347 return "fsl,mpc5125-psc";
348
349 return NULL;
350}
351
352static const char *__init mpc512x_select_reset_compat(void)
353{
354 if (of_machine_is_compatible(compat: "fsl,mpc5121"))
355 return "fsl,mpc5121-reset";
356
357 if (of_machine_is_compatible(compat: "fsl,mpc5125"))
358 return "fsl,mpc5125-reset";
359
360 return NULL;
361}
362
363static unsigned int __init get_fifo_size(struct device_node *np,
364 char *prop_name)
365{
366 const unsigned int *fp;
367
368 fp = of_get_property(node: np, name: prop_name, NULL);
369 if (fp)
370 return *fp;
371
372 pr_warn("no %s property in %pOF node, defaulting to %d\n",
373 prop_name, np, DEFAULT_FIFO_SIZE);
374
375 return DEFAULT_FIFO_SIZE;
376}
377
378#define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \
379 ((u32)(_base) + sizeof(struct mpc52xx_psc)))
380
381/* Init PSC FIFO space for TX and RX slices */
382static void __init mpc512x_psc_fifo_init(void)
383{
384 struct device_node *np;
385 void __iomem *psc;
386 unsigned int tx_fifo_size;
387 unsigned int rx_fifo_size;
388 const char *psc_compat;
389 int fifobase = 0; /* current fifo address in 32 bit words */
390
391 psc_compat = mpc512x_select_psc_compat();
392 if (!psc_compat) {
393 pr_err("%s: no compatible devices found\n", __func__);
394 return;
395 }
396
397 for_each_compatible_node(np, NULL, psc_compat) {
398 tx_fifo_size = get_fifo_size(np, prop_name: "fsl,tx-fifo-size");
399 rx_fifo_size = get_fifo_size(np, prop_name: "fsl,rx-fifo-size");
400
401 /* size in register is in 4 byte units */
402 tx_fifo_size /= 4;
403 rx_fifo_size /= 4;
404 if (!tx_fifo_size)
405 tx_fifo_size = 1;
406 if (!rx_fifo_size)
407 rx_fifo_size = 1;
408
409 psc = of_iomap(node: np, index: 0);
410 if (!psc) {
411 pr_err("%s: Can't map %pOF device\n",
412 __func__, np);
413 continue;
414 }
415
416 /* FIFO space is 4KiB, check if requested size is available */
417 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) {
418 pr_err("%s: no fifo space available for %pOF\n",
419 __func__, np);
420 iounmap(addr: psc);
421 /*
422 * chances are that another device requests less
423 * fifo space, so we continue.
424 */
425 continue;
426 }
427
428 /* set tx and rx fifo size registers */
429 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size);
430 fifobase += tx_fifo_size;
431 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size);
432 fifobase += rx_fifo_size;
433
434 /* reset and enable the slices */
435 out_be32(&FIFOC(psc)->txcmd, 0x80);
436 out_be32(&FIFOC(psc)->txcmd, 0x01);
437 out_be32(&FIFOC(psc)->rxcmd, 0x80);
438 out_be32(&FIFOC(psc)->rxcmd, 0x01);
439
440 iounmap(addr: psc);
441 }
442}
443
444static void __init mpc512x_restart_init(void)
445{
446 struct device_node *np;
447 const char *reset_compat;
448
449 reset_compat = mpc512x_select_reset_compat();
450 np = of_find_compatible_node(NULL, NULL, compat: reset_compat);
451 if (!np)
452 return;
453
454 reset_module_base = of_iomap(node: np, index: 0);
455 of_node_put(node: np);
456}
457
458void __init mpc512x_init_early(void)
459{
460 mpc512x_restart_init();
461 if (IS_ENABLED(CONFIG_FB_FSL_DIU))
462 mpc512x_init_diu();
463}
464
465void __init mpc512x_init(void)
466{
467 mpc5121_clk_init();
468 mpc512x_declare_of_platform_devices();
469 mpc512x_psc_fifo_init();
470}
471
472void __init mpc512x_setup_arch(void)
473{
474 if (IS_ENABLED(CONFIG_FB_FSL_DIU))
475 mpc512x_setup_diu();
476}
477
478/**
479 * mpc512x_cs_config - Setup chip select configuration
480 * @cs: chip select number
481 * @val: chip select configuration value
482 *
483 * Perform chip select configuration for devices on LocalPlus Bus.
484 * Intended to dynamically reconfigure the chip select parameters
485 * for configurable devices on the bus.
486 */
487int mpc512x_cs_config(unsigned int cs, u32 val)
488{
489 static struct mpc512x_lpc __iomem *lpc;
490 struct device_node *np;
491
492 if (cs > 7)
493 return -EINVAL;
494
495 if (!lpc) {
496 np = of_find_compatible_node(NULL, NULL, compat: "fsl,mpc5121-lpc");
497 lpc = of_iomap(node: np, index: 0);
498 of_node_put(node: np);
499 if (!lpc)
500 return -ENOMEM;
501 }
502
503 out_be32(&lpc->cs_cfg[cs], val);
504 return 0;
505}
506EXPORT_SYMBOL(mpc512x_cs_config);
507

source code of linux/arch/powerpc/platforms/512x/mpc512x_shared.c