1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC5200 General Purpose Timer device driver
4 *
5 * Copyright (c) 2009 Secret Lab Technologies Ltd.
6 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
7 *
8 * This file is a driver for the General Purpose Timer (gpt) devices
9 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
10 * for GPIO or can be used to raise interrupts. The timer function can
11 * be used independently from the IO pin, or it can be used to control
12 * output signals or measure input signals.
13 *
14 * This driver supports the GPIO and IRQ controller functions of the GPT
15 * device. Timer functions are not yet supported.
16 *
17 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used,
18 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
20 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
21 * this means that gpt0 is locked in wdt mode until the next reboot - this
22 * may be a requirement in safety applications.
23 *
24 * To use the GPIO function, the following two properties must be added
25 * to the device tree node for the gpt device (typically in the .dts file
26 * for the board):
27 * gpio-controller;
28 * #gpio-cells = < 2 >;
29 * This driver will register the GPIO pin if it finds the gpio-controller
30 * property in the device tree.
31 *
32 * To use the IRQ controller function, the following two properties must
33 * be added to the device tree node for the gpt device:
34 * interrupt-controller;
35 * #interrupt-cells = < 1 >;
36 * The IRQ controller binding only uses one cell to specify the interrupt,
37 * and the IRQ flags are encoded in the cell. A cell is not used to encode
38 * the IRQ number because the GPT only has a single IRQ source. For flags,
39 * a value of '1' means rising edge sensitive and '2' means falling edge.
40 *
41 * The GPIO and the IRQ controller functions can be used at the same time,
42 * but in this use case the IO line will only work as an input. Trying to
43 * use it as a GPIO output will not work.
44 *
45 * When using the GPIO line as an output, it can either be driven as normal
46 * IO, or it can be an Open Collector (OC) output. At the moment it is the
47 * responsibility of either the bootloader or the platform setup code to set
48 * the output mode. This driver does not change the output mode setting.
49 */
50
51#include <linux/gpio/driver.h>
52#include <linux/irq.h>
53#include <linux/interrupt.h>
54#include <linux/io.h>
55#include <linux/list.h>
56#include <linux/mutex.h>
57#include <linux/of.h>
58#include <linux/of_address.h>
59#include <linux/of_irq.h>
60#include <linux/platform_device.h>
61#include <linux/kernel.h>
62#include <linux/property.h>
63#include <linux/slab.h>
64#include <linux/fs.h>
65#include <linux/watchdog.h>
66#include <linux/miscdevice.h>
67#include <linux/uaccess.h>
68#include <linux/module.h>
69#include <asm/div64.h>
70#include <asm/mpc52xx.h>
71
72MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
73MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
74MODULE_LICENSE("GPL");
75
76/**
77 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
78 * @dev: pointer to device structure
79 * @regs: virtual address of GPT registers
80 * @lock: spinlock to coordinate between different functions.
81 * @gc: gpio_chip instance structure; used when GPIO is enabled
82 * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
83 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
84 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
85 * if the timer is actively used as wdt which blocks gpt functions
86 */
87struct mpc52xx_gpt_priv {
88 struct list_head list; /* List of all GPT devices */
89 struct device *dev;
90 struct mpc52xx_gpt __iomem *regs;
91 raw_spinlock_t lock;
92 struct irq_domain *irqhost;
93 u32 ipb_freq;
94 u8 wdt_mode;
95
96#if defined(CONFIG_GPIOLIB)
97 struct gpio_chip gc;
98#endif
99};
100
101LIST_HEAD(mpc52xx_gpt_list);
102DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
103
104#define MPC52xx_GPT_MODE_MS_MASK (0x07)
105#define MPC52xx_GPT_MODE_MS_IC (0x01)
106#define MPC52xx_GPT_MODE_MS_OC (0x02)
107#define MPC52xx_GPT_MODE_MS_PWM (0x03)
108#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
109
110#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
111#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
112#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
113
114#define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000)
115#define MPC52xx_GPT_MODE_CONTINUOUS (0x0400)
116#define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200)
117#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
118#define MPC52xx_GPT_MODE_WDT_EN (0x8000)
119
120#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
121#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
122#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
123#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
124
125#define MPC52xx_GPT_MODE_WDT_PING (0xa5)
126
127#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
128
129#define MPC52xx_GPT_CAN_WDT (1 << 0)
130#define MPC52xx_GPT_IS_WDT (1 << 1)
131
132
133/* ---------------------------------------------------------------------
134 * Cascaded interrupt controller hooks
135 */
136
137static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
138{
139 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
140 unsigned long flags;
141
142 raw_spin_lock_irqsave(&gpt->lock, flags);
143 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
144 raw_spin_unlock_irqrestore(&gpt->lock, flags);
145}
146
147static void mpc52xx_gpt_irq_mask(struct irq_data *d)
148{
149 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
150 unsigned long flags;
151
152 raw_spin_lock_irqsave(&gpt->lock, flags);
153 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
154 raw_spin_unlock_irqrestore(&gpt->lock, flags);
155}
156
157static void mpc52xx_gpt_irq_ack(struct irq_data *d)
158{
159 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
160
161 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
162}
163
164static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
165{
166 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
167 unsigned long flags;
168 u32 reg;
169
170 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
171
172 raw_spin_lock_irqsave(&gpt->lock, flags);
173 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
174 if (flow_type & IRQF_TRIGGER_RISING)
175 reg |= MPC52xx_GPT_MODE_ICT_RISING;
176 if (flow_type & IRQF_TRIGGER_FALLING)
177 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
178 out_be32(&gpt->regs->mode, reg);
179 raw_spin_unlock_irqrestore(&gpt->lock, flags);
180
181 return 0;
182}
183
184static struct irq_chip mpc52xx_gpt_irq_chip = {
185 .name = "MPC52xx GPT",
186 .irq_unmask = mpc52xx_gpt_irq_unmask,
187 .irq_mask = mpc52xx_gpt_irq_mask,
188 .irq_ack = mpc52xx_gpt_irq_ack,
189 .irq_set_type = mpc52xx_gpt_irq_set_type,
190};
191
192static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
193{
194 struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
195 u32 status;
196
197 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
198 if (status)
199 generic_handle_domain_irq(domain: gpt->irqhost, hwirq: 0);
200}
201
202static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
203 irq_hw_number_t hw)
204{
205 struct mpc52xx_gpt_priv *gpt = h->host_data;
206
207 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
208 irq_set_chip_data(irq: virq, data: gpt);
209 irq_set_chip_and_handler(irq: virq, chip: &mpc52xx_gpt_irq_chip, handle: handle_edge_irq);
210
211 return 0;
212}
213
214static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
215 const u32 *intspec, unsigned int intsize,
216 irq_hw_number_t *out_hwirq,
217 unsigned int *out_flags)
218{
219 struct mpc52xx_gpt_priv *gpt = h->host_data;
220
221 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
222
223 if ((intsize < 1) || (intspec[0] > 3)) {
224 dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
225 return -EINVAL;
226 }
227
228 *out_hwirq = 0; /* The GPT only has 1 IRQ line */
229 *out_flags = intspec[0];
230
231 return 0;
232}
233
234static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
235 .map = mpc52xx_gpt_irq_map,
236 .xlate = mpc52xx_gpt_irq_xlate,
237};
238
239static void
240mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
241{
242 int cascade_virq;
243 unsigned long flags;
244 u32 mode;
245
246 cascade_virq = irq_of_parse_and_map(node, index: 0);
247 if (!cascade_virq)
248 return;
249
250 gpt->irqhost = irq_domain_create_linear(of_fwnode_handle(node), size: 1, ops: &mpc52xx_gpt_irq_ops, host_data: gpt);
251 if (!gpt->irqhost) {
252 dev_err(gpt->dev, "irq_domain_create_linear() failed\n");
253 return;
254 }
255
256 irq_set_handler_data(irq: cascade_virq, data: gpt);
257 irq_set_chained_handler(irq: cascade_virq, handle: mpc52xx_gpt_irq_cascade);
258
259 /* If the GPT is currently disabled, then change it to be in Input
260 * Capture mode. If the mode is non-zero, then the pin could be
261 * already in use for something. */
262 raw_spin_lock_irqsave(&gpt->lock, flags);
263 mode = in_be32(&gpt->regs->mode);
264 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
265 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
266 raw_spin_unlock_irqrestore(&gpt->lock, flags);
267
268 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
269}
270
271
272/* ---------------------------------------------------------------------
273 * GPIOLIB hooks
274 */
275#if defined(CONFIG_GPIOLIB)
276static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
277{
278 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
279
280 return (in_be32(&gpt->regs->status) >> 8) & 1;
281}
282
283static int
284mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
285{
286 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
287 unsigned long flags;
288 u32 r;
289
290 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
291 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
292
293 raw_spin_lock_irqsave(&gpt->lock, flags);
294 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
295 raw_spin_unlock_irqrestore(&gpt->lock, flags);
296
297 return 0;
298}
299
300static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
301{
302 struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
303 unsigned long flags;
304
305 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
306
307 raw_spin_lock_irqsave(&gpt->lock, flags);
308 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
309 raw_spin_unlock_irqrestore(&gpt->lock, flags);
310
311 return 0;
312}
313
314static int
315mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
316{
317 mpc52xx_gpt_gpio_set(gc, gpio, v: val);
318 return 0;
319}
320
321static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt)
322{
323 int rc;
324
325 /* Only setup GPIO if the device claims the GPT is a GPIO controller */
326 if (!device_property_present(dev: gpt->dev, propname: "gpio-controller"))
327 return;
328
329 gpt->gc.label = kasprintf(GFP_KERNEL, fmt: "%pfw", dev_fwnode(gpt->dev));
330 if (!gpt->gc.label) {
331 dev_err(gpt->dev, "out of memory\n");
332 return;
333 }
334
335 gpt->gc.ngpio = 1;
336 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
337 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
338 gpt->gc.get = mpc52xx_gpt_gpio_get;
339 gpt->gc.set = mpc52xx_gpt_gpio_set;
340 gpt->gc.base = -1;
341 gpt->gc.parent = gpt->dev;
342
343 /* Setup external pin in GPIO mode */
344 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
345 MPC52xx_GPT_MODE_MS_GPIO);
346
347 rc = gpiochip_add_data(&gpt->gc, gpt);
348 if (rc)
349 dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
350
351 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
352}
353#else /* defined(CONFIG_GPIOLIB) */
354static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt) { }
355#endif /* defined(CONFIG_GPIOLIB) */
356
357/***********************************************************************
358 * Timer API
359 */
360
361/**
362 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
363 * @irq: irq of timer.
364 */
365struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
366{
367 struct mpc52xx_gpt_priv *gpt;
368 struct list_head *pos;
369
370 /* Iterate over the list of timers looking for a matching device */
371 mutex_lock(&mpc52xx_gpt_list_mutex);
372 list_for_each(pos, &mpc52xx_gpt_list) {
373 gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
374 if (gpt->irqhost && irq == irq_find_mapping(domain: gpt->irqhost, hwirq: 0)) {
375 mutex_unlock(lock: &mpc52xx_gpt_list_mutex);
376 return gpt;
377 }
378 }
379 mutex_unlock(lock: &mpc52xx_gpt_list_mutex);
380
381 return NULL;
382}
383EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
384
385static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
386 int continuous, int as_wdt)
387{
388 u32 clear, set;
389 u64 clocks;
390 u32 prescale;
391 unsigned long flags;
392
393 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
394 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
395 if (as_wdt) {
396 clear |= MPC52xx_GPT_MODE_IRQ_EN;
397 set |= MPC52xx_GPT_MODE_WDT_EN;
398 } else if (continuous)
399 set |= MPC52xx_GPT_MODE_CONTINUOUS;
400
401 /* Determine the number of clocks in the requested period. 64 bit
402 * arithmetic is done here to preserve the precision until the value
403 * is scaled back down into the u32 range. Period is in 'ns', bus
404 * frequency is in Hz. */
405 clocks = period * (u64)gpt->ipb_freq;
406 do_div(clocks, 1000000000); /* Scale it down to ns range */
407
408 /* This device cannot handle a clock count greater than 32 bits */
409 if (clocks > 0xffffffff)
410 return -EINVAL;
411
412 /* Calculate the prescaler and count values from the clocks value.
413 * 'clocks' is the number of clock ticks in the period. The timer
414 * has 16 bit precision and a 16 bit prescaler. Prescaler is
415 * calculated by integer dividing the clocks by 0x10000 (shifting
416 * down 16 bits) to obtain the smallest possible divisor for clocks
417 * to get a 16 bit count value.
418 *
419 * Note: the prescale register is '1' based, not '0' based. ie. a
420 * value of '1' means divide the clock by one. 0xffff divides the
421 * clock by 0xffff. '0x0000' does not divide by zero, but wraps
422 * around and divides by 0x10000. That is why prescale must be
423 * a u32 variable, not a u16, for this calculation. */
424 prescale = (clocks >> 16) + 1;
425 do_div(clocks, prescale);
426 if (clocks > 0xffff) {
427 pr_err("calculation error; prescale:%x clocks:%llx\n",
428 prescale, clocks);
429 return -EINVAL;
430 }
431
432 /* Set and enable the timer, reject an attempt to use a wdt as gpt */
433 raw_spin_lock_irqsave(&gpt->lock, flags);
434 if (as_wdt)
435 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
436 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
437 raw_spin_unlock_irqrestore(&gpt->lock, flags);
438 return -EBUSY;
439 }
440 out_be32(&gpt->regs->count, prescale << 16 | clocks);
441 clrsetbits_be32(&gpt->regs->mode, clear, set);
442 raw_spin_unlock_irqrestore(&gpt->lock, flags);
443
444 return 0;
445}
446
447/**
448 * mpc52xx_gpt_start_timer - Set and enable the GPT timer
449 * @gpt: Pointer to gpt private data structure
450 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
451 * @continuous: set to 1 to make timer continuous free running
452 *
453 * An interrupt will be generated every time the timer fires
454 */
455int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
456 int continuous)
457{
458 return mpc52xx_gpt_do_start(gpt, period, continuous, as_wdt: 0);
459}
460EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
461
462/**
463 * mpc52xx_gpt_stop_timer - Stop a gpt
464 * @gpt: Pointer to gpt private data structure
465 *
466 * Returns an error if attempting to stop a wdt
467 */
468int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
469{
470 unsigned long flags;
471
472 /* reject the operation if the timer is used as watchdog (gpt 0 only) */
473 raw_spin_lock_irqsave(&gpt->lock, flags);
474 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
475 raw_spin_unlock_irqrestore(&gpt->lock, flags);
476 return -EBUSY;
477 }
478
479 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
480 raw_spin_unlock_irqrestore(&gpt->lock, flags);
481 return 0;
482}
483EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
484
485/**
486 * mpc52xx_gpt_timer_period - Read the timer period
487 * @gpt: Pointer to gpt private data structure
488 *
489 * Returns the timer period in ns
490 */
491u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
492{
493 u64 period;
494 u64 prescale;
495 unsigned long flags;
496
497 raw_spin_lock_irqsave(&gpt->lock, flags);
498 period = in_be32(&gpt->regs->count);
499 raw_spin_unlock_irqrestore(&gpt->lock, flags);
500
501 prescale = period >> 16;
502 period &= 0xffff;
503 if (prescale == 0)
504 prescale = 0x10000;
505 period = period * prescale * 1000000000ULL;
506 do_div(period, gpt->ipb_freq);
507 return period;
508}
509EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
510
511#if defined(CONFIG_MPC5200_WDT)
512/***********************************************************************
513 * Watchdog API for gpt0
514 */
515
516#define WDT_IDENTITY "mpc52xx watchdog on GPT0"
517
518/* wdt_is_active stores whether or not the /dev/watchdog device is opened */
519static unsigned long wdt_is_active;
520
521/* wdt-capable gpt */
522static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
523
524/* low-level wdt functions */
525static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
526{
527 unsigned long flags;
528
529 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
530 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
531 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
532}
533
534/* wdt misc device api */
535static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
536 size_t len, loff_t *ppos)
537{
538 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
539 mpc52xx_gpt_wdt_ping(gpt_wdt);
540 return 0;
541}
542
543static const struct watchdog_info mpc5200_wdt_info = {
544 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
545 .identity = WDT_IDENTITY,
546};
547
548static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
549 unsigned long arg)
550{
551 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
552 int __user *data = (int __user *)arg;
553 int timeout;
554 u64 real_timeout;
555 int ret = 0;
556
557 switch (cmd) {
558 case WDIOC_GETSUPPORT:
559 ret = copy_to_user(to: data, from: &mpc5200_wdt_info,
560 n: sizeof(mpc5200_wdt_info));
561 if (ret)
562 ret = -EFAULT;
563 break;
564
565 case WDIOC_GETSTATUS:
566 case WDIOC_GETBOOTSTATUS:
567 ret = put_user(0, data);
568 break;
569
570 case WDIOC_KEEPALIVE:
571 mpc52xx_gpt_wdt_ping(gpt_wdt);
572 break;
573
574 case WDIOC_SETTIMEOUT:
575 ret = get_user(timeout, data);
576 if (ret)
577 break;
578 real_timeout = (u64) timeout * 1000000000ULL;
579 ret = mpc52xx_gpt_do_start(gpt: gpt_wdt, period: real_timeout, continuous: 0, as_wdt: 1);
580 if (ret)
581 break;
582 /* fall through and return the timeout */
583 fallthrough;
584
585 case WDIOC_GETTIMEOUT:
586 /* we need to round here as to avoid e.g. the following
587 * situation:
588 * - timeout requested is 1 second;
589 * - real timeout @33MHz is 999997090ns
590 * - the int divide by 10^9 will return 0.
591 */
592 real_timeout =
593 mpc52xx_gpt_timer_period(gpt: gpt_wdt) + 500000000ULL;
594 do_div(real_timeout, 1000000000ULL);
595 timeout = (int) real_timeout;
596 ret = put_user(timeout, data);
597 break;
598
599 default:
600 ret = -ENOTTY;
601 }
602 return ret;
603}
604
605static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
606{
607 int ret;
608
609 /* sanity check */
610 if (!mpc52xx_gpt_wdt)
611 return -ENODEV;
612
613 /* /dev/watchdog can only be opened once */
614 if (test_and_set_bit(nr: 0, addr: &wdt_is_active))
615 return -EBUSY;
616
617 /* Set and activate the watchdog with 30 seconds timeout */
618 ret = mpc52xx_gpt_do_start(gpt: mpc52xx_gpt_wdt, period: 30ULL * 1000000000ULL,
619 continuous: 0, as_wdt: 1);
620 if (ret) {
621 clear_bit(nr: 0, addr: &wdt_is_active);
622 return ret;
623 }
624
625 file->private_data = mpc52xx_gpt_wdt;
626 return stream_open(inode, filp: file);
627}
628
629static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
630{
631 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */
632#if !defined(CONFIG_WATCHDOG_NOWAYOUT)
633 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
634 unsigned long flags;
635
636 raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
637 clrbits32(&gpt_wdt->regs->mode,
638 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
639 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
640 raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
641#endif
642 clear_bit(nr: 0, addr: &wdt_is_active);
643 return 0;
644}
645
646
647static const struct file_operations mpc52xx_wdt_fops = {
648 .owner = THIS_MODULE,
649 .write = mpc52xx_wdt_write,
650 .unlocked_ioctl = mpc52xx_wdt_ioctl,
651 .compat_ioctl = compat_ptr_ioctl,
652 .open = mpc52xx_wdt_open,
653 .release = mpc52xx_wdt_release,
654};
655
656static struct miscdevice mpc52xx_wdt_miscdev = {
657 .minor = WATCHDOG_MINOR,
658 .name = "watchdog",
659 .fops = &mpc52xx_wdt_fops,
660};
661
662static int mpc52xx_gpt_wdt_init(void)
663{
664 int err;
665
666 /* try to register the watchdog misc device */
667 err = misc_register(misc: &mpc52xx_wdt_miscdev);
668 if (err)
669 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
670 else
671 pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
672 return err;
673}
674
675static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
676 const u32 *period)
677{
678 u64 real_timeout;
679
680 /* remember the gpt for the wdt operation */
681 mpc52xx_gpt_wdt = gpt;
682
683 /* configure the wdt if the device tree contained a timeout */
684 if (!period || *period == 0)
685 return 0;
686
687 real_timeout = (u64) *period * 1000000000ULL;
688 if (mpc52xx_gpt_do_start(gpt, period: real_timeout, continuous: 0, as_wdt: 1))
689 dev_warn(gpt->dev, "starting as wdt failed\n");
690 else
691 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
692 return 0;
693}
694
695#else
696
697static int mpc52xx_gpt_wdt_init(void)
698{
699 return 0;
700}
701
702static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
703 const u32 *period)
704{
705 return 0;
706}
707
708#endif /* CONFIG_MPC5200_WDT */
709
710/* ---------------------------------------------------------------------
711 * of_platform bus binding code
712 */
713static int mpc52xx_gpt_probe(struct platform_device *ofdev)
714{
715 struct mpc52xx_gpt_priv *gpt;
716
717 gpt = devm_kzalloc(dev: &ofdev->dev, size: sizeof *gpt, GFP_KERNEL);
718 if (!gpt)
719 return -ENOMEM;
720
721 raw_spin_lock_init(&gpt->lock);
722 gpt->dev = &ofdev->dev;
723 gpt->ipb_freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
724 gpt->regs = of_iomap(node: ofdev->dev.of_node, index: 0);
725 if (!gpt->regs)
726 return -ENOMEM;
727
728 dev_set_drvdata(dev: &ofdev->dev, data: gpt);
729
730 mpc52xx_gpt_gpio_setup(gpt);
731 mpc52xx_gpt_irq_setup(gpt, node: ofdev->dev.of_node);
732
733 mutex_lock(&mpc52xx_gpt_list_mutex);
734 list_add(new: &gpt->list, head: &mpc52xx_gpt_list);
735 mutex_unlock(lock: &mpc52xx_gpt_list_mutex);
736
737 /* check if this device could be a watchdog */
738 if (of_property_read_bool(np: ofdev->dev.of_node, propname: "fsl,has-wdt") ||
739 of_property_read_bool(np: ofdev->dev.of_node, propname: "has-wdt")) {
740 const u32 *on_boot_wdt;
741
742 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
743 on_boot_wdt = of_get_property(node: ofdev->dev.of_node,
744 name: "fsl,wdt-on-boot", NULL);
745 if (on_boot_wdt) {
746 dev_info(gpt->dev, "used as watchdog\n");
747 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
748 } else
749 dev_info(gpt->dev, "can function as watchdog\n");
750 mpc52xx_gpt_wdt_setup(gpt, period: on_boot_wdt);
751 }
752
753 return 0;
754}
755
756static const struct of_device_id mpc52xx_gpt_match[] = {
757 { .compatible = "fsl,mpc5200-gpt", },
758
759 /* Depreciated compatible values; don't use for new dts files */
760 { .compatible = "fsl,mpc5200-gpt-gpio", },
761 { .compatible = "mpc5200-gpt", },
762 {}
763};
764
765static struct platform_driver mpc52xx_gpt_driver = {
766 .driver = {
767 .name = "mpc52xx-gpt",
768 .suppress_bind_attrs = true,
769 .of_match_table = mpc52xx_gpt_match,
770 },
771 .probe = mpc52xx_gpt_probe,
772};
773
774static int __init mpc52xx_gpt_init(void)
775{
776 return platform_driver_register(&mpc52xx_gpt_driver);
777}
778
779/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
780subsys_initcall(mpc52xx_gpt_init);
781device_initcall(mpc52xx_gpt_wdt_init);
782

source code of linux/arch/powerpc/platforms/52xx/mpc52xx_gpt.c