1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * sbus.c: UltraSparc SBUS controller support. |
4 | * |
5 | * Copyright (C) 1999 David S. Miller (davem@redhat.com) |
6 | */ |
7 | |
8 | #include <linux/kernel.h> |
9 | #include <linux/types.h> |
10 | #include <linux/mm.h> |
11 | #include <linux/spinlock.h> |
12 | #include <linux/slab.h> |
13 | #include <linux/export.h> |
14 | #include <linux/init.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_platform.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/numa.h> |
20 | |
21 | #include <asm/page.h> |
22 | #include <asm/io.h> |
23 | #include <asm/upa.h> |
24 | #include <asm/cache.h> |
25 | #include <asm/dma.h> |
26 | #include <asm/irq.h> |
27 | #include <asm/prom.h> |
28 | #include <asm/oplib.h> |
29 | #include <asm/starfire.h> |
30 | |
31 | #include "iommu_common.h" |
32 | |
33 | #define MAP_BASE ((u32)0xc0000000) |
34 | |
35 | /* Offsets from iommu_regs */ |
36 | #define SYSIO_IOMMUREG_BASE 0x2400UL |
37 | #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */ |
38 | #define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */ |
39 | #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */ |
40 | #define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */ |
41 | #define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */ |
42 | #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */ |
43 | #define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */ |
44 | #define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */ |
45 | |
46 | #define IOMMU_DRAM_VALID (1UL << 30UL) |
47 | |
48 | /* Offsets from strbuf_regs */ |
49 | #define SYSIO_STRBUFREG_BASE 0x2800UL |
50 | #define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */ |
51 | #define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */ |
52 | #define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */ |
53 | #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */ |
54 | #define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */ |
55 | #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */ |
56 | #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */ |
57 | |
58 | #define STRBUF_TAG_VALID 0x02UL |
59 | |
60 | /* Enable 64-bit DVMA mode for the given device. */ |
61 | void sbus_set_sbus64(struct device *dev, int bursts) |
62 | { |
63 | struct iommu *iommu = dev->archdata.iommu; |
64 | struct platform_device *op = to_platform_device(dev); |
65 | const struct linux_prom_registers *regs; |
66 | unsigned long cfg_reg; |
67 | int slot; |
68 | u64 val; |
69 | |
70 | regs = of_get_property(node: op->dev.of_node, name: "reg" , NULL); |
71 | if (!regs) { |
72 | printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %pOF\n" , |
73 | op->dev.of_node); |
74 | return; |
75 | } |
76 | slot = regs->which_io; |
77 | |
78 | cfg_reg = iommu->write_complete_reg; |
79 | switch (slot) { |
80 | case 0: |
81 | cfg_reg += 0x20UL; |
82 | break; |
83 | case 1: |
84 | cfg_reg += 0x28UL; |
85 | break; |
86 | case 2: |
87 | cfg_reg += 0x30UL; |
88 | break; |
89 | case 3: |
90 | cfg_reg += 0x38UL; |
91 | break; |
92 | case 13: |
93 | cfg_reg += 0x40UL; |
94 | break; |
95 | case 14: |
96 | cfg_reg += 0x48UL; |
97 | break; |
98 | case 15: |
99 | cfg_reg += 0x50UL; |
100 | break; |
101 | |
102 | default: |
103 | return; |
104 | } |
105 | |
106 | val = upa_readq(cfg_reg); |
107 | if (val & (1UL << 14UL)) { |
108 | /* Extended transfer mode already enabled. */ |
109 | return; |
110 | } |
111 | |
112 | val |= (1UL << 14UL); |
113 | |
114 | if (bursts & DMA_BURST8) |
115 | val |= (1UL << 1UL); |
116 | if (bursts & DMA_BURST16) |
117 | val |= (1UL << 2UL); |
118 | if (bursts & DMA_BURST32) |
119 | val |= (1UL << 3UL); |
120 | if (bursts & DMA_BURST64) |
121 | val |= (1UL << 4UL); |
122 | upa_writeq(val, cfg_reg); |
123 | } |
124 | EXPORT_SYMBOL(sbus_set_sbus64); |
125 | |
126 | /* INO number to IMAP register offset for SYSIO external IRQ's. |
127 | * This should conform to both Sunfire/Wildfire server and Fusion |
128 | * desktop designs. |
129 | */ |
130 | #define SYSIO_IMAP_SLOT0 0x2c00UL |
131 | #define SYSIO_IMAP_SLOT1 0x2c08UL |
132 | #define SYSIO_IMAP_SLOT2 0x2c10UL |
133 | #define SYSIO_IMAP_SLOT3 0x2c18UL |
134 | #define SYSIO_IMAP_SCSI 0x3000UL |
135 | #define SYSIO_IMAP_ETH 0x3008UL |
136 | #define SYSIO_IMAP_BPP 0x3010UL |
137 | #define SYSIO_IMAP_AUDIO 0x3018UL |
138 | #define SYSIO_IMAP_PFAIL 0x3020UL |
139 | #define SYSIO_IMAP_KMS 0x3028UL |
140 | #define SYSIO_IMAP_FLPY 0x3030UL |
141 | #define SYSIO_IMAP_SHW 0x3038UL |
142 | #define SYSIO_IMAP_KBD 0x3040UL |
143 | #define SYSIO_IMAP_MS 0x3048UL |
144 | #define SYSIO_IMAP_SER 0x3050UL |
145 | #define SYSIO_IMAP_TIM0 0x3060UL |
146 | #define SYSIO_IMAP_TIM1 0x3068UL |
147 | #define SYSIO_IMAP_UE 0x3070UL |
148 | #define SYSIO_IMAP_CE 0x3078UL |
149 | #define SYSIO_IMAP_SBERR 0x3080UL |
150 | #define SYSIO_IMAP_PMGMT 0x3088UL |
151 | #define SYSIO_IMAP_GFX 0x3090UL |
152 | #define SYSIO_IMAP_EUPA 0x3098UL |
153 | |
154 | #define bogon ((unsigned long) -1) |
155 | static unsigned long sysio_irq_offsets[] = { |
156 | /* SBUS Slot 0 --> 3, level 1 --> 7 */ |
157 | SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, |
158 | SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, |
159 | SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, |
160 | SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, |
161 | SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, |
162 | SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, |
163 | SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, |
164 | SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, |
165 | |
166 | /* Onboard devices (not relevant/used on SunFire). */ |
167 | SYSIO_IMAP_SCSI, |
168 | SYSIO_IMAP_ETH, |
169 | SYSIO_IMAP_BPP, |
170 | bogon, |
171 | SYSIO_IMAP_AUDIO, |
172 | SYSIO_IMAP_PFAIL, |
173 | bogon, |
174 | bogon, |
175 | SYSIO_IMAP_KMS, |
176 | SYSIO_IMAP_FLPY, |
177 | SYSIO_IMAP_SHW, |
178 | SYSIO_IMAP_KBD, |
179 | SYSIO_IMAP_MS, |
180 | SYSIO_IMAP_SER, |
181 | bogon, |
182 | bogon, |
183 | SYSIO_IMAP_TIM0, |
184 | SYSIO_IMAP_TIM1, |
185 | bogon, |
186 | bogon, |
187 | SYSIO_IMAP_UE, |
188 | SYSIO_IMAP_CE, |
189 | SYSIO_IMAP_SBERR, |
190 | SYSIO_IMAP_PMGMT, |
191 | }; |
192 | |
193 | #undef bogon |
194 | |
195 | #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets) |
196 | |
197 | /* Convert Interrupt Mapping register pointer to associated |
198 | * Interrupt Clear register pointer, SYSIO specific version. |
199 | */ |
200 | #define SYSIO_ICLR_UNUSED0 0x3400UL |
201 | #define SYSIO_ICLR_SLOT0 0x3408UL |
202 | #define SYSIO_ICLR_SLOT1 0x3448UL |
203 | #define SYSIO_ICLR_SLOT2 0x3488UL |
204 | #define SYSIO_ICLR_SLOT3 0x34c8UL |
205 | static unsigned long sysio_imap_to_iclr(unsigned long imap) |
206 | { |
207 | unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0; |
208 | return imap + diff; |
209 | } |
210 | |
211 | static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino) |
212 | { |
213 | struct iommu *iommu = op->dev.archdata.iommu; |
214 | unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; |
215 | unsigned long imap, iclr; |
216 | int sbus_level = 0; |
217 | |
218 | imap = sysio_irq_offsets[ino]; |
219 | if (imap == ((unsigned long)-1)) { |
220 | prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n" , |
221 | ino); |
222 | prom_halt(); |
223 | } |
224 | imap += reg_base; |
225 | |
226 | /* SYSIO inconsistency. For external SLOTS, we have to select |
227 | * the right ICLR register based upon the lower SBUS irq level |
228 | * bits. |
229 | */ |
230 | if (ino >= 0x20) { |
231 | iclr = sysio_imap_to_iclr(imap); |
232 | } else { |
233 | int sbus_slot = (ino & 0x18)>>3; |
234 | |
235 | sbus_level = ino & 0x7; |
236 | |
237 | switch(sbus_slot) { |
238 | case 0: |
239 | iclr = reg_base + SYSIO_ICLR_SLOT0; |
240 | break; |
241 | case 1: |
242 | iclr = reg_base + SYSIO_ICLR_SLOT1; |
243 | break; |
244 | case 2: |
245 | iclr = reg_base + SYSIO_ICLR_SLOT2; |
246 | break; |
247 | default: |
248 | case 3: |
249 | iclr = reg_base + SYSIO_ICLR_SLOT3; |
250 | break; |
251 | } |
252 | |
253 | iclr += ((unsigned long)sbus_level - 1UL) * 8UL; |
254 | } |
255 | return build_irq(sbus_level, iclr, imap); |
256 | } |
257 | |
258 | /* Error interrupt handling. */ |
259 | #define SYSIO_UE_AFSR 0x0030UL |
260 | #define SYSIO_UE_AFAR 0x0038UL |
261 | #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ |
262 | #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ |
263 | #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ |
264 | #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
265 | #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ |
266 | #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ |
267 | #define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
268 | #define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */ |
269 | #define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ |
270 | #define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ |
271 | #define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ |
272 | static irqreturn_t sysio_ue_handler(int irq, void *dev_id) |
273 | { |
274 | struct platform_device *op = dev_id; |
275 | struct iommu *iommu = op->dev.archdata.iommu; |
276 | unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; |
277 | unsigned long afsr_reg, afar_reg; |
278 | unsigned long afsr, afar, error_bits; |
279 | int reported, portid; |
280 | |
281 | afsr_reg = reg_base + SYSIO_UE_AFSR; |
282 | afar_reg = reg_base + SYSIO_UE_AFAR; |
283 | |
284 | /* Latch error status. */ |
285 | afsr = upa_readq(afsr_reg); |
286 | afar = upa_readq(afar_reg); |
287 | |
288 | /* Clear primary/secondary error status bits. */ |
289 | error_bits = afsr & |
290 | (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR | |
291 | SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR); |
292 | upa_writeq(error_bits, afsr_reg); |
293 | |
294 | portid = of_getintprop_default(op->dev.of_node, "portid" , -1); |
295 | |
296 | /* Log the error. */ |
297 | printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n" , |
298 | portid, |
299 | (((error_bits & SYSIO_UEAFSR_PPIO) ? |
300 | "PIO" : |
301 | ((error_bits & SYSIO_UEAFSR_PDRD) ? |
302 | "DVMA Read" : |
303 | ((error_bits & SYSIO_UEAFSR_PDWR) ? |
304 | "DVMA Write" : "???" ))))); |
305 | printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n" , |
306 | portid, |
307 | (afsr & SYSIO_UEAFSR_DOFF) >> 45UL, |
308 | (afsr & SYSIO_UEAFSR_SIZE) >> 42UL, |
309 | (afsr & SYSIO_UEAFSR_MID) >> 37UL); |
310 | printk("SYSIO[%x]: AFAR[%016lx]\n" , portid, afar); |
311 | printk("SYSIO[%x]: Secondary UE errors [" , portid); |
312 | reported = 0; |
313 | if (afsr & SYSIO_UEAFSR_SPIO) { |
314 | reported++; |
315 | printk("(PIO)" ); |
316 | } |
317 | if (afsr & SYSIO_UEAFSR_SDRD) { |
318 | reported++; |
319 | printk("(DVMA Read)" ); |
320 | } |
321 | if (afsr & SYSIO_UEAFSR_SDWR) { |
322 | reported++; |
323 | printk("(DVMA Write)" ); |
324 | } |
325 | if (!reported) |
326 | printk("(none)" ); |
327 | printk("]\n" ); |
328 | |
329 | return IRQ_HANDLED; |
330 | } |
331 | |
332 | #define SYSIO_CE_AFSR 0x0040UL |
333 | #define SYSIO_CE_AFAR 0x0048UL |
334 | #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */ |
335 | #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */ |
336 | #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */ |
337 | #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */ |
338 | #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */ |
339 | #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/ |
340 | #define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
341 | #define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
342 | #define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */ |
343 | #define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */ |
344 | #define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */ |
345 | #define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */ |
346 | static irqreturn_t sysio_ce_handler(int irq, void *dev_id) |
347 | { |
348 | struct platform_device *op = dev_id; |
349 | struct iommu *iommu = op->dev.archdata.iommu; |
350 | unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; |
351 | unsigned long afsr_reg, afar_reg; |
352 | unsigned long afsr, afar, error_bits; |
353 | int reported, portid; |
354 | |
355 | afsr_reg = reg_base + SYSIO_CE_AFSR; |
356 | afar_reg = reg_base + SYSIO_CE_AFAR; |
357 | |
358 | /* Latch error status. */ |
359 | afsr = upa_readq(afsr_reg); |
360 | afar = upa_readq(afar_reg); |
361 | |
362 | /* Clear primary/secondary error status bits. */ |
363 | error_bits = afsr & |
364 | (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR | |
365 | SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR); |
366 | upa_writeq(error_bits, afsr_reg); |
367 | |
368 | portid = of_getintprop_default(op->dev.of_node, "portid" , -1); |
369 | |
370 | printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n" , |
371 | portid, |
372 | (((error_bits & SYSIO_CEAFSR_PPIO) ? |
373 | "PIO" : |
374 | ((error_bits & SYSIO_CEAFSR_PDRD) ? |
375 | "DVMA Read" : |
376 | ((error_bits & SYSIO_CEAFSR_PDWR) ? |
377 | "DVMA Write" : "???" ))))); |
378 | |
379 | /* XXX Use syndrome and afar to print out module string just like |
380 | * XXX UDB CE trap handler does... -DaveM |
381 | */ |
382 | printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n" , |
383 | portid, |
384 | (afsr & SYSIO_CEAFSR_DOFF) >> 45UL, |
385 | (afsr & SYSIO_CEAFSR_ESYND) >> 48UL, |
386 | (afsr & SYSIO_CEAFSR_SIZE) >> 42UL, |
387 | (afsr & SYSIO_CEAFSR_MID) >> 37UL); |
388 | printk("SYSIO[%x]: AFAR[%016lx]\n" , portid, afar); |
389 | |
390 | printk("SYSIO[%x]: Secondary CE errors [" , portid); |
391 | reported = 0; |
392 | if (afsr & SYSIO_CEAFSR_SPIO) { |
393 | reported++; |
394 | printk("(PIO)" ); |
395 | } |
396 | if (afsr & SYSIO_CEAFSR_SDRD) { |
397 | reported++; |
398 | printk("(DVMA Read)" ); |
399 | } |
400 | if (afsr & SYSIO_CEAFSR_SDWR) { |
401 | reported++; |
402 | printk("(DVMA Write)" ); |
403 | } |
404 | if (!reported) |
405 | printk("(none)" ); |
406 | printk("]\n" ); |
407 | |
408 | return IRQ_HANDLED; |
409 | } |
410 | |
411 | #define SYSIO_SBUS_AFSR 0x2010UL |
412 | #define SYSIO_SBUS_AFAR 0x2018UL |
413 | #define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */ |
414 | #define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */ |
415 | #define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */ |
416 | #define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */ |
417 | #define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */ |
418 | #define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */ |
419 | #define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
420 | #define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */ |
421 | #define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */ |
422 | #define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */ |
423 | #define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */ |
424 | #define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */ |
425 | static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id) |
426 | { |
427 | struct platform_device *op = dev_id; |
428 | struct iommu *iommu = op->dev.archdata.iommu; |
429 | unsigned long afsr_reg, afar_reg, reg_base; |
430 | unsigned long afsr, afar, error_bits; |
431 | int reported, portid; |
432 | |
433 | reg_base = iommu->write_complete_reg - 0x2000UL; |
434 | afsr_reg = reg_base + SYSIO_SBUS_AFSR; |
435 | afar_reg = reg_base + SYSIO_SBUS_AFAR; |
436 | |
437 | afsr = upa_readq(afsr_reg); |
438 | afar = upa_readq(afar_reg); |
439 | |
440 | /* Clear primary/secondary error status bits. */ |
441 | error_bits = afsr & |
442 | (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR | |
443 | SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR); |
444 | upa_writeq(error_bits, afsr_reg); |
445 | |
446 | portid = of_getintprop_default(op->dev.of_node, "portid" , -1); |
447 | |
448 | /* Log the error. */ |
449 | printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n" , |
450 | portid, |
451 | (((error_bits & SYSIO_SBAFSR_PLE) ? |
452 | "Late PIO Error" : |
453 | ((error_bits & SYSIO_SBAFSR_PTO) ? |
454 | "Time Out" : |
455 | ((error_bits & SYSIO_SBAFSR_PBERR) ? |
456 | "Error Ack" : "???" )))), |
457 | (afsr & SYSIO_SBAFSR_RD) ? 1 : 0); |
458 | printk("SYSIO[%x]: size[%lx] MID[%lx]\n" , |
459 | portid, |
460 | (afsr & SYSIO_SBAFSR_SIZE) >> 42UL, |
461 | (afsr & SYSIO_SBAFSR_MID) >> 37UL); |
462 | printk("SYSIO[%x]: AFAR[%016lx]\n" , portid, afar); |
463 | printk("SYSIO[%x]: Secondary SBUS errors [" , portid); |
464 | reported = 0; |
465 | if (afsr & SYSIO_SBAFSR_SLE) { |
466 | reported++; |
467 | printk("(Late PIO Error)" ); |
468 | } |
469 | if (afsr & SYSIO_SBAFSR_STO) { |
470 | reported++; |
471 | printk("(Time Out)" ); |
472 | } |
473 | if (afsr & SYSIO_SBAFSR_SBERR) { |
474 | reported++; |
475 | printk("(Error Ack)" ); |
476 | } |
477 | if (!reported) |
478 | printk("(none)" ); |
479 | printk("]\n" ); |
480 | |
481 | /* XXX check iommu/strbuf for further error status XXX */ |
482 | |
483 | return IRQ_HANDLED; |
484 | } |
485 | |
486 | #define ECC_CONTROL 0x0020UL |
487 | #define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */ |
488 | #define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */ |
489 | #define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */ |
490 | |
491 | #define SYSIO_UE_INO 0x34 |
492 | #define SYSIO_CE_INO 0x35 |
493 | #define SYSIO_SBUSERR_INO 0x36 |
494 | |
495 | static void __init sysio_register_error_handlers(struct platform_device *op) |
496 | { |
497 | struct iommu *iommu = op->dev.archdata.iommu; |
498 | unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; |
499 | unsigned int irq; |
500 | u64 control; |
501 | int portid; |
502 | |
503 | portid = of_getintprop_default(op->dev.of_node, "portid" , -1); |
504 | |
505 | irq = sbus_build_irq(op, SYSIO_UE_INO); |
506 | if (request_irq(irq, handler: sysio_ue_handler, flags: 0, |
507 | name: "SYSIO_UE" , dev: op) < 0) { |
508 | prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n" , |
509 | portid); |
510 | prom_halt(); |
511 | } |
512 | |
513 | irq = sbus_build_irq(op, SYSIO_CE_INO); |
514 | if (request_irq(irq, handler: sysio_ce_handler, flags: 0, |
515 | name: "SYSIO_CE" , dev: op) < 0) { |
516 | prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n" , |
517 | portid); |
518 | prom_halt(); |
519 | } |
520 | |
521 | irq = sbus_build_irq(op, SYSIO_SBUSERR_INO); |
522 | if (request_irq(irq, handler: sysio_sbus_error_handler, flags: 0, |
523 | name: "SYSIO_SBERR" , dev: op) < 0) { |
524 | prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n" , |
525 | portid); |
526 | prom_halt(); |
527 | } |
528 | |
529 | /* Now turn the error interrupts on and also enable ECC checking. */ |
530 | upa_writeq((SYSIO_ECNTRL_ECCEN | |
531 | SYSIO_ECNTRL_UEEN | |
532 | SYSIO_ECNTRL_CEEN), |
533 | reg_base + ECC_CONTROL); |
534 | |
535 | control = upa_readq(iommu->write_complete_reg); |
536 | control |= 0x100UL; /* SBUS Error Interrupt Enable */ |
537 | upa_writeq(control, iommu->write_complete_reg); |
538 | } |
539 | |
540 | /* Boot time initialization. */ |
541 | static void __init sbus_iommu_init(struct platform_device *op) |
542 | { |
543 | const struct linux_prom64_registers *pr; |
544 | struct device_node *dp = op->dev.of_node; |
545 | struct iommu *iommu; |
546 | struct strbuf *strbuf; |
547 | unsigned long regs, reg_base; |
548 | int i, portid; |
549 | u64 control; |
550 | |
551 | pr = of_get_property(node: dp, name: "reg" , NULL); |
552 | if (!pr) { |
553 | prom_printf("sbus_iommu_init: Cannot map SYSIO " |
554 | "control registers.\n" ); |
555 | prom_halt(); |
556 | } |
557 | regs = pr->phys_addr; |
558 | |
559 | iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC); |
560 | strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC); |
561 | if (!iommu || !strbuf) |
562 | goto fatal_memory_error; |
563 | |
564 | op->dev.archdata.iommu = iommu; |
565 | op->dev.archdata.stc = strbuf; |
566 | op->dev.archdata.numa_node = NUMA_NO_NODE; |
567 | |
568 | reg_base = regs + SYSIO_IOMMUREG_BASE; |
569 | iommu->iommu_control = reg_base + IOMMU_CONTROL; |
570 | iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE; |
571 | iommu->iommu_flush = reg_base + IOMMU_FLUSH; |
572 | iommu->iommu_tags = iommu->iommu_control + |
573 | (IOMMU_TAGDIAG - IOMMU_CONTROL); |
574 | |
575 | reg_base = regs + SYSIO_STRBUFREG_BASE; |
576 | strbuf->strbuf_control = reg_base + STRBUF_CONTROL; |
577 | strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH; |
578 | strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC; |
579 | |
580 | strbuf->strbuf_enabled = 1; |
581 | |
582 | strbuf->strbuf_flushflag = (volatile unsigned long *) |
583 | ((((unsigned long)&strbuf->__flushflag_buf[0]) |
584 | + 63UL) |
585 | & ~63UL); |
586 | strbuf->strbuf_flushflag_pa = (unsigned long) |
587 | __pa(strbuf->strbuf_flushflag); |
588 | |
589 | /* The SYSIO SBUS control register is used for dummy reads |
590 | * in order to ensure write completion. |
591 | */ |
592 | iommu->write_complete_reg = regs + 0x2000UL; |
593 | |
594 | portid = of_getintprop_default(op->dev.of_node, "portid" , -1); |
595 | printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n" , |
596 | portid, regs); |
597 | |
598 | /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */ |
599 | if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1)) |
600 | goto fatal_memory_error; |
601 | |
602 | control = upa_readq(iommu->iommu_control); |
603 | control = ((7UL << 16UL) | |
604 | (0UL << 2UL) | |
605 | (1UL << 1UL) | |
606 | (1UL << 0UL)); |
607 | upa_writeq(control, iommu->iommu_control); |
608 | |
609 | /* Clean out any cruft in the IOMMU using |
610 | * diagnostic accesses. |
611 | */ |
612 | for (i = 0; i < 16; i++) { |
613 | unsigned long dram, tag; |
614 | |
615 | dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL); |
616 | tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL); |
617 | |
618 | dram += (unsigned long)i * 8UL; |
619 | tag += (unsigned long)i * 8UL; |
620 | upa_writeq(0, dram); |
621 | upa_writeq(0, tag); |
622 | } |
623 | upa_readq(iommu->write_complete_reg); |
624 | |
625 | /* Give the TSB to SYSIO. */ |
626 | upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); |
627 | |
628 | /* Setup streaming buffer, DE=1 SB_EN=1 */ |
629 | control = (1UL << 1UL) | (1UL << 0UL); |
630 | upa_writeq(control, strbuf->strbuf_control); |
631 | |
632 | /* Clear out the tags using diagnostics. */ |
633 | for (i = 0; i < 16; i++) { |
634 | unsigned long ptag, ltag; |
635 | |
636 | ptag = strbuf->strbuf_control + |
637 | (STRBUF_PTAGDIAG - STRBUF_CONTROL); |
638 | ltag = strbuf->strbuf_control + |
639 | (STRBUF_LTAGDIAG - STRBUF_CONTROL); |
640 | ptag += (unsigned long)i * 8UL; |
641 | ltag += (unsigned long)i * 8UL; |
642 | |
643 | upa_writeq(0UL, ptag); |
644 | upa_writeq(0UL, ltag); |
645 | } |
646 | |
647 | /* Enable DVMA arbitration for all devices/slots. */ |
648 | control = upa_readq(iommu->write_complete_reg); |
649 | control |= 0x3fUL; |
650 | upa_writeq(control, iommu->write_complete_reg); |
651 | |
652 | /* Now some Xfire specific grot... */ |
653 | if (this_is_starfire) |
654 | starfire_hookup(portid); |
655 | |
656 | sysio_register_error_handlers(op); |
657 | return; |
658 | |
659 | fatal_memory_error: |
660 | kfree(objp: iommu); |
661 | kfree(objp: strbuf); |
662 | prom_printf("sbus_iommu_init: Fatal memory allocation error.\n" ); |
663 | } |
664 | |
665 | static int __init sbus_init(void) |
666 | { |
667 | struct device_node *dp; |
668 | |
669 | for_each_node_by_name(dp, "sbus" ) { |
670 | struct platform_device *op = of_find_device_by_node(np: dp); |
671 | |
672 | sbus_iommu_init(op); |
673 | of_propagate_archdata(op); |
674 | } |
675 | |
676 | return 0; |
677 | } |
678 | |
679 | subsys_initcall(sbus_init); |
680 | |