1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6#include <linux/static_call.h>
7
8#include <asm/alternative.h>
9#include <asm/cpufeature.h>
10#include <asm/apicdef.h>
11#include <linux/atomic.h>
12#include <asm/fixmap.h>
13#include <asm/mpspec.h>
14#include <asm/msr.h>
15#include <asm/hardirq.h>
16#include <asm/io.h>
17#include <asm/posted_intr.h>
18
19#define ARCH_APICTIMER_STOPS_ON_C3 1
20
21/* Macros for apic_extnmi which controls external NMI masking */
22#define APIC_EXTNMI_BSP 0 /* Default */
23#define APIC_EXTNMI_ALL 1
24#define APIC_EXTNMI_NONE 2
25
26/*
27 * Debugging macros
28 */
29#define APIC_QUIET 0
30#define APIC_VERBOSE 1
31#define APIC_DEBUG 2
32
33/*
34 * Define the default level of output to be very little This can be turned
35 * up by using apic=verbose for more information and apic=debug for _lots_
36 * of information. apic_verbosity is defined in apic.c
37 */
38#define apic_printk(v, s, a...) \
39do { \
40 if ((v) <= apic_verbosity) \
41 printk(s, ##a); \
42} while (0)
43
44#define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a)
45#define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a)
46#define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a)
47/* Unconditional debug prints for code which is guarded by apic_verbosity already */
48#define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a)
49
50#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
51extern void x86_32_probe_apic(void);
52#else
53static inline void x86_32_probe_apic(void) { }
54#endif
55
56extern u32 cpuid_to_apicid[];
57
58#define CPU_ACPIID_INVALID U32_MAX
59
60#ifdef CONFIG_X86_LOCAL_APIC
61
62extern int apic_verbosity;
63extern int local_apic_timer_c2_ok;
64
65extern bool apic_is_disabled;
66extern unsigned int lapic_timer_period;
67
68extern enum apic_intr_mode_id apic_intr_mode;
69enum apic_intr_mode_id {
70 APIC_PIC,
71 APIC_VIRTUAL_WIRE,
72 APIC_VIRTUAL_WIRE_NO_CONFIG,
73 APIC_SYMMETRIC_IO,
74 APIC_SYMMETRIC_IO_NO_ROUTING
75};
76
77/*
78 * With 82489DX we can't rely on apic feature bit
79 * retrieved via cpuid but still have to deal with
80 * such an apic chip so we assume that SMP configuration
81 * is found from MP table (64bit case uses ACPI mostly
82 * which set smp presence flag as well so we are safe
83 * to use this helper too).
84 */
85static inline bool apic_from_smp_config(void)
86{
87 return smp_found_config && !apic_is_disabled;
88}
89
90/*
91 * Basic functions accessing APICs.
92 */
93#ifdef CONFIG_PARAVIRT
94#include <asm/paravirt.h>
95#endif
96
97static inline void native_apic_mem_write(u32 reg, u32 v)
98{
99 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
100
101 alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,
102 ASM_OUTPUT("=r" (v), "=m" (*addr)),
103 ASM_INPUT("0" (v), "m" (*addr)));
104}
105
106static inline u32 native_apic_mem_read(u32 reg)
107{
108 return readl(addr: (void __iomem *)(APIC_BASE + reg));
109}
110
111static inline void native_apic_mem_eoi(void)
112{
113 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
114}
115
116extern void native_apic_icr_write(u32 low, u32 id);
117extern u64 native_apic_icr_read(void);
118
119static inline bool apic_is_x2apic_enabled(void)
120{
121 u64 msr;
122
123 if (rdmsrq_safe(MSR_IA32_APICBASE, p: &msr))
124 return false;
125 return msr & X2APIC_ENABLE;
126}
127
128extern void enable_IR_x2apic(void);
129
130extern int lapic_get_maxlvt(void);
131extern void clear_local_APIC(void);
132extern void disconnect_bsp_APIC(int virt_wire_setup);
133extern void disable_local_APIC(void);
134extern void apic_soft_disable(void);
135extern void lapic_shutdown(void);
136extern void sync_Arb_IDs(void);
137extern void init_bsp_APIC(void);
138extern void apic_intr_mode_select(void);
139extern void apic_intr_mode_init(void);
140extern void init_apic_mappings(void);
141void register_lapic_address(unsigned long address);
142extern void setup_boot_APIC_clock(void);
143extern void setup_secondary_APIC_clock(void);
144extern void lapic_update_tsc_freq(void);
145
146#ifdef CONFIG_X86_64
147static inline bool apic_force_enable(unsigned long addr)
148{
149 return false;
150}
151#else
152extern bool apic_force_enable(unsigned long addr);
153#endif
154
155extern void apic_ap_setup(void);
156
157/*
158 * On 32bit this is mach-xxx local
159 */
160#ifdef CONFIG_X86_64
161extern int apic_is_clustered_box(void);
162#else
163static inline int apic_is_clustered_box(void)
164{
165 return 0;
166}
167#endif
168
169extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
170extern void lapic_assign_system_vectors(void);
171extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
172extern void lapic_update_legacy_vectors(void);
173extern void lapic_online(void);
174extern void lapic_offline(void);
175extern bool apic_needs_pit(void);
176
177extern void apic_send_IPI_allbutself(unsigned int vector);
178
179extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present);
180extern void topology_register_boot_apic(u32 apic_id);
181extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id);
182extern void topology_hotunplug_apic(unsigned int cpu);
183extern void topology_apply_cmdline_limits_early(void);
184extern void topology_init_possible_cpus(void);
185extern void topology_reset_possible_cpus_up(void);
186
187#else /* !CONFIG_X86_LOCAL_APIC */
188static inline void lapic_shutdown(void) { }
189#define local_apic_timer_c2_ok 1
190static inline void init_apic_mappings(void) { }
191static inline void disable_local_APIC(void) { }
192# define setup_boot_APIC_clock x86_init_noop
193# define setup_secondary_APIC_clock x86_init_noop
194static inline void lapic_update_tsc_freq(void) { }
195static inline void init_bsp_APIC(void) { }
196static inline void apic_intr_mode_select(void) { }
197static inline void apic_intr_mode_init(void) { }
198static inline void lapic_assign_system_vectors(void) { }
199static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
200static inline bool apic_needs_pit(void) { return true; }
201static inline void topology_apply_cmdline_limits_early(void) { }
202static inline void topology_init_possible_cpus(void) { }
203#endif /* !CONFIG_X86_LOCAL_APIC */
204
205#ifdef CONFIG_X86_X2APIC
206static inline void native_apic_msr_write(u32 reg, u32 v)
207{
208 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
209 reg == APIC_LVR)
210 return;
211
212 wrmsrq(APIC_BASE_MSR + (reg >> 4), val: v);
213}
214
215static inline void native_apic_msr_eoi(void)
216{
217 native_wrmsrq(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK);
218}
219
220static inline u32 native_apic_msr_read(u32 reg)
221{
222 u64 msr;
223
224 if (reg == APIC_DFR)
225 return -1;
226
227 rdmsrq(APIC_BASE_MSR + (reg >> 4), msr);
228 return (u32)msr;
229}
230
231static inline void native_x2apic_icr_write(u32 low, u32 id)
232{
233 wrmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val: ((__u64) id) << 32 | low);
234}
235
236static inline u64 native_x2apic_icr_read(void)
237{
238 unsigned long val;
239
240 rdmsrq(APIC_BASE_MSR + (APIC_ICR >> 4), val);
241 return val;
242}
243
244extern int x2apic_mode;
245extern int x2apic_phys;
246extern void __init x2apic_set_max_apicid(u32 apicid);
247extern void x2apic_setup(void);
248static inline int x2apic_enabled(void)
249{
250 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
251}
252
253#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
254#else /* !CONFIG_X86_X2APIC */
255static inline void x2apic_setup(void) { }
256static inline int x2apic_enabled(void) { return 0; }
257static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
258#define x2apic_mode (0)
259#define x2apic_supported() (0)
260#endif /* !CONFIG_X86_X2APIC */
261extern void __init check_x2apic(void);
262
263struct irq_data;
264
265/*
266 * Copyright 2004 James Cleverdon, IBM.
267 *
268 * Generic APIC sub-arch data struct.
269 *
270 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
271 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
272 * James Cleverdon.
273 */
274struct apic {
275 /* Hotpath functions first */
276 void (*eoi)(void);
277 void (*native_eoi)(void);
278 void (*write)(u32 reg, u32 v);
279 u32 (*read)(u32 reg);
280
281 /* IPI related functions */
282 void (*wait_icr_idle)(void);
283 u32 (*safe_wait_icr_idle)(void);
284
285 void (*send_IPI)(int cpu, int vector);
286 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
287 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
288 void (*send_IPI_allbutself)(int vector);
289 void (*send_IPI_all)(int vector);
290 void (*send_IPI_self)(int vector);
291
292 u32 disable_esr : 1,
293 dest_mode_logical : 1,
294 x2apic_set_max_apicid : 1,
295 nmi_to_offline_cpu : 1;
296
297 u32 (*calc_dest_apicid)(unsigned int cpu);
298
299 /* ICR related functions */
300 u64 (*icr_read)(void);
301 void (*icr_write)(u32 low, u32 high);
302
303 /* The limit of the APIC ID space. */
304 u32 max_apic_id;
305
306 /* Probe, setup and smpboot functions */
307 int (*probe)(void);
308 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
309
310 void (*init_apic_ldr)(void);
311 u32 (*cpu_present_to_apicid)(int mps_cpu);
312
313 u32 (*get_apic_id)(u32 id);
314
315 /* wakeup_secondary_cpu */
316 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu);
317 /* wakeup secondary CPU using 64-bit wakeup point */
318 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu);
319
320 char *name;
321};
322
323struct apic_override {
324 void (*eoi)(void);
325 void (*native_eoi)(void);
326 void (*write)(u32 reg, u32 v);
327 u32 (*read)(u32 reg);
328 void (*send_IPI)(int cpu, int vector);
329 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
330 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
331 void (*send_IPI_allbutself)(int vector);
332 void (*send_IPI_all)(int vector);
333 void (*send_IPI_self)(int vector);
334 u64 (*icr_read)(void);
335 void (*icr_write)(u32 low, u32 high);
336 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip, unsigned int cpu);
337 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsigned int cpu);
338};
339
340/*
341 * Pointer to the local APIC driver in use on this system (there's
342 * always just one such driver in use - the kernel decides via an
343 * early probing process which one it picks - and then sticks to it):
344 */
345extern struct apic *apic;
346
347/*
348 * APIC drivers are probed based on how they are listed in the .apicdrivers
349 * section. So the order is important and enforced by the ordering
350 * of different apic driver files in the Makefile.
351 */
352#define apic_driver(sym) \
353 static const struct apic *__apicdrivers_##sym __used \
354 __aligned(sizeof(struct apic *)) \
355 __section(".apicdrivers") = { &sym }
356
357extern struct apic *__apicdrivers[], *__apicdrivers_end[];
358
359/*
360 * APIC functionality to boot other CPUs - only used on SMP:
361 */
362#ifdef CONFIG_SMP
363extern int lapic_can_unplug_cpu(void);
364#endif
365
366#ifdef CONFIG_X86_LOCAL_APIC
367extern struct apic_override __x86_apic_override;
368
369void __init apic_setup_apic_calls(void);
370void __init apic_install_driver(struct apic *driver);
371
372#define apic_update_callback(_callback, _fn) { \
373 __x86_apic_override._callback = _fn; \
374 apic->_callback = _fn; \
375 static_call_update(apic_call_##_callback, _fn); \
376 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
377}
378
379#define DECLARE_APIC_CALL(__cb) \
380 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)
381
382DECLARE_APIC_CALL(eoi);
383DECLARE_APIC_CALL(native_eoi);
384DECLARE_APIC_CALL(icr_read);
385DECLARE_APIC_CALL(icr_write);
386DECLARE_APIC_CALL(read);
387DECLARE_APIC_CALL(send_IPI);
388DECLARE_APIC_CALL(send_IPI_mask);
389DECLARE_APIC_CALL(send_IPI_mask_allbutself);
390DECLARE_APIC_CALL(send_IPI_allbutself);
391DECLARE_APIC_CALL(send_IPI_all);
392DECLARE_APIC_CALL(send_IPI_self);
393DECLARE_APIC_CALL(wait_icr_idle);
394DECLARE_APIC_CALL(wakeup_secondary_cpu);
395DECLARE_APIC_CALL(wakeup_secondary_cpu_64);
396DECLARE_APIC_CALL(write);
397
398static __always_inline u32 apic_read(u32 reg)
399{
400 return static_call(apic_call_read)(reg);
401}
402
403static __always_inline void apic_write(u32 reg, u32 val)
404{
405 static_call(apic_call_write)(reg, val);
406}
407
408static __always_inline void apic_eoi(void)
409{
410 static_call(apic_call_eoi)();
411}
412
413static __always_inline void apic_native_eoi(void)
414{
415 static_call(apic_call_native_eoi)();
416}
417
418static __always_inline u64 apic_icr_read(void)
419{
420 return static_call(apic_call_icr_read)();
421}
422
423static __always_inline void apic_icr_write(u32 low, u32 high)
424{
425 static_call(apic_call_icr_write)(low, high);
426}
427
428static __always_inline void __apic_send_IPI(int cpu, int vector)
429{
430 static_call(apic_call_send_IPI)(cpu, vector);
431}
432
433static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
434{
435 static_call_mod(apic_call_send_IPI_mask)(mask, vector);
436}
437
438static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
439{
440 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector);
441}
442
443static __always_inline void __apic_send_IPI_allbutself(int vector)
444{
445 static_call(apic_call_send_IPI_allbutself)(vector);
446}
447
448static __always_inline void __apic_send_IPI_all(int vector)
449{
450 static_call(apic_call_send_IPI_all)(vector);
451}
452
453static __always_inline void __apic_send_IPI_self(int vector)
454{
455 static_call_mod(apic_call_send_IPI_self)(vector);
456}
457
458static __always_inline void apic_wait_icr_idle(void)
459{
460 static_call_cond(apic_call_wait_icr_idle)();
461}
462
463static __always_inline u32 safe_apic_wait_icr_idle(void)
464{
465 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
466}
467
468static __always_inline bool apic_id_valid(u32 apic_id)
469{
470 return apic_id <= apic->max_apic_id;
471}
472
473#else /* CONFIG_X86_LOCAL_APIC */
474
475static inline u32 apic_read(u32 reg) { return 0; }
476static inline void apic_write(u32 reg, u32 val) { }
477static inline void apic_eoi(void) { }
478static inline u64 apic_icr_read(void) { return 0; }
479static inline void apic_icr_write(u32 low, u32 high) { }
480static inline void apic_wait_icr_idle(void) { }
481static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
482static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
483static inline void apic_setup_apic_calls(void) { }
484
485#define apic_update_callback(_callback, _fn) do { } while (0)
486
487#endif /* CONFIG_X86_LOCAL_APIC */
488
489extern void apic_ack_irq(struct irq_data *data);
490
491static inline bool lapic_vector_set_in_irr(unsigned int vector)
492{
493 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
494
495 return !!(irr & (1U << (vector % 32)));
496}
497
498static inline bool is_vector_pending(unsigned int vector)
499{
500 return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector);
501}
502
503/*
504 * Warm reset vector position:
505 */
506#define TRAMPOLINE_PHYS_LOW 0x467
507#define TRAMPOLINE_PHYS_HIGH 0x469
508
509#ifdef CONFIG_X86_LOCAL_APIC
510
511#include <asm/smp.h>
512
513extern struct apic apic_noop;
514
515static inline u32 read_apic_id(void)
516{
517 u32 reg = apic_read(APIC_ID);
518
519 return apic->get_apic_id(reg);
520}
521
522#ifdef CONFIG_X86_64
523typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
524extern int default_acpi_madt_oem_check(char *, char *);
525extern void x86_64_probe_apic(void);
526#else
527static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
528static inline void x86_64_probe_apic(void) { }
529#endif
530
531extern u32 apic_default_calc_apicid(unsigned int cpu);
532extern u32 apic_flat_calc_apicid(unsigned int cpu);
533
534extern u32 default_cpu_present_to_apicid(int mps_cpu);
535
536void apic_send_nmi_to_offline_cpu(unsigned int cpu);
537
538#else /* CONFIG_X86_LOCAL_APIC */
539
540static inline u32 read_apic_id(void) { return 0; }
541
542#endif /* !CONFIG_X86_LOCAL_APIC */
543
544#ifdef CONFIG_SMP
545void apic_smt_update(void);
546#else
547static inline void apic_smt_update(void) { }
548#endif
549
550struct msi_msg;
551struct irq_cfg;
552
553extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
554 bool dmar);
555
556extern void ioapic_zap_locks(void);
557
558#endif /* _ASM_X86_APIC_H */
559

source code of linux/arch/x86/include/asm/apic.h