1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
4 | * |
5 | * Written by Jacob Shin - AMD, Inc. |
6 | * Maintained by: Borislav Petkov <bp@alien8.de> |
7 | * |
8 | * All MC4_MISCi registers are shared between cores on a node. |
9 | */ |
10 | #include <linux/interrupt.h> |
11 | #include <linux/notifier.h> |
12 | #include <linux/kobject.h> |
13 | #include <linux/percpu.h> |
14 | #include <linux/errno.h> |
15 | #include <linux/sched.h> |
16 | #include <linux/sysfs.h> |
17 | #include <linux/slab.h> |
18 | #include <linux/init.h> |
19 | #include <linux/cpu.h> |
20 | #include <linux/smp.h> |
21 | #include <linux/string.h> |
22 | |
23 | #include <asm/amd_nb.h> |
24 | #include <asm/traps.h> |
25 | #include <asm/apic.h> |
26 | #include <asm/mce.h> |
27 | #include <asm/msr.h> |
28 | #include <asm/trace/irq_vectors.h> |
29 | |
30 | #include "internal.h" |
31 | |
32 | #define NR_BLOCKS 5 |
33 | #define THRESHOLD_MAX 0xFFF |
34 | #define INT_TYPE_APIC 0x00020000 |
35 | #define MASK_VALID_HI 0x80000000 |
36 | #define MASK_CNTP_HI 0x40000000 |
37 | #define MASK_LOCKED_HI 0x20000000 |
38 | #define MASK_LVTOFF_HI 0x00F00000 |
39 | #define MASK_COUNT_EN_HI 0x00080000 |
40 | #define MASK_INT_TYPE_HI 0x00060000 |
41 | #define MASK_OVERFLOW_HI 0x00010000 |
42 | #define MASK_ERR_COUNT_HI 0x00000FFF |
43 | #define MASK_BLKPTR_LO 0xFF000000 |
44 | #define MCG_XBLK_ADDR 0xC0000400 |
45 | |
46 | /* Deferred error settings */ |
47 | #define MSR_CU_DEF_ERR 0xC0000410 |
48 | #define MASK_DEF_LVTOFF 0x000000F0 |
49 | #define MASK_DEF_INT_TYPE 0x00000006 |
50 | #define DEF_LVT_OFF 0x2 |
51 | #define DEF_INT_TYPE_APIC 0x2 |
52 | |
53 | /* Scalable MCA: */ |
54 | |
55 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ |
56 | #define SMCA_THR_LVT_OFF 0xF000 |
57 | |
58 | static bool thresholding_irq_en; |
59 | |
60 | static const char * const th_names[] = { |
61 | "load_store" , |
62 | "insn_fetch" , |
63 | "combined_unit" , |
64 | "decode_unit" , |
65 | "northbridge" , |
66 | "execution_unit" , |
67 | }; |
68 | |
69 | static const char * const smca_umc_block_names[] = { |
70 | "dram_ecc" , |
71 | "misc_umc" |
72 | }; |
73 | |
74 | #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) |
75 | |
76 | struct smca_hwid { |
77 | unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ |
78 | u32 hwid_mcatype; /* (hwid,mcatype) tuple */ |
79 | }; |
80 | |
81 | struct smca_bank { |
82 | const struct smca_hwid *hwid; |
83 | u32 id; /* Value of MCA_IPID[InstanceId]. */ |
84 | u8 sysfs_id; /* Value used for sysfs name. */ |
85 | }; |
86 | |
87 | static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); |
88 | static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); |
89 | |
90 | static const char * const smca_names[] = { |
91 | [SMCA_LS ... SMCA_LS_V2] = "load_store" , |
92 | [SMCA_IF] = "insn_fetch" , |
93 | [SMCA_L2_CACHE] = "l2_cache" , |
94 | [SMCA_DE] = "decode_unit" , |
95 | [SMCA_RESERVED] = "reserved" , |
96 | [SMCA_EX] = "execution_unit" , |
97 | [SMCA_FP] = "floating_point" , |
98 | [SMCA_L3_CACHE] = "l3_cache" , |
99 | [SMCA_CS ... SMCA_CS_V2] = "coherent_slave" , |
100 | [SMCA_PIE] = "pie" , |
101 | |
102 | /* UMC v2 is separate because both of them can exist in a single system. */ |
103 | [SMCA_UMC] = "umc" , |
104 | [SMCA_UMC_V2] = "umc_v2" , |
105 | [SMCA_MA_LLC] = "ma_llc" , |
106 | [SMCA_PB] = "param_block" , |
107 | [SMCA_PSP ... SMCA_PSP_V2] = "psp" , |
108 | [SMCA_SMU ... SMCA_SMU_V2] = "smu" , |
109 | [SMCA_MP5] = "mp5" , |
110 | [SMCA_MPDMA] = "mpdma" , |
111 | [SMCA_NBIO] = "nbio" , |
112 | [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie" , |
113 | [SMCA_XGMI_PCS] = "xgmi_pcs" , |
114 | [SMCA_NBIF] = "nbif" , |
115 | [SMCA_SHUB] = "shub" , |
116 | [SMCA_SATA] = "sata" , |
117 | [SMCA_USB] = "usb" , |
118 | [SMCA_USR_DP] = "usr_dp" , |
119 | [SMCA_USR_CP] = "usr_cp" , |
120 | [SMCA_GMI_PCS] = "gmi_pcs" , |
121 | [SMCA_XGMI_PHY] = "xgmi_phy" , |
122 | [SMCA_WAFL_PHY] = "wafl_phy" , |
123 | [SMCA_GMI_PHY] = "gmi_phy" , |
124 | }; |
125 | |
126 | static const char *smca_get_name(enum smca_bank_types t) |
127 | { |
128 | if (t >= N_SMCA_BANK_TYPES) |
129 | return NULL; |
130 | |
131 | return smca_names[t]; |
132 | } |
133 | |
134 | enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) |
135 | { |
136 | struct smca_bank *b; |
137 | |
138 | if (bank >= MAX_NR_BANKS) |
139 | return N_SMCA_BANK_TYPES; |
140 | |
141 | b = &per_cpu(smca_banks, cpu)[bank]; |
142 | if (!b->hwid) |
143 | return N_SMCA_BANK_TYPES; |
144 | |
145 | return b->hwid->bank_type; |
146 | } |
147 | EXPORT_SYMBOL_GPL(smca_get_bank_type); |
148 | |
149 | static const struct smca_hwid smca_hwid_mcatypes[] = { |
150 | /* { bank_type, hwid_mcatype } */ |
151 | |
152 | /* Reserved type */ |
153 | { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) }, |
154 | |
155 | /* ZN Core (HWID=0xB0) MCA types */ |
156 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) }, |
157 | { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) }, |
158 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) }, |
159 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) }, |
160 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) }, |
161 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ |
162 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) }, |
163 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) }, |
164 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) }, |
165 | |
166 | /* Data Fabric MCA types */ |
167 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) }, |
168 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) }, |
169 | { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) }, |
170 | { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) }, |
171 | |
172 | /* Unified Memory Controller MCA type */ |
173 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) }, |
174 | { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) }, |
175 | |
176 | /* Parameter Block MCA type */ |
177 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0) }, |
178 | |
179 | /* Platform Security Processor MCA type */ |
180 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) }, |
181 | { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) }, |
182 | |
183 | /* System Management Unit MCA type */ |
184 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) }, |
185 | { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) }, |
186 | |
187 | /* Microprocessor 5 Unit MCA type */ |
188 | { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) }, |
189 | |
190 | /* MPDMA MCA type */ |
191 | { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) }, |
192 | |
193 | /* Northbridge IO Unit MCA type */ |
194 | { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) }, |
195 | |
196 | /* PCI Express Unit MCA type */ |
197 | { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) }, |
198 | { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) }, |
199 | |
200 | { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) }, |
201 | { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) }, |
202 | { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) }, |
203 | { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) }, |
204 | { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) }, |
205 | { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) }, |
206 | { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) }, |
207 | { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) }, |
208 | { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) }, |
209 | { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) }, |
210 | { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, |
211 | }; |
212 | |
213 | /* |
214 | * In SMCA enabled processors, we can have multiple banks for a given IP type. |
215 | * So to define a unique name for each bank, we use a temp c-string to append |
216 | * the MCA_IPID[InstanceId] to type's name in get_name(). |
217 | * |
218 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN |
219 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. |
220 | */ |
221 | #define MAX_MCATYPE_NAME_LEN 30 |
222 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; |
223 | |
224 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
225 | |
226 | /* |
227 | * A list of the banks enabled on each logical CPU. Controls which respective |
228 | * descriptors to initialize later in mce_threshold_create_device(). |
229 | */ |
230 | static DEFINE_PER_CPU(u64, bank_map); |
231 | |
232 | /* Map of banks that have more than MCA_MISC0 available. */ |
233 | static DEFINE_PER_CPU(u64, smca_misc_banks_map); |
234 | |
235 | static void amd_threshold_interrupt(void); |
236 | static void amd_deferred_error_interrupt(void); |
237 | |
238 | static void default_deferred_error_interrupt(void) |
239 | { |
240 | pr_err("Unexpected deferred interrupt at vector %x\n" , DEFERRED_ERROR_VECTOR); |
241 | } |
242 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; |
243 | |
244 | static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) |
245 | { |
246 | u32 low, high; |
247 | |
248 | /* |
249 | * For SMCA enabled processors, BLKPTR field of the first MISC register |
250 | * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). |
251 | */ |
252 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
253 | return; |
254 | |
255 | if (!(low & MCI_CONFIG_MCAX)) |
256 | return; |
257 | |
258 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) |
259 | return; |
260 | |
261 | if (low & MASK_BLKPTR_LO) |
262 | per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); |
263 | |
264 | } |
265 | |
266 | static void smca_configure(unsigned int bank, unsigned int cpu) |
267 | { |
268 | u8 *bank_counts = this_cpu_ptr(smca_bank_counts); |
269 | const struct smca_hwid *s_hwid; |
270 | unsigned int i, hwid_mcatype; |
271 | u32 high, low; |
272 | u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
273 | |
274 | /* Set appropriate bits in MCA_CONFIG */ |
275 | if (!rdmsr_safe(smca_config, &low, &high)) { |
276 | /* |
277 | * OS is required to set the MCAX bit to acknowledge that it is |
278 | * now using the new MSR ranges and new registers under each |
279 | * bank. It also means that the OS will configure deferred |
280 | * errors in the new MCx_CONFIG register. If the bit is not set, |
281 | * uncorrectable errors will cause a system panic. |
282 | * |
283 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) |
284 | */ |
285 | high |= BIT(0); |
286 | |
287 | /* |
288 | * SMCA sets the Deferred Error Interrupt type per bank. |
289 | * |
290 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us |
291 | * if the DeferredIntType bit field is available. |
292 | * |
293 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the |
294 | * high portion of the MSR). OS should set this to 0x1 to enable |
295 | * APIC based interrupt. First, check that no interrupt has been |
296 | * set. |
297 | */ |
298 | if ((low & BIT(5)) && !((high >> 5) & 0x3)) |
299 | high |= BIT(5); |
300 | |
301 | this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); |
302 | |
303 | wrmsr(smca_config, low, high); |
304 | } |
305 | |
306 | smca_set_misc_banks_map(bank, cpu); |
307 | |
308 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { |
309 | pr_warn("Failed to read MCA_IPID for bank %d\n" , bank); |
310 | return; |
311 | } |
312 | |
313 | hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, |
314 | (high & MCI_IPID_MCATYPE) >> 16); |
315 | |
316 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { |
317 | s_hwid = &smca_hwid_mcatypes[i]; |
318 | |
319 | if (hwid_mcatype == s_hwid->hwid_mcatype) { |
320 | this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; |
321 | this_cpu_ptr(smca_banks)[bank].id = low; |
322 | this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; |
323 | break; |
324 | } |
325 | } |
326 | } |
327 | |
328 | struct thresh_restart { |
329 | struct threshold_block *b; |
330 | int reset; |
331 | int set_lvt_off; |
332 | int lvt_off; |
333 | u16 old_limit; |
334 | }; |
335 | |
336 | static inline bool is_shared_bank(int bank) |
337 | { |
338 | /* |
339 | * Scalable MCA provides for only one core to have access to the MSRs of |
340 | * a shared bank. |
341 | */ |
342 | if (mce_flags.smca) |
343 | return false; |
344 | |
345 | /* Bank 4 is for northbridge reporting and is thus shared */ |
346 | return (bank == 4); |
347 | } |
348 | |
349 | static const char *bank4_names(const struct threshold_block *b) |
350 | { |
351 | switch (b->address) { |
352 | /* MSR4_MISC0 */ |
353 | case 0x00000413: |
354 | return "dram" ; |
355 | |
356 | case 0xc0000408: |
357 | return "ht_links" ; |
358 | |
359 | case 0xc0000409: |
360 | return "l3_cache" ; |
361 | |
362 | default: |
363 | WARN(1, "Funny MSR: 0x%08x\n" , b->address); |
364 | return "" ; |
365 | } |
366 | }; |
367 | |
368 | |
369 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
370 | { |
371 | /* |
372 | * bank 4 supports APIC LVT interrupts implicitly since forever. |
373 | */ |
374 | if (bank == 4) |
375 | return true; |
376 | |
377 | /* |
378 | * IntP: interrupt present; if this bit is set, the thresholding |
379 | * bank can generate APIC LVT interrupts |
380 | */ |
381 | return msr_high_bits & BIT(28); |
382 | } |
383 | |
384 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
385 | { |
386 | int msr = (hi & MASK_LVTOFF_HI) >> 20; |
387 | |
388 | if (apic < 0) { |
389 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " |
390 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n" , b->cpu, |
391 | b->bank, b->block, b->address, hi, lo); |
392 | return 0; |
393 | } |
394 | |
395 | if (apic != msr) { |
396 | /* |
397 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and |
398 | * the BIOS provides the value. The original field where LVT offset |
399 | * was set is reserved. Return early here: |
400 | */ |
401 | if (mce_flags.smca) |
402 | return 0; |
403 | |
404 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
405 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n" , |
406 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); |
407 | return 0; |
408 | } |
409 | |
410 | return 1; |
411 | }; |
412 | |
413 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
414 | static void threshold_restart_bank(void *_tr) |
415 | { |
416 | struct thresh_restart *tr = _tr; |
417 | u32 hi, lo; |
418 | |
419 | /* sysfs write might race against an offline operation */ |
420 | if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) |
421 | return; |
422 | |
423 | rdmsr(tr->b->address, lo, hi); |
424 | |
425 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
426 | tr->reset = 1; /* limit cannot be lower than err count */ |
427 | |
428 | if (tr->reset) { /* reset err count and overflow bit */ |
429 | hi = |
430 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | |
431 | (THRESHOLD_MAX - tr->b->threshold_limit); |
432 | } else if (tr->old_limit) { /* change limit w/o reset */ |
433 | int new_count = (hi & THRESHOLD_MAX) + |
434 | (tr->old_limit - tr->b->threshold_limit); |
435 | |
436 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
437 | (new_count & THRESHOLD_MAX); |
438 | } |
439 | |
440 | /* clear IntType */ |
441 | hi &= ~MASK_INT_TYPE_HI; |
442 | |
443 | if (!tr->b->interrupt_capable) |
444 | goto done; |
445 | |
446 | if (tr->set_lvt_off) { |
447 | if (lvt_off_valid(b: tr->b, apic: tr->lvt_off, lo, hi)) { |
448 | /* set new lvt offset */ |
449 | hi &= ~MASK_LVTOFF_HI; |
450 | hi |= tr->lvt_off << 20; |
451 | } |
452 | } |
453 | |
454 | if (tr->b->interrupt_enable) |
455 | hi |= INT_TYPE_APIC; |
456 | |
457 | done: |
458 | |
459 | hi |= MASK_COUNT_EN_HI; |
460 | wrmsr(tr->b->address, lo, hi); |
461 | } |
462 | |
463 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
464 | { |
465 | struct thresh_restart tr = { |
466 | .b = b, |
467 | .set_lvt_off = 1, |
468 | .lvt_off = offset, |
469 | }; |
470 | |
471 | b->threshold_limit = THRESHOLD_MAX; |
472 | threshold_restart_bank(tr: &tr); |
473 | }; |
474 | |
475 | static int setup_APIC_mce_threshold(int reserved, int new) |
476 | { |
477 | if (reserved < 0 && !setup_APIC_eilvt(lvt_off: new, THRESHOLD_APIC_VECTOR, |
478 | APIC_EILVT_MSG_FIX, mask: 0)) |
479 | return new; |
480 | |
481 | return reserved; |
482 | } |
483 | |
484 | static int setup_APIC_deferred_error(int reserved, int new) |
485 | { |
486 | if (reserved < 0 && !setup_APIC_eilvt(lvt_off: new, DEFERRED_ERROR_VECTOR, |
487 | APIC_EILVT_MSG_FIX, mask: 0)) |
488 | return new; |
489 | |
490 | return reserved; |
491 | } |
492 | |
493 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) |
494 | { |
495 | u32 low = 0, high = 0; |
496 | int def_offset = -1, def_new; |
497 | |
498 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) |
499 | return; |
500 | |
501 | def_new = (low & MASK_DEF_LVTOFF) >> 4; |
502 | if (!(low & MASK_DEF_LVTOFF)) { |
503 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n" ); |
504 | def_new = DEF_LVT_OFF; |
505 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); |
506 | } |
507 | |
508 | def_offset = setup_APIC_deferred_error(reserved: def_offset, new: def_new); |
509 | if ((def_offset == def_new) && |
510 | (deferred_error_int_vector != amd_deferred_error_interrupt)) |
511 | deferred_error_int_vector = amd_deferred_error_interrupt; |
512 | |
513 | if (!mce_flags.smca) |
514 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; |
515 | |
516 | wrmsr(MSR_CU_DEF_ERR, low, high); |
517 | } |
518 | |
519 | static u32 smca_get_block_address(unsigned int bank, unsigned int block, |
520 | unsigned int cpu) |
521 | { |
522 | if (!block) |
523 | return MSR_AMD64_SMCA_MCx_MISC(bank); |
524 | |
525 | if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank))) |
526 | return 0; |
527 | |
528 | return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); |
529 | } |
530 | |
531 | static u32 get_block_address(u32 current_addr, u32 low, u32 high, |
532 | unsigned int bank, unsigned int block, |
533 | unsigned int cpu) |
534 | { |
535 | u32 addr = 0, offset = 0; |
536 | |
537 | if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS)) |
538 | return addr; |
539 | |
540 | if (mce_flags.smca) |
541 | return smca_get_block_address(bank, block, cpu); |
542 | |
543 | /* Fall back to method we used for older processors: */ |
544 | switch (block) { |
545 | case 0: |
546 | addr = mca_msr_reg(bank, reg: MCA_MISC); |
547 | break; |
548 | case 1: |
549 | offset = ((low & MASK_BLKPTR_LO) >> 21); |
550 | if (offset) |
551 | addr = MCG_XBLK_ADDR + offset; |
552 | break; |
553 | default: |
554 | addr = ++current_addr; |
555 | } |
556 | return addr; |
557 | } |
558 | |
559 | static int |
560 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, |
561 | int offset, u32 misc_high) |
562 | { |
563 | unsigned int cpu = smp_processor_id(); |
564 | u32 smca_low, smca_high; |
565 | struct threshold_block b; |
566 | int new; |
567 | |
568 | if (!block) |
569 | per_cpu(bank_map, cpu) |= BIT_ULL(bank); |
570 | |
571 | memset(&b, 0, sizeof(b)); |
572 | b.cpu = cpu; |
573 | b.bank = bank; |
574 | b.block = block; |
575 | b.address = addr; |
576 | b.interrupt_capable = lvt_interrupt_supported(bank, msr_high_bits: misc_high); |
577 | |
578 | if (!b.interrupt_capable) |
579 | goto done; |
580 | |
581 | b.interrupt_enable = 1; |
582 | |
583 | if (!mce_flags.smca) { |
584 | new = (misc_high & MASK_LVTOFF_HI) >> 20; |
585 | goto set_offset; |
586 | } |
587 | |
588 | /* Gather LVT offset for thresholding: */ |
589 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) |
590 | goto out; |
591 | |
592 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; |
593 | |
594 | set_offset: |
595 | offset = setup_APIC_mce_threshold(reserved: offset, new); |
596 | if (offset == new) |
597 | thresholding_irq_en = true; |
598 | |
599 | done: |
600 | mce_threshold_block_init(b: &b, offset); |
601 | |
602 | out: |
603 | return offset; |
604 | } |
605 | |
606 | bool amd_filter_mce(struct mce *m) |
607 | { |
608 | enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); |
609 | struct cpuinfo_x86 *c = &boot_cpu_data; |
610 | |
611 | /* See Family 17h Models 10h-2Fh Erratum #1114. */ |
612 | if (c->x86 == 0x17 && |
613 | c->x86_model >= 0x10 && c->x86_model <= 0x2F && |
614 | bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) |
615 | return true; |
616 | |
617 | /* NB GART TLB error reporting is disabled by default. */ |
618 | if (c->x86 < 0x17) { |
619 | if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) |
620 | return true; |
621 | } |
622 | |
623 | return false; |
624 | } |
625 | |
626 | /* |
627 | * Turn off thresholding banks for the following conditions: |
628 | * - MC4_MISC thresholding is not supported on Family 0x15. |
629 | * - Prevent possible spurious interrupts from the IF bank on Family 0x17 |
630 | * Models 0x10-0x2F due to Erratum #1114. |
631 | */ |
632 | static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) |
633 | { |
634 | int i, num_msrs; |
635 | u64 hwcr; |
636 | bool need_toggle; |
637 | u32 msrs[NR_BLOCKS]; |
638 | |
639 | if (c->x86 == 0x15 && bank == 4) { |
640 | msrs[0] = 0x00000413; /* MC4_MISC0 */ |
641 | msrs[1] = 0xc0000408; /* MC4_MISC1 */ |
642 | num_msrs = 2; |
643 | } else if (c->x86 == 0x17 && |
644 | (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { |
645 | |
646 | if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) |
647 | return; |
648 | |
649 | msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank); |
650 | num_msrs = 1; |
651 | } else { |
652 | return; |
653 | } |
654 | |
655 | rdmsrl(MSR_K7_HWCR, hwcr); |
656 | |
657 | /* McStatusWrEn has to be set */ |
658 | need_toggle = !(hwcr & BIT(18)); |
659 | if (need_toggle) |
660 | wrmsrl(MSR_K7_HWCR, val: hwcr | BIT(18)); |
661 | |
662 | /* Clear CntP bit safely */ |
663 | for (i = 0; i < num_msrs; i++) |
664 | msr_clear_bit(msr: msrs[i], bit: 62); |
665 | |
666 | /* restore old settings */ |
667 | if (need_toggle) |
668 | wrmsrl(MSR_K7_HWCR, val: hwcr); |
669 | } |
670 | |
671 | /* cpu init entry point, called from mce.c with preempt off */ |
672 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
673 | { |
674 | unsigned int bank, block, cpu = smp_processor_id(); |
675 | u32 low = 0, high = 0, address = 0; |
676 | int offset = -1; |
677 | |
678 | |
679 | for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { |
680 | if (mce_flags.smca) |
681 | smca_configure(bank, cpu); |
682 | |
683 | disable_err_thresholding(c, bank); |
684 | |
685 | for (block = 0; block < NR_BLOCKS; ++block) { |
686 | address = get_block_address(current_addr: address, low, high, bank, block, cpu); |
687 | if (!address) |
688 | break; |
689 | |
690 | if (rdmsr_safe(address, &low, &high)) |
691 | break; |
692 | |
693 | if (!(high & MASK_VALID_HI)) |
694 | continue; |
695 | |
696 | if (!(high & MASK_CNTP_HI) || |
697 | (high & MASK_LOCKED_HI)) |
698 | continue; |
699 | |
700 | offset = prepare_threshold_block(bank, block, addr: address, offset, misc_high: high); |
701 | } |
702 | } |
703 | |
704 | if (mce_flags.succor) |
705 | deferred_error_interrupt_enable(c); |
706 | } |
707 | |
708 | /* |
709 | * DRAM ECC errors are reported in the Northbridge (bank 4) with |
710 | * Extended Error Code 8. |
711 | */ |
712 | static bool legacy_mce_is_memory_error(struct mce *m) |
713 | { |
714 | return m->bank == 4 && XEC(m->status, 0x1f) == 8; |
715 | } |
716 | |
717 | /* |
718 | * DRAM ECC errors are reported in Unified Memory Controllers with |
719 | * Extended Error Code 0. |
720 | */ |
721 | static bool smca_mce_is_memory_error(struct mce *m) |
722 | { |
723 | enum smca_bank_types bank_type; |
724 | |
725 | if (XEC(m->status, 0x3f)) |
726 | return false; |
727 | |
728 | bank_type = smca_get_bank_type(m->extcpu, m->bank); |
729 | |
730 | return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2; |
731 | } |
732 | |
733 | bool amd_mce_is_memory_error(struct mce *m) |
734 | { |
735 | if (mce_flags.smca) |
736 | return smca_mce_is_memory_error(m); |
737 | else |
738 | return legacy_mce_is_memory_error(m); |
739 | } |
740 | |
741 | /* |
742 | * AMD systems do not have an explicit indicator that the value in MCA_ADDR is |
743 | * a system physical address. Therefore, individual cases need to be detected. |
744 | * Future cases and checks will be added as needed. |
745 | * |
746 | * 1) General case |
747 | * a) Assume address is not usable. |
748 | * 2) Poison errors |
749 | * a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy |
750 | * northbridge (bank 4). |
751 | * b) Refers to poison consumption in the core. Does not include "no action", |
752 | * "action optional", or "deferred" error severities. |
753 | * c) Will include a usable address so that immediate action can be taken. |
754 | * 3) Northbridge DRAM ECC errors |
755 | * a) Reported in legacy bank 4 with extended error code (XEC) 8. |
756 | * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore, |
757 | * this bit should not be checked. |
758 | * |
759 | * NOTE: SMCA UMC memory errors fall into case #1. |
760 | */ |
761 | bool amd_mce_usable_address(struct mce *m) |
762 | { |
763 | /* Check special northbridge case 3) first. */ |
764 | if (!mce_flags.smca) { |
765 | if (legacy_mce_is_memory_error(m)) |
766 | return true; |
767 | else if (m->bank == 4) |
768 | return false; |
769 | } |
770 | |
771 | /* Check poison bit for all other bank types. */ |
772 | if (m->status & MCI_STATUS_POISON) |
773 | return true; |
774 | |
775 | /* Assume address is not usable for all others. */ |
776 | return false; |
777 | } |
778 | |
779 | static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) |
780 | { |
781 | struct mce m; |
782 | |
783 | mce_setup(m: &m); |
784 | |
785 | m.status = status; |
786 | m.misc = misc; |
787 | m.bank = bank; |
788 | m.tsc = rdtsc(); |
789 | |
790 | if (m.status & MCI_STATUS_ADDRV) { |
791 | m.addr = addr; |
792 | |
793 | smca_extract_err_addr(m: &m); |
794 | } |
795 | |
796 | if (mce_flags.smca) { |
797 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); |
798 | |
799 | if (m.status & MCI_STATUS_SYNDV) |
800 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); |
801 | } |
802 | |
803 | mce_log(m: &m); |
804 | } |
805 | |
806 | DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) |
807 | { |
808 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); |
809 | inc_irq_stat(irq_deferred_error_count); |
810 | deferred_error_int_vector(); |
811 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); |
812 | apic_eoi(); |
813 | } |
814 | |
815 | /* |
816 | * Returns true if the logged error is deferred. False, otherwise. |
817 | */ |
818 | static inline bool |
819 | _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) |
820 | { |
821 | u64 status, addr = 0; |
822 | |
823 | rdmsrl(msr_stat, status); |
824 | if (!(status & MCI_STATUS_VAL)) |
825 | return false; |
826 | |
827 | if (status & MCI_STATUS_ADDRV) |
828 | rdmsrl(msr_addr, addr); |
829 | |
830 | __log_error(bank, status, addr, misc); |
831 | |
832 | wrmsrl(msr: msr_stat, val: 0); |
833 | |
834 | return status & MCI_STATUS_DEFERRED; |
835 | } |
836 | |
837 | static bool _log_error_deferred(unsigned int bank, u32 misc) |
838 | { |
839 | if (!_log_error_bank(bank, msr_stat: mca_msr_reg(bank, reg: MCA_STATUS), |
840 | msr_addr: mca_msr_reg(bank, reg: MCA_ADDR), misc)) |
841 | return false; |
842 | |
843 | /* |
844 | * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. |
845 | * Return true here to avoid accessing these registers. |
846 | */ |
847 | if (!mce_flags.smca) |
848 | return true; |
849 | |
850 | /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ |
851 | wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), val: 0); |
852 | return true; |
853 | } |
854 | |
855 | /* |
856 | * We have three scenarios for checking for Deferred errors: |
857 | * |
858 | * 1) Non-SMCA systems check MCA_STATUS and log error if found. |
859 | * 2) SMCA systems check MCA_STATUS. If error is found then log it and also |
860 | * clear MCA_DESTAT. |
861 | * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and |
862 | * log it. |
863 | */ |
864 | static void log_error_deferred(unsigned int bank) |
865 | { |
866 | if (_log_error_deferred(bank, misc: 0)) |
867 | return; |
868 | |
869 | /* |
870 | * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check |
871 | * for a valid error. |
872 | */ |
873 | _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), |
874 | MSR_AMD64_SMCA_MCx_DEADDR(bank), misc: 0); |
875 | } |
876 | |
877 | /* APIC interrupt handler for deferred errors */ |
878 | static void amd_deferred_error_interrupt(void) |
879 | { |
880 | unsigned int bank; |
881 | |
882 | for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) |
883 | log_error_deferred(bank); |
884 | } |
885 | |
886 | static void log_error_thresholding(unsigned int bank, u64 misc) |
887 | { |
888 | _log_error_deferred(bank, misc); |
889 | } |
890 | |
891 | static void log_and_reset_block(struct threshold_block *block) |
892 | { |
893 | struct thresh_restart tr; |
894 | u32 low = 0, high = 0; |
895 | |
896 | if (!block) |
897 | return; |
898 | |
899 | if (rdmsr_safe(block->address, &low, &high)) |
900 | return; |
901 | |
902 | if (!(high & MASK_OVERFLOW_HI)) |
903 | return; |
904 | |
905 | /* Log the MCE which caused the threshold event. */ |
906 | log_error_thresholding(bank: block->bank, misc: ((u64)high << 32) | low); |
907 | |
908 | /* Reset threshold block after logging error. */ |
909 | memset(&tr, 0, sizeof(tr)); |
910 | tr.b = block; |
911 | threshold_restart_bank(tr: &tr); |
912 | } |
913 | |
914 | /* |
915 | * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt |
916 | * goes off when error_count reaches threshold_limit. |
917 | */ |
918 | static void amd_threshold_interrupt(void) |
919 | { |
920 | struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; |
921 | struct threshold_bank **bp = this_cpu_read(threshold_banks); |
922 | unsigned int bank, cpu = smp_processor_id(); |
923 | |
924 | /* |
925 | * Validate that the threshold bank has been initialized already. The |
926 | * handler is installed at boot time, but on a hotplug event the |
927 | * interrupt might fire before the data has been initialized. |
928 | */ |
929 | if (!bp) |
930 | return; |
931 | |
932 | for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { |
933 | if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) |
934 | continue; |
935 | |
936 | first_block = bp[bank]->blocks; |
937 | if (!first_block) |
938 | continue; |
939 | |
940 | /* |
941 | * The first block is also the head of the list. Check it first |
942 | * before iterating over the rest. |
943 | */ |
944 | log_and_reset_block(block: first_block); |
945 | list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) |
946 | log_and_reset_block(block); |
947 | } |
948 | } |
949 | |
950 | /* |
951 | * Sysfs Interface |
952 | */ |
953 | |
954 | struct threshold_attr { |
955 | struct attribute attr; |
956 | ssize_t (*show) (struct threshold_block *, char *); |
957 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); |
958 | }; |
959 | |
960 | #define SHOW_FIELDS(name) \ |
961 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ |
962 | { \ |
963 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
964 | } |
965 | SHOW_FIELDS(interrupt_enable) |
966 | SHOW_FIELDS(threshold_limit) |
967 | |
968 | static ssize_t |
969 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
970 | { |
971 | struct thresh_restart tr; |
972 | unsigned long new; |
973 | |
974 | if (!b->interrupt_capable) |
975 | return -EINVAL; |
976 | |
977 | if (kstrtoul(s: buf, base: 0, res: &new) < 0) |
978 | return -EINVAL; |
979 | |
980 | b->interrupt_enable = !!new; |
981 | |
982 | memset(&tr, 0, sizeof(tr)); |
983 | tr.b = b; |
984 | |
985 | if (smp_call_function_single(cpuid: b->cpu, func: threshold_restart_bank, info: &tr, wait: 1)) |
986 | return -ENODEV; |
987 | |
988 | return size; |
989 | } |
990 | |
991 | static ssize_t |
992 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
993 | { |
994 | struct thresh_restart tr; |
995 | unsigned long new; |
996 | |
997 | if (kstrtoul(s: buf, base: 0, res: &new) < 0) |
998 | return -EINVAL; |
999 | |
1000 | if (new > THRESHOLD_MAX) |
1001 | new = THRESHOLD_MAX; |
1002 | if (new < 1) |
1003 | new = 1; |
1004 | |
1005 | memset(&tr, 0, sizeof(tr)); |
1006 | tr.old_limit = b->threshold_limit; |
1007 | b->threshold_limit = new; |
1008 | tr.b = b; |
1009 | |
1010 | if (smp_call_function_single(cpuid: b->cpu, func: threshold_restart_bank, info: &tr, wait: 1)) |
1011 | return -ENODEV; |
1012 | |
1013 | return size; |
1014 | } |
1015 | |
1016 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
1017 | { |
1018 | u32 lo, hi; |
1019 | |
1020 | /* CPU might be offline by now */ |
1021 | if (rdmsr_on_cpu(cpu: b->cpu, msr_no: b->address, l: &lo, h: &hi)) |
1022 | return -ENODEV; |
1023 | |
1024 | return sprintf(buf, fmt: "%u\n" , ((hi & THRESHOLD_MAX) - |
1025 | (THRESHOLD_MAX - b->threshold_limit))); |
1026 | } |
1027 | |
1028 | static struct threshold_attr error_count = { |
1029 | .attr = {.name = __stringify(error_count), .mode = 0444 }, |
1030 | .show = show_error_count, |
1031 | }; |
1032 | |
1033 | #define RW_ATTR(val) \ |
1034 | static struct threshold_attr val = { \ |
1035 | .attr = {.name = __stringify(val), .mode = 0644 }, \ |
1036 | .show = show_## val, \ |
1037 | .store = store_## val, \ |
1038 | }; |
1039 | |
1040 | RW_ATTR(interrupt_enable); |
1041 | RW_ATTR(threshold_limit); |
1042 | |
1043 | static struct attribute *default_attrs[] = { |
1044 | &threshold_limit.attr, |
1045 | &error_count.attr, |
1046 | NULL, /* possibly interrupt_enable if supported, see below */ |
1047 | NULL, |
1048 | }; |
1049 | ATTRIBUTE_GROUPS(default); |
1050 | |
1051 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
1052 | #define to_attr(a) container_of(a, struct threshold_attr, attr) |
1053 | |
1054 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) |
1055 | { |
1056 | struct threshold_block *b = to_block(kobj); |
1057 | struct threshold_attr *a = to_attr(attr); |
1058 | ssize_t ret; |
1059 | |
1060 | ret = a->show ? a->show(b, buf) : -EIO; |
1061 | |
1062 | return ret; |
1063 | } |
1064 | |
1065 | static ssize_t store(struct kobject *kobj, struct attribute *attr, |
1066 | const char *buf, size_t count) |
1067 | { |
1068 | struct threshold_block *b = to_block(kobj); |
1069 | struct threshold_attr *a = to_attr(attr); |
1070 | ssize_t ret; |
1071 | |
1072 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1073 | |
1074 | return ret; |
1075 | } |
1076 | |
1077 | static const struct sysfs_ops threshold_ops = { |
1078 | .show = show, |
1079 | .store = store, |
1080 | }; |
1081 | |
1082 | static void threshold_block_release(struct kobject *kobj); |
1083 | |
1084 | static const struct kobj_type threshold_ktype = { |
1085 | .sysfs_ops = &threshold_ops, |
1086 | .default_groups = default_groups, |
1087 | .release = threshold_block_release, |
1088 | }; |
1089 | |
1090 | static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b) |
1091 | { |
1092 | enum smca_bank_types bank_type; |
1093 | |
1094 | if (!mce_flags.smca) { |
1095 | if (b && bank == 4) |
1096 | return bank4_names(b); |
1097 | |
1098 | return th_names[bank]; |
1099 | } |
1100 | |
1101 | bank_type = smca_get_bank_type(cpu, bank); |
1102 | if (bank_type >= N_SMCA_BANK_TYPES) |
1103 | return NULL; |
1104 | |
1105 | if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) { |
1106 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) |
1107 | return smca_umc_block_names[b->block]; |
1108 | return NULL; |
1109 | } |
1110 | |
1111 | if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1) |
1112 | return smca_get_name(t: bank_type); |
1113 | |
1114 | snprintf(buf: buf_mcatype, MAX_MCATYPE_NAME_LEN, |
1115 | fmt: "%s_%u" , smca_get_name(t: bank_type), |
1116 | per_cpu(smca_banks, cpu)[bank].sysfs_id); |
1117 | return buf_mcatype; |
1118 | } |
1119 | |
1120 | static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb, |
1121 | unsigned int bank, unsigned int block, |
1122 | u32 address) |
1123 | { |
1124 | struct threshold_block *b = NULL; |
1125 | u32 low, high; |
1126 | int err; |
1127 | |
1128 | if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS)) |
1129 | return 0; |
1130 | |
1131 | if (rdmsr_safe(address, &low, &high)) |
1132 | return 0; |
1133 | |
1134 | if (!(high & MASK_VALID_HI)) { |
1135 | if (block) |
1136 | goto recurse; |
1137 | else |
1138 | return 0; |
1139 | } |
1140 | |
1141 | if (!(high & MASK_CNTP_HI) || |
1142 | (high & MASK_LOCKED_HI)) |
1143 | goto recurse; |
1144 | |
1145 | b = kzalloc(size: sizeof(struct threshold_block), GFP_KERNEL); |
1146 | if (!b) |
1147 | return -ENOMEM; |
1148 | |
1149 | b->block = block; |
1150 | b->bank = bank; |
1151 | b->cpu = cpu; |
1152 | b->address = address; |
1153 | b->interrupt_enable = 0; |
1154 | b->interrupt_capable = lvt_interrupt_supported(bank, msr_high_bits: high); |
1155 | b->threshold_limit = THRESHOLD_MAX; |
1156 | |
1157 | if (b->interrupt_capable) { |
1158 | default_attrs[2] = &interrupt_enable.attr; |
1159 | b->interrupt_enable = 1; |
1160 | } else { |
1161 | default_attrs[2] = NULL; |
1162 | } |
1163 | |
1164 | INIT_LIST_HEAD(list: &b->miscj); |
1165 | |
1166 | /* This is safe as @tb is not visible yet */ |
1167 | if (tb->blocks) |
1168 | list_add(new: &b->miscj, head: &tb->blocks->miscj); |
1169 | else |
1170 | tb->blocks = b; |
1171 | |
1172 | err = kobject_init_and_add(kobj: &b->kobj, ktype: &threshold_ktype, parent: tb->kobj, fmt: get_name(cpu, bank, b)); |
1173 | if (err) |
1174 | goto out_free; |
1175 | recurse: |
1176 | address = get_block_address(current_addr: address, low, high, bank, block: ++block, cpu); |
1177 | if (!address) |
1178 | return 0; |
1179 | |
1180 | err = allocate_threshold_blocks(cpu, tb, bank, block, address); |
1181 | if (err) |
1182 | goto out_free; |
1183 | |
1184 | if (b) |
1185 | kobject_uevent(kobj: &b->kobj, action: KOBJ_ADD); |
1186 | |
1187 | return 0; |
1188 | |
1189 | out_free: |
1190 | if (b) { |
1191 | list_del(entry: &b->miscj); |
1192 | kobject_put(kobj: &b->kobj); |
1193 | } |
1194 | return err; |
1195 | } |
1196 | |
1197 | static int __threshold_add_blocks(struct threshold_bank *b) |
1198 | { |
1199 | struct list_head *head = &b->blocks->miscj; |
1200 | struct threshold_block *pos = NULL; |
1201 | struct threshold_block *tmp = NULL; |
1202 | int err = 0; |
1203 | |
1204 | err = kobject_add(kobj: &b->blocks->kobj, parent: b->kobj, fmt: b->blocks->kobj.name); |
1205 | if (err) |
1206 | return err; |
1207 | |
1208 | list_for_each_entry_safe(pos, tmp, head, miscj) { |
1209 | |
1210 | err = kobject_add(kobj: &pos->kobj, parent: b->kobj, fmt: pos->kobj.name); |
1211 | if (err) { |
1212 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) |
1213 | kobject_del(kobj: &pos->kobj); |
1214 | |
1215 | return err; |
1216 | } |
1217 | } |
1218 | return err; |
1219 | } |
1220 | |
1221 | static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu, |
1222 | unsigned int bank) |
1223 | { |
1224 | struct device *dev = this_cpu_read(mce_device); |
1225 | struct amd_northbridge *nb = NULL; |
1226 | struct threshold_bank *b = NULL; |
1227 | const char *name = get_name(cpu, bank, NULL); |
1228 | int err = 0; |
1229 | |
1230 | if (!dev) |
1231 | return -ENODEV; |
1232 | |
1233 | if (is_shared_bank(bank)) { |
1234 | nb = node_to_amd_nb(topology_amd_node_id(cpu)); |
1235 | |
1236 | /* threshold descriptor already initialized on this node? */ |
1237 | if (nb && nb->bank4) { |
1238 | /* yes, use it */ |
1239 | b = nb->bank4; |
1240 | err = kobject_add(kobj: b->kobj, parent: &dev->kobj, fmt: name); |
1241 | if (err) |
1242 | goto out; |
1243 | |
1244 | bp[bank] = b; |
1245 | refcount_inc(r: &b->cpus); |
1246 | |
1247 | err = __threshold_add_blocks(b); |
1248 | |
1249 | goto out; |
1250 | } |
1251 | } |
1252 | |
1253 | b = kzalloc(size: sizeof(struct threshold_bank), GFP_KERNEL); |
1254 | if (!b) { |
1255 | err = -ENOMEM; |
1256 | goto out; |
1257 | } |
1258 | |
1259 | /* Associate the bank with the per-CPU MCE device */ |
1260 | b->kobj = kobject_create_and_add(name, parent: &dev->kobj); |
1261 | if (!b->kobj) { |
1262 | err = -EINVAL; |
1263 | goto out_free; |
1264 | } |
1265 | |
1266 | if (is_shared_bank(bank)) { |
1267 | b->shared = 1; |
1268 | refcount_set(r: &b->cpus, n: 1); |
1269 | |
1270 | /* nb is already initialized, see above */ |
1271 | if (nb) { |
1272 | WARN_ON(nb->bank4); |
1273 | nb->bank4 = b; |
1274 | } |
1275 | } |
1276 | |
1277 | err = allocate_threshold_blocks(cpu, tb: b, bank, block: 0, address: mca_msr_reg(bank, reg: MCA_MISC)); |
1278 | if (err) |
1279 | goto out_kobj; |
1280 | |
1281 | bp[bank] = b; |
1282 | return 0; |
1283 | |
1284 | out_kobj: |
1285 | kobject_put(kobj: b->kobj); |
1286 | out_free: |
1287 | kfree(objp: b); |
1288 | out: |
1289 | return err; |
1290 | } |
1291 | |
1292 | static void threshold_block_release(struct kobject *kobj) |
1293 | { |
1294 | kfree(to_block(kobj)); |
1295 | } |
1296 | |
1297 | static void deallocate_threshold_blocks(struct threshold_bank *bank) |
1298 | { |
1299 | struct threshold_block *pos, *tmp; |
1300 | |
1301 | list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { |
1302 | list_del(entry: &pos->miscj); |
1303 | kobject_put(kobj: &pos->kobj); |
1304 | } |
1305 | |
1306 | kobject_put(kobj: &bank->blocks->kobj); |
1307 | } |
1308 | |
1309 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1310 | { |
1311 | struct threshold_block *pos = NULL; |
1312 | struct threshold_block *tmp = NULL; |
1313 | |
1314 | kobject_put(kobj: b->kobj); |
1315 | |
1316 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) |
1317 | kobject_put(kobj: b->kobj); |
1318 | } |
1319 | |
1320 | static void threshold_remove_bank(struct threshold_bank *bank) |
1321 | { |
1322 | struct amd_northbridge *nb; |
1323 | |
1324 | if (!bank->blocks) |
1325 | goto out_free; |
1326 | |
1327 | if (!bank->shared) |
1328 | goto out_dealloc; |
1329 | |
1330 | if (!refcount_dec_and_test(r: &bank->cpus)) { |
1331 | __threshold_remove_blocks(b: bank); |
1332 | return; |
1333 | } else { |
1334 | /* |
1335 | * The last CPU on this node using the shared bank is going |
1336 | * away, remove that bank now. |
1337 | */ |
1338 | nb = node_to_amd_nb(topology_amd_node_id(smp_processor_id())); |
1339 | nb->bank4 = NULL; |
1340 | } |
1341 | |
1342 | out_dealloc: |
1343 | deallocate_threshold_blocks(bank); |
1344 | |
1345 | out_free: |
1346 | kobject_put(kobj: bank->kobj); |
1347 | kfree(objp: bank); |
1348 | } |
1349 | |
1350 | static void __threshold_remove_device(struct threshold_bank **bp) |
1351 | { |
1352 | unsigned int bank, numbanks = this_cpu_read(mce_num_banks); |
1353 | |
1354 | for (bank = 0; bank < numbanks; bank++) { |
1355 | if (!bp[bank]) |
1356 | continue; |
1357 | |
1358 | threshold_remove_bank(bank: bp[bank]); |
1359 | bp[bank] = NULL; |
1360 | } |
1361 | kfree(objp: bp); |
1362 | } |
1363 | |
1364 | int mce_threshold_remove_device(unsigned int cpu) |
1365 | { |
1366 | struct threshold_bank **bp = this_cpu_read(threshold_banks); |
1367 | |
1368 | if (!bp) |
1369 | return 0; |
1370 | |
1371 | /* |
1372 | * Clear the pointer before cleaning up, so that the interrupt won't |
1373 | * touch anything of this. |
1374 | */ |
1375 | this_cpu_write(threshold_banks, NULL); |
1376 | |
1377 | __threshold_remove_device(bp); |
1378 | return 0; |
1379 | } |
1380 | |
1381 | /** |
1382 | * mce_threshold_create_device - Create the per-CPU MCE threshold device |
1383 | * @cpu: The plugged in CPU |
1384 | * |
1385 | * Create directories and files for all valid threshold banks. |
1386 | * |
1387 | * This is invoked from the CPU hotplug callback which was installed in |
1388 | * mcheck_init_device(). The invocation happens in context of the hotplug |
1389 | * thread running on @cpu. The callback is invoked on all CPUs which are |
1390 | * online when the callback is installed or during a real hotplug event. |
1391 | */ |
1392 | int mce_threshold_create_device(unsigned int cpu) |
1393 | { |
1394 | unsigned int numbanks, bank; |
1395 | struct threshold_bank **bp; |
1396 | int err; |
1397 | |
1398 | if (!mce_flags.amd_threshold) |
1399 | return 0; |
1400 | |
1401 | bp = this_cpu_read(threshold_banks); |
1402 | if (bp) |
1403 | return 0; |
1404 | |
1405 | numbanks = this_cpu_read(mce_num_banks); |
1406 | bp = kcalloc(n: numbanks, size: sizeof(*bp), GFP_KERNEL); |
1407 | if (!bp) |
1408 | return -ENOMEM; |
1409 | |
1410 | for (bank = 0; bank < numbanks; ++bank) { |
1411 | if (!(this_cpu_read(bank_map) & BIT_ULL(bank))) |
1412 | continue; |
1413 | err = threshold_create_bank(bp, cpu, bank); |
1414 | if (err) { |
1415 | __threshold_remove_device(bp); |
1416 | return err; |
1417 | } |
1418 | } |
1419 | this_cpu_write(threshold_banks, bp); |
1420 | |
1421 | if (thresholding_irq_en) |
1422 | mce_threshold_vector = amd_threshold_interrupt; |
1423 | return 0; |
1424 | } |
1425 | |