1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
4 *
5 * Written by Jacob Shin - AMD, Inc.
6 * Maintained by: Borislav Petkov <bp@alien8.de>
7 */
8#include <linux/interrupt.h>
9#include <linux/notifier.h>
10#include <linux/kobject.h>
11#include <linux/percpu.h>
12#include <linux/errno.h>
13#include <linux/sched.h>
14#include <linux/sysfs.h>
15#include <linux/slab.h>
16#include <linux/init.h>
17#include <linux/cpu.h>
18#include <linux/smp.h>
19#include <linux/string.h>
20
21#include <asm/traps.h>
22#include <asm/apic.h>
23#include <asm/mce.h>
24#include <asm/msr.h>
25#include <asm/trace/irq_vectors.h>
26
27#include "internal.h"
28
29#define NR_BLOCKS 5
30#define THRESHOLD_MAX 0xFFF
31#define INT_TYPE_APIC 0x00020000
32#define MASK_VALID_HI 0x80000000
33#define MASK_CNTP_HI 0x40000000
34#define MASK_LOCKED_HI 0x20000000
35#define MASK_LVTOFF_HI 0x00F00000
36#define MASK_COUNT_EN_HI 0x00080000
37#define MASK_INT_TYPE_HI 0x00060000
38#define MASK_OVERFLOW_HI 0x00010000
39#define MASK_ERR_COUNT_HI 0x00000FFF
40#define MASK_BLKPTR_LO 0xFF000000
41#define MCG_XBLK_ADDR 0xC0000400
42
43/* Deferred error settings */
44#define MSR_CU_DEF_ERR 0xC0000410
45#define MASK_DEF_LVTOFF 0x000000F0
46#define MASK_DEF_INT_TYPE 0x00000006
47#define DEF_LVT_OFF 0x2
48#define DEF_INT_TYPE_APIC 0x2
49
50/* Scalable MCA: */
51
52/* Threshold LVT offset is at MSR0xC0000410[15:12] */
53#define SMCA_THR_LVT_OFF 0xF000
54
55static bool thresholding_irq_en;
56
57static const char * const th_names[] = {
58 "load_store",
59 "insn_fetch",
60 "combined_unit",
61 "decode_unit",
62 "northbridge",
63 "execution_unit",
64};
65
66static const char * const smca_umc_block_names[] = {
67 "dram_ecc",
68 "misc_umc"
69};
70
71#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
72
73struct smca_hwid {
74 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
75 u32 hwid_mcatype; /* (hwid,mcatype) tuple */
76};
77
78struct smca_bank {
79 const struct smca_hwid *hwid;
80 u32 id; /* Value of MCA_IPID[InstanceId]. */
81 u8 sysfs_id; /* Value used for sysfs name. */
82};
83
84static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
85static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
86
87static const char * const smca_names[] = {
88 [SMCA_LS ... SMCA_LS_V2] = "load_store",
89 [SMCA_IF] = "insn_fetch",
90 [SMCA_L2_CACHE] = "l2_cache",
91 [SMCA_DE] = "decode_unit",
92 [SMCA_RESERVED] = "reserved",
93 [SMCA_EX] = "execution_unit",
94 [SMCA_FP] = "floating_point",
95 [SMCA_L3_CACHE] = "l3_cache",
96 [SMCA_CS ... SMCA_CS_V2] = "coherent_slave",
97 [SMCA_PIE] = "pie",
98
99 /* UMC v2 is separate because both of them can exist in a single system. */
100 [SMCA_UMC] = "umc",
101 [SMCA_UMC_V2] = "umc_v2",
102 [SMCA_MA_LLC] = "ma_llc",
103 [SMCA_PB] = "param_block",
104 [SMCA_PSP ... SMCA_PSP_V2] = "psp",
105 [SMCA_SMU ... SMCA_SMU_V2] = "smu",
106 [SMCA_MP5] = "mp5",
107 [SMCA_MPDMA] = "mpdma",
108 [SMCA_NBIO] = "nbio",
109 [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
110 [SMCA_XGMI_PCS] = "xgmi_pcs",
111 [SMCA_NBIF] = "nbif",
112 [SMCA_SHUB] = "shub",
113 [SMCA_SATA] = "sata",
114 [SMCA_USB] = "usb",
115 [SMCA_USR_DP] = "usr_dp",
116 [SMCA_USR_CP] = "usr_cp",
117 [SMCA_GMI_PCS] = "gmi_pcs",
118 [SMCA_XGMI_PHY] = "xgmi_phy",
119 [SMCA_WAFL_PHY] = "wafl_phy",
120 [SMCA_GMI_PHY] = "gmi_phy",
121};
122
123static const char *smca_get_name(enum smca_bank_types t)
124{
125 if (t >= N_SMCA_BANK_TYPES)
126 return NULL;
127
128 return smca_names[t];
129}
130
131enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
132{
133 struct smca_bank *b;
134
135 if (bank >= MAX_NR_BANKS)
136 return N_SMCA_BANK_TYPES;
137
138 b = &per_cpu(smca_banks, cpu)[bank];
139 if (!b->hwid)
140 return N_SMCA_BANK_TYPES;
141
142 return b->hwid->bank_type;
143}
144EXPORT_SYMBOL_GPL(smca_get_bank_type);
145
146static const struct smca_hwid smca_hwid_mcatypes[] = {
147 /* { bank_type, hwid_mcatype } */
148
149 /* Reserved type */
150 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
151
152 /* ZN Core (HWID=0xB0) MCA types */
153 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
154 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
155 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
156 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
157 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) },
158 /* HWID 0xB0 MCATYPE 0x4 is Reserved */
159 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) },
160 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) },
161 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) },
162
163 /* Data Fabric MCA types */
164 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
165 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
166 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
167 { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) },
168
169 /* Unified Memory Controller MCA type */
170 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
171 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
172
173 /* Parameter Block MCA type */
174 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
175
176 /* Platform Security Processor MCA type */
177 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
178 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
179
180 /* System Management Unit MCA type */
181 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
182 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
183
184 /* Microprocessor 5 Unit MCA type */
185 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) },
186
187 /* MPDMA MCA type */
188 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) },
189
190 /* Northbridge IO Unit MCA type */
191 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) },
192
193 /* PCI Express Unit MCA type */
194 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) },
195 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) },
196
197 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
198 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
199 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
200 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) },
201 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) },
202 { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) },
203 { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) },
204 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
205 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
206 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) },
207 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
208};
209
210/*
211 * In SMCA enabled processors, we can have multiple banks for a given IP type.
212 * So to define a unique name for each bank, we use a temp c-string to append
213 * the MCA_IPID[InstanceId] to type's name in get_name().
214 *
215 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
216 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
217 */
218#define MAX_MCATYPE_NAME_LEN 30
219static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
220
221struct threshold_block {
222 /* This block's number within its bank. */
223 unsigned int block;
224 /* MCA bank number that contains this block. */
225 unsigned int bank;
226 /* CPU which controls this block's MCA bank. */
227 unsigned int cpu;
228 /* MCA_MISC MSR address for this block. */
229 u32 address;
230 /* Enable/Disable APIC interrupt. */
231 bool interrupt_enable;
232 /* Bank can generate an interrupt. */
233 bool interrupt_capable;
234 /* Value upon which threshold interrupt is generated. */
235 u16 threshold_limit;
236 /* sysfs object */
237 struct kobject kobj;
238 /* List of threshold blocks within this block's MCA bank. */
239 struct list_head miscj;
240};
241
242struct threshold_bank {
243 struct kobject *kobj;
244 struct threshold_block *blocks;
245};
246
247static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
248
249/*
250 * A list of the banks enabled on each logical CPU. Controls which respective
251 * descriptors to initialize later in mce_threshold_create_device().
252 */
253static DEFINE_PER_CPU(u64, bank_map);
254
255/* Map of banks that have more than MCA_MISC0 available. */
256static DEFINE_PER_CPU(u64, smca_misc_banks_map);
257
258static void amd_threshold_interrupt(void);
259static void amd_deferred_error_interrupt(void);
260
261static void default_deferred_error_interrupt(void)
262{
263 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
264}
265void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
266
267static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
268{
269 u32 low, high;
270
271 /*
272 * For SMCA enabled processors, BLKPTR field of the first MISC register
273 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
274 */
275 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
276 return;
277
278 if (!(low & MCI_CONFIG_MCAX))
279 return;
280
281 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))
282 return;
283
284 if (low & MASK_BLKPTR_LO)
285 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank);
286
287}
288
289static void smca_configure(unsigned int bank, unsigned int cpu)
290{
291 u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
292 const struct smca_hwid *s_hwid;
293 unsigned int i, hwid_mcatype;
294 u32 high, low;
295 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
296
297 /* Set appropriate bits in MCA_CONFIG */
298 if (!rdmsr_safe(smca_config, &low, &high)) {
299 /*
300 * OS is required to set the MCAX bit to acknowledge that it is
301 * now using the new MSR ranges and new registers under each
302 * bank. It also means that the OS will configure deferred
303 * errors in the new MCx_CONFIG register. If the bit is not set,
304 * uncorrectable errors will cause a system panic.
305 *
306 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
307 */
308 high |= BIT(0);
309
310 /*
311 * SMCA sets the Deferred Error Interrupt type per bank.
312 *
313 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
314 * if the DeferredIntType bit field is available.
315 *
316 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
317 * high portion of the MSR). OS should set this to 0x1 to enable
318 * APIC based interrupt. First, check that no interrupt has been
319 * set.
320 */
321 if ((low & BIT(5)) && !((high >> 5) & 0x3))
322 high |= BIT(5);
323
324 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
325
326 wrmsr(msr: smca_config, low, high);
327 }
328
329 smca_set_misc_banks_map(bank, cpu);
330
331 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
332 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
333 return;
334 }
335
336 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
337 (high & MCI_IPID_MCATYPE) >> 16);
338
339 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
340 s_hwid = &smca_hwid_mcatypes[i];
341
342 if (hwid_mcatype == s_hwid->hwid_mcatype) {
343 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
344 this_cpu_ptr(smca_banks)[bank].id = low;
345 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
346 break;
347 }
348 }
349}
350
351struct thresh_restart {
352 struct threshold_block *b;
353 int reset;
354 int set_lvt_off;
355 int lvt_off;
356 u16 old_limit;
357};
358
359static const char *bank4_names(const struct threshold_block *b)
360{
361 switch (b->address) {
362 /* MSR4_MISC0 */
363 case 0x00000413:
364 return "dram";
365
366 case 0xc0000408:
367 return "ht_links";
368
369 case 0xc0000409:
370 return "l3_cache";
371
372 default:
373 WARN(1, "Funny MSR: 0x%08x\n", b->address);
374 return "";
375 }
376};
377
378
379static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
380{
381 /*
382 * bank 4 supports APIC LVT interrupts implicitly since forever.
383 */
384 if (bank == 4)
385 return true;
386
387 /*
388 * IntP: interrupt present; if this bit is set, the thresholding
389 * bank can generate APIC LVT interrupts
390 */
391 return msr_high_bits & BIT(28);
392}
393
394static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
395{
396 int msr = (hi & MASK_LVTOFF_HI) >> 20;
397
398 if (apic < 0) {
399 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
400 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
401 b->bank, b->block, b->address, hi, lo);
402 return false;
403 }
404
405 if (apic != msr) {
406 /*
407 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
408 * the BIOS provides the value. The original field where LVT offset
409 * was set is reserved. Return early here:
410 */
411 if (mce_flags.smca)
412 return false;
413
414 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
415 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
416 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
417 return false;
418 }
419
420 return true;
421};
422
423/* Reprogram MCx_MISC MSR behind this threshold bank. */
424static void threshold_restart_bank(void *_tr)
425{
426 struct thresh_restart *tr = _tr;
427 u32 hi, lo;
428
429 /* sysfs write might race against an offline operation */
430 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
431 return;
432
433 rdmsr(tr->b->address, lo, hi);
434
435 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
436 tr->reset = 1; /* limit cannot be lower than err count */
437
438 if (tr->reset) { /* reset err count and overflow bit */
439 hi =
440 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
441 (THRESHOLD_MAX - tr->b->threshold_limit);
442 } else if (tr->old_limit) { /* change limit w/o reset */
443 int new_count = (hi & THRESHOLD_MAX) +
444 (tr->old_limit - tr->b->threshold_limit);
445
446 hi = (hi & ~MASK_ERR_COUNT_HI) |
447 (new_count & THRESHOLD_MAX);
448 }
449
450 /* clear IntType */
451 hi &= ~MASK_INT_TYPE_HI;
452
453 if (!tr->b->interrupt_capable)
454 goto done;
455
456 if (tr->set_lvt_off) {
457 if (lvt_off_valid(b: tr->b, apic: tr->lvt_off, lo, hi)) {
458 /* set new lvt offset */
459 hi &= ~MASK_LVTOFF_HI;
460 hi |= tr->lvt_off << 20;
461 }
462 }
463
464 if (tr->b->interrupt_enable)
465 hi |= INT_TYPE_APIC;
466
467 done:
468
469 hi |= MASK_COUNT_EN_HI;
470 wrmsr(msr: tr->b->address, low: lo, high: hi);
471}
472
473static void mce_threshold_block_init(struct threshold_block *b, int offset)
474{
475 struct thresh_restart tr = {
476 .b = b,
477 .set_lvt_off = 1,
478 .lvt_off = offset,
479 };
480
481 b->threshold_limit = THRESHOLD_MAX;
482 threshold_restart_bank(tr: &tr);
483};
484
485static int setup_APIC_mce_threshold(int reserved, int new)
486{
487 if (reserved < 0 && !setup_APIC_eilvt(lvt_off: new, THRESHOLD_APIC_VECTOR,
488 APIC_EILVT_MSG_FIX, mask: 0))
489 return new;
490
491 return reserved;
492}
493
494static int setup_APIC_deferred_error(int reserved, int new)
495{
496 if (reserved < 0 && !setup_APIC_eilvt(lvt_off: new, DEFERRED_ERROR_VECTOR,
497 APIC_EILVT_MSG_FIX, mask: 0))
498 return new;
499
500 return reserved;
501}
502
503static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
504{
505 u32 low = 0, high = 0;
506 int def_offset = -1, def_new;
507
508 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
509 return;
510
511 def_new = (low & MASK_DEF_LVTOFF) >> 4;
512 if (!(low & MASK_DEF_LVTOFF)) {
513 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
514 def_new = DEF_LVT_OFF;
515 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
516 }
517
518 def_offset = setup_APIC_deferred_error(reserved: def_offset, new: def_new);
519 if ((def_offset == def_new) &&
520 (deferred_error_int_vector != amd_deferred_error_interrupt))
521 deferred_error_int_vector = amd_deferred_error_interrupt;
522
523 if (!mce_flags.smca)
524 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
525
526 wrmsr(MSR_CU_DEF_ERR, low, high);
527}
528
529static u32 smca_get_block_address(unsigned int bank, unsigned int block,
530 unsigned int cpu)
531{
532 if (!block)
533 return MSR_AMD64_SMCA_MCx_MISC(bank);
534
535 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank)))
536 return 0;
537
538 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
539}
540
541static u32 get_block_address(u32 current_addr, u32 low, u32 high,
542 unsigned int bank, unsigned int block,
543 unsigned int cpu)
544{
545 u32 addr = 0, offset = 0;
546
547 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
548 return addr;
549
550 if (mce_flags.smca)
551 return smca_get_block_address(bank, block, cpu);
552
553 /* Fall back to method we used for older processors: */
554 switch (block) {
555 case 0:
556 addr = mca_msr_reg(bank, reg: MCA_MISC);
557 break;
558 case 1:
559 offset = ((low & MASK_BLKPTR_LO) >> 21);
560 if (offset)
561 addr = MCG_XBLK_ADDR + offset;
562 break;
563 default:
564 addr = ++current_addr;
565 }
566 return addr;
567}
568
569static int
570prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
571 int offset, u32 misc_high)
572{
573 unsigned int cpu = smp_processor_id();
574 u32 smca_low, smca_high;
575 struct threshold_block b;
576 int new;
577
578 if (!block)
579 per_cpu(bank_map, cpu) |= BIT_ULL(bank);
580
581 memset(&b, 0, sizeof(b));
582 b.cpu = cpu;
583 b.bank = bank;
584 b.block = block;
585 b.address = addr;
586 b.interrupt_capable = lvt_interrupt_supported(bank, msr_high_bits: misc_high);
587
588 if (!b.interrupt_capable)
589 goto done;
590
591 b.interrupt_enable = 1;
592
593 if (!mce_flags.smca) {
594 new = (misc_high & MASK_LVTOFF_HI) >> 20;
595 goto set_offset;
596 }
597
598 /* Gather LVT offset for thresholding: */
599 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
600 goto out;
601
602 new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
603
604set_offset:
605 offset = setup_APIC_mce_threshold(reserved: offset, new);
606 if (offset == new)
607 thresholding_irq_en = true;
608
609done:
610 mce_threshold_block_init(b: &b, offset);
611
612out:
613 return offset;
614}
615
616bool amd_filter_mce(struct mce *m)
617{
618 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
619 struct cpuinfo_x86 *c = &boot_cpu_data;
620
621 /* See Family 17h Models 10h-2Fh Erratum #1114. */
622 if (c->x86 == 0x17 &&
623 c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
624 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
625 return true;
626
627 /* NB GART TLB error reporting is disabled by default. */
628 if (c->x86 < 0x17) {
629 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
630 return true;
631 }
632
633 return false;
634}
635
636/*
637 * Turn off thresholding banks for the following conditions:
638 * - MC4_MISC thresholding is not supported on Family 0x15.
639 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
640 * Models 0x10-0x2F due to Erratum #1114.
641 */
642static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
643{
644 int i, num_msrs;
645 u64 hwcr;
646 bool need_toggle;
647 u32 msrs[NR_BLOCKS];
648
649 if (c->x86 == 0x15 && bank == 4) {
650 msrs[0] = 0x00000413; /* MC4_MISC0 */
651 msrs[1] = 0xc0000408; /* MC4_MISC1 */
652 num_msrs = 2;
653 } else if (c->x86 == 0x17 &&
654 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
655
656 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)
657 return;
658
659 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
660 num_msrs = 1;
661 } else {
662 return;
663 }
664
665 rdmsrq(MSR_K7_HWCR, hwcr);
666
667 /* McStatusWrEn has to be set */
668 need_toggle = !(hwcr & BIT(18));
669 if (need_toggle)
670 wrmsrq(MSR_K7_HWCR, val: hwcr | BIT(18));
671
672 /* Clear CntP bit safely */
673 for (i = 0; i < num_msrs; i++)
674 msr_clear_bit(msr: msrs[i], bit: 62);
675
676 /* restore old settings */
677 if (need_toggle)
678 wrmsrq(MSR_K7_HWCR, val: hwcr);
679}
680
681/* cpu init entry point, called from mce.c with preempt off */
682void mce_amd_feature_init(struct cpuinfo_x86 *c)
683{
684 unsigned int bank, block, cpu = smp_processor_id();
685 u32 low = 0, high = 0, address = 0;
686 int offset = -1;
687
688
689 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
690 if (mce_flags.smca)
691 smca_configure(bank, cpu);
692
693 disable_err_thresholding(c, bank);
694
695 for (block = 0; block < NR_BLOCKS; ++block) {
696 address = get_block_address(current_addr: address, low, high, bank, block, cpu);
697 if (!address)
698 break;
699
700 if (rdmsr_safe(address, &low, &high))
701 break;
702
703 if (!(high & MASK_VALID_HI))
704 continue;
705
706 if (!(high & MASK_CNTP_HI) ||
707 (high & MASK_LOCKED_HI))
708 continue;
709
710 offset = prepare_threshold_block(bank, block, addr: address, offset, misc_high: high);
711 }
712 }
713
714 if (mce_flags.succor)
715 deferred_error_interrupt_enable(c);
716}
717
718/*
719 * DRAM ECC errors are reported in the Northbridge (bank 4) with
720 * Extended Error Code 8.
721 */
722static bool legacy_mce_is_memory_error(struct mce *m)
723{
724 return m->bank == 4 && XEC(m->status, 0x1f) == 8;
725}
726
727/*
728 * DRAM ECC errors are reported in Unified Memory Controllers with
729 * Extended Error Code 0.
730 */
731static bool smca_mce_is_memory_error(struct mce *m)
732{
733 enum smca_bank_types bank_type;
734
735 if (XEC(m->status, 0x3f))
736 return false;
737
738 bank_type = smca_get_bank_type(m->extcpu, m->bank);
739
740 return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2;
741}
742
743bool amd_mce_is_memory_error(struct mce *m)
744{
745 if (mce_flags.smca)
746 return smca_mce_is_memory_error(m);
747 else
748 return legacy_mce_is_memory_error(m);
749}
750
751/*
752 * AMD systems do not have an explicit indicator that the value in MCA_ADDR is
753 * a system physical address. Therefore, individual cases need to be detected.
754 * Future cases and checks will be added as needed.
755 *
756 * 1) General case
757 * a) Assume address is not usable.
758 * 2) Poison errors
759 * a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy
760 * northbridge (bank 4).
761 * b) Refers to poison consumption in the core. Does not include "no action",
762 * "action optional", or "deferred" error severities.
763 * c) Will include a usable address so that immediate action can be taken.
764 * 3) Northbridge DRAM ECC errors
765 * a) Reported in legacy bank 4 with extended error code (XEC) 8.
766 * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
767 * this bit should not be checked.
768 *
769 * NOTE: SMCA UMC memory errors fall into case #1.
770 */
771bool amd_mce_usable_address(struct mce *m)
772{
773 /* Check special northbridge case 3) first. */
774 if (!mce_flags.smca) {
775 if (legacy_mce_is_memory_error(m))
776 return true;
777 else if (m->bank == 4)
778 return false;
779 }
780
781 /* Check poison bit for all other bank types. */
782 if (m->status & MCI_STATUS_POISON)
783 return true;
784
785 /* Assume address is not usable for all others. */
786 return false;
787}
788
789static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
790{
791 struct mce_hw_err err;
792 struct mce *m = &err.m;
793
794 mce_prep_record(err: &err);
795
796 m->status = status;
797 m->misc = misc;
798 m->bank = bank;
799 m->tsc = rdtsc();
800
801 if (m->status & MCI_STATUS_ADDRV) {
802 m->addr = addr;
803
804 smca_extract_err_addr(m);
805 }
806
807 if (mce_flags.smca) {
808 rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid);
809
810 if (m->status & MCI_STATUS_SYNDV) {
811 rdmsrq(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd);
812 rdmsrq(MSR_AMD64_SMCA_MCx_SYND1(bank), err.vendor.amd.synd1);
813 rdmsrq(MSR_AMD64_SMCA_MCx_SYND2(bank), err.vendor.amd.synd2);
814 }
815 }
816
817 mce_log(err: &err);
818}
819
820DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)
821{
822 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
823 inc_irq_stat(irq_deferred_error_count);
824 deferred_error_int_vector();
825 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
826 apic_eoi();
827}
828
829/*
830 * Returns true if the logged error is deferred. False, otherwise.
831 */
832static inline bool
833_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
834{
835 u64 status, addr = 0;
836
837 rdmsrq(msr_stat, status);
838 if (!(status & MCI_STATUS_VAL))
839 return false;
840
841 if (status & MCI_STATUS_ADDRV)
842 rdmsrq(msr_addr, addr);
843
844 __log_error(bank, status, addr, misc);
845
846 wrmsrq(msr: msr_stat, val: 0);
847
848 return status & MCI_STATUS_DEFERRED;
849}
850
851static bool _log_error_deferred(unsigned int bank, u32 misc)
852{
853 if (!_log_error_bank(bank, msr_stat: mca_msr_reg(bank, reg: MCA_STATUS),
854 msr_addr: mca_msr_reg(bank, reg: MCA_ADDR), misc))
855 return false;
856
857 /*
858 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers.
859 * Return true here to avoid accessing these registers.
860 */
861 if (!mce_flags.smca)
862 return true;
863
864 /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */
865 wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(bank), val: 0);
866 return true;
867}
868
869/*
870 * We have three scenarios for checking for Deferred errors:
871 *
872 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
873 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
874 * clear MCA_DESTAT.
875 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
876 * log it.
877 */
878static void log_error_deferred(unsigned int bank)
879{
880 if (_log_error_deferred(bank, misc: 0))
881 return;
882
883 /*
884 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
885 * for a valid error.
886 */
887 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
888 MSR_AMD64_SMCA_MCx_DEADDR(bank), misc: 0);
889}
890
891/* APIC interrupt handler for deferred errors */
892static void amd_deferred_error_interrupt(void)
893{
894 unsigned int bank;
895
896 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)
897 log_error_deferred(bank);
898}
899
900static void log_error_thresholding(unsigned int bank, u64 misc)
901{
902 _log_error_deferred(bank, misc);
903}
904
905static void log_and_reset_block(struct threshold_block *block)
906{
907 struct thresh_restart tr;
908 u32 low = 0, high = 0;
909
910 if (!block)
911 return;
912
913 if (rdmsr_safe(block->address, &low, &high))
914 return;
915
916 if (!(high & MASK_OVERFLOW_HI))
917 return;
918
919 /* Log the MCE which caused the threshold event. */
920 log_error_thresholding(bank: block->bank, misc: ((u64)high << 32) | low);
921
922 /* Reset threshold block after logging error. */
923 memset(&tr, 0, sizeof(tr));
924 tr.b = block;
925 threshold_restart_bank(tr: &tr);
926}
927
928/*
929 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
930 * goes off when error_count reaches threshold_limit.
931 */
932static void amd_threshold_interrupt(void)
933{
934 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
935 struct threshold_bank **bp = this_cpu_read(threshold_banks);
936 unsigned int bank, cpu = smp_processor_id();
937
938 /*
939 * Validate that the threshold bank has been initialized already. The
940 * handler is installed at boot time, but on a hotplug event the
941 * interrupt might fire before the data has been initialized.
942 */
943 if (!bp)
944 return;
945
946 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
947 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank)))
948 continue;
949
950 first_block = bp[bank]->blocks;
951 if (!first_block)
952 continue;
953
954 /*
955 * The first block is also the head of the list. Check it first
956 * before iterating over the rest.
957 */
958 log_and_reset_block(block: first_block);
959 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
960 log_and_reset_block(block);
961 }
962}
963
964/*
965 * Sysfs Interface
966 */
967
968struct threshold_attr {
969 struct attribute attr;
970 ssize_t (*show) (struct threshold_block *, char *);
971 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
972};
973
974#define SHOW_FIELDS(name) \
975static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
976{ \
977 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
978}
979SHOW_FIELDS(interrupt_enable)
980SHOW_FIELDS(threshold_limit)
981
982static ssize_t
983store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
984{
985 struct thresh_restart tr;
986 unsigned long new;
987
988 if (!b->interrupt_capable)
989 return -EINVAL;
990
991 if (kstrtoul(s: buf, base: 0, res: &new) < 0)
992 return -EINVAL;
993
994 b->interrupt_enable = !!new;
995
996 memset(&tr, 0, sizeof(tr));
997 tr.b = b;
998
999 if (smp_call_function_single(cpuid: b->cpu, func: threshold_restart_bank, info: &tr, wait: 1))
1000 return -ENODEV;
1001
1002 return size;
1003}
1004
1005static ssize_t
1006store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
1007{
1008 struct thresh_restart tr;
1009 unsigned long new;
1010
1011 if (kstrtoul(s: buf, base: 0, res: &new) < 0)
1012 return -EINVAL;
1013
1014 if (new > THRESHOLD_MAX)
1015 new = THRESHOLD_MAX;
1016 if (new < 1)
1017 new = 1;
1018
1019 memset(&tr, 0, sizeof(tr));
1020 tr.old_limit = b->threshold_limit;
1021 b->threshold_limit = new;
1022 tr.b = b;
1023
1024 if (smp_call_function_single(cpuid: b->cpu, func: threshold_restart_bank, info: &tr, wait: 1))
1025 return -ENODEV;
1026
1027 return size;
1028}
1029
1030static ssize_t show_error_count(struct threshold_block *b, char *buf)
1031{
1032 u32 lo, hi;
1033
1034 /* CPU might be offline by now */
1035 if (rdmsr_on_cpu(cpu: b->cpu, msr_no: b->address, l: &lo, h: &hi))
1036 return -ENODEV;
1037
1038 return sprintf(buf, fmt: "%u\n", ((hi & THRESHOLD_MAX) -
1039 (THRESHOLD_MAX - b->threshold_limit)));
1040}
1041
1042static struct threshold_attr error_count = {
1043 .attr = {.name = __stringify(error_count), .mode = 0444 },
1044 .show = show_error_count,
1045};
1046
1047#define RW_ATTR(val) \
1048static struct threshold_attr val = { \
1049 .attr = {.name = __stringify(val), .mode = 0644 }, \
1050 .show = show_## val, \
1051 .store = store_## val, \
1052};
1053
1054RW_ATTR(interrupt_enable);
1055RW_ATTR(threshold_limit);
1056
1057static struct attribute *default_attrs[] = {
1058 &threshold_limit.attr,
1059 &error_count.attr,
1060 NULL, /* possibly interrupt_enable if supported, see below */
1061 NULL,
1062};
1063ATTRIBUTE_GROUPS(default);
1064
1065#define to_block(k) container_of(k, struct threshold_block, kobj)
1066#define to_attr(a) container_of(a, struct threshold_attr, attr)
1067
1068static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1069{
1070 struct threshold_block *b = to_block(kobj);
1071 struct threshold_attr *a = to_attr(attr);
1072 ssize_t ret;
1073
1074 ret = a->show ? a->show(b, buf) : -EIO;
1075
1076 return ret;
1077}
1078
1079static ssize_t store(struct kobject *kobj, struct attribute *attr,
1080 const char *buf, size_t count)
1081{
1082 struct threshold_block *b = to_block(kobj);
1083 struct threshold_attr *a = to_attr(attr);
1084 ssize_t ret;
1085
1086 ret = a->store ? a->store(b, buf, count) : -EIO;
1087
1088 return ret;
1089}
1090
1091static const struct sysfs_ops threshold_ops = {
1092 .show = show,
1093 .store = store,
1094};
1095
1096static void threshold_block_release(struct kobject *kobj);
1097
1098static const struct kobj_type threshold_ktype = {
1099 .sysfs_ops = &threshold_ops,
1100 .default_groups = default_groups,
1101 .release = threshold_block_release,
1102};
1103
1104static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)
1105{
1106 enum smca_bank_types bank_type;
1107
1108 if (!mce_flags.smca) {
1109 if (b && bank == 4)
1110 return bank4_names(b);
1111
1112 return th_names[bank];
1113 }
1114
1115 bank_type = smca_get_bank_type(cpu, bank);
1116 if (bank_type >= N_SMCA_BANK_TYPES)
1117 return NULL;
1118
1119 if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) {
1120 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1121 return smca_umc_block_names[b->block];
1122 return NULL;
1123 }
1124
1125 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1)
1126 return smca_get_name(t: bank_type);
1127
1128 snprintf(buf: buf_mcatype, MAX_MCATYPE_NAME_LEN,
1129 fmt: "%s_%u", smca_get_name(t: bank_type),
1130 per_cpu(smca_banks, cpu)[bank].sysfs_id);
1131 return buf_mcatype;
1132}
1133
1134static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1135 unsigned int bank, unsigned int block,
1136 u32 address)
1137{
1138 struct threshold_block *b = NULL;
1139 u32 low, high;
1140 int err;
1141
1142 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
1143 return 0;
1144
1145 if (rdmsr_safe(address, &low, &high))
1146 return 0;
1147
1148 if (!(high & MASK_VALID_HI)) {
1149 if (block)
1150 goto recurse;
1151 else
1152 return 0;
1153 }
1154
1155 if (!(high & MASK_CNTP_HI) ||
1156 (high & MASK_LOCKED_HI))
1157 goto recurse;
1158
1159 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1160 if (!b)
1161 return -ENOMEM;
1162
1163 b->block = block;
1164 b->bank = bank;
1165 b->cpu = cpu;
1166 b->address = address;
1167 b->interrupt_enable = 0;
1168 b->interrupt_capable = lvt_interrupt_supported(bank, msr_high_bits: high);
1169 b->threshold_limit = THRESHOLD_MAX;
1170
1171 if (b->interrupt_capable) {
1172 default_attrs[2] = &interrupt_enable.attr;
1173 b->interrupt_enable = 1;
1174 } else {
1175 default_attrs[2] = NULL;
1176 }
1177
1178 INIT_LIST_HEAD(list: &b->miscj);
1179
1180 /* This is safe as @tb is not visible yet */
1181 if (tb->blocks)
1182 list_add(new: &b->miscj, head: &tb->blocks->miscj);
1183 else
1184 tb->blocks = b;
1185
1186 err = kobject_init_and_add(kobj: &b->kobj, ktype: &threshold_ktype, parent: tb->kobj, fmt: get_name(cpu, bank, b));
1187 if (err)
1188 goto out_free;
1189recurse:
1190 address = get_block_address(current_addr: address, low, high, bank, block: ++block, cpu);
1191 if (!address)
1192 return 0;
1193
1194 err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1195 if (err)
1196 goto out_free;
1197
1198 if (b)
1199 kobject_uevent(kobj: &b->kobj, action: KOBJ_ADD);
1200
1201 return 0;
1202
1203out_free:
1204 if (b) {
1205 list_del(entry: &b->miscj);
1206 kobject_put(kobj: &b->kobj);
1207 }
1208 return err;
1209}
1210
1211static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
1212 unsigned int bank)
1213{
1214 struct device *dev = this_cpu_read(mce_device);
1215 struct threshold_bank *b = NULL;
1216 const char *name = get_name(cpu, bank, NULL);
1217 int err = 0;
1218
1219 if (!dev)
1220 return -ENODEV;
1221
1222 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1223 if (!b) {
1224 err = -ENOMEM;
1225 goto out;
1226 }
1227
1228 /* Associate the bank with the per-CPU MCE device */
1229 b->kobj = kobject_create_and_add(name, parent: &dev->kobj);
1230 if (!b->kobj) {
1231 err = -EINVAL;
1232 goto out_free;
1233 }
1234
1235 err = allocate_threshold_blocks(cpu, tb: b, bank, block: 0, address: mca_msr_reg(bank, reg: MCA_MISC));
1236 if (err)
1237 goto out_kobj;
1238
1239 bp[bank] = b;
1240 return 0;
1241
1242out_kobj:
1243 kobject_put(kobj: b->kobj);
1244out_free:
1245 kfree(objp: b);
1246out:
1247 return err;
1248}
1249
1250static void threshold_block_release(struct kobject *kobj)
1251{
1252 kfree(to_block(kobj));
1253}
1254
1255static void deallocate_threshold_blocks(struct threshold_bank *bank)
1256{
1257 struct threshold_block *pos, *tmp;
1258
1259 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) {
1260 list_del(entry: &pos->miscj);
1261 kobject_put(kobj: &pos->kobj);
1262 }
1263
1264 kobject_put(kobj: &bank->blocks->kobj);
1265}
1266
1267static void threshold_remove_bank(struct threshold_bank *bank)
1268{
1269 if (!bank->blocks)
1270 goto out_free;
1271
1272 deallocate_threshold_blocks(bank);
1273
1274out_free:
1275 kobject_put(kobj: bank->kobj);
1276 kfree(objp: bank);
1277}
1278
1279static void __threshold_remove_device(struct threshold_bank **bp)
1280{
1281 unsigned int bank, numbanks = this_cpu_read(mce_num_banks);
1282
1283 for (bank = 0; bank < numbanks; bank++) {
1284 if (!bp[bank])
1285 continue;
1286
1287 threshold_remove_bank(bank: bp[bank]);
1288 bp[bank] = NULL;
1289 }
1290 kfree(objp: bp);
1291}
1292
1293int mce_threshold_remove_device(unsigned int cpu)
1294{
1295 struct threshold_bank **bp = this_cpu_read(threshold_banks);
1296
1297 if (!bp)
1298 return 0;
1299
1300 /*
1301 * Clear the pointer before cleaning up, so that the interrupt won't
1302 * touch anything of this.
1303 */
1304 this_cpu_write(threshold_banks, NULL);
1305
1306 __threshold_remove_device(bp);
1307 return 0;
1308}
1309
1310/**
1311 * mce_threshold_create_device - Create the per-CPU MCE threshold device
1312 * @cpu: The plugged in CPU
1313 *
1314 * Create directories and files for all valid threshold banks.
1315 *
1316 * This is invoked from the CPU hotplug callback which was installed in
1317 * mcheck_init_device(). The invocation happens in context of the hotplug
1318 * thread running on @cpu. The callback is invoked on all CPUs which are
1319 * online when the callback is installed or during a real hotplug event.
1320 */
1321int mce_threshold_create_device(unsigned int cpu)
1322{
1323 unsigned int numbanks, bank;
1324 struct threshold_bank **bp;
1325 int err;
1326
1327 if (!mce_flags.amd_threshold)
1328 return 0;
1329
1330 bp = this_cpu_read(threshold_banks);
1331 if (bp)
1332 return 0;
1333
1334 numbanks = this_cpu_read(mce_num_banks);
1335 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL);
1336 if (!bp)
1337 return -ENOMEM;
1338
1339 for (bank = 0; bank < numbanks; ++bank) {
1340 if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))
1341 continue;
1342 err = threshold_create_bank(bp, cpu, bank);
1343 if (err) {
1344 __threshold_remove_device(bp);
1345 return err;
1346 }
1347 }
1348 this_cpu_write(threshold_banks, bp);
1349
1350 if (thresholding_irq_en)
1351 mce_threshold_vector = amd_threshold_interrupt;
1352 return 0;
1353}
1354

source code of linux/arch/x86/kernel/cpu/mce/amd.c