1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD CPU Microcode Update Driver for Linux
4 *
5 * This driver allows to upgrade microcode on F10h AMD
6 * CPUs and later.
7 *
8 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
9 * 2013-2018 Borislav Petkov <bp@alien8.de>
10 *
11 * Author: Peter Oruba <peter.oruba@amd.com>
12 *
13 * Based on work by:
14 * Tigran Aivazian <aivazian.tigran@gmail.com>
15 *
16 * early loader:
17 * Copyright (C) 2013 Advanced Micro Devices, Inc.
18 *
19 * Author: Jacob Shin <jacob.shin@amd.com>
20 * Fixes: Borislav Petkov <bp@suse.de>
21 */
22#define pr_fmt(fmt) "microcode: " fmt
23
24#include <linux/earlycpio.h>
25#include <linux/firmware.h>
26#include <linux/bsearch.h>
27#include <linux/uaccess.h>
28#include <linux/vmalloc.h>
29#include <linux/initrd.h>
30#include <linux/kernel.h>
31#include <linux/pci.h>
32
33#include <crypto/sha2.h>
34
35#include <asm/microcode.h>
36#include <asm/processor.h>
37#include <asm/cmdline.h>
38#include <asm/setup.h>
39#include <asm/cpu.h>
40#include <asm/msr.h>
41#include <asm/tlb.h>
42
43#include "internal.h"
44
45struct ucode_patch {
46 struct list_head plist;
47 void *data;
48 unsigned int size;
49 u32 patch_id;
50 u16 equiv_cpu;
51};
52
53static LIST_HEAD(microcode_cache);
54
55#define UCODE_MAGIC 0x00414d44
56#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
57#define UCODE_UCODE_TYPE 0x00000001
58
59#define SECTION_HDR_SIZE 8
60#define CONTAINER_HDR_SZ 12
61
62struct equiv_cpu_entry {
63 u32 installed_cpu;
64 u32 fixed_errata_mask;
65 u32 fixed_errata_compare;
66 u16 equiv_cpu;
67 u16 res;
68} __packed;
69
70struct microcode_header_amd {
71 u32 data_code;
72 u32 patch_id;
73 u16 mc_patch_data_id;
74 u8 mc_patch_data_len;
75 u8 init_flag;
76 u32 mc_patch_data_checksum;
77 u32 nb_dev_id;
78 u32 sb_dev_id;
79 u16 processor_rev_id;
80 u8 nb_rev_id;
81 u8 sb_rev_id;
82 u8 bios_api_rev;
83 u8 reserved1[3];
84 u32 match_reg[8];
85} __packed;
86
87struct microcode_amd {
88 struct microcode_header_amd hdr;
89 unsigned int mpb[];
90};
91
92static struct equiv_cpu_table {
93 unsigned int num_entries;
94 struct equiv_cpu_entry *entry;
95} equiv_table;
96
97union zen_patch_rev {
98 struct {
99 __u32 rev : 8,
100 stepping : 4,
101 model : 4,
102 __reserved : 4,
103 ext_model : 4,
104 ext_fam : 8;
105 };
106 __u32 ucode_rev;
107};
108
109union cpuid_1_eax {
110 struct {
111 __u32 stepping : 4,
112 model : 4,
113 family : 4,
114 __reserved0 : 4,
115 ext_model : 4,
116 ext_fam : 8,
117 __reserved1 : 4;
118 };
119 __u32 full;
120};
121
122/*
123 * This points to the current valid container of microcode patches which we will
124 * save from the initrd/builtin before jettisoning its contents. @mc is the
125 * microcode patch we found to match.
126 */
127struct cont_desc {
128 struct microcode_amd *mc;
129 u32 psize;
130 u8 *data;
131 size_t size;
132};
133
134/*
135 * Microcode patch container file is prepended to the initrd in cpio
136 * format. See Documentation/arch/x86/microcode.rst
137 */
138static const char
139ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
140
141/*
142 * This is CPUID(1).EAX on the BSP. It is used in two ways:
143 *
144 * 1. To ignore the equivalence table on Zen1 and newer.
145 *
146 * 2. To match which patches to load because the patch revision ID
147 * already contains the f/m/s for which the microcode is destined
148 * for.
149 */
150static u32 bsp_cpuid_1_eax __ro_after_init;
151
152static bool sha_check = true;
153
154struct patch_digest {
155 u32 patch_id;
156 u8 sha256[SHA256_DIGEST_SIZE];
157};
158
159#include "amd_shas.c"
160
161static int cmp_id(const void *key, const void *elem)
162{
163 struct patch_digest *pd = (struct patch_digest *)elem;
164 u32 patch_id = *(u32 *)key;
165
166 if (patch_id == pd->patch_id)
167 return 0;
168 else if (patch_id < pd->patch_id)
169 return -1;
170 else
171 return 1;
172}
173
174static bool need_sha_check(u32 cur_rev)
175{
176 switch (cur_rev >> 8) {
177 case 0x80012: return cur_rev <= 0x800126f; break;
178 case 0x80082: return cur_rev <= 0x800820f; break;
179 case 0x83010: return cur_rev <= 0x830107c; break;
180 case 0x86001: return cur_rev <= 0x860010e; break;
181 case 0x86081: return cur_rev <= 0x8608108; break;
182 case 0x87010: return cur_rev <= 0x8701034; break;
183 case 0x8a000: return cur_rev <= 0x8a0000a; break;
184 case 0xa0010: return cur_rev <= 0xa00107a; break;
185 case 0xa0011: return cur_rev <= 0xa0011da; break;
186 case 0xa0012: return cur_rev <= 0xa001243; break;
187 case 0xa0082: return cur_rev <= 0xa00820e; break;
188 case 0xa1011: return cur_rev <= 0xa101153; break;
189 case 0xa1012: return cur_rev <= 0xa10124e; break;
190 case 0xa1081: return cur_rev <= 0xa108109; break;
191 case 0xa2010: return cur_rev <= 0xa20102f; break;
192 case 0xa2012: return cur_rev <= 0xa201212; break;
193 case 0xa4041: return cur_rev <= 0xa404109; break;
194 case 0xa5000: return cur_rev <= 0xa500013; break;
195 case 0xa6012: return cur_rev <= 0xa60120a; break;
196 case 0xa7041: return cur_rev <= 0xa704109; break;
197 case 0xa7052: return cur_rev <= 0xa705208; break;
198 case 0xa7080: return cur_rev <= 0xa708009; break;
199 case 0xa70c0: return cur_rev <= 0xa70C009; break;
200 case 0xaa001: return cur_rev <= 0xaa00116; break;
201 case 0xaa002: return cur_rev <= 0xaa00218; break;
202 case 0xb0021: return cur_rev <= 0xb002146; break;
203 case 0xb1010: return cur_rev <= 0xb101046; break;
204 case 0xb2040: return cur_rev <= 0xb204031; break;
205 case 0xb4040: return cur_rev <= 0xb404031; break;
206 case 0xb6000: return cur_rev <= 0xb600031; break;
207 case 0xb7000: return cur_rev <= 0xb700031; break;
208 default: break;
209 }
210
211 pr_info("You should not be seeing this. Please send the following couple of lines to x86-<at>-kernel.org\n");
212 pr_info("CPUID(1).EAX: 0x%x, current revision: 0x%x\n", bsp_cpuid_1_eax, cur_rev);
213 return true;
214}
215
216static bool verify_sha256_digest(u32 patch_id, u32 cur_rev, const u8 *data, unsigned int len)
217{
218 struct patch_digest *pd = NULL;
219 u8 digest[SHA256_DIGEST_SIZE];
220 int i;
221
222 if (x86_family(sig: bsp_cpuid_1_eax) < 0x17)
223 return true;
224
225 if (!need_sha_check(cur_rev))
226 return true;
227
228 if (!sha_check)
229 return true;
230
231 pd = bsearch(key: &patch_id, base: phashes, ARRAY_SIZE(phashes), size: sizeof(struct patch_digest), cmp: cmp_id);
232 if (!pd) {
233 pr_err("No sha256 digest for patch ID: 0x%x found\n", patch_id);
234 return false;
235 }
236
237 sha256(data, len, out: digest);
238
239 if (memcmp(p: digest, q: pd->sha256, size: sizeof(digest))) {
240 pr_err("Patch 0x%x SHA256 digest mismatch!\n", patch_id);
241
242 for (i = 0; i < SHA256_DIGEST_SIZE; i++)
243 pr_cont("0x%x ", digest[i]);
244 pr_info("\n");
245
246 return false;
247 }
248
249 return true;
250}
251
252static u32 get_patch_level(void)
253{
254 u32 rev, dummy __always_unused;
255
256 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
257
258 return rev;
259}
260
261static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val)
262{
263 union zen_patch_rev p;
264 union cpuid_1_eax c;
265
266 p.ucode_rev = val;
267 c.full = 0;
268
269 c.stepping = p.stepping;
270 c.model = p.model;
271 c.ext_model = p.ext_model;
272 c.family = 0xf;
273 c.ext_fam = p.ext_fam;
274
275 return c;
276}
277
278static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
279{
280 unsigned int i;
281
282 /* Zen and newer do not need an equivalence table. */
283 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17)
284 return 0;
285
286 if (!et || !et->num_entries)
287 return 0;
288
289 for (i = 0; i < et->num_entries; i++) {
290 struct equiv_cpu_entry *e = &et->entry[i];
291
292 if (sig == e->installed_cpu)
293 return e->equiv_cpu;
294 }
295 return 0;
296}
297
298/*
299 * Check whether there is a valid microcode container file at the beginning
300 * of @buf of size @buf_size.
301 */
302static bool verify_container(const u8 *buf, size_t buf_size)
303{
304 u32 cont_magic;
305
306 if (buf_size <= CONTAINER_HDR_SZ) {
307 pr_debug("Truncated microcode container header.\n");
308 return false;
309 }
310
311 cont_magic = *(const u32 *)buf;
312 if (cont_magic != UCODE_MAGIC) {
313 pr_debug("Invalid magic value (0x%08x).\n", cont_magic);
314 return false;
315 }
316
317 return true;
318}
319
320/*
321 * Check whether there is a valid, non-truncated CPU equivalence table at the
322 * beginning of @buf of size @buf_size.
323 */
324static bool verify_equivalence_table(const u8 *buf, size_t buf_size)
325{
326 const u32 *hdr = (const u32 *)buf;
327 u32 cont_type, equiv_tbl_len;
328
329 if (!verify_container(buf, buf_size))
330 return false;
331
332 /* Zen and newer do not need an equivalence table. */
333 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17)
334 return true;
335
336 cont_type = hdr[1];
337 if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) {
338 pr_debug("Wrong microcode container equivalence table type: %u.\n",
339 cont_type);
340 return false;
341 }
342
343 buf_size -= CONTAINER_HDR_SZ;
344
345 equiv_tbl_len = hdr[2];
346 if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) ||
347 buf_size < equiv_tbl_len) {
348 pr_debug("Truncated equivalence table.\n");
349 return false;
350 }
351
352 return true;
353}
354
355/*
356 * Check whether there is a valid, non-truncated microcode patch section at the
357 * beginning of @buf of size @buf_size.
358 *
359 * On success, @sh_psize returns the patch size according to the section header,
360 * to the caller.
361 */
362static bool __verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize)
363{
364 u32 p_type, p_size;
365 const u32 *hdr;
366
367 if (buf_size < SECTION_HDR_SIZE) {
368 pr_debug("Truncated patch section.\n");
369 return false;
370 }
371
372 hdr = (const u32 *)buf;
373 p_type = hdr[0];
374 p_size = hdr[1];
375
376 if (p_type != UCODE_UCODE_TYPE) {
377 pr_debug("Invalid type field (0x%x) in container file section header.\n",
378 p_type);
379 return false;
380 }
381
382 if (p_size < sizeof(struct microcode_header_amd)) {
383 pr_debug("Patch of size %u too short.\n", p_size);
384 return false;
385 }
386
387 *sh_psize = p_size;
388
389 return true;
390}
391
392/*
393 * Check whether the passed remaining file @buf_size is large enough to contain
394 * a patch of the indicated @sh_psize (and also whether this size does not
395 * exceed the per-family maximum). @sh_psize is the size read from the section
396 * header.
397 */
398static bool __verify_patch_size(u32 sh_psize, size_t buf_size)
399{
400 u8 family = x86_family(sig: bsp_cpuid_1_eax);
401 u32 max_size;
402
403 if (family >= 0x15)
404 goto ret;
405
406#define F1XH_MPB_MAX_SIZE 2048
407#define F14H_MPB_MAX_SIZE 1824
408
409 switch (family) {
410 case 0x10 ... 0x12:
411 max_size = F1XH_MPB_MAX_SIZE;
412 break;
413 case 0x14:
414 max_size = F14H_MPB_MAX_SIZE;
415 break;
416 default:
417 WARN(1, "%s: WTF family: 0x%x\n", __func__, family);
418 return false;
419 }
420
421 if (sh_psize > max_size)
422 return false;
423
424ret:
425 /* Working with the whole buffer so < is ok. */
426 return sh_psize <= buf_size;
427}
428
429/*
430 * Verify the patch in @buf.
431 *
432 * Returns:
433 * negative: on error
434 * positive: patch is not for this family, skip it
435 * 0: success
436 */
437static int verify_patch(const u8 *buf, size_t buf_size, u32 *patch_size)
438{
439 u8 family = x86_family(sig: bsp_cpuid_1_eax);
440 struct microcode_header_amd *mc_hdr;
441 u32 sh_psize;
442 u16 proc_id;
443 u8 patch_fam;
444
445 if (!__verify_patch_section(buf, buf_size, sh_psize: &sh_psize))
446 return -1;
447
448 /*
449 * The section header length is not included in this indicated size
450 * but is present in the leftover file length so we need to subtract
451 * it before passing this value to the function below.
452 */
453 buf_size -= SECTION_HDR_SIZE;
454
455 /*
456 * Check if the remaining buffer is big enough to contain a patch of
457 * size sh_psize, as the section claims.
458 */
459 if (buf_size < sh_psize) {
460 pr_debug("Patch of size %u truncated.\n", sh_psize);
461 return -1;
462 }
463
464 if (!__verify_patch_size(sh_psize, buf_size)) {
465 pr_debug("Per-family patch size mismatch.\n");
466 return -1;
467 }
468
469 *patch_size = sh_psize;
470
471 mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE);
472 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
473 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id);
474 return -1;
475 }
476
477 proc_id = mc_hdr->processor_rev_id;
478 patch_fam = 0xf + (proc_id >> 12);
479 if (patch_fam != family)
480 return 1;
481
482 return 0;
483}
484
485static bool mc_patch_matches(struct microcode_amd *mc, u16 eq_id)
486{
487 /* Zen and newer do not need an equivalence table. */
488 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17)
489 return ucode_rev_to_cpuid(val: mc->hdr.patch_id).full == bsp_cpuid_1_eax;
490 else
491 return eq_id == mc->hdr.processor_rev_id;
492}
493
494/*
495 * This scans the ucode blob for the proper container as we can have multiple
496 * containers glued together.
497 *
498 * Returns the amount of bytes consumed while scanning. @desc contains all the
499 * data we're going to use in later stages of the application.
500 */
501static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc)
502{
503 struct equiv_cpu_table table;
504 size_t orig_size = size;
505 u32 *hdr = (u32 *)ucode;
506 u16 eq_id;
507 u8 *buf;
508
509 if (!verify_equivalence_table(buf: ucode, buf_size: size))
510 return 0;
511
512 buf = ucode;
513
514 table.entry = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
515 table.num_entries = hdr[2] / sizeof(struct equiv_cpu_entry);
516
517 /*
518 * Find the equivalence ID of our CPU in this table. Even if this table
519 * doesn't contain a patch for the CPU, scan through the whole container
520 * so that it can be skipped in case there are other containers appended.
521 */
522 eq_id = find_equiv_id(et: &table, sig: bsp_cpuid_1_eax);
523
524 buf += hdr[2] + CONTAINER_HDR_SZ;
525 size -= hdr[2] + CONTAINER_HDR_SZ;
526
527 /*
528 * Scan through the rest of the container to find where it ends. We do
529 * some basic sanity-checking too.
530 */
531 while (size > 0) {
532 struct microcode_amd *mc;
533 u32 patch_size;
534 int ret;
535
536 ret = verify_patch(buf, buf_size: size, patch_size: &patch_size);
537 if (ret < 0) {
538 /*
539 * Patch verification failed, skip to the next container, if
540 * there is one. Before exit, check whether that container has
541 * found a patch already. If so, use it.
542 */
543 goto out;
544 } else if (ret > 0) {
545 goto skip;
546 }
547
548 mc = (struct microcode_amd *)(buf + SECTION_HDR_SIZE);
549 if (mc_patch_matches(mc, eq_id)) {
550 desc->psize = patch_size;
551 desc->mc = mc;
552 }
553
554skip:
555 /* Skip patch section header too: */
556 buf += patch_size + SECTION_HDR_SIZE;
557 size -= patch_size + SECTION_HDR_SIZE;
558 }
559
560out:
561 /*
562 * If we have found a patch (desc->mc), it means we're looking at the
563 * container which has a patch for this CPU so return 0 to mean, @ucode
564 * already points to the proper container. Otherwise, we return the size
565 * we scanned so that we can advance to the next container in the
566 * buffer.
567 */
568 if (desc->mc) {
569 desc->data = ucode;
570 desc->size = orig_size - size;
571
572 return 0;
573 }
574
575 return orig_size - size;
576}
577
578/*
579 * Scan the ucode blob for the proper container as we can have multiple
580 * containers glued together.
581 */
582static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
583{
584 while (size) {
585 size_t s = parse_container(ucode, size, desc);
586 if (!s)
587 return;
588
589 /* catch wraparound */
590 if (size >= s) {
591 ucode += s;
592 size -= s;
593 } else {
594 return;
595 }
596 }
597}
598
599static bool __apply_microcode_amd(struct microcode_amd *mc, u32 *cur_rev,
600 unsigned int psize)
601{
602 unsigned long p_addr = (unsigned long)&mc->hdr.data_code;
603
604 if (!verify_sha256_digest(patch_id: mc->hdr.patch_id, cur_rev: *cur_rev, data: (const u8 *)p_addr, len: psize))
605 return false;
606
607 native_wrmsrq(MSR_AMD64_PATCH_LOADER, p_addr);
608
609 if (x86_family(sig: bsp_cpuid_1_eax) == 0x17) {
610 unsigned long p_addr_end = p_addr + psize - 1;
611
612 invlpg(addr: p_addr);
613
614 /*
615 * Flush next page too if patch image is crossing a page
616 * boundary.
617 */
618 if (p_addr >> PAGE_SHIFT != p_addr_end >> PAGE_SHIFT)
619 invlpg(addr: p_addr_end);
620 }
621
622 /* verify patch application was successful */
623 *cur_rev = get_patch_level();
624 if (*cur_rev != mc->hdr.patch_id)
625 return false;
626
627 return true;
628}
629
630static bool get_builtin_microcode(struct cpio_data *cp)
631{
632 char fw_name[36] = "amd-ucode/microcode_amd.bin";
633 u8 family = x86_family(sig: bsp_cpuid_1_eax);
634 struct firmware fw;
635
636 if (IS_ENABLED(CONFIG_X86_32))
637 return false;
638
639 if (family >= 0x15)
640 snprintf(buf: fw_name, size: sizeof(fw_name),
641 fmt: "amd-ucode/microcode_amd_fam%02hhxh.bin", family);
642
643 if (firmware_request_builtin(fw: &fw, name: fw_name)) {
644 cp->size = fw.size;
645 cp->data = (void *)fw.data;
646 return true;
647 }
648
649 return false;
650}
651
652static bool __init find_blobs_in_containers(struct cpio_data *ret)
653{
654 struct cpio_data cp;
655 bool found;
656
657 if (!get_builtin_microcode(cp: &cp))
658 cp = find_microcode_in_initrd(path: ucode_path);
659
660 found = cp.data && cp.size;
661 if (found)
662 *ret = cp;
663
664 return found;
665}
666
667/*
668 * Early load occurs before we can vmalloc(). So we look for the microcode
669 * patch container file in initrd, traverse equivalent cpu table, look for a
670 * matching microcode patch, and update, all in initrd memory in place.
671 * When vmalloc() is available for use later -- on 64-bit during first AP load,
672 * and on 32-bit during save_microcode_in_initrd() -- we can call
673 * load_microcode_amd() to save equivalent cpu table and microcode patches in
674 * kernel heap memory.
675 */
676void __init load_ucode_amd_bsp(struct early_load_data *ed, unsigned int cpuid_1_eax)
677{
678 struct cont_desc desc = { };
679 struct microcode_amd *mc;
680 struct cpio_data cp = { };
681 char buf[4];
682 u32 rev;
683
684 if (cmdline_find_option(cmdline_ptr: boot_command_line, option: "microcode.amd_sha_check", buffer: buf, bufsize: 4)) {
685 if (!strncmp(buf, "off", 3)) {
686 sha_check = false;
687 pr_warn_once("It is a very very bad idea to disable the blobs SHA check!\n");
688 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
689 }
690 }
691
692 bsp_cpuid_1_eax = cpuid_1_eax;
693
694 rev = get_patch_level();
695 ed->old_rev = rev;
696
697 /* Needed in load_microcode_amd() */
698 ucode_cpu_info[0].cpu_sig.sig = cpuid_1_eax;
699
700 if (!find_blobs_in_containers(ret: &cp))
701 return;
702
703 scan_containers(ucode: cp.data, size: cp.size, desc: &desc);
704
705 mc = desc.mc;
706 if (!mc)
707 return;
708
709 /*
710 * Allow application of the same revision to pick up SMT-specific
711 * changes even if the revision of the other SMT thread is already
712 * up-to-date.
713 */
714 if (ed->old_rev > mc->hdr.patch_id)
715 return;
716
717 if (__apply_microcode_amd(mc, cur_rev: &rev, psize: desc.psize))
718 ed->new_rev = rev;
719}
720
721static inline bool patch_cpus_equivalent(struct ucode_patch *p,
722 struct ucode_patch *n,
723 bool ignore_stepping)
724{
725 /* Zen and newer hardcode the f/m/s in the patch ID */
726 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17) {
727 union cpuid_1_eax p_cid = ucode_rev_to_cpuid(val: p->patch_id);
728 union cpuid_1_eax n_cid = ucode_rev_to_cpuid(val: n->patch_id);
729
730 if (ignore_stepping) {
731 p_cid.stepping = 0;
732 n_cid.stepping = 0;
733 }
734
735 return p_cid.full == n_cid.full;
736 } else {
737 return p->equiv_cpu == n->equiv_cpu;
738 }
739}
740
741/*
742 * a small, trivial cache of per-family ucode patches
743 */
744static struct ucode_patch *cache_find_patch(struct ucode_cpu_info *uci, u16 equiv_cpu)
745{
746 struct ucode_patch *p;
747 struct ucode_patch n;
748
749 n.equiv_cpu = equiv_cpu;
750 n.patch_id = uci->cpu_sig.rev;
751
752 WARN_ON_ONCE(!n.patch_id);
753
754 list_for_each_entry(p, &microcode_cache, plist)
755 if (patch_cpus_equivalent(p, n: &n, ignore_stepping: false))
756 return p;
757
758 return NULL;
759}
760
761static inline int patch_newer(struct ucode_patch *p, struct ucode_patch *n)
762{
763 /* Zen and newer hardcode the f/m/s in the patch ID */
764 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17) {
765 union zen_patch_rev zp, zn;
766
767 zp.ucode_rev = p->patch_id;
768 zn.ucode_rev = n->patch_id;
769
770 if (zn.stepping != zp.stepping)
771 return -1;
772
773 return zn.rev > zp.rev;
774 } else {
775 return n->patch_id > p->patch_id;
776 }
777}
778
779static void update_cache(struct ucode_patch *new_patch)
780{
781 struct ucode_patch *p;
782 int ret;
783
784 list_for_each_entry(p, &microcode_cache, plist) {
785 if (patch_cpus_equivalent(p, n: new_patch, ignore_stepping: true)) {
786 ret = patch_newer(p, n: new_patch);
787 if (ret < 0)
788 continue;
789 else if (!ret) {
790 /* we already have the latest patch */
791 kfree(objp: new_patch->data);
792 kfree(objp: new_patch);
793 return;
794 }
795
796 list_replace(old: &p->plist, new: &new_patch->plist);
797 kfree(objp: p->data);
798 kfree(objp: p);
799 return;
800 }
801 }
802 /* no patch found, add it */
803 list_add_tail(new: &new_patch->plist, head: &microcode_cache);
804}
805
806static void free_cache(void)
807{
808 struct ucode_patch *p, *tmp;
809
810 list_for_each_entry_safe(p, tmp, &microcode_cache, plist) {
811 __list_del(prev: p->plist.prev, next: p->plist.next);
812 kfree(objp: p->data);
813 kfree(objp: p);
814 }
815}
816
817static struct ucode_patch *find_patch(unsigned int cpu)
818{
819 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
820 u16 equiv_id = 0;
821
822 uci->cpu_sig.rev = get_patch_level();
823
824 if (x86_family(sig: bsp_cpuid_1_eax) < 0x17) {
825 equiv_id = find_equiv_id(et: &equiv_table, sig: uci->cpu_sig.sig);
826 if (!equiv_id)
827 return NULL;
828 }
829
830 return cache_find_patch(uci, equiv_cpu: equiv_id);
831}
832
833void reload_ucode_amd(unsigned int cpu)
834{
835 u32 rev, dummy __always_unused;
836 struct microcode_amd *mc;
837 struct ucode_patch *p;
838
839 p = find_patch(cpu);
840 if (!p)
841 return;
842
843 mc = p->data;
844
845 rev = get_patch_level();
846 if (rev < mc->hdr.patch_id) {
847 if (__apply_microcode_amd(mc, cur_rev: &rev, psize: p->size))
848 pr_info_once("reload revision: 0x%08x\n", rev);
849 }
850}
851
852static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
853{
854 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
855 struct ucode_patch *p;
856
857 csig->sig = cpuid_eax(op: 0x00000001);
858 csig->rev = get_patch_level();
859
860 /*
861 * a patch could have been loaded early, set uci->mc so that
862 * mc_bp_resume() can call apply_microcode()
863 */
864 p = find_patch(cpu);
865 if (p && (p->patch_id == csig->rev))
866 uci->mc = p->data;
867
868 return 0;
869}
870
871static enum ucode_state apply_microcode_amd(int cpu)
872{
873 struct cpuinfo_x86 *c = &cpu_data(cpu);
874 struct microcode_amd *mc_amd;
875 struct ucode_cpu_info *uci;
876 struct ucode_patch *p;
877 enum ucode_state ret;
878 u32 rev;
879
880 BUG_ON(raw_smp_processor_id() != cpu);
881
882 uci = ucode_cpu_info + cpu;
883
884 p = find_patch(cpu);
885 if (!p)
886 return UCODE_NFOUND;
887
888 rev = uci->cpu_sig.rev;
889
890 mc_amd = p->data;
891 uci->mc = p->data;
892
893 /* need to apply patch? */
894 if (rev > mc_amd->hdr.patch_id) {
895 ret = UCODE_OK;
896 goto out;
897 }
898
899 if (!__apply_microcode_amd(mc: mc_amd, cur_rev: &rev, psize: p->size)) {
900 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
901 cpu, mc_amd->hdr.patch_id);
902 return UCODE_ERROR;
903 }
904
905 rev = mc_amd->hdr.patch_id;
906 ret = UCODE_UPDATED;
907
908out:
909 uci->cpu_sig.rev = rev;
910 c->microcode = rev;
911
912 /* Update boot_cpu_data's revision too, if we're on the BSP: */
913 if (c->cpu_index == boot_cpu_data.cpu_index)
914 boot_cpu_data.microcode = rev;
915
916 return ret;
917}
918
919void load_ucode_amd_ap(unsigned int cpuid_1_eax)
920{
921 unsigned int cpu = smp_processor_id();
922
923 ucode_cpu_info[cpu].cpu_sig.sig = cpuid_1_eax;
924 apply_microcode_amd(cpu);
925}
926
927static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
928{
929 u32 equiv_tbl_len;
930 const u32 *hdr;
931
932 if (!verify_equivalence_table(buf, buf_size))
933 return 0;
934
935 hdr = (const u32 *)buf;
936 equiv_tbl_len = hdr[2];
937
938 /* Zen and newer do not need an equivalence table. */
939 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17)
940 goto out;
941
942 equiv_table.entry = vmalloc(equiv_tbl_len);
943 if (!equiv_table.entry) {
944 pr_err("failed to allocate equivalent CPU table\n");
945 return 0;
946 }
947
948 memcpy(equiv_table.entry, buf + CONTAINER_HDR_SZ, equiv_tbl_len);
949 equiv_table.num_entries = equiv_tbl_len / sizeof(struct equiv_cpu_entry);
950
951out:
952 /* add header length */
953 return equiv_tbl_len + CONTAINER_HDR_SZ;
954}
955
956static void free_equiv_cpu_table(void)
957{
958 if (x86_family(sig: bsp_cpuid_1_eax) >= 0x17)
959 return;
960
961 vfree(addr: equiv_table.entry);
962 memset(&equiv_table, 0, sizeof(equiv_table));
963}
964
965static void cleanup(void)
966{
967 free_equiv_cpu_table();
968 free_cache();
969}
970
971/*
972 * Return a non-negative value even if some of the checks failed so that
973 * we can skip over the next patch. If we return a negative value, we
974 * signal a grave error like a memory allocation has failed and the
975 * driver cannot continue functioning normally. In such cases, we tear
976 * down everything we've used up so far and exit.
977 */
978static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover,
979 unsigned int *patch_size)
980{
981 struct microcode_header_amd *mc_hdr;
982 struct ucode_patch *patch;
983 u16 proc_id;
984 int ret;
985
986 ret = verify_patch(buf: fw, buf_size: leftover, patch_size);
987 if (ret)
988 return ret;
989
990 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
991 if (!patch) {
992 pr_err("Patch allocation failure.\n");
993 return -EINVAL;
994 }
995
996 patch->data = kmemdup(fw + SECTION_HDR_SIZE, *patch_size, GFP_KERNEL);
997 if (!patch->data) {
998 pr_err("Patch data allocation failure.\n");
999 kfree(objp: patch);
1000 return -EINVAL;
1001 }
1002 patch->size = *patch_size;
1003
1004 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
1005 proc_id = mc_hdr->processor_rev_id;
1006
1007 INIT_LIST_HEAD(list: &patch->plist);
1008 patch->patch_id = mc_hdr->patch_id;
1009 patch->equiv_cpu = proc_id;
1010
1011 pr_debug("%s: Adding patch_id: 0x%08x, proc_id: 0x%04x\n",
1012 __func__, patch->patch_id, proc_id);
1013
1014 /* ... and add to cache. */
1015 update_cache(new_patch: patch);
1016
1017 return 0;
1018}
1019
1020/* Scan the blob in @data and add microcode patches to the cache. */
1021static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, size_t size)
1022{
1023 u8 *fw = (u8 *)data;
1024 size_t offset;
1025
1026 offset = install_equiv_cpu_table(buf: data, buf_size: size);
1027 if (!offset)
1028 return UCODE_ERROR;
1029
1030 fw += offset;
1031 size -= offset;
1032
1033 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
1034 pr_err("invalid type field in container file section header\n");
1035 free_equiv_cpu_table();
1036 return UCODE_ERROR;
1037 }
1038
1039 while (size > 0) {
1040 unsigned int crnt_size = 0;
1041 int ret;
1042
1043 ret = verify_and_add_patch(family, fw, leftover: size, patch_size: &crnt_size);
1044 if (ret < 0)
1045 return UCODE_ERROR;
1046
1047 fw += crnt_size + SECTION_HDR_SIZE;
1048 size -= (crnt_size + SECTION_HDR_SIZE);
1049 }
1050
1051 return UCODE_OK;
1052}
1053
1054static enum ucode_state _load_microcode_amd(u8 family, const u8 *data, size_t size)
1055{
1056 enum ucode_state ret;
1057
1058 /* free old equiv table */
1059 free_equiv_cpu_table();
1060
1061 ret = __load_microcode_amd(family, data, size);
1062 if (ret != UCODE_OK)
1063 cleanup();
1064
1065 return ret;
1066}
1067
1068static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
1069{
1070 struct cpuinfo_x86 *c;
1071 unsigned int nid, cpu;
1072 struct ucode_patch *p;
1073 enum ucode_state ret;
1074
1075 ret = _load_microcode_amd(family, data, size);
1076 if (ret != UCODE_OK)
1077 return ret;
1078
1079 for_each_node_with_cpus(nid) {
1080 cpu = cpumask_first(srcp: cpumask_of_node(node: nid));
1081 c = &cpu_data(cpu);
1082
1083 p = find_patch(cpu);
1084 if (!p)
1085 continue;
1086
1087 if (c->microcode >= p->patch_id)
1088 continue;
1089
1090 ret = UCODE_NEW;
1091 }
1092
1093 return ret;
1094}
1095
1096static int __init save_microcode_in_initrd(void)
1097{
1098 struct cpuinfo_x86 *c = &boot_cpu_data;
1099 struct cont_desc desc = { 0 };
1100 unsigned int cpuid_1_eax;
1101 enum ucode_state ret;
1102 struct cpio_data cp;
1103
1104 if (microcode_loader_disabled() || c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10)
1105 return 0;
1106
1107 cpuid_1_eax = native_cpuid_eax(op: 1);
1108
1109 if (!find_blobs_in_containers(ret: &cp))
1110 return -EINVAL;
1111
1112 scan_containers(ucode: cp.data, size: cp.size, desc: &desc);
1113 if (!desc.mc)
1114 return -EINVAL;
1115
1116 ret = _load_microcode_amd(family: x86_family(sig: cpuid_1_eax), data: desc.data, size: desc.size);
1117 if (ret > UCODE_UPDATED)
1118 return -EINVAL;
1119
1120 return 0;
1121}
1122early_initcall(save_microcode_in_initrd);
1123
1124/*
1125 * AMD microcode firmware naming convention, up to family 15h they are in
1126 * the legacy file:
1127 *
1128 * amd-ucode/microcode_amd.bin
1129 *
1130 * This legacy file is always smaller than 2K in size.
1131 *
1132 * Beginning with family 15h, they are in family-specific firmware files:
1133 *
1134 * amd-ucode/microcode_amd_fam15h.bin
1135 * amd-ucode/microcode_amd_fam16h.bin
1136 * ...
1137 *
1138 * These might be larger than 2K.
1139 */
1140static enum ucode_state request_microcode_amd(int cpu, struct device *device)
1141{
1142 char fw_name[36] = "amd-ucode/microcode_amd.bin";
1143 struct cpuinfo_x86 *c = &cpu_data(cpu);
1144 enum ucode_state ret = UCODE_NFOUND;
1145 const struct firmware *fw;
1146
1147 if (force_minrev)
1148 return UCODE_NFOUND;
1149
1150 if (c->x86 >= 0x15)
1151 snprintf(buf: fw_name, size: sizeof(fw_name), fmt: "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
1152
1153 if (request_firmware_direct(fw: &fw, name: (const char *)fw_name, device)) {
1154 pr_debug("failed to load file %s\n", fw_name);
1155 goto out;
1156 }
1157
1158 ret = UCODE_ERROR;
1159 if (!verify_container(buf: fw->data, buf_size: fw->size))
1160 goto fw_release;
1161
1162 ret = load_microcode_amd(family: c->x86, data: fw->data, size: fw->size);
1163
1164 fw_release:
1165 release_firmware(fw);
1166
1167 out:
1168 return ret;
1169}
1170
1171static void microcode_fini_cpu_amd(int cpu)
1172{
1173 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
1174
1175 uci->mc = NULL;
1176}
1177
1178static void finalize_late_load_amd(int result)
1179{
1180 if (result)
1181 cleanup();
1182}
1183
1184static struct microcode_ops microcode_amd_ops = {
1185 .request_microcode_fw = request_microcode_amd,
1186 .collect_cpu_info = collect_cpu_info_amd,
1187 .apply_microcode = apply_microcode_amd,
1188 .microcode_fini_cpu = microcode_fini_cpu_amd,
1189 .finalize_late_load = finalize_late_load_amd,
1190 .nmi_safe = true,
1191};
1192
1193struct microcode_ops * __init init_amd_microcode(void)
1194{
1195 struct cpuinfo_x86 *c = &boot_cpu_data;
1196
1197 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
1198 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
1199 return NULL;
1200 }
1201 return &microcode_amd_ops;
1202}
1203
1204void __exit exit_amd_microcode(void)
1205{
1206 cleanup();
1207}
1208

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source code of linux/arch/x86/kernel/cpu/microcode/amd.c