1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef ARCH_X86_KVM_X86_H
3#define ARCH_X86_KVM_X86_H
4
5#include <linux/kvm_host.h>
6#include <asm/fpu/xstate.h>
7#include <asm/mce.h>
8#include <asm/pvclock.h>
9#include "kvm_cache_regs.h"
10#include "kvm_emulate.h"
11#include "cpuid.h"
12
13#define KVM_MAX_MCE_BANKS 32
14
15struct kvm_caps {
16 /* control of guest tsc rate supported? */
17 bool has_tsc_control;
18 /* maximum supported tsc_khz for guests */
19 u32 max_guest_tsc_khz;
20 /* number of bits of the fractional part of the TSC scaling ratio */
21 u8 tsc_scaling_ratio_frac_bits;
22 /* maximum allowed value of TSC scaling ratio */
23 u64 max_tsc_scaling_ratio;
24 /* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */
25 u64 default_tsc_scaling_ratio;
26 /* bus lock detection supported? */
27 bool has_bus_lock_exit;
28 /* notify VM exit supported? */
29 bool has_notify_vmexit;
30 /* bit mask of VM types */
31 u32 supported_vm_types;
32
33 u64 supported_mce_cap;
34 u64 supported_xcr0;
35 u64 supported_xss;
36 u64 supported_perf_cap;
37
38 u64 supported_quirks;
39 u64 inapplicable_quirks;
40};
41
42struct kvm_host_values {
43 /*
44 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical
45 * address bits irrespective of features that repurpose legal bits,
46 * e.g. MKTME.
47 */
48 u8 maxphyaddr;
49
50 u64 efer;
51 u64 xcr0;
52 u64 xss;
53 u64 s_cet;
54 u64 arch_capabilities;
55};
56
57void kvm_spurious_fault(void);
58
59#define SIZE_OF_MEMSLOTS_HASHTABLE \
60 (sizeof(((struct kvm_memslots *)0)->id_hash) * 2 * KVM_MAX_NR_ADDRESS_SPACES)
61
62/* Sanity check the size of the memslot hash tables. */
63static_assert(SIZE_OF_MEMSLOTS_HASHTABLE ==
64 (1024 * (1 + IS_ENABLED(CONFIG_X86_64)) * (1 + IS_ENABLED(CONFIG_KVM_SMM))));
65
66/*
67 * Assert that "struct kvm_{svm,vmx,tdx}" is an order-0 or order-1 allocation.
68 * Spilling over to an order-2 allocation isn't fundamentally problematic, but
69 * isn't expected to happen in the foreseeable future (O(years)). Assert that
70 * the size is an order-0 allocation when ignoring the memslot hash tables, to
71 * help detect and debug unexpected size increases.
72 */
73#define KVM_SANITY_CHECK_VM_STRUCT_SIZE(x) \
74do { \
75 BUILD_BUG_ON(get_order(sizeof(struct x) - SIZE_OF_MEMSLOTS_HASHTABLE) && \
76 !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN)); \
77 BUILD_BUG_ON(get_order(sizeof(struct x)) > 1 && \
78 !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN)); \
79} while (0)
80
81#define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
82({ \
83 bool failed = (consistency_check); \
84 if (failed) \
85 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
86 failed; \
87})
88
89/*
90 * The first...last VMX feature MSRs that are emulated by KVM. This may or may
91 * not cover all known VMX MSRs, as KVM doesn't emulate an MSR until there's an
92 * associated feature that KVM supports for nested virtualization.
93 */
94#define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC
95#define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC
96
97#define KVM_DEFAULT_PLE_GAP 128
98#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
99#define KVM_DEFAULT_PLE_WINDOW_GROW 2
100#define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
101#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
102#define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
103#define KVM_SVM_DEFAULT_PLE_WINDOW 3000
104
105/*
106 * KVM's internal, non-ABI indices for synthetic MSRs. The values themselves
107 * are arbitrary and have no meaning, the only requirement is that they don't
108 * conflict with "real" MSRs that KVM supports. Use values at the upper end
109 * of KVM's reserved paravirtual MSR range to minimize churn, i.e. these values
110 * will be usable until KVM exhausts its supply of paravirtual MSR indices.
111 */
112
113#define MSR_KVM_INTERNAL_GUEST_SSP 0x4b564dff
114
115static inline unsigned int __grow_ple_window(unsigned int val,
116 unsigned int base, unsigned int modifier, unsigned int max)
117{
118 u64 ret = val;
119
120 if (modifier < 1)
121 return base;
122
123 if (modifier < base)
124 ret *= modifier;
125 else
126 ret += modifier;
127
128 return min(ret, (u64)max);
129}
130
131static inline unsigned int __shrink_ple_window(unsigned int val,
132 unsigned int base, unsigned int modifier, unsigned int min)
133{
134 if (modifier < 1)
135 return base;
136
137 if (modifier < base)
138 val /= modifier;
139 else
140 val -= modifier;
141
142 return max(val, min);
143}
144
145#define MSR_IA32_CR_PAT_DEFAULT \
146 PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC)
147
148void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);
149int kvm_check_nested_events(struct kvm_vcpu *vcpu);
150
151/* Forcibly leave the nested mode in cases like a vCPU reset */
152static inline void kvm_leave_nested(struct kvm_vcpu *vcpu)
153{
154 kvm_x86_ops.nested_ops->leave_nested(vcpu);
155}
156
157/*
158 * If IBRS is advertised to the vCPU, KVM must flush the indirect branch
159 * predictors when transitioning from L2 to L1, as L1 expects hardware (KVM in
160 * this case) to provide separate predictor modes. Bare metal isolates the host
161 * from the guest, but doesn't isolate different guests from one another (in
162 * this case L1 and L2). The exception is if bare metal supports same mode IBRS,
163 * which offers protection within the same mode, and hence protects L1 from L2.
164 */
165static inline void kvm_nested_vmexit_handle_ibrs(struct kvm_vcpu *vcpu)
166{
167 if (cpu_feature_enabled(X86_FEATURE_AMD_IBRS_SAME_MODE))
168 return;
169
170 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) ||
171 guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBRS))
172 indirect_branch_prediction_barrier();
173}
174
175static inline bool kvm_vcpu_has_run(struct kvm_vcpu *vcpu)
176{
177 return vcpu->arch.last_vmentry_cpu != -1;
178}
179
180static inline void kvm_set_mp_state(struct kvm_vcpu *vcpu, int mp_state)
181{
182 vcpu->arch.mp_state = mp_state;
183 if (mp_state == KVM_MP_STATE_RUNNABLE)
184 vcpu->arch.pv.pv_unhalted = false;
185}
186
187static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu)
188{
189 return vcpu->arch.exception.pending ||
190 vcpu->arch.exception_vmexit.pending ||
191 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
192}
193
194static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
195{
196 vcpu->arch.exception.pending = false;
197 vcpu->arch.exception.injected = false;
198 vcpu->arch.exception_vmexit.pending = false;
199}
200
201static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
202 bool soft)
203{
204 vcpu->arch.interrupt.injected = true;
205 vcpu->arch.interrupt.soft = soft;
206 vcpu->arch.interrupt.nr = vector;
207}
208
209static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
210{
211 vcpu->arch.interrupt.injected = false;
212}
213
214static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
215{
216 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
217 vcpu->arch.nmi_injected;
218}
219
220static inline bool kvm_exception_is_soft(unsigned int nr)
221{
222 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
223}
224
225static inline bool is_protmode(struct kvm_vcpu *vcpu)
226{
227 return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE);
228}
229
230static inline bool is_long_mode(struct kvm_vcpu *vcpu)
231{
232#ifdef CONFIG_X86_64
233 return !!(vcpu->arch.efer & EFER_LMA);
234#else
235 return false;
236#endif
237}
238
239static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
240{
241 int cs_db, cs_l;
242
243 WARN_ON_ONCE(vcpu->arch.guest_state_protected);
244
245 if (!is_long_mode(vcpu))
246 return false;
247 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
248 return cs_l;
249}
250
251static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu)
252{
253 /*
254 * If running with protected guest state, the CS register is not
255 * accessible. The hypercall register values will have had to been
256 * provided in 64-bit mode, so assume the guest is in 64-bit.
257 */
258 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu);
259}
260
261static inline bool x86_exception_has_error_code(unsigned int vector)
262{
263 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
264 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
265 BIT(PF_VECTOR) | BIT(AC_VECTOR);
266
267 return (1U << vector) & exception_has_error_code;
268}
269
270static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
271{
272 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
273}
274
275static inline bool is_pae(struct kvm_vcpu *vcpu)
276{
277 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PAE);
278}
279
280static inline bool is_pse(struct kvm_vcpu *vcpu)
281{
282 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PSE);
283}
284
285static inline bool is_paging(struct kvm_vcpu *vcpu)
286{
287 return likely(kvm_is_cr0_bit_set(vcpu, X86_CR0_PG));
288}
289
290static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
291{
292 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
293}
294
295static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
296{
297 return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48;
298}
299
300static inline u8 max_host_virt_addr_bits(void)
301{
302 return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48;
303}
304
305/*
306 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and
307 * IDT/GDT bases have static canonicality checks, the size of which depends
308 * only on the CPU's support for 5-level paging, rather than on the state of
309 * CR4.LA57. This applies to both WRMSR and to other instructions that set
310 * their values, e.g. SGDT.
311 *
312 * KVM passes through most of these MSRS and also doesn't intercept the
313 * instructions that set the hidden segment bases.
314 *
315 * Because of this, to be consistent with hardware, even if the guest doesn't
316 * have LA57 enabled in its CPUID, perform canonicality checks based on *host*
317 * support for 5 level paging.
318 *
319 * Finally, instructions which are related to MMU invalidation of a given
320 * linear address, also have a similar static canonical check on address.
321 * This allows for example to invalidate 5-level addresses of a guest from a
322 * host which uses 4-level paging.
323 */
324static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu,
325 unsigned int flags)
326{
327 if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD))
328 return !__is_canonical_address(vaddr: la, vaddr_bits: max_host_virt_addr_bits());
329 else
330 return !__is_canonical_address(vaddr: la, vaddr_bits: vcpu_virt_addr_bits(vcpu));
331}
332
333static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu)
334{
335 return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR);
336}
337
338static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu)
339{
340 return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD);
341}
342
343static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu)
344{
345 return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG);
346}
347
348static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
349 gva_t gva, gfn_t gfn, unsigned access)
350{
351 u64 gen = kvm_memslots(kvm: vcpu->kvm)->generation;
352
353 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
354 return;
355
356 /*
357 * If this is a shadow nested page table, the "GVA" is
358 * actually a nGPA.
359 */
360 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
361 vcpu->arch.mmio_access = access;
362 vcpu->arch.mmio_gfn = gfn;
363 vcpu->arch.mmio_gen = gen;
364}
365
366static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
367{
368 return vcpu->arch.mmio_gen == kvm_memslots(kvm: vcpu->kvm)->generation;
369}
370
371/*
372 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
373 * clear all mmio cache info.
374 */
375#define MMIO_GVA_ANY (~(gva_t)0)
376
377static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
378{
379 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
380 return;
381
382 vcpu->arch.mmio_gva = 0;
383}
384
385static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
386{
387 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
388 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
389 return true;
390
391 return false;
392}
393
394static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
395{
396 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
397 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
398 return true;
399
400 return false;
401}
402
403static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg)
404{
405 unsigned long val = kvm_register_read_raw(vcpu, reg);
406
407 return is_64_bit_mode(vcpu) ? val : (u32)val;
408}
409
410static inline void kvm_register_write(struct kvm_vcpu *vcpu,
411 int reg, unsigned long val)
412{
413 if (!is_64_bit_mode(vcpu))
414 val = (u32)val;
415 return kvm_register_write_raw(vcpu, reg, val);
416}
417
418static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
419{
420 return !(kvm->arch.disabled_quirks & quirk);
421}
422
423static __always_inline void kvm_request_l1tf_flush_l1d(void)
424{
425#if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL)
426 /*
427 * Use a raw write to set the per-CPU flag, as KVM will ensure a flush
428 * even if preemption is currently enabled.. If the current vCPU task
429 * is migrated to a different CPU (or userspace runs the vCPU on a
430 * different task) before the next VM-Entry, then kvm_arch_vcpu_load()
431 * will request a flush on the new CPU.
432 */
433 raw_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1);
434#endif
435}
436
437void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
438
439u64 get_kvmclock_ns(struct kvm *kvm);
440uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm);
441bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp);
442int kvm_guest_time_update(struct kvm_vcpu *v);
443
444int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
445 gva_t addr, void *val, unsigned int bytes,
446 struct x86_exception *exception);
447
448int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
449 gva_t addr, void *val, unsigned int bytes,
450 struct x86_exception *exception);
451
452int handle_ud(struct kvm_vcpu *vcpu);
453
454void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
455 struct kvm_queued_exception *ex);
456
457int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
458int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
459void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
460int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
461 void *insn, int insn_len);
462int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
463 int emulation_type, void *insn, int insn_len);
464fastpath_t handle_fastpath_wrmsr(struct kvm_vcpu *vcpu);
465fastpath_t handle_fastpath_wrmsr_imm(struct kvm_vcpu *vcpu, u32 msr, int reg);
466fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu);
467fastpath_t handle_fastpath_invd(struct kvm_vcpu *vcpu);
468
469extern struct kvm_caps kvm_caps;
470extern struct kvm_host_values kvm_host;
471
472extern bool enable_pmu;
473
474void kvm_setup_xss_caps(void);
475
476/*
477 * Get a filtered version of KVM's supported XCR0 that strips out dynamic
478 * features for which the current process doesn't (yet) have permission to use.
479 * This is intended to be used only when enumerating support to userspace,
480 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be
481 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if
482 * userspace attempts to enable unpermitted features.
483 */
484static inline u64 kvm_get_filtered_xcr0(void)
485{
486 u64 permitted_xcr0 = kvm_caps.supported_xcr0;
487
488 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA);
489
490 if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) {
491 permitted_xcr0 &= xstate_get_guest_group_perm();
492
493 /*
494 * Treat XTILE_CFG as unsupported if the current process isn't
495 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in
496 * XCR0 without setting XTILE_DATA is architecturally illegal.
497 */
498 if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA))
499 permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG;
500 }
501 return permitted_xcr0;
502}
503
504static inline bool kvm_mpx_supported(void)
505{
506 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
507 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
508}
509
510extern unsigned int min_timer_period_us;
511
512extern bool enable_vmware_backdoor;
513
514extern int pi_inject_timer;
515
516extern bool report_ignored_msrs;
517
518extern bool eager_page_split;
519
520static inline void kvm_pr_unimpl_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
521{
522 if (report_ignored_msrs)
523 vcpu_unimpl(vcpu, "Unhandled WRMSR(0x%x) = 0x%llx\n", msr, data);
524}
525
526static inline void kvm_pr_unimpl_rdmsr(struct kvm_vcpu *vcpu, u32 msr)
527{
528 if (report_ignored_msrs)
529 vcpu_unimpl(vcpu, "Unhandled RDMSR(0x%x)\n", msr);
530}
531
532static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
533{
534 return pvclock_scale_delta(delta: nsec, mul_frac: vcpu->arch.virtual_tsc_mult,
535 shift: vcpu->arch.virtual_tsc_shift);
536}
537
538/* Same "calling convention" as do_div:
539 * - divide (n << 32) by base
540 * - put result in n
541 * - return remainder
542 */
543#define do_shl32_div32(n, base) \
544 ({ \
545 u32 __quot, __rem; \
546 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
547 : "rm" (base), "0" (0), "1" ((u32) n)); \
548 n = __quot; \
549 __rem; \
550 })
551
552static inline void kvm_disable_exits(struct kvm *kvm, u64 mask)
553{
554 kvm->arch.disabled_exits |= mask;
555}
556
557static inline bool kvm_mwait_in_guest(struct kvm *kvm)
558{
559 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_MWAIT;
560}
561
562static inline bool kvm_hlt_in_guest(struct kvm *kvm)
563{
564 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_HLT;
565}
566
567static inline bool kvm_pause_in_guest(struct kvm *kvm)
568{
569 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_PAUSE;
570}
571
572static inline bool kvm_cstate_in_guest(struct kvm *kvm)
573{
574 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_CSTATE;
575}
576
577static inline bool kvm_aperfmperf_in_guest(struct kvm *kvm)
578{
579 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_APERFMPERF;
580}
581
582static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm)
583{
584 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED;
585}
586
587static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu,
588 enum kvm_intr_type intr)
589{
590 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr);
591}
592
593static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
594{
595 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0);
596}
597
598static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu)
599{
600 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI;
601}
602
603static inline bool kvm_pat_valid(u64 data)
604{
605 if (data & 0xF8F8F8F8F8F8F8F8ull)
606 return false;
607 /* 0, 1, 4, 5, 6, 7 are valid values. */
608 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
609}
610
611static inline bool kvm_dr7_valid(u64 data)
612{
613 /* Bits [63:32] are reserved */
614 return !(data >> 32);
615}
616static inline bool kvm_dr6_valid(u64 data)
617{
618 /* Bits [63:32] are reserved */
619 return !(data >> 32);
620}
621
622/*
623 * Trigger machine check on the host. We assume all the MSRs are already set up
624 * by the CPU and that we still run on the same CPU as the MCE occurred on.
625 * We pass a fake environment to the machine check handler because we want
626 * the guest to be always treated like user space, no matter what context
627 * it used internally.
628 */
629static inline void kvm_machine_check(void)
630{
631#if defined(CONFIG_X86_MCE)
632 struct pt_regs regs = {
633 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
634 .flags = X86_EFLAGS_IF,
635 };
636
637 do_machine_check(pt_regs: &regs);
638#endif
639}
640
641int kvm_spec_ctrl_test_value(u64 value);
642int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
643 struct x86_exception *e);
644int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
645bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
646
647enum kvm_msr_access {
648 MSR_TYPE_R = BIT(0),
649 MSR_TYPE_W = BIT(1),
650 MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W,
651};
652
653/*
654 * Internal error codes that are used to indicate that MSR emulation encountered
655 * an error that should result in #GP in the guest, unless userspace handles it.
656 * Note, '1', '0', and negative numbers are off limits, as they are used by KVM
657 * as part of KVM's lightly documented internal KVM_RUN return codes.
658 *
659 * UNSUPPORTED - The MSR isn't supported, either because it is completely
660 * unknown to KVM, or because the MSR should not exist according
661 * to the vCPU model.
662 *
663 * FILTERED - Access to the MSR is denied by a userspace MSR filter.
664 */
665#define KVM_MSR_RET_UNSUPPORTED 2
666#define KVM_MSR_RET_FILTERED 3
667
668static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
669{
670 return !(cr4 & vcpu->arch.cr4_guest_rsvd_bits);
671}
672
673#define __cr4_reserved_bits(__cpu_has, __c) \
674({ \
675 u64 __reserved_bits = CR4_RESERVED_BITS; \
676 \
677 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
678 __reserved_bits |= X86_CR4_OSXSAVE; \
679 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
680 __reserved_bits |= X86_CR4_SMEP; \
681 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
682 __reserved_bits |= X86_CR4_SMAP; \
683 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
684 __reserved_bits |= X86_CR4_FSGSBASE; \
685 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
686 __reserved_bits |= X86_CR4_PKE; \
687 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
688 __reserved_bits |= X86_CR4_LA57; \
689 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
690 __reserved_bits |= X86_CR4_UMIP; \
691 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
692 __reserved_bits |= X86_CR4_VMXE; \
693 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
694 __reserved_bits |= X86_CR4_PCIDE; \
695 if (!__cpu_has(__c, X86_FEATURE_LAM)) \
696 __reserved_bits |= X86_CR4_LAM_SUP; \
697 if (!__cpu_has(__c, X86_FEATURE_SHSTK) && \
698 !__cpu_has(__c, X86_FEATURE_IBT)) \
699 __reserved_bits |= X86_CR4_CET; \
700 __reserved_bits; \
701})
702
703int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
704 void *dst);
705int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
706 void *dst);
707int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
708 unsigned int port, void *data, unsigned int count,
709 int in);
710
711static inline bool user_exit_on_hypercall(struct kvm *kvm, unsigned long hc_nr)
712{
713 return kvm->arch.hypercall_exit_enabled & BIT(hc_nr);
714}
715
716int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, int cpl,
717 int (*complete_hypercall)(struct kvm_vcpu *));
718
719#define __kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall) \
720({ \
721 int __ret; \
722 __ret = ____kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall); \
723 \
724 if (__ret > 0) \
725 __ret = complete_hypercall(_vcpu); \
726 __ret; \
727})
728
729int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
730
731#define CET_US_RESERVED_BITS GENMASK(9, 6)
732#define CET_US_SHSTK_MASK_BITS GENMASK(1, 0)
733#define CET_US_IBT_MASK_BITS (GENMASK_ULL(5, 2) | GENMASK_ULL(63, 10))
734#define CET_US_LEGACY_BITMAP_BASE(data) ((data) >> 12)
735
736static inline bool kvm_is_valid_u_s_cet(struct kvm_vcpu *vcpu, u64 data)
737{
738 if (data & CET_US_RESERVED_BITS)
739 return false;
740 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) &&
741 (data & CET_US_SHSTK_MASK_BITS))
742 return false;
743 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_IBT) &&
744 (data & CET_US_IBT_MASK_BITS))
745 return false;
746 if (!IS_ALIGNED(CET_US_LEGACY_BITMAP_BASE(data), 4))
747 return false;
748 /* IBT can be suppressed iff the TRACKER isn't WAIT_ENDBR. */
749 if ((data & CET_SUPPRESS) && (data & CET_WAIT_ENDBR))
750 return false;
751
752 return true;
753}
754#endif
755

source code of linux/arch/x86/kvm/x86.h