1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * Copyright 2018-2021 NXP |
4 | * Dong Aisheng <aisheng.dong@nxp.com> |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/err.h> |
9 | #include <linux/io.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/slab.h> |
14 | |
15 | #include "clk-scu.h" |
16 | |
17 | #include <dt-bindings/firmware/imx/rsrc.h> |
18 | |
19 | static const char *dc0_sels[] = { |
20 | "clk_dummy" , |
21 | "clk_dummy" , |
22 | "dc0_pll0_clk" , |
23 | "dc0_pll1_clk" , |
24 | "dc0_bypass0_clk" , |
25 | }; |
26 | |
27 | static const char * const dc1_sels[] = { |
28 | "clk_dummy" , |
29 | "clk_dummy" , |
30 | "dc1_pll0_clk" , |
31 | "dc1_pll1_clk" , |
32 | "dc1_bypass0_clk" , |
33 | }; |
34 | |
35 | static const char * const enet0_rgmii_txc_sels[] = { |
36 | "enet0_ref_div" , |
37 | "clk_dummy" , |
38 | }; |
39 | |
40 | static const char * const enet1_rgmii_txc_sels[] = { |
41 | "enet1_ref_div" , |
42 | "clk_dummy" , |
43 | }; |
44 | |
45 | static const char * const hdmi_sels[] = { |
46 | "clk_dummy" , |
47 | "hdmi_dig_pll_clk" , |
48 | "clk_dummy" , |
49 | "clk_dummy" , |
50 | "hdmi_av_pll_clk" , |
51 | }; |
52 | |
53 | static const char * const hdmi_rx_sels[] = { |
54 | "clk_dummy" , |
55 | "hdmi_rx_dig_pll_clk" , |
56 | "clk_dummy" , |
57 | "clk_dummy" , |
58 | "hdmi_rx_bypass_clk" , |
59 | }; |
60 | |
61 | static const char * const lcd_pxl_sels[] = { |
62 | "clk_dummy" , |
63 | "clk_dummy" , |
64 | "clk_dummy" , |
65 | "clk_dummy" , |
66 | "lcd_pxl_bypass_div_clk" , |
67 | }; |
68 | |
69 | static const char *const lvds0_sels[] = { |
70 | "clk_dummy" , |
71 | "clk_dummy" , |
72 | "clk_dummy" , |
73 | "clk_dummy" , |
74 | "mipi0_lvds_bypass_clk" , |
75 | }; |
76 | |
77 | static const char *const lvds1_sels[] = { |
78 | "clk_dummy" , |
79 | "clk_dummy" , |
80 | "clk_dummy" , |
81 | "clk_dummy" , |
82 | "mipi1_lvds_bypass_clk" , |
83 | }; |
84 | |
85 | static const char * const mipi_sels[] = { |
86 | "clk_dummy" , |
87 | "clk_dummy" , |
88 | "mipi_pll_div2_clk" , |
89 | "clk_dummy" , |
90 | "clk_dummy" , |
91 | }; |
92 | |
93 | static const char * const lcd_sels[] = { |
94 | "clk_dummy" , |
95 | "clk_dummy" , |
96 | "clk_dummy" , |
97 | "clk_dummy" , |
98 | "elcdif_pll" , |
99 | }; |
100 | |
101 | static const char * const pi_pll0_sels[] = { |
102 | "clk_dummy" , |
103 | "pi_dpll_clk" , |
104 | "clk_dummy" , |
105 | "clk_dummy" , |
106 | "clk_dummy" , |
107 | }; |
108 | |
109 | static inline bool clk_on_imx8dxl(struct device_node *node) |
110 | { |
111 | return of_device_is_compatible(device: node, "fsl,imx8dxl-clk" ); |
112 | } |
113 | |
114 | static int imx8qxp_clk_probe(struct platform_device *pdev) |
115 | { |
116 | struct device_node *ccm_node = pdev->dev.of_node; |
117 | const struct imx_clk_scu_rsrc_table *rsrc_table; |
118 | int ret; |
119 | |
120 | rsrc_table = of_device_get_match_data(dev: &pdev->dev); |
121 | ret = imx_clk_scu_init(np: ccm_node, data: rsrc_table); |
122 | if (ret) |
123 | return ret; |
124 | |
125 | /* ARM core */ |
126 | imx_clk_scu(name: "a35_clk" , IMX_SC_R_A35, IMX_SC_PM_CLK_CPU); |
127 | imx_clk_scu(name: "a53_clk" , IMX_SC_R_A53, IMX_SC_PM_CLK_CPU); |
128 | imx_clk_scu(name: "a72_clk" , IMX_SC_R_A72, IMX_SC_PM_CLK_CPU); |
129 | |
130 | /* LSIO SS */ |
131 | imx_clk_scu(name: "pwm0_clk" , IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER); |
132 | imx_clk_scu(name: "pwm1_clk" , IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER); |
133 | imx_clk_scu(name: "pwm2_clk" , IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER); |
134 | imx_clk_scu(name: "pwm3_clk" , IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER); |
135 | imx_clk_scu(name: "pwm4_clk" , IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER); |
136 | imx_clk_scu(name: "pwm5_clk" , IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER); |
137 | imx_clk_scu(name: "pwm6_clk" , IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER); |
138 | imx_clk_scu(name: "pwm7_clk" , IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER); |
139 | imx_clk_scu(name: "gpt0_clk" , IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER); |
140 | imx_clk_scu(name: "gpt1_clk" , IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER); |
141 | imx_clk_scu(name: "gpt2_clk" , IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER); |
142 | imx_clk_scu(name: "gpt3_clk" , IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER); |
143 | imx_clk_scu(name: "gpt4_clk" , IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER); |
144 | imx_clk_scu(name: "fspi0_clk" , IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER); |
145 | imx_clk_scu(name: "fspi1_clk" , IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER); |
146 | |
147 | /* DMA SS */ |
148 | imx_clk_scu(name: "uart0_clk" , IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER); |
149 | imx_clk_scu(name: "uart1_clk" , IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER); |
150 | imx_clk_scu(name: "uart2_clk" , IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER); |
151 | imx_clk_scu(name: "uart3_clk" , IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER); |
152 | imx_clk_scu(name: "uart4_clk" , IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER); |
153 | imx_clk_scu(name: "sim0_clk" , IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER); |
154 | imx_clk_scu(name: "spi0_clk" , IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER); |
155 | imx_clk_scu(name: "spi1_clk" , IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER); |
156 | imx_clk_scu(name: "spi2_clk" , IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER); |
157 | imx_clk_scu(name: "spi3_clk" , IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER); |
158 | imx_clk_scu(name: "can0_clk" , IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER); |
159 | imx_clk_scu(name: "can1_clk" , IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER); |
160 | imx_clk_scu(name: "can2_clk" , IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER); |
161 | imx_clk_scu(name: "i2c0_clk" , IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER); |
162 | imx_clk_scu(name: "i2c1_clk" , IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER); |
163 | imx_clk_scu(name: "i2c2_clk" , IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER); |
164 | imx_clk_scu(name: "i2c3_clk" , IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER); |
165 | imx_clk_scu(name: "i2c4_clk" , IMX_SC_R_I2C_4, IMX_SC_PM_CLK_PER); |
166 | imx_clk_scu(name: "ftm0_clk" , IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER); |
167 | imx_clk_scu(name: "ftm1_clk" , IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER); |
168 | imx_clk_scu(name: "adc0_clk" , IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER); |
169 | imx_clk_scu(name: "adc1_clk" , IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER); |
170 | imx_clk_scu(name: "pwm_clk" , IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER); |
171 | imx_clk_scu(name: "elcdif_pll" , IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL); |
172 | imx_clk_scu2(name: "lcd_clk" , parents: lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER); |
173 | imx_clk_scu2(name: "lcd_pxl_clk" , parents: lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0); |
174 | imx_clk_scu(name: "lcd_pxl_bypass_div_clk" , IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS); |
175 | |
176 | /* Audio SS */ |
177 | imx_clk_scu(name: "audio_pll0_clk" , IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL); |
178 | imx_clk_scu(name: "audio_pll1_clk" , IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL); |
179 | imx_clk_scu(name: "audio_pll_div_clk0_clk" , IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0); |
180 | imx_clk_scu(name: "audio_pll_div_clk1_clk" , IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0); |
181 | imx_clk_scu(name: "audio_rec_clk0_clk" , IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1); |
182 | imx_clk_scu(name: "audio_rec_clk1_clk" , IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1); |
183 | |
184 | /* Connectivity */ |
185 | imx_clk_scu(name: "sdhc0_clk" , IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER); |
186 | imx_clk_scu(name: "sdhc1_clk" , IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER); |
187 | imx_clk_scu(name: "sdhc2_clk" , IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER); |
188 | imx_clk_scu(name: "enet0_root_clk" , IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER); |
189 | imx_clk_divider_gpr_scu(name: "enet0_ref_div" , parent_name: "enet0_root_clk" , IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV); |
190 | imx_clk_mux_gpr_scu(name: "enet0_rgmii_txc_sel" , parent_names: enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK); |
191 | imx_clk_scu(name: "enet0_bypass_clk" , IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS); |
192 | imx_clk_gate_gpr_scu(name: "enet0_ref_50_clk" , parent_name: "clk_dummy" , IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, invert: true); |
193 | if (!clk_on_imx8dxl(node: ccm_node)) { |
194 | imx_clk_scu(name: "enet0_rgmii_rx_clk" , IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0); |
195 | imx_clk_scu(name: "enet1_rgmii_rx_clk" , IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0); |
196 | } |
197 | imx_clk_scu(name: "enet1_root_clk" , IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER); |
198 | imx_clk_divider_gpr_scu(name: "enet1_ref_div" , parent_name: "enet1_root_clk" , IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV); |
199 | imx_clk_mux_gpr_scu(name: "enet1_rgmii_txc_sel" , parent_names: enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK); |
200 | imx_clk_scu(name: "enet1_bypass_clk" , IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS); |
201 | imx_clk_gate_gpr_scu(name: "enet1_ref_50_clk" , parent_name: "clk_dummy" , IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, invert: true); |
202 | imx_clk_scu(name: "gpmi_io_clk" , IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS); |
203 | imx_clk_scu(name: "gpmi_bch_clk" , IMX_SC_R_NAND, IMX_SC_PM_CLK_PER); |
204 | imx_clk_scu(name: "usb3_aclk_div" , IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER); |
205 | imx_clk_scu(name: "usb3_bus_div" , IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS); |
206 | imx_clk_scu(name: "usb3_lpm_div" , IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC); |
207 | |
208 | /* Display controller SS */ |
209 | imx_clk_scu2(name: "dc0_disp0_clk" , parents: dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0); |
210 | imx_clk_scu2(name: "dc0_disp1_clk" , parents: dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1); |
211 | imx_clk_scu(name: "dc0_pll0_clk" , IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL); |
212 | imx_clk_scu(name: "dc0_pll1_clk" , IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL); |
213 | imx_clk_scu(name: "dc0_bypass0_clk" , IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS); |
214 | imx_clk_scu(name: "dc0_bypass1_clk" , IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS); |
215 | |
216 | imx_clk_scu2(name: "dc1_disp0_clk" , parents: dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0); |
217 | imx_clk_scu2(name: "dc1_disp1_clk" , parents: dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1); |
218 | imx_clk_scu(name: "dc1_pll0_clk" , IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL); |
219 | imx_clk_scu(name: "dc1_pll1_clk" , IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL); |
220 | imx_clk_scu(name: "dc1_bypass0_clk" , IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS); |
221 | imx_clk_scu(name: "dc1_bypass1_clk" , IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS); |
222 | |
223 | /* MIPI-LVDS SS */ |
224 | imx_clk_scu(name: "mipi0_bypass_clk" , IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); |
225 | imx_clk_scu(name: "mipi0_pixel_clk" , IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); |
226 | imx_clk_scu(name: "mipi0_lvds_bypass_clk" , IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); |
227 | imx_clk_scu2(name: "mipi0_lvds_pixel_clk" , parents: lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); |
228 | imx_clk_scu2(name: "mipi0_lvds_phy_clk" , parents: lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); |
229 | imx_clk_scu2(name: "mipi0_dsi_tx_esc_clk" , parents: mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); |
230 | imx_clk_scu2(name: "mipi0_dsi_rx_esc_clk" , parents: mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); |
231 | imx_clk_scu2(name: "mipi0_dsi_phy_clk" , parents: mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); |
232 | imx_clk_scu(name: "mipi0_i2c0_clk" , IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2); |
233 | imx_clk_scu(name: "mipi0_i2c1_clk" , IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2); |
234 | imx_clk_scu(name: "mipi0_pwm0_clk" , IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER); |
235 | |
236 | imx_clk_scu(name: "mipi1_bypass_clk" , IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); |
237 | imx_clk_scu(name: "mipi1_pixel_clk" , IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); |
238 | imx_clk_scu(name: "mipi1_lvds_bypass_clk" , IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); |
239 | imx_clk_scu2(name: "mipi1_lvds_pixel_clk" , parents: lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); |
240 | imx_clk_scu2(name: "mipi1_lvds_phy_clk" , parents: lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); |
241 | |
242 | imx_clk_scu2(name: "mipi1_dsi_tx_esc_clk" , parents: mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); |
243 | imx_clk_scu2(name: "mipi1_dsi_rx_esc_clk" , parents: mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); |
244 | imx_clk_scu2(name: "mipi1_dsi_phy_clk" , parents: mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY); |
245 | imx_clk_scu(name: "mipi1_i2c0_clk" , IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2); |
246 | imx_clk_scu(name: "mipi1_i2c1_clk" , IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2); |
247 | imx_clk_scu(name: "mipi1_pwm0_clk" , IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER); |
248 | |
249 | imx_clk_scu(name: "lvds0_i2c0_clk" , IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER); |
250 | imx_clk_scu(name: "lvds0_i2c1_clk" , IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER); |
251 | imx_clk_scu(name: "lvds0_pwm0_clk" , IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER); |
252 | |
253 | imx_clk_scu(name: "lvds1_i2c0_clk" , IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER); |
254 | imx_clk_scu(name: "lvds1_i2c1_clk" , IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER); |
255 | imx_clk_scu(name: "lvds1_pwm0_clk" , IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER); |
256 | |
257 | /* MIPI CSI SS */ |
258 | imx_clk_scu(name: "mipi_csi0_core_clk" , IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER); |
259 | imx_clk_scu(name: "mipi_csi0_esc_clk" , IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC); |
260 | imx_clk_scu(name: "mipi_csi0_i2c0_clk" , IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER); |
261 | imx_clk_scu(name: "mipi_csi0_pwm0_clk" , IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER); |
262 | imx_clk_scu(name: "mipi_csi1_core_clk" , IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER); |
263 | imx_clk_scu(name: "mipi_csi1_esc_clk" , IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC); |
264 | imx_clk_scu(name: "mipi_csi1_i2c0_clk" , IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER); |
265 | imx_clk_scu(name: "mipi_csi1_pwm0_clk" , IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER); |
266 | |
267 | /* Parallel Interface SS */ |
268 | imx_clk_scu(name: "pi_dpll_clk" , IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL); |
269 | imx_clk_scu2(name: "pi_per_div_clk" , parents: pi_pll0_sels, ARRAY_SIZE(pi_pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER); |
270 | imx_clk_scu(name: "pi_mclk_div_clk" , IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0); |
271 | imx_clk_scu(name: "pi_i2c0_div_clk" , IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER); |
272 | |
273 | /* GPU SS */ |
274 | imx_clk_scu(name: "gpu_core0_clk" , IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER); |
275 | imx_clk_scu(name: "gpu_shader0_clk" , IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC); |
276 | |
277 | imx_clk_scu(name: "gpu_core1_clk" , IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER); |
278 | imx_clk_scu(name: "gpu_shader1_clk" , IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC); |
279 | |
280 | /* CM40 SS */ |
281 | imx_clk_scu(name: "cm40_i2c_div" , IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER); |
282 | imx_clk_scu(name: "cm40_lpuart_div" , IMX_SC_R_M4_0_UART, IMX_SC_PM_CLK_PER); |
283 | |
284 | /* CM41 SS */ |
285 | imx_clk_scu(name: "cm41_i2c_div" , IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER); |
286 | |
287 | /* HDMI TX SS */ |
288 | imx_clk_scu(name: "hdmi_dig_pll_clk" , IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL); |
289 | imx_clk_scu(name: "hdmi_av_pll_clk" , IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL); |
290 | imx_clk_scu2(name: "hdmi_pixel_mux_clk" , parents: hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0); |
291 | imx_clk_scu2(name: "hdmi_pixel_link_clk" , parents: hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1); |
292 | imx_clk_scu(name: "hdmi_ipg_clk" , IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4); |
293 | imx_clk_scu(name: "hdmi_i2c0_clk" , IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2); |
294 | imx_clk_scu(name: "hdmi_hdp_core_clk" , IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2); |
295 | imx_clk_scu2(name: "hdmi_pxl_clk" , parents: hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3); |
296 | imx_clk_scu(name: "hdmi_i2s_bypass_clk" , IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS); |
297 | imx_clk_scu(name: "hdmi_i2s_clk" , IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0); |
298 | |
299 | /* HDMI RX SS */ |
300 | imx_clk_scu(name: "hdmi_rx_i2s_bypass_clk" , IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC0); |
301 | imx_clk_scu(name: "hdmi_rx_spdif_bypass_clk" , IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC1); |
302 | imx_clk_scu(name: "hdmi_rx_bypass_clk" , IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC2); |
303 | imx_clk_scu(name: "hdmi_rx_i2c0_clk" , IMX_SC_R_HDMI_RX_I2C_0, IMX_SC_PM_CLK_MISC2); |
304 | imx_clk_scu(name: "hdmi_rx_pwm_clk" , IMX_SC_R_HDMI_RX_PWM_0, IMX_SC_PM_CLK_MISC2); |
305 | imx_clk_scu(name: "hdmi_rx_spdif_clk" , IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC0); |
306 | imx_clk_scu2(name: "hdmi_rx_hd_ref_clk" , parents: hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC1); |
307 | imx_clk_scu2(name: "hdmi_rx_hd_core_clk" , parents: hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC2); |
308 | imx_clk_scu2(name: "hdmi_rx_pxl_clk" , parents: hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC3); |
309 | imx_clk_scu(name: "hdmi_rx_i2s_clk" , IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC4); |
310 | |
311 | ret = of_clk_add_hw_provider(np: ccm_node, get: imx_scu_of_clk_src_get, data: imx_scu_clks); |
312 | if (ret) |
313 | imx_clk_scu_unregister(); |
314 | |
315 | return ret; |
316 | } |
317 | |
318 | static const struct of_device_id imx8qxp_match[] = { |
319 | { .compatible = "fsl,scu-clk" , }, |
320 | { .compatible = "fsl,imx8dxl-clk" , &imx_clk_scu_rsrc_imx8dxl, }, |
321 | { .compatible = "fsl,imx8qxp-clk" , &imx_clk_scu_rsrc_imx8qxp, }, |
322 | { .compatible = "fsl,imx8qm-clk" , &imx_clk_scu_rsrc_imx8qm, }, |
323 | { /* sentinel */ } |
324 | }; |
325 | |
326 | static struct platform_driver imx8qxp_clk_driver = { |
327 | .driver = { |
328 | .name = "imx8qxp-clk" , |
329 | .of_match_table = imx8qxp_match, |
330 | .suppress_bind_attrs = true, |
331 | }, |
332 | .probe = imx8qxp_clk_probe, |
333 | }; |
334 | module_platform_driver(imx8qxp_clk_driver); |
335 | |
336 | MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>" ); |
337 | MODULE_DESCRIPTION("NXP i.MX8QXP clock driver" ); |
338 | MODULE_LICENSE("GPL v2" ); |
339 | |