| 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | /* |
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| 3 | * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org> |
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| 4 | */ |
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| 5 | |
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| 6 | #include <linux/clk-provider.h> |
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| 7 | #include <linux/of.h> |
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| 8 | #include <linux/of_address.h> |
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| 9 | #include <linux/of_device.h> |
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| 10 | #include <linux/platform_device.h> |
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| 11 | #include "clk-mtk.h" |
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| 12 | #include "clk-gate.h" |
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| 13 | #include <dt-bindings/clock/mediatek,mt7988-clk.h> |
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| 14 | |
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| 15 | /* Register to control USXGMII XFI PLL analog */ |
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| 16 | #define XFI_PLL_ANA_GLB8 0x108 |
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| 17 | #define RG_XFI_PLL_ANA_SWWA 0x02283248 |
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| 18 | |
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| 19 | static const struct mtk_gate_regs xfipll_cg_regs = { |
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| 20 | .set_ofs = 0x8, |
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| 21 | .clr_ofs = 0x8, |
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| 22 | .sta_ofs = 0x8, |
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| 23 | }; |
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| 24 | |
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| 25 | #define GATE_XFIPLL(_id, _name, _parent, _shift) \ |
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| 26 | { \ |
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| 27 | .id = _id, \ |
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| 28 | .name = _name, \ |
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| 29 | .parent_name = _parent, \ |
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| 30 | .regs = &xfipll_cg_regs, \ |
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| 31 | .shift = _shift, \ |
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| 32 | .ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
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| 33 | } |
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| 34 | |
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| 35 | static const struct mtk_fixed_factor xfipll_divs[] = { |
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| 36 | FACTOR(CLK_XFIPLL_PLL, "xfipll_pll" , "top_xtal" , 125, 32), |
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| 37 | }; |
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| 38 | |
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| 39 | static const struct mtk_gate xfipll_clks[] = { |
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| 40 | GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en" , "xfipll_pll" , 31), |
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| 41 | }; |
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| 42 | |
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| 43 | static const struct mtk_clk_desc xfipll_desc = { |
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| 44 | .clks = xfipll_clks, |
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| 45 | .num_clks = ARRAY_SIZE(xfipll_clks), |
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| 46 | .factor_clks = xfipll_divs, |
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| 47 | .num_factor_clks = ARRAY_SIZE(xfipll_divs), |
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| 48 | }; |
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| 49 | |
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| 50 | static int clk_mt7988_xfipll_probe(struct platform_device *pdev) |
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| 51 | { |
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| 52 | struct device_node *node = pdev->dev.of_node; |
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| 53 | void __iomem *base = of_iomap(node, index: 0); |
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| 54 | |
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| 55 | if (!base) |
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| 56 | return -ENOMEM; |
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| 57 | |
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| 58 | /* Apply software workaround for USXGMII PLL TCL issue */ |
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| 59 | writel(RG_XFI_PLL_ANA_SWWA, addr: base + XFI_PLL_ANA_GLB8); |
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| 60 | iounmap(addr: base); |
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| 61 | |
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| 62 | return mtk_clk_simple_probe(pdev); |
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| 63 | }; |
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| 64 | |
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| 65 | static const struct of_device_id of_match_clk_mt7988_xfipll[] = { |
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| 66 | { .compatible = "mediatek,mt7988-xfi-pll" , .data = &xfipll_desc }, |
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| 67 | { /* sentinel */ } |
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| 68 | }; |
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| 69 | MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll); |
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| 70 | |
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| 71 | static struct platform_driver clk_mt7988_xfipll_drv = { |
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| 72 | .driver = { |
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| 73 | .name = "clk-mt7988-xfipll" , |
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| 74 | .of_match_table = of_match_clk_mt7988_xfipll, |
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| 75 | }, |
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| 76 | .probe = clk_mt7988_xfipll_probe, |
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| 77 | .remove_new = mtk_clk_simple_remove, |
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| 78 | }; |
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| 79 | module_platform_driver(clk_mt7988_xfipll_drv); |
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| 80 | |
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| 81 | MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver" ); |
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| 82 | MODULE_LICENSE("GPL" ); |
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| 83 | |
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