1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ |
2 | /* |
3 | * Copyright 2015-2016 Freescale Semiconductor Inc. |
4 | * Copyright 2017-2018 NXP |
5 | */ |
6 | |
7 | #ifndef _CAAMALG_QI2_H_ |
8 | #define _CAAMALG_QI2_H_ |
9 | |
10 | #include <crypto/internal/skcipher.h> |
11 | #include <linux/compiler_attributes.h> |
12 | #include <soc/fsl/dpaa2-io.h> |
13 | #include <soc/fsl/dpaa2-fd.h> |
14 | #include <linux/threads.h> |
15 | #include <linux/netdevice.h> |
16 | #include "dpseci.h" |
17 | #include "desc_constr.h" |
18 | |
19 | #define DPAA2_CAAM_STORE_SIZE 16 |
20 | /* NAPI weight *must* be a multiple of the store size. */ |
21 | #define DPAA2_CAAM_NAPI_WEIGHT 512 |
22 | |
23 | /* The congestion entrance threshold was chosen so that on LS2088 |
24 | * we support the maximum throughput for the available memory |
25 | */ |
26 | #define DPAA2_SEC_CONG_ENTRY_THRESH (128 * 1024 * 1024) |
27 | #define DPAA2_SEC_CONG_EXIT_THRESH (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10) |
28 | |
29 | /** |
30 | * dpaa2_caam_priv - driver private data |
31 | * @dpseci_id: DPSECI object unique ID |
32 | * @major_ver: DPSECI major version |
33 | * @minor_ver: DPSECI minor version |
34 | * @dpseci_attr: DPSECI attributes |
35 | * @sec_attr: SEC engine attributes |
36 | * @rx_queue_attr: array of Rx queue attributes |
37 | * @tx_queue_attr: array of Tx queue attributes |
38 | * @cscn_mem: pointer to memory region containing the congestion SCN |
39 | * it's size is larger than to accommodate alignment |
40 | * @cscn_dma: dma address used by the QMAN to write CSCN messages |
41 | * @dev: device associated with the DPSECI object |
42 | * @mc_io: pointer to MC portal's I/O object |
43 | * @domain: IOMMU domain |
44 | * @ppriv: per CPU pointers to privata data |
45 | */ |
46 | struct dpaa2_caam_priv { |
47 | int dpsec_id; |
48 | |
49 | u16 major_ver; |
50 | u16 minor_ver; |
51 | |
52 | struct dpseci_attr dpseci_attr; |
53 | struct dpseci_sec_attr sec_attr; |
54 | struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM]; |
55 | struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM]; |
56 | int num_pairs; |
57 | |
58 | /* congestion */ |
59 | void *cscn_mem; |
60 | dma_addr_t cscn_dma; |
61 | |
62 | struct device *dev; |
63 | struct fsl_mc_io *mc_io; |
64 | struct iommu_domain *domain; |
65 | |
66 | struct dpaa2_caam_priv_per_cpu __percpu *ppriv; |
67 | struct dentry *dfs_root; |
68 | }; |
69 | |
70 | /** |
71 | * dpaa2_caam_priv_per_cpu - per CPU private data |
72 | * @napi: napi structure |
73 | * @net_dev: netdev used by napi |
74 | * @req_fqid: (virtual) request (Tx / enqueue) FQID |
75 | * @rsp_fqid: (virtual) response (Rx / dequeue) FQID |
76 | * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr |
77 | * @nctx: notification context of response FQ |
78 | * @store: where dequeued frames are stored |
79 | * @priv: backpointer to dpaa2_caam_priv |
80 | * @dpio: portal used for data path operations |
81 | */ |
82 | struct dpaa2_caam_priv_per_cpu { |
83 | struct napi_struct napi; |
84 | struct net_device net_dev; |
85 | int req_fqid; |
86 | int rsp_fqid; |
87 | int prio; |
88 | struct dpaa2_io_notification_ctx nctx; |
89 | struct dpaa2_io_store *store; |
90 | struct dpaa2_caam_priv *priv; |
91 | struct dpaa2_io *dpio; |
92 | }; |
93 | |
94 | /* Length of a single buffer in the QI driver memory cache */ |
95 | #define CAAM_QI_MEMCACHE_SIZE 512 |
96 | |
97 | /* |
98 | * aead_edesc - s/w-extended aead descriptor |
99 | * @src_nents: number of segments in input scatterlist |
100 | * @dst_nents: number of segments in output scatterlist |
101 | * @iv_dma: dma address of iv for checking continuity and link table |
102 | * @qm_sg_bytes: length of dma mapped h/w link table |
103 | * @qm_sg_dma: bus physical mapped address of h/w link table |
104 | * @assoclen: associated data length, in CAAM endianness |
105 | * @assoclen_dma: bus physical mapped address of req->assoclen |
106 | * @sgt: the h/w link table, followed by IV |
107 | */ |
108 | struct aead_edesc { |
109 | int src_nents; |
110 | int dst_nents; |
111 | dma_addr_t iv_dma; |
112 | int qm_sg_bytes; |
113 | dma_addr_t qm_sg_dma; |
114 | unsigned int assoclen; |
115 | dma_addr_t assoclen_dma; |
116 | struct dpaa2_sg_entry sgt[]; |
117 | }; |
118 | |
119 | /* |
120 | * skcipher_edesc - s/w-extended skcipher descriptor |
121 | * @src_nents: number of segments in input scatterlist |
122 | * @dst_nents: number of segments in output scatterlist |
123 | * @iv_dma: dma address of iv for checking continuity and link table |
124 | * @qm_sg_bytes: length of dma mapped qm_sg space |
125 | * @qm_sg_dma: I/O virtual address of h/w link table |
126 | * @sgt: the h/w link table, followed by IV |
127 | */ |
128 | struct skcipher_edesc { |
129 | int src_nents; |
130 | int dst_nents; |
131 | dma_addr_t iv_dma; |
132 | int qm_sg_bytes; |
133 | dma_addr_t qm_sg_dma; |
134 | struct dpaa2_sg_entry sgt[]; |
135 | }; |
136 | |
137 | /* |
138 | * ahash_edesc - s/w-extended ahash descriptor |
139 | * @qm_sg_dma: I/O virtual address of h/w link table |
140 | * @src_nents: number of segments in input scatterlist |
141 | * @qm_sg_bytes: length of dma mapped qm_sg space |
142 | * @sgt: pointer to h/w link table |
143 | */ |
144 | struct ahash_edesc { |
145 | dma_addr_t qm_sg_dma; |
146 | int src_nents; |
147 | int qm_sg_bytes; |
148 | struct dpaa2_sg_entry sgt[]; |
149 | }; |
150 | |
151 | /** |
152 | * caam_flc - Flow Context (FLC) |
153 | * @flc: Flow Context options |
154 | * @sh_desc: Shared Descriptor |
155 | */ |
156 | struct caam_flc { |
157 | u32 flc[16]; |
158 | u32 sh_desc[MAX_SDLEN]; |
159 | } __aligned(CRYPTO_DMA_ALIGN); |
160 | |
161 | enum optype { |
162 | ENCRYPT = 0, |
163 | DECRYPT, |
164 | NUM_OP |
165 | }; |
166 | |
167 | /** |
168 | * caam_request - the request structure the driver application should fill while |
169 | * submitting a job to driver. |
170 | * @fd_flt: Frame list table defining input and output |
171 | * fd_flt[0] - FLE pointing to output buffer |
172 | * fd_flt[1] - FLE pointing to input buffer |
173 | * @fd_flt_dma: DMA address for the frame list table |
174 | * @flc: Flow Context |
175 | * @flc_dma: I/O virtual address of Flow Context |
176 | * @cbk: Callback function to invoke when job is completed |
177 | * @ctx: arbit context attached with request by the application |
178 | * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc |
179 | */ |
180 | struct caam_request { |
181 | struct dpaa2_fl_entry fd_flt[2] __aligned(CRYPTO_DMA_ALIGN); |
182 | dma_addr_t fd_flt_dma; |
183 | struct caam_flc *flc; |
184 | dma_addr_t flc_dma; |
185 | void (*cbk)(void *ctx, u32 err); |
186 | void *ctx; |
187 | void *edesc; |
188 | struct skcipher_request fallback_req; |
189 | }; |
190 | |
191 | /** |
192 | * dpaa2_caam_enqueue() - enqueue a crypto request |
193 | * @dev: device associated with the DPSECI object |
194 | * @req: pointer to caam_request |
195 | */ |
196 | int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req); |
197 | |
198 | #endif /* _CAAMALG_QI2_H_ */ |
199 | |