1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel Tangier GPIO driver
4 *
5 * Copyright (c) 2016, 2021, 2023 Intel Corporation.
6 *
7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8 * Pandith N <pandith.n@intel.com>
9 * Raag Jadav <raag.jadav@intel.com>
10 */
11
12#include <linux/bitops.h>
13#include <linux/cleanup.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/export.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/math.h>
21#include <linux/module.h>
22#include <linux/pinctrl/pinconf-generic.h>
23#include <linux/pm.h>
24#include <linux/spinlock.h>
25#include <linux/string_helpers.h>
26#include <linux/types.h>
27
28#include <linux/gpio/driver.h>
29
30#include "gpio-tangier.h"
31
32#define GCCR 0x000 /* Controller configuration */
33#define GPLR 0x004 /* Pin level r/o */
34#define GPDR 0x01c /* Pin direction */
35#define GPSR 0x034 /* Pin set w/o */
36#define GPCR 0x04c /* Pin clear w/o */
37#define GRER 0x064 /* Rising edge detect */
38#define GFER 0x07c /* Falling edge detect */
39#define GFBR 0x094 /* Glitch filter bypass */
40#define GIMR 0x0ac /* Interrupt mask */
41#define GISR 0x0c4 /* Interrupt source */
42#define GITR 0x300 /* Input type */
43#define GLPR 0x318 /* Level input polarity */
44
45/**
46 * struct tng_gpio_context - Context to be saved during suspend-resume
47 * @level: Pin level
48 * @gpdr: Pin direction
49 * @grer: Rising edge detect enable
50 * @gfer: Falling edge detect enable
51 * @gimr: Interrupt mask
52 * @gwmr: Wake mask
53 */
54struct tng_gpio_context {
55 u32 level;
56 u32 gpdr;
57 u32 grer;
58 u32 gfer;
59 u32 gimr;
60 u32 gwmr;
61};
62
63static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
64 unsigned int reg)
65{
66 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
67 u8 reg_offset = offset / 32;
68
69 return priv->reg_base + reg + reg_offset * 4;
70}
71
72static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset,
73 unsigned int reg, u8 *bit)
74{
75 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
76 u8 reg_offset = offset / 32;
77 u8 shift = offset % 32;
78
79 *bit = shift;
80 return priv->reg_base + reg + reg_offset * 4;
81}
82
83static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset)
84{
85 void __iomem *gplr;
86 u8 shift;
87
88 gplr = gpio_reg_and_bit(chip, offset, GPLR, bit: &shift);
89
90 return !!(readl(addr: gplr) & BIT(shift));
91}
92
93static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
94{
95 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
96 void __iomem *reg;
97 u8 shift;
98
99 reg = gpio_reg_and_bit(chip, offset, reg: value ? GPSR : GPCR, bit: &shift);
100
101 guard(raw_spinlock_irqsave)(l: &priv->lock);
102
103 writel(BIT(shift), addr: reg);
104}
105
106static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
107{
108 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
109 void __iomem *gpdr;
110 u32 value;
111 u8 shift;
112
113 gpdr = gpio_reg_and_bit(chip, offset, GPDR, bit: &shift);
114
115 guard(raw_spinlock_irqsave)(l: &priv->lock);
116
117 value = readl(addr: gpdr);
118 value &= ~BIT(shift);
119 writel(val: value, addr: gpdr);
120
121 return 0;
122}
123
124static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
125 int value)
126{
127 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
128 void __iomem *gpdr;
129 u8 shift;
130
131 gpdr = gpio_reg_and_bit(chip, offset, GPDR, bit: &shift);
132 tng_gpio_set(chip, offset, value);
133
134 guard(raw_spinlock_irqsave)(l: &priv->lock);
135
136 value = readl(addr: gpdr);
137 value |= BIT(shift);
138 writel(val: value, addr: gpdr);
139
140 return 0;
141}
142
143static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
144{
145 void __iomem *gpdr;
146 u8 shift;
147
148 gpdr = gpio_reg_and_bit(chip, offset, GPDR, bit: &shift);
149
150 if (readl(addr: gpdr) & BIT(shift))
151 return GPIO_LINE_DIRECTION_OUT;
152
153 return GPIO_LINE_DIRECTION_IN;
154}
155
156static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
157 unsigned int debounce)
158{
159 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
160 void __iomem *gfbr;
161 u32 value;
162 u8 shift;
163
164 gfbr = gpio_reg_and_bit(chip, offset, GFBR, bit: &shift);
165
166 guard(raw_spinlock_irqsave)(l: &priv->lock);
167
168 value = readl(addr: gfbr);
169 if (debounce)
170 value &= ~BIT(shift);
171 else
172 value |= BIT(shift);
173 writel(val: value, addr: gfbr);
174
175 return 0;
176}
177
178static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
179 unsigned long config)
180{
181 u32 debounce;
182
183 switch (pinconf_to_config_param(config)) {
184 case PIN_CONFIG_BIAS_DISABLE:
185 case PIN_CONFIG_BIAS_PULL_UP:
186 case PIN_CONFIG_BIAS_PULL_DOWN:
187 return gpiochip_generic_config(gc: chip, offset, config);
188 case PIN_CONFIG_INPUT_DEBOUNCE:
189 debounce = pinconf_to_config_argument(config);
190 return tng_gpio_set_debounce(chip, offset, debounce);
191 default:
192 return -ENOTSUPP;
193 }
194}
195
196static void tng_irq_ack(struct irq_data *d)
197{
198 struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
199 irq_hw_number_t gpio = irqd_to_hwirq(d);
200 void __iomem *gisr;
201 u8 shift;
202
203 gisr = gpio_reg_and_bit(chip: &priv->chip, offset: gpio, GISR, bit: &shift);
204
205 guard(raw_spinlock_irqsave)(l: &priv->lock);
206
207 writel(BIT(shift), addr: gisr);
208}
209
210static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask)
211{
212 void __iomem *gimr;
213 u32 value;
214 u8 shift;
215
216 gimr = gpio_reg_and_bit(chip: &priv->chip, offset: gpio, GIMR, bit: &shift);
217
218 guard(raw_spinlock_irqsave)(l: &priv->lock);
219
220 value = readl(addr: gimr);
221 if (unmask)
222 value |= BIT(shift);
223 else
224 value &= ~BIT(shift);
225 writel(val: value, addr: gimr);
226}
227
228static void tng_irq_mask(struct irq_data *d)
229{
230 struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
231 irq_hw_number_t gpio = irqd_to_hwirq(d);
232
233 tng_irq_unmask_mask(priv, gpio, unmask: false);
234 gpiochip_disable_irq(gc: &priv->chip, offset: gpio);
235}
236
237static void tng_irq_unmask(struct irq_data *d)
238{
239 struct tng_gpio *priv = irq_data_get_irq_chip_data(d);
240 irq_hw_number_t gpio = irqd_to_hwirq(d);
241
242 gpiochip_enable_irq(gc: &priv->chip, offset: gpio);
243 tng_irq_unmask_mask(priv, gpio, unmask: true);
244}
245
246static int tng_irq_set_type(struct irq_data *d, unsigned int type)
247{
248 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
249 struct tng_gpio *priv = gpiochip_get_data(gc);
250 irq_hw_number_t gpio = irqd_to_hwirq(d);
251 void __iomem *grer = gpio_reg(chip: &priv->chip, offset: gpio, GRER);
252 void __iomem *gfer = gpio_reg(chip: &priv->chip, offset: gpio, GFER);
253 void __iomem *gitr = gpio_reg(chip: &priv->chip, offset: gpio, GITR);
254 void __iomem *glpr = gpio_reg(chip: &priv->chip, offset: gpio, GLPR);
255 u8 shift = gpio % 32;
256 u32 value;
257
258 guard(raw_spinlock_irqsave)(l: &priv->lock);
259
260 value = readl(addr: grer);
261 if (type & IRQ_TYPE_EDGE_RISING)
262 value |= BIT(shift);
263 else
264 value &= ~BIT(shift);
265 writel(val: value, addr: grer);
266
267 value = readl(addr: gfer);
268 if (type & IRQ_TYPE_EDGE_FALLING)
269 value |= BIT(shift);
270 else
271 value &= ~BIT(shift);
272 writel(val: value, addr: gfer);
273
274 /*
275 * To prevent glitches from triggering an unintended level interrupt,
276 * configure GLPR register first and then configure GITR.
277 */
278 value = readl(addr: glpr);
279 if (type & IRQ_TYPE_LEVEL_LOW)
280 value |= BIT(shift);
281 else
282 value &= ~BIT(shift);
283 writel(val: value, addr: glpr);
284
285 if (type & IRQ_TYPE_LEVEL_MASK) {
286 value = readl(addr: gitr);
287 value |= BIT(shift);
288 writel(val: value, addr: gitr);
289
290 irq_set_handler_locked(data: d, handler: handle_level_irq);
291 } else if (type & IRQ_TYPE_EDGE_BOTH) {
292 value = readl(addr: gitr);
293 value &= ~BIT(shift);
294 writel(val: value, addr: gitr);
295
296 irq_set_handler_locked(data: d, handler: handle_edge_irq);
297 }
298
299 return 0;
300}
301
302static int tng_irq_set_wake(struct irq_data *d, unsigned int on)
303{
304 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
305 struct tng_gpio *priv = gpiochip_get_data(gc);
306 irq_hw_number_t gpio = irqd_to_hwirq(d);
307 void __iomem *gwmr = gpio_reg(chip: &priv->chip, offset: gpio, reg: priv->wake_regs.gwmr);
308 void __iomem *gwsr = gpio_reg(chip: &priv->chip, offset: gpio, reg: priv->wake_regs.gwsr);
309 u8 shift = gpio % 32;
310 u32 value;
311
312 dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio);
313
314 guard(raw_spinlock_irqsave)(l: &priv->lock);
315
316 /* Clear the existing wake status */
317 writel(BIT(shift), addr: gwsr);
318
319 value = readl(addr: gwmr);
320 if (on)
321 value |= BIT(shift);
322 else
323 value &= ~BIT(shift);
324 writel(val: value, addr: gwmr);
325
326 return 0;
327}
328
329static const struct irq_chip tng_irqchip = {
330 .name = "gpio-tangier",
331 .irq_ack = tng_irq_ack,
332 .irq_mask = tng_irq_mask,
333 .irq_unmask = tng_irq_unmask,
334 .irq_set_type = tng_irq_set_type,
335 .irq_set_wake = tng_irq_set_wake,
336 .flags = IRQCHIP_IMMUTABLE,
337 GPIOCHIP_IRQ_RESOURCE_HELPERS,
338};
339
340static void tng_irq_handler(struct irq_desc *desc)
341{
342 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
343 struct tng_gpio *priv = gpiochip_get_data(gc);
344 struct irq_chip *irqchip = irq_desc_get_chip(desc);
345 unsigned long base, gpio;
346
347 chained_irq_enter(chip: irqchip, desc);
348
349 /* Check GPIO controller to check which pin triggered the interrupt */
350 for (base = 0; base < priv->chip.ngpio; base += 32) {
351 void __iomem *gisr = gpio_reg(chip: &priv->chip, offset: base, GISR);
352 void __iomem *gimr = gpio_reg(chip: &priv->chip, offset: base, GIMR);
353 unsigned long pending, enabled;
354
355 pending = readl(addr: gisr);
356 enabled = readl(addr: gimr);
357
358 /* Only interrupts that are enabled */
359 pending &= enabled;
360
361 for_each_set_bit(gpio, &pending, 32)
362 generic_handle_domain_irq(domain: gc->irq.domain, hwirq: base + gpio);
363 }
364
365 chained_irq_exit(chip: irqchip, desc);
366}
367
368static int tng_irq_init_hw(struct gpio_chip *chip)
369{
370 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
371 void __iomem *reg;
372 unsigned int base;
373
374 for (base = 0; base < priv->chip.ngpio; base += 32) {
375 /* Clear the rising-edge detect register */
376 reg = gpio_reg(chip: &priv->chip, offset: base, GRER);
377 writel(val: 0, addr: reg);
378
379 /* Clear the falling-edge detect register */
380 reg = gpio_reg(chip: &priv->chip, offset: base, GFER);
381 writel(val: 0, addr: reg);
382 }
383
384 return 0;
385}
386
387static int tng_gpio_add_pin_ranges(struct gpio_chip *chip)
388{
389 struct tng_gpio *priv = gpiochip_get_data(gc: chip);
390 const struct tng_gpio_pinrange *range;
391 unsigned int i;
392 int ret;
393
394 for (i = 0; i < priv->pin_info.nranges; i++) {
395 range = &priv->pin_info.pin_ranges[i];
396 ret = gpiochip_add_pin_range(gc: &priv->chip,
397 pinctl_name: priv->pin_info.name,
398 gpio_offset: range->gpio_base,
399 pin_offset: range->pin_base,
400 npins: range->npins);
401 if (ret) {
402 dev_err(priv->dev, "failed to add GPIO pin range\n");
403 return ret;
404 }
405 }
406
407 return 0;
408}
409
410int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio)
411{
412 const struct tng_gpio_info *info = &gpio->info;
413 size_t nctx = DIV_ROUND_UP(info->ngpio, 32);
414 struct gpio_irq_chip *girq;
415 int ret;
416
417 gpio->ctx = devm_kcalloc(dev, n: nctx, size: sizeof(*gpio->ctx), GFP_KERNEL);
418 if (!gpio->ctx)
419 return -ENOMEM;
420
421 gpio->chip.label = dev_name(dev);
422 gpio->chip.parent = dev;
423 gpio->chip.request = gpiochip_generic_request;
424 gpio->chip.free = gpiochip_generic_free;
425 gpio->chip.direction_input = tng_gpio_direction_input;
426 gpio->chip.direction_output = tng_gpio_direction_output;
427 gpio->chip.get = tng_gpio_get;
428 gpio->chip.set = tng_gpio_set;
429 gpio->chip.get_direction = tng_gpio_get_direction;
430 gpio->chip.set_config = tng_gpio_set_config;
431 gpio->chip.base = info->base;
432 gpio->chip.ngpio = info->ngpio;
433 gpio->chip.can_sleep = false;
434 gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges;
435
436 raw_spin_lock_init(&gpio->lock);
437
438 girq = &gpio->chip.irq;
439 gpio_irq_chip_set_chip(girq, chip: &tng_irqchip);
440 girq->init_hw = tng_irq_init_hw;
441 girq->parent_handler = tng_irq_handler;
442 girq->num_parents = 1;
443 girq->parents = devm_kcalloc(dev, n: girq->num_parents,
444 size: sizeof(*girq->parents), GFP_KERNEL);
445 if (!girq->parents)
446 return -ENOMEM;
447
448 girq->parents[0] = gpio->irq;
449 girq->first = info->first;
450 girq->default_type = IRQ_TYPE_NONE;
451 girq->handler = handle_bad_irq;
452
453 ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio);
454 if (ret)
455 return dev_err_probe(dev, err: ret, fmt: "gpiochip_add error\n");
456
457 return 0;
458}
459EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER);
460
461static int tng_gpio_suspend(struct device *dev)
462{
463 struct tng_gpio *priv = dev_get_drvdata(dev);
464 struct tng_gpio_context *ctx = priv->ctx;
465 unsigned int base;
466
467 guard(raw_spinlock_irqsave)(l: &priv->lock);
468
469 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
470 /* GPLR is RO, values read will be restored using GPSR */
471 ctx->level = readl(addr: gpio_reg(chip: &priv->chip, offset: base, GPLR));
472
473 ctx->gpdr = readl(addr: gpio_reg(chip: &priv->chip, offset: base, GPDR));
474 ctx->grer = readl(addr: gpio_reg(chip: &priv->chip, offset: base, GRER));
475 ctx->gfer = readl(addr: gpio_reg(chip: &priv->chip, offset: base, GFER));
476 ctx->gimr = readl(addr: gpio_reg(chip: &priv->chip, offset: base, GIMR));
477
478 ctx->gwmr = readl(addr: gpio_reg(chip: &priv->chip, offset: base, reg: priv->wake_regs.gwmr));
479 }
480
481 return 0;
482}
483
484static int tng_gpio_resume(struct device *dev)
485{
486 struct tng_gpio *priv = dev_get_drvdata(dev);
487 struct tng_gpio_context *ctx = priv->ctx;
488 unsigned int base;
489
490 guard(raw_spinlock_irqsave)(l: &priv->lock);
491
492 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) {
493 /* GPLR is RO, values read will be restored using GPSR */
494 writel(val: ctx->level, addr: gpio_reg(chip: &priv->chip, offset: base, GPSR));
495
496 writel(val: ctx->gpdr, addr: gpio_reg(chip: &priv->chip, offset: base, GPDR));
497 writel(val: ctx->grer, addr: gpio_reg(chip: &priv->chip, offset: base, GRER));
498 writel(val: ctx->gfer, addr: gpio_reg(chip: &priv->chip, offset: base, GFER));
499 writel(val: ctx->gimr, addr: gpio_reg(chip: &priv->chip, offset: base, GIMR));
500
501 writel(val: ctx->gwmr, addr: gpio_reg(chip: &priv->chip, offset: base, reg: priv->wake_regs.gwmr));
502 }
503
504 return 0;
505}
506
507EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS(tng_gpio_pm_ops, tng_gpio_suspend, tng_gpio_resume, GPIO_TANGIER);
508
509MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
510MODULE_AUTHOR("Pandith N <pandith.n@intel.com>");
511MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>");
512MODULE_DESCRIPTION("Intel Tangier GPIO driver");
513MODULE_LICENSE("GPL");
514

source code of linux/drivers/gpio/gpio-tangier.c