1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Xilinx gpio driver for xps/axi_gpio IP. |
4 | * |
5 | * Copyright 2008 - 2013 Xilinx, Inc. |
6 | */ |
7 | |
8 | #include <linux/bitmap.h> |
9 | #include <linux/bitops.h> |
10 | #include <linux/clk.h> |
11 | #include <linux/errno.h> |
12 | #include <linux/gpio/driver.h> |
13 | #include <linux/init.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/io.h> |
16 | #include <linux/irq.h> |
17 | #include <linux/module.h> |
18 | #include <linux/of.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/pm_runtime.h> |
21 | #include <linux/slab.h> |
22 | |
23 | /* Register Offset Definitions */ |
24 | #define XGPIO_DATA_OFFSET (0x0) /* Data register */ |
25 | #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ |
26 | |
27 | #define XGPIO_CHANNEL0_OFFSET 0x0 |
28 | #define XGPIO_CHANNEL1_OFFSET 0x8 |
29 | |
30 | #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ |
31 | #define XGPIO_GIER_IE BIT(31) |
32 | #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ |
33 | #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ |
34 | |
35 | /* Read/Write access to the GPIO registers */ |
36 | #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) |
37 | # define xgpio_readreg(offset) readl(offset) |
38 | # define xgpio_writereg(offset, val) writel(val, offset) |
39 | #else |
40 | # define xgpio_readreg(offset) __raw_readl(offset) |
41 | # define xgpio_writereg(offset, val) __raw_writel(val, offset) |
42 | #endif |
43 | |
44 | /** |
45 | * struct xgpio_instance - Stores information about GPIO device |
46 | * @gc: GPIO chip |
47 | * @regs: register block |
48 | * @hw_map: GPIO pin mapping on hardware side |
49 | * @sw_map: GPIO pin mapping on software side |
50 | * @state: GPIO write state shadow register |
51 | * @last_irq_read: GPIO read state register from last interrupt |
52 | * @dir: GPIO direction shadow register |
53 | * @gpio_lock: Lock used for synchronization |
54 | * @irq: IRQ used by GPIO device |
55 | * @enable: GPIO IRQ enable/disable bitfield |
56 | * @rising_edge: GPIO IRQ rising edge enable/disable bitfield |
57 | * @falling_edge: GPIO IRQ falling edge enable/disable bitfield |
58 | * @clk: clock resource for this driver |
59 | */ |
60 | struct xgpio_instance { |
61 | struct gpio_chip gc; |
62 | void __iomem *regs; |
63 | DECLARE_BITMAP(hw_map, 64); |
64 | DECLARE_BITMAP(sw_map, 64); |
65 | DECLARE_BITMAP(state, 64); |
66 | DECLARE_BITMAP(last_irq_read, 64); |
67 | DECLARE_BITMAP(dir, 64); |
68 | spinlock_t gpio_lock; /* For serializing operations */ |
69 | int irq; |
70 | DECLARE_BITMAP(enable, 64); |
71 | DECLARE_BITMAP(rising_edge, 64); |
72 | DECLARE_BITMAP(falling_edge, 64); |
73 | struct clk *clk; |
74 | }; |
75 | |
76 | static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit) |
77 | { |
78 | return bitmap_bitremap(oldbit: bit, old: chip->hw_map, new: chip->sw_map, bits: 64); |
79 | } |
80 | |
81 | static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio) |
82 | { |
83 | return bitmap_bitremap(oldbit: gpio, old: chip->sw_map, new: chip->hw_map, bits: 64); |
84 | } |
85 | |
86 | static inline u32 xgpio_get_value32(const unsigned long *map, int bit) |
87 | { |
88 | const size_t index = BIT_WORD(bit); |
89 | const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); |
90 | |
91 | return (map[index] >> offset) & 0xFFFFFFFFul; |
92 | } |
93 | |
94 | static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v) |
95 | { |
96 | const size_t index = BIT_WORD(bit); |
97 | const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5); |
98 | |
99 | map[index] &= ~(0xFFFFFFFFul << offset); |
100 | map[index] |= (unsigned long)v << offset; |
101 | } |
102 | |
103 | static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) |
104 | { |
105 | switch (ch) { |
106 | case 0: |
107 | return XGPIO_CHANNEL0_OFFSET; |
108 | case 1: |
109 | return XGPIO_CHANNEL1_OFFSET; |
110 | default: |
111 | return -EINVAL; |
112 | } |
113 | } |
114 | |
115 | static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) |
116 | { |
117 | void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, ch: bit / 32); |
118 | |
119 | xgpio_set_value32(map: a, bit, xgpio_readreg(addr)); |
120 | } |
121 | |
122 | static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) |
123 | { |
124 | void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, ch: bit / 32); |
125 | |
126 | xgpio_writereg(addr, xgpio_get_value32(a, bit)); |
127 | } |
128 | |
129 | static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) |
130 | { |
131 | int bit, lastbit = xgpio_to_bit(chip, gpio: chip->gc.ngpio - 1); |
132 | |
133 | for (bit = 0; bit <= lastbit ; bit += 32) |
134 | xgpio_read_ch(chip, reg, bit, a); |
135 | } |
136 | |
137 | static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) |
138 | { |
139 | int bit, lastbit = xgpio_to_bit(chip, gpio: chip->gc.ngpio - 1); |
140 | |
141 | for (bit = 0; bit <= lastbit ; bit += 32) |
142 | xgpio_write_ch(chip, reg, bit, a); |
143 | } |
144 | |
145 | /** |
146 | * xgpio_get - Read the specified signal of the GPIO device. |
147 | * @gc: Pointer to gpio_chip device structure. |
148 | * @gpio: GPIO signal number. |
149 | * |
150 | * This function reads the specified signal of the GPIO device. |
151 | * |
152 | * Return: |
153 | * 0 if direction of GPIO signals is set as input otherwise it |
154 | * returns negative error value. |
155 | */ |
156 | static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) |
157 | { |
158 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
159 | int bit = xgpio_to_bit(chip, gpio); |
160 | DECLARE_BITMAP(state, 64); |
161 | |
162 | xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, a: state); |
163 | |
164 | return test_bit(bit, state); |
165 | } |
166 | |
167 | /** |
168 | * xgpio_set - Write the specified signal of the GPIO device. |
169 | * @gc: Pointer to gpio_chip device structure. |
170 | * @gpio: GPIO signal number. |
171 | * @val: Value to be written to specified signal. |
172 | * |
173 | * This function writes the specified value in to the specified signal of the |
174 | * GPIO device. |
175 | */ |
176 | static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
177 | { |
178 | unsigned long flags; |
179 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
180 | int bit = xgpio_to_bit(chip, gpio); |
181 | |
182 | spin_lock_irqsave(&chip->gpio_lock, flags); |
183 | |
184 | /* Write to GPIO signal and set its direction to output */ |
185 | __assign_bit(nr: bit, addr: chip->state, value: val); |
186 | |
187 | xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, a: chip->state); |
188 | |
189 | spin_unlock_irqrestore(lock: &chip->gpio_lock, flags); |
190 | } |
191 | |
192 | /** |
193 | * xgpio_set_multiple - Write the specified signals of the GPIO device. |
194 | * @gc: Pointer to gpio_chip device structure. |
195 | * @mask: Mask of the GPIOS to modify. |
196 | * @bits: Value to be wrote on each GPIO |
197 | * |
198 | * This function writes the specified values into the specified signals of the |
199 | * GPIO devices. |
200 | */ |
201 | static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, |
202 | unsigned long *bits) |
203 | { |
204 | DECLARE_BITMAP(hw_mask, 64); |
205 | DECLARE_BITMAP(hw_bits, 64); |
206 | DECLARE_BITMAP(state, 64); |
207 | unsigned long flags; |
208 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
209 | |
210 | bitmap_remap(dst: hw_mask, src: mask, old: chip->sw_map, new: chip->hw_map, nbits: 64); |
211 | bitmap_remap(dst: hw_bits, src: bits, old: chip->sw_map, new: chip->hw_map, nbits: 64); |
212 | |
213 | spin_lock_irqsave(&chip->gpio_lock, flags); |
214 | |
215 | bitmap_replace(dst: state, old: chip->state, new: hw_bits, mask: hw_mask, nbits: 64); |
216 | |
217 | xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, a: state); |
218 | |
219 | bitmap_copy(dst: chip->state, src: state, nbits: 64); |
220 | |
221 | spin_unlock_irqrestore(lock: &chip->gpio_lock, flags); |
222 | } |
223 | |
224 | /** |
225 | * xgpio_dir_in - Set the direction of the specified GPIO signal as input. |
226 | * @gc: Pointer to gpio_chip device structure. |
227 | * @gpio: GPIO signal number. |
228 | * |
229 | * Return: |
230 | * 0 - if direction of GPIO signals is set as input |
231 | * otherwise it returns negative error value. |
232 | */ |
233 | static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
234 | { |
235 | unsigned long flags; |
236 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
237 | int bit = xgpio_to_bit(chip, gpio); |
238 | |
239 | spin_lock_irqsave(&chip->gpio_lock, flags); |
240 | |
241 | /* Set the GPIO bit in shadow register and set direction as input */ |
242 | __set_bit(bit, chip->dir); |
243 | xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, a: chip->dir); |
244 | |
245 | spin_unlock_irqrestore(lock: &chip->gpio_lock, flags); |
246 | |
247 | return 0; |
248 | } |
249 | |
250 | /** |
251 | * xgpio_dir_out - Set the direction of the specified GPIO signal as output. |
252 | * @gc: Pointer to gpio_chip device structure. |
253 | * @gpio: GPIO signal number. |
254 | * @val: Value to be written to specified signal. |
255 | * |
256 | * This function sets the direction of specified GPIO signal as output. |
257 | * |
258 | * Return: |
259 | * If all GPIO signals of GPIO chip is configured as input then it returns |
260 | * error otherwise it returns 0. |
261 | */ |
262 | static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
263 | { |
264 | unsigned long flags; |
265 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
266 | int bit = xgpio_to_bit(chip, gpio); |
267 | |
268 | spin_lock_irqsave(&chip->gpio_lock, flags); |
269 | |
270 | /* Write state of GPIO signal */ |
271 | __assign_bit(nr: bit, addr: chip->state, value: val); |
272 | xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, a: chip->state); |
273 | |
274 | /* Clear the GPIO bit in shadow register and set direction as output */ |
275 | __clear_bit(bit, chip->dir); |
276 | xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, a: chip->dir); |
277 | |
278 | spin_unlock_irqrestore(lock: &chip->gpio_lock, flags); |
279 | |
280 | return 0; |
281 | } |
282 | |
283 | /** |
284 | * xgpio_save_regs - Set initial values of GPIO pins |
285 | * @chip: Pointer to GPIO instance |
286 | */ |
287 | static void xgpio_save_regs(struct xgpio_instance *chip) |
288 | { |
289 | xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, a: chip->state); |
290 | xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, a: chip->dir); |
291 | } |
292 | |
293 | static int xgpio_request(struct gpio_chip *chip, unsigned int offset) |
294 | { |
295 | int ret; |
296 | |
297 | ret = pm_runtime_get_sync(dev: chip->parent); |
298 | /* |
299 | * If the device is already active pm_runtime_get() will return 1 on |
300 | * success, but gpio_request still needs to return 0. |
301 | */ |
302 | return ret < 0 ? ret : 0; |
303 | } |
304 | |
305 | static void xgpio_free(struct gpio_chip *chip, unsigned int offset) |
306 | { |
307 | pm_runtime_put(dev: chip->parent); |
308 | } |
309 | |
310 | static int __maybe_unused xgpio_suspend(struct device *dev) |
311 | { |
312 | struct xgpio_instance *gpio = dev_get_drvdata(dev); |
313 | struct irq_data *data = irq_get_irq_data(irq: gpio->irq); |
314 | |
315 | if (!data) { |
316 | dev_dbg(dev, "IRQ not connected\n" ); |
317 | return pm_runtime_force_suspend(dev); |
318 | } |
319 | |
320 | if (!irqd_is_wakeup_set(d: data)) |
321 | return pm_runtime_force_suspend(dev); |
322 | |
323 | return 0; |
324 | } |
325 | |
326 | /** |
327 | * xgpio_remove - Remove method for the GPIO device. |
328 | * @pdev: pointer to the platform device |
329 | * |
330 | * This function remove gpiochips and frees all the allocated resources. |
331 | * |
332 | * Return: 0 always |
333 | */ |
334 | static void xgpio_remove(struct platform_device *pdev) |
335 | { |
336 | struct xgpio_instance *gpio = platform_get_drvdata(pdev); |
337 | |
338 | pm_runtime_get_sync(dev: &pdev->dev); |
339 | pm_runtime_put_noidle(dev: &pdev->dev); |
340 | pm_runtime_disable(dev: &pdev->dev); |
341 | clk_disable_unprepare(clk: gpio->clk); |
342 | } |
343 | |
344 | /** |
345 | * xgpio_irq_ack - Acknowledge a child GPIO interrupt. |
346 | * @irq_data: per IRQ and chip data passed down to chip functions |
347 | * This currently does nothing, but irq_ack is unconditionally called by |
348 | * handle_edge_irq and therefore must be defined. |
349 | */ |
350 | static void xgpio_irq_ack(struct irq_data *irq_data) |
351 | { |
352 | } |
353 | |
354 | static int __maybe_unused xgpio_resume(struct device *dev) |
355 | { |
356 | struct xgpio_instance *gpio = dev_get_drvdata(dev); |
357 | struct irq_data *data = irq_get_irq_data(irq: gpio->irq); |
358 | |
359 | if (!data) { |
360 | dev_dbg(dev, "IRQ not connected\n" ); |
361 | return pm_runtime_force_resume(dev); |
362 | } |
363 | |
364 | if (!irqd_is_wakeup_set(d: data)) |
365 | return pm_runtime_force_resume(dev); |
366 | |
367 | return 0; |
368 | } |
369 | |
370 | static int __maybe_unused xgpio_runtime_suspend(struct device *dev) |
371 | { |
372 | struct xgpio_instance *gpio = dev_get_drvdata(dev); |
373 | |
374 | clk_disable(clk: gpio->clk); |
375 | |
376 | return 0; |
377 | } |
378 | |
379 | static int __maybe_unused xgpio_runtime_resume(struct device *dev) |
380 | { |
381 | struct xgpio_instance *gpio = dev_get_drvdata(dev); |
382 | |
383 | return clk_enable(clk: gpio->clk); |
384 | } |
385 | |
386 | static const struct dev_pm_ops xgpio_dev_pm_ops = { |
387 | SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) |
388 | SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, |
389 | xgpio_runtime_resume, NULL) |
390 | }; |
391 | |
392 | /** |
393 | * xgpio_irq_mask - Write the specified signal of the GPIO device. |
394 | * @irq_data: per IRQ and chip data passed down to chip functions |
395 | */ |
396 | static void xgpio_irq_mask(struct irq_data *irq_data) |
397 | { |
398 | unsigned long flags; |
399 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(d: irq_data); |
400 | int irq_offset = irqd_to_hwirq(d: irq_data); |
401 | int bit = xgpio_to_bit(chip, gpio: irq_offset); |
402 | u32 mask = BIT(bit / 32), temp; |
403 | |
404 | spin_lock_irqsave(&chip->gpio_lock, flags); |
405 | |
406 | __clear_bit(bit, chip->enable); |
407 | |
408 | if (xgpio_get_value32(map: chip->enable, bit) == 0) { |
409 | /* Disable per channel interrupt */ |
410 | temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); |
411 | temp &= ~mask; |
412 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); |
413 | } |
414 | spin_unlock_irqrestore(lock: &chip->gpio_lock, flags); |
415 | |
416 | gpiochip_disable_irq(gc: &chip->gc, offset: irq_offset); |
417 | } |
418 | |
419 | /** |
420 | * xgpio_irq_unmask - Write the specified signal of the GPIO device. |
421 | * @irq_data: per IRQ and chip data passed down to chip functions |
422 | */ |
423 | static void xgpio_irq_unmask(struct irq_data *irq_data) |
424 | { |
425 | unsigned long flags; |
426 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(d: irq_data); |
427 | int irq_offset = irqd_to_hwirq(d: irq_data); |
428 | int bit = xgpio_to_bit(chip, gpio: irq_offset); |
429 | u32 old_enable = xgpio_get_value32(map: chip->enable, bit); |
430 | u32 mask = BIT(bit / 32), val; |
431 | |
432 | gpiochip_enable_irq(gc: &chip->gc, offset: irq_offset); |
433 | |
434 | spin_lock_irqsave(&chip->gpio_lock, flags); |
435 | |
436 | __set_bit(bit, chip->enable); |
437 | |
438 | if (old_enable == 0) { |
439 | /* Clear any existing per-channel interrupts */ |
440 | val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
441 | val &= mask; |
442 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); |
443 | |
444 | /* Update GPIO IRQ read data before enabling interrupt*/ |
445 | xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, a: chip->last_irq_read); |
446 | |
447 | /* Enable per channel interrupt */ |
448 | val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); |
449 | val |= mask; |
450 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); |
451 | } |
452 | |
453 | spin_unlock_irqrestore(lock: &chip->gpio_lock, flags); |
454 | } |
455 | |
456 | /** |
457 | * xgpio_set_irq_type - Write the specified signal of the GPIO device. |
458 | * @irq_data: Per IRQ and chip data passed down to chip functions |
459 | * @type: Interrupt type that is to be set for the gpio pin |
460 | * |
461 | * Return: |
462 | * 0 if interrupt type is supported otherwise -EINVAL |
463 | */ |
464 | static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) |
465 | { |
466 | struct xgpio_instance *chip = irq_data_get_irq_chip_data(d: irq_data); |
467 | int irq_offset = irqd_to_hwirq(d: irq_data); |
468 | int bit = xgpio_to_bit(chip, gpio: irq_offset); |
469 | |
470 | /* |
471 | * The Xilinx GPIO hardware provides a single interrupt status |
472 | * indication for any state change in a given GPIO channel (bank). |
473 | * Therefore, only rising edge or falling edge triggers are |
474 | * supported. |
475 | */ |
476 | switch (type & IRQ_TYPE_SENSE_MASK) { |
477 | case IRQ_TYPE_EDGE_BOTH: |
478 | __set_bit(bit, chip->rising_edge); |
479 | __set_bit(bit, chip->falling_edge); |
480 | break; |
481 | case IRQ_TYPE_EDGE_RISING: |
482 | __set_bit(bit, chip->rising_edge); |
483 | __clear_bit(bit, chip->falling_edge); |
484 | break; |
485 | case IRQ_TYPE_EDGE_FALLING: |
486 | __clear_bit(bit, chip->rising_edge); |
487 | __set_bit(bit, chip->falling_edge); |
488 | break; |
489 | default: |
490 | return -EINVAL; |
491 | } |
492 | |
493 | irq_set_handler_locked(data: irq_data, handler: handle_edge_irq); |
494 | return 0; |
495 | } |
496 | |
497 | /** |
498 | * xgpio_irqhandler - Gpio interrupt service routine |
499 | * @desc: Pointer to interrupt description |
500 | */ |
501 | static void xgpio_irqhandler(struct irq_desc *desc) |
502 | { |
503 | struct xgpio_instance *chip = irq_desc_get_handler_data(desc); |
504 | struct gpio_chip *gc = &chip->gc; |
505 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
506 | DECLARE_BITMAP(rising, 64); |
507 | DECLARE_BITMAP(falling, 64); |
508 | DECLARE_BITMAP(all, 64); |
509 | int irq_offset; |
510 | u32 status; |
511 | u32 bit; |
512 | |
513 | status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
514 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); |
515 | |
516 | chained_irq_enter(chip: irqchip, desc); |
517 | |
518 | spin_lock(lock: &chip->gpio_lock); |
519 | |
520 | xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, a: all); |
521 | |
522 | bitmap_complement(dst: rising, src: chip->last_irq_read, nbits: 64); |
523 | bitmap_and(dst: rising, src1: rising, src2: all, nbits: 64); |
524 | bitmap_and(dst: rising, src1: rising, src2: chip->enable, nbits: 64); |
525 | bitmap_and(dst: rising, src1: rising, src2: chip->rising_edge, nbits: 64); |
526 | |
527 | bitmap_complement(dst: falling, src: all, nbits: 64); |
528 | bitmap_and(dst: falling, src1: falling, src2: chip->last_irq_read, nbits: 64); |
529 | bitmap_and(dst: falling, src1: falling, src2: chip->enable, nbits: 64); |
530 | bitmap_and(dst: falling, src1: falling, src2: chip->falling_edge, nbits: 64); |
531 | |
532 | bitmap_copy(dst: chip->last_irq_read, src: all, nbits: 64); |
533 | bitmap_or(dst: all, src1: rising, src2: falling, nbits: 64); |
534 | |
535 | spin_unlock(lock: &chip->gpio_lock); |
536 | |
537 | dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n" , 64, rising, 64, falling); |
538 | |
539 | for_each_set_bit(bit, all, 64) { |
540 | irq_offset = xgpio_from_bit(chip, bit); |
541 | generic_handle_domain_irq(domain: gc->irq.domain, hwirq: irq_offset); |
542 | } |
543 | |
544 | chained_irq_exit(chip: irqchip, desc); |
545 | } |
546 | |
547 | static const struct irq_chip xgpio_irq_chip = { |
548 | .name = "gpio-xilinx" , |
549 | .irq_ack = xgpio_irq_ack, |
550 | .irq_mask = xgpio_irq_mask, |
551 | .irq_unmask = xgpio_irq_unmask, |
552 | .irq_set_type = xgpio_set_irq_type, |
553 | .flags = IRQCHIP_IMMUTABLE, |
554 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
555 | }; |
556 | |
557 | /** |
558 | * xgpio_probe - Probe method for the GPIO device. |
559 | * @pdev: pointer to the platform device |
560 | * |
561 | * Return: |
562 | * It returns 0, if the driver is bound to the GPIO device, or |
563 | * a negative value if there is an error. |
564 | */ |
565 | static int xgpio_probe(struct platform_device *pdev) |
566 | { |
567 | struct xgpio_instance *chip; |
568 | int status = 0; |
569 | struct device_node *np = pdev->dev.of_node; |
570 | u32 is_dual = 0; |
571 | u32 width[2]; |
572 | u32 state[2]; |
573 | u32 dir[2]; |
574 | struct gpio_irq_chip *girq; |
575 | u32 temp; |
576 | |
577 | chip = devm_kzalloc(dev: &pdev->dev, size: sizeof(*chip), GFP_KERNEL); |
578 | if (!chip) |
579 | return -ENOMEM; |
580 | |
581 | platform_set_drvdata(pdev, data: chip); |
582 | |
583 | /* First, check if the device is dual-channel */ |
584 | of_property_read_u32(np, propname: "xlnx,is-dual" , out_value: &is_dual); |
585 | |
586 | /* Setup defaults */ |
587 | memset32(s: width, v: 0, ARRAY_SIZE(width)); |
588 | memset32(s: state, v: 0, ARRAY_SIZE(state)); |
589 | memset32(s: dir, v: 0xFFFFFFFF, ARRAY_SIZE(dir)); |
590 | |
591 | /* Update GPIO state shadow register with default value */ |
592 | of_property_read_u32(np, propname: "xlnx,dout-default" , out_value: &state[0]); |
593 | of_property_read_u32(np, propname: "xlnx,dout-default-2" , out_value: &state[1]); |
594 | |
595 | bitmap_from_arr32(bitmap: chip->state, buf: state, nbits: 64); |
596 | |
597 | /* Update GPIO direction shadow register with default value */ |
598 | of_property_read_u32(np, propname: "xlnx,tri-default" , out_value: &dir[0]); |
599 | of_property_read_u32(np, propname: "xlnx,tri-default-2" , out_value: &dir[1]); |
600 | |
601 | bitmap_from_arr32(bitmap: chip->dir, buf: dir, nbits: 64); |
602 | |
603 | /* |
604 | * Check device node and parent device node for device width |
605 | * and assume default width of 32 |
606 | */ |
607 | if (of_property_read_u32(np, propname: "xlnx,gpio-width" , out_value: &width[0])) |
608 | width[0] = 32; |
609 | |
610 | if (width[0] > 32) |
611 | return -EINVAL; |
612 | |
613 | if (is_dual && of_property_read_u32(np, propname: "xlnx,gpio2-width" , out_value: &width[1])) |
614 | width[1] = 32; |
615 | |
616 | if (width[1] > 32) |
617 | return -EINVAL; |
618 | |
619 | /* Setup software pin mapping */ |
620 | bitmap_set(map: chip->sw_map, start: 0, nbits: width[0] + width[1]); |
621 | |
622 | /* Setup hardware pin mapping */ |
623 | bitmap_set(map: chip->hw_map, start: 0, nbits: width[0]); |
624 | bitmap_set(map: chip->hw_map, start: 32, nbits: width[1]); |
625 | |
626 | spin_lock_init(&chip->gpio_lock); |
627 | |
628 | chip->gc.base = -1; |
629 | chip->gc.ngpio = bitmap_weight(src: chip->hw_map, nbits: 64); |
630 | chip->gc.parent = &pdev->dev; |
631 | chip->gc.direction_input = xgpio_dir_in; |
632 | chip->gc.direction_output = xgpio_dir_out; |
633 | chip->gc.get = xgpio_get; |
634 | chip->gc.set = xgpio_set; |
635 | chip->gc.request = xgpio_request; |
636 | chip->gc.free = xgpio_free; |
637 | chip->gc.set_multiple = xgpio_set_multiple; |
638 | |
639 | chip->gc.label = dev_name(dev: &pdev->dev); |
640 | |
641 | chip->regs = devm_platform_ioremap_resource(pdev, index: 0); |
642 | if (IS_ERR(ptr: chip->regs)) { |
643 | dev_err(&pdev->dev, "failed to ioremap memory resource\n" ); |
644 | return PTR_ERR(ptr: chip->regs); |
645 | } |
646 | |
647 | chip->clk = devm_clk_get_optional(dev: &pdev->dev, NULL); |
648 | if (IS_ERR(ptr: chip->clk)) |
649 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: chip->clk), fmt: "input clock not found.\n" ); |
650 | |
651 | status = clk_prepare_enable(clk: chip->clk); |
652 | if (status < 0) { |
653 | dev_err(&pdev->dev, "Failed to prepare clk\n" ); |
654 | return status; |
655 | } |
656 | pm_runtime_get_noresume(dev: &pdev->dev); |
657 | pm_runtime_set_active(dev: &pdev->dev); |
658 | pm_runtime_enable(dev: &pdev->dev); |
659 | |
660 | xgpio_save_regs(chip); |
661 | |
662 | chip->irq = platform_get_irq_optional(pdev, 0); |
663 | if (chip->irq <= 0) |
664 | goto skip_irq; |
665 | |
666 | /* Disable per-channel interrupts */ |
667 | xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); |
668 | /* Clear any existing per-channel interrupts */ |
669 | temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); |
670 | xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); |
671 | /* Enable global interrupts */ |
672 | xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); |
673 | |
674 | girq = &chip->gc.irq; |
675 | gpio_irq_chip_set_chip(girq, chip: &xgpio_irq_chip); |
676 | girq->parent_handler = xgpio_irqhandler; |
677 | girq->num_parents = 1; |
678 | girq->parents = devm_kcalloc(dev: &pdev->dev, n: 1, |
679 | size: sizeof(*girq->parents), |
680 | GFP_KERNEL); |
681 | if (!girq->parents) { |
682 | status = -ENOMEM; |
683 | goto err_pm_put; |
684 | } |
685 | girq->parents[0] = chip->irq; |
686 | girq->default_type = IRQ_TYPE_NONE; |
687 | girq->handler = handle_bad_irq; |
688 | |
689 | skip_irq: |
690 | status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); |
691 | if (status) { |
692 | dev_err(&pdev->dev, "failed to add GPIO chip\n" ); |
693 | goto err_pm_put; |
694 | } |
695 | |
696 | pm_runtime_put(dev: &pdev->dev); |
697 | return 0; |
698 | |
699 | err_pm_put: |
700 | pm_runtime_disable(dev: &pdev->dev); |
701 | pm_runtime_put_noidle(dev: &pdev->dev); |
702 | clk_disable_unprepare(clk: chip->clk); |
703 | return status; |
704 | } |
705 | |
706 | static const struct of_device_id xgpio_of_match[] = { |
707 | { .compatible = "xlnx,xps-gpio-1.00.a" , }, |
708 | { /* end of list */ }, |
709 | }; |
710 | |
711 | MODULE_DEVICE_TABLE(of, xgpio_of_match); |
712 | |
713 | static struct platform_driver xgpio_plat_driver = { |
714 | .probe = xgpio_probe, |
715 | .remove_new = xgpio_remove, |
716 | .driver = { |
717 | .name = "gpio-xilinx" , |
718 | .of_match_table = xgpio_of_match, |
719 | .pm = &xgpio_dev_pm_ops, |
720 | }, |
721 | }; |
722 | |
723 | static int __init xgpio_init(void) |
724 | { |
725 | return platform_driver_register(&xgpio_plat_driver); |
726 | } |
727 | |
728 | subsys_initcall(xgpio_init); |
729 | |
730 | static void __exit xgpio_exit(void) |
731 | { |
732 | platform_driver_unregister(&xgpio_plat_driver); |
733 | } |
734 | module_exit(xgpio_exit); |
735 | |
736 | MODULE_AUTHOR("Xilinx, Inc." ); |
737 | MODULE_DESCRIPTION("Xilinx GPIO driver" ); |
738 | MODULE_LICENSE("GPL" ); |
739 | |