1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/amdgpu_drm.h>
25#include "amdgpu.h"
26#include "atomfirmware.h"
27#include "amdgpu_atomfirmware.h"
28#include "atom.h"
29#include "atombios.h"
30#include "soc15_hw_ip.h"
31
32union firmware_info {
33 struct atom_firmware_info_v3_1 v31;
34 struct atom_firmware_info_v3_2 v32;
35 struct atom_firmware_info_v3_3 v33;
36 struct atom_firmware_info_v3_4 v34;
37 struct atom_firmware_info_v3_5 v35;
38};
39
40/*
41 * Helper function to query firmware capability
42 *
43 * @adev: amdgpu_device pointer
44 *
45 * Return firmware_capability in firmwareinfo table on success or 0 if not
46 */
47uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev)
48{
49 struct amdgpu_mode_info *mode_info = &adev->mode_info;
50 int index;
51 u16 data_offset, size;
52 union firmware_info *firmware_info;
53 u8 frev, crev;
54 u32 fw_cap = 0;
55
56 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
57 firmwareinfo);
58
59 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context,
60 index, size: &size, frev: &frev, crev: &crev, data_start: &data_offset)) {
61 /* support firmware_info 3.1 + */
62 if ((frev == 3 && crev >= 1) || (frev > 3)) {
63 firmware_info = (union firmware_info *)
64 (mode_info->atom_context->bios + data_offset);
65 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
66 }
67 }
68
69 return fw_cap;
70}
71
72/*
73 * Helper function to query gpu virtualizaiton capability
74 *
75 * @adev: amdgpu_device pointer
76 *
77 * Return true if gpu virtualization is supported or false if not
78 */
79bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev)
80{
81 u32 fw_cap;
82
83 fw_cap = adev->mode_info.firmware_flags;
84
85 return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;
86}
87
88void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
89{
90 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
91 firmwareinfo);
92 uint16_t data_offset;
93
94 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context, index, NULL,
95 NULL, NULL, data_start: &data_offset)) {
96 struct atom_firmware_info_v3_1 *firmware_info =
97 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
98 data_offset);
99
100 adev->bios_scratch_reg_offset =
101 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
102 }
103}
104
105static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
106 struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes)
107{
108 u32 start_addr, fw_size, drv_size;
109
110 start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
111 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
112 drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
113
114 DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
115 start_addr,
116 fw_size,
117 drv_size);
118
119 if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
120 (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
121 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
122 /* Firmware request VRAM reservation for SR-IOV */
123 adev->mman.fw_vram_usage_start_offset = (start_addr &
124 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
125 adev->mman.fw_vram_usage_size = fw_size << 10;
126 /* Use the default scratch size */
127 *usage_bytes = 0;
128 } else {
129 *usage_bytes = drv_size << 10;
130 }
131 return 0;
132}
133
134static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
135 struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes)
136{
137 u32 fw_start_addr, fw_size, drv_start_addr, drv_size;
138
139 fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
140 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
141
142 drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
143 drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
144
145 DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n",
146 fw_start_addr,
147 fw_size,
148 drv_start_addr,
149 drv_size);
150
151 if (amdgpu_sriov_vf(adev) &&
152 ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
153 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
154 /* Firmware request VRAM reservation for SR-IOV */
155 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
156 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
157 adev->mman.fw_vram_usage_size = fw_size << 10;
158 }
159
160 if (amdgpu_sriov_vf(adev) &&
161 ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
162 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
163 /* driver request VRAM reservation for SR-IOV */
164 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
165 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
166 adev->mman.drv_vram_usage_size = drv_size << 10;
167 }
168
169 *usage_bytes = 0;
170 return 0;
171}
172
173int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
174{
175 struct atom_context *ctx = adev->mode_info.atom_context;
176 int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
177 vram_usagebyfirmware);
178 struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1;
179 struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2;
180 u16 data_offset;
181 u8 frev, crev;
182 int usage_bytes = 0;
183
184 if (amdgpu_atom_parse_data_header(ctx, index, NULL, frev: &frev, crev: &crev, data_start: &data_offset)) {
185 if (frev == 2 && crev == 1) {
186 fw_usage_v2_1 =
187 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
188 amdgpu_atomfirmware_allocate_fb_v2_1(adev,
189 fw_usage: fw_usage_v2_1,
190 usage_bytes: &usage_bytes);
191 } else if (frev >= 2 && crev >= 2) {
192 fw_usage_v2_2 =
193 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
194 amdgpu_atomfirmware_allocate_fb_v2_2(adev,
195 fw_usage: fw_usage_v2_2,
196 usage_bytes: &usage_bytes);
197 }
198 }
199
200 ctx->scratch_size_bytes = 0;
201 if (usage_bytes == 0)
202 usage_bytes = 20 * 1024;
203 /* allocate some scratch memory */
204 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
205 if (!ctx->scratch)
206 return -ENOMEM;
207 ctx->scratch_size_bytes = usage_bytes;
208 return 0;
209}
210
211union igp_info {
212 struct atom_integrated_system_info_v1_11 v11;
213 struct atom_integrated_system_info_v1_12 v12;
214 struct atom_integrated_system_info_v2_1 v21;
215 struct atom_integrated_system_info_v2_3 v23;
216};
217
218union umc_info {
219 struct atom_umc_info_v3_1 v31;
220 struct atom_umc_info_v3_2 v32;
221 struct atom_umc_info_v3_3 v33;
222 struct atom_umc_info_v4_0 v40;
223};
224
225union vram_info {
226 struct atom_vram_info_header_v2_3 v23;
227 struct atom_vram_info_header_v2_4 v24;
228 struct atom_vram_info_header_v2_5 v25;
229 struct atom_vram_info_header_v2_6 v26;
230 struct atom_vram_info_header_v3_0 v30;
231};
232
233union vram_module {
234 struct atom_vram_module_v9 v9;
235 struct atom_vram_module_v10 v10;
236 struct atom_vram_module_v11 v11;
237 struct atom_vram_module_v3_0 v30;
238};
239
240static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
241 int atom_mem_type)
242{
243 int vram_type;
244
245 if (adev->flags & AMD_IS_APU) {
246 switch (atom_mem_type) {
247 case Ddr2MemType:
248 case LpDdr2MemType:
249 vram_type = AMDGPU_VRAM_TYPE_DDR2;
250 break;
251 case Ddr3MemType:
252 case LpDdr3MemType:
253 vram_type = AMDGPU_VRAM_TYPE_DDR3;
254 break;
255 case Ddr4MemType:
256 vram_type = AMDGPU_VRAM_TYPE_DDR4;
257 break;
258 case LpDdr4MemType:
259 vram_type = AMDGPU_VRAM_TYPE_LPDDR4;
260 break;
261 case Ddr5MemType:
262 vram_type = AMDGPU_VRAM_TYPE_DDR5;
263 break;
264 case LpDdr5MemType:
265 vram_type = AMDGPU_VRAM_TYPE_LPDDR5;
266 break;
267 default:
268 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
269 break;
270 }
271 } else {
272 switch (atom_mem_type) {
273 case ATOM_DGPU_VRAM_TYPE_GDDR5:
274 vram_type = AMDGPU_VRAM_TYPE_GDDR5;
275 break;
276 case ATOM_DGPU_VRAM_TYPE_HBM2:
277 case ATOM_DGPU_VRAM_TYPE_HBM2E:
278 case ATOM_DGPU_VRAM_TYPE_HBM3:
279 vram_type = AMDGPU_VRAM_TYPE_HBM;
280 break;
281 case ATOM_DGPU_VRAM_TYPE_GDDR6:
282 vram_type = AMDGPU_VRAM_TYPE_GDDR6;
283 break;
284 case ATOM_DGPU_VRAM_TYPE_HBM3E:
285 vram_type = AMDGPU_VRAM_TYPE_HBM3E;
286 break;
287 default:
288 vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
289 break;
290 }
291 }
292
293 return vram_type;
294}
295
296int
297amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
298 int *vram_width, int *vram_type,
299 int *vram_vendor)
300{
301 struct amdgpu_mode_info *mode_info = &adev->mode_info;
302 int index, i = 0;
303 u16 data_offset, size;
304 union igp_info *igp_info;
305 union vram_info *vram_info;
306 union umc_info *umc_info;
307 union vram_module *vram_module;
308 u8 frev, crev;
309 u8 mem_type;
310 u8 mem_vendor;
311 u32 mem_channel_number;
312 u32 mem_channel_width;
313 u32 module_id;
314
315 if (adev->flags & AMD_IS_APU)
316 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
317 integratedsysteminfo);
318 else {
319 switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) {
320 case IP_VERSION(12, 0, 0):
321 case IP_VERSION(12, 0, 1):
322 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);
323 break;
324 default:
325 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);
326 }
327 }
328 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context,
329 index, size: &size,
330 frev: &frev, crev: &crev, data_start: &data_offset)) {
331 if (adev->flags & AMD_IS_APU) {
332 igp_info = (union igp_info *)
333 (mode_info->atom_context->bios + data_offset);
334 switch (frev) {
335 case 1:
336 switch (crev) {
337 case 11:
338 case 12:
339 mem_channel_number = igp_info->v11.umachannelnumber;
340 if (!mem_channel_number)
341 mem_channel_number = 1;
342 mem_type = igp_info->v11.memorytype;
343 if (mem_type == LpDdr5MemType)
344 mem_channel_width = 32;
345 else
346 mem_channel_width = 64;
347 if (vram_width)
348 *vram_width = mem_channel_number * mem_channel_width;
349 if (vram_type)
350 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
351 break;
352 default:
353 return -EINVAL;
354 }
355 break;
356 case 2:
357 switch (crev) {
358 case 1:
359 case 2:
360 mem_channel_number = igp_info->v21.umachannelnumber;
361 if (!mem_channel_number)
362 mem_channel_number = 1;
363 mem_type = igp_info->v21.memorytype;
364 if (mem_type == LpDdr5MemType)
365 mem_channel_width = 32;
366 else
367 mem_channel_width = 64;
368 if (vram_width)
369 *vram_width = mem_channel_number * mem_channel_width;
370 if (vram_type)
371 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
372 break;
373 case 3:
374 mem_channel_number = igp_info->v23.umachannelnumber;
375 if (!mem_channel_number)
376 mem_channel_number = 1;
377 mem_type = igp_info->v23.memorytype;
378 if (mem_type == LpDdr5MemType)
379 mem_channel_width = 32;
380 else
381 mem_channel_width = 64;
382 if (vram_width)
383 *vram_width = mem_channel_number * mem_channel_width;
384 if (vram_type)
385 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
386 break;
387 default:
388 return -EINVAL;
389 }
390 break;
391 default:
392 return -EINVAL;
393 }
394 } else {
395 switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) {
396 case IP_VERSION(12, 0, 0):
397 case IP_VERSION(12, 0, 1):
398 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
399
400 if (frev == 4) {
401 switch (crev) {
402 case 0:
403 mem_channel_number = le32_to_cpu(umc_info->v40.channel_num);
404 mem_type = le32_to_cpu(umc_info->v40.vram_type);
405 mem_channel_width = le32_to_cpu(umc_info->v40.channel_width);
406 mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;
407 if (vram_vendor)
408 *vram_vendor = mem_vendor;
409 if (vram_type)
410 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
411 if (vram_width)
412 *vram_width = mem_channel_number * (1 << mem_channel_width);
413 break;
414 default:
415 return -EINVAL;
416 }
417 } else
418 return -EINVAL;
419 break;
420 default:
421 vram_info = (union vram_info *)
422 (mode_info->atom_context->bios + data_offset);
423
424 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
425 if (frev == 3) {
426 switch (crev) {
427 /* v30 */
428 case 0:
429 vram_module = (union vram_module *)vram_info->v30.vram_module;
430 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
431 if (vram_vendor)
432 *vram_vendor = mem_vendor;
433 mem_type = vram_info->v30.memory_type;
434 if (vram_type)
435 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
436 mem_channel_number = vram_info->v30.channel_num;
437 mem_channel_width = vram_info->v30.channel_width;
438 if (vram_width)
439 *vram_width = mem_channel_number * 16;
440 break;
441 default:
442 return -EINVAL;
443 }
444 } else if (frev == 2) {
445 switch (crev) {
446 /* v23 */
447 case 3:
448 if (module_id > vram_info->v23.vram_module_num)
449 module_id = 0;
450 vram_module = (union vram_module *)vram_info->v23.vram_module;
451 while (i < module_id) {
452 vram_module = (union vram_module *)
453 ((u8 *)vram_module + vram_module->v9.vram_module_size);
454 i++;
455 }
456 mem_type = vram_module->v9.memory_type;
457 if (vram_type)
458 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
459 mem_channel_number = vram_module->v9.channel_num;
460 mem_channel_width = vram_module->v9.channel_width;
461 if (vram_width)
462 *vram_width = mem_channel_number * (1 << mem_channel_width);
463 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
464 if (vram_vendor)
465 *vram_vendor = mem_vendor;
466 break;
467 /* v24 */
468 case 4:
469 if (module_id > vram_info->v24.vram_module_num)
470 module_id = 0;
471 vram_module = (union vram_module *)vram_info->v24.vram_module;
472 while (i < module_id) {
473 vram_module = (union vram_module *)
474 ((u8 *)vram_module + vram_module->v10.vram_module_size);
475 i++;
476 }
477 mem_type = vram_module->v10.memory_type;
478 if (vram_type)
479 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
480 mem_channel_number = vram_module->v10.channel_num;
481 mem_channel_width = vram_module->v10.channel_width;
482 if (vram_width)
483 *vram_width = mem_channel_number * (1 << mem_channel_width);
484 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
485 if (vram_vendor)
486 *vram_vendor = mem_vendor;
487 break;
488 /* v25 */
489 case 5:
490 if (module_id > vram_info->v25.vram_module_num)
491 module_id = 0;
492 vram_module = (union vram_module *)vram_info->v25.vram_module;
493 while (i < module_id) {
494 vram_module = (union vram_module *)
495 ((u8 *)vram_module + vram_module->v11.vram_module_size);
496 i++;
497 }
498 mem_type = vram_module->v11.memory_type;
499 if (vram_type)
500 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
501 mem_channel_number = vram_module->v11.channel_num;
502 mem_channel_width = vram_module->v11.channel_width;
503 if (vram_width)
504 *vram_width = mem_channel_number * (1 << mem_channel_width);
505 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
506 if (vram_vendor)
507 *vram_vendor = mem_vendor;
508 break;
509 /* v26 */
510 case 6:
511 if (module_id > vram_info->v26.vram_module_num)
512 module_id = 0;
513 vram_module = (union vram_module *)vram_info->v26.vram_module;
514 while (i < module_id) {
515 vram_module = (union vram_module *)
516 ((u8 *)vram_module + vram_module->v9.vram_module_size);
517 i++;
518 }
519 mem_type = vram_module->v9.memory_type;
520 if (vram_type)
521 *vram_type = convert_atom_mem_type_to_vram_type(adev, atom_mem_type: mem_type);
522 mem_channel_number = vram_module->v9.channel_num;
523 mem_channel_width = vram_module->v9.channel_width;
524 if (vram_width)
525 *vram_width = mem_channel_number * (1 << mem_channel_width);
526 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
527 if (vram_vendor)
528 *vram_vendor = mem_vendor;
529 break;
530 default:
531 return -EINVAL;
532 }
533 } else {
534 /* invalid frev */
535 return -EINVAL;
536 }
537 }
538 }
539 }
540
541 return 0;
542}
543
544/*
545 * Return true if vbios enabled ecc by default, if umc info table is available
546 * or false if ecc is not enabled or umc info table is not available
547 */
548bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
549{
550 struct amdgpu_mode_info *mode_info = &adev->mode_info;
551 int index;
552 u16 data_offset, size;
553 union umc_info *umc_info;
554 u8 frev, crev;
555 bool mem_ecc_enabled = false;
556 u8 umc_config;
557 u32 umc_config1;
558 adev->ras_default_ecc_enabled = false;
559
560 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
561 umc_info);
562
563 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context,
564 index, size: &size, frev: &frev, crev: &crev, data_start: &data_offset)) {
565 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
566 if (frev == 3) {
567 switch (crev) {
568 case 1:
569 umc_config = le32_to_cpu(umc_info->v31.umc_config);
570 mem_ecc_enabled =
571 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
572 break;
573 case 2:
574 umc_config = le32_to_cpu(umc_info->v32.umc_config);
575 mem_ecc_enabled =
576 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
577 break;
578 case 3:
579 umc_config = le32_to_cpu(umc_info->v33.umc_config);
580 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
581 mem_ecc_enabled =
582 ((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
583 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
584 adev->ras_default_ecc_enabled =
585 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
586 break;
587 default:
588 /* unsupported crev */
589 return false;
590 }
591 } else if (frev == 4) {
592 switch (crev) {
593 case 0:
594 umc_config = le32_to_cpu(umc_info->v40.umc_config);
595 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
596 mem_ecc_enabled =
597 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
598 adev->ras_default_ecc_enabled =
599 (umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
600 break;
601 default:
602 /* unsupported crev */
603 return false;
604 }
605 } else {
606 /* unsupported frev */
607 return false;
608 }
609 }
610
611 return mem_ecc_enabled;
612}
613
614/*
615 * Helper function to query sram ecc capablity
616 *
617 * @adev: amdgpu_device pointer
618 *
619 * Return true if vbios supports sram ecc or false if not
620 */
621bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
622{
623 u32 fw_cap;
624
625 fw_cap = adev->mode_info.firmware_flags;
626
627 return (fw_cap & ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
628}
629
630/*
631 * Helper function to query dynamic boot config capability
632 *
633 * @adev: amdgpu_device pointer
634 *
635 * Return true if vbios supports dynamic boot config or false if not
636 */
637bool amdgpu_atomfirmware_dynamic_boot_config_supported(struct amdgpu_device *adev)
638{
639 u32 fw_cap;
640
641 fw_cap = adev->mode_info.firmware_flags;
642
643 return (fw_cap & ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE) ? true : false;
644}
645
646/**
647 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
648 * @adev: amdgpu_device pointer
649 * @i2c_address: pointer to u8; if not NULL, will contain
650 * the RAS EEPROM address if the function returns true
651 *
652 * Return true if VBIOS supports RAS EEPROM address reporting,
653 * else return false. If true and @i2c_address is not NULL,
654 * will contain the RAS ROM address.
655 */
656bool amdgpu_atomfirmware_ras_rom_addr(struct amdgpu_device *adev,
657 u8 *i2c_address)
658{
659 struct amdgpu_mode_info *mode_info = &adev->mode_info;
660 int index;
661 u16 data_offset, size;
662 union firmware_info *firmware_info;
663 u8 frev, crev;
664
665 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
666 firmwareinfo);
667
668 if (amdgpu_atom_parse_data_header(ctx: adev->mode_info.atom_context,
669 index, size: &size, frev: &frev, crev: &crev,
670 data_start: &data_offset)) {
671 /* support firmware_info 3.4 + */
672 if ((frev == 3 && crev >= 4) || (frev > 3)) {
673 firmware_info = (union firmware_info *)
674 (mode_info->atom_context->bios + data_offset);
675 /* The ras_rom_i2c_slave_addr should ideally
676 * be a 19-bit EEPROM address, which would be
677 * used as is by the driver; see top of
678 * amdgpu_eeprom.c.
679 *
680 * When this is the case, 0 is of course a
681 * valid RAS EEPROM address, in which case,
682 * we'll drop the first "if (firm...)" and only
683 * leave the check for the pointer.
684 *
685 * The reason this works right now is because
686 * ras_rom_i2c_slave_addr contains the EEPROM
687 * device type qualifier 1010b in the top 4
688 * bits.
689 */
690 if (firmware_info->v34.ras_rom_i2c_slave_addr) {
691 if (i2c_address)
692 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
693 return true;
694 }
695 }
696 }
697
698 return false;
699}
700
701
702union smu_info {
703 struct atom_smu_info_v3_1 v31;
704 struct atom_smu_info_v4_0 v40;
705};
706
707union gfx_info {
708 struct atom_gfx_info_v2_2 v22;
709 struct atom_gfx_info_v2_4 v24;
710 struct atom_gfx_info_v2_7 v27;
711 struct atom_gfx_info_v3_0 v30;
712};
713
714int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
715{
716 struct amdgpu_mode_info *mode_info = &adev->mode_info;
717 struct amdgpu_pll *spll = &adev->clock.spll;
718 struct amdgpu_pll *mpll = &adev->clock.mpll;
719 uint8_t frev, crev;
720 uint16_t data_offset;
721 int ret = -EINVAL, index;
722
723 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
724 firmwareinfo);
725 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
726 frev: &frev, crev: &crev, data_start: &data_offset)) {
727 union firmware_info *firmware_info =
728 (union firmware_info *)(mode_info->atom_context->bios +
729 data_offset);
730
731 adev->clock.default_sclk =
732 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
733 adev->clock.default_mclk =
734 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
735
736 adev->pm.current_sclk = adev->clock.default_sclk;
737 adev->pm.current_mclk = adev->clock.default_mclk;
738
739 ret = 0;
740 }
741
742 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
743 smu_info);
744 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
745 frev: &frev, crev: &crev, data_start: &data_offset)) {
746 union smu_info *smu_info =
747 (union smu_info *)(mode_info->atom_context->bios +
748 data_offset);
749
750 /* system clock */
751 if (frev == 3)
752 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
753 else if (frev == 4)
754 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
755
756 spll->reference_div = 0;
757 spll->min_post_div = 1;
758 spll->max_post_div = 1;
759 spll->min_ref_div = 2;
760 spll->max_ref_div = 0xff;
761 spll->min_feedback_div = 4;
762 spll->max_feedback_div = 0xff;
763 spll->best_vco = 0;
764
765 ret = 0;
766 }
767
768 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
769 umc_info);
770 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
771 frev: &frev, crev: &crev, data_start: &data_offset)) {
772 union umc_info *umc_info =
773 (union umc_info *)(mode_info->atom_context->bios +
774 data_offset);
775
776 /* memory clock */
777 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
778
779 mpll->reference_div = 0;
780 mpll->min_post_div = 1;
781 mpll->max_post_div = 1;
782 mpll->min_ref_div = 2;
783 mpll->max_ref_div = 0xff;
784 mpll->min_feedback_div = 4;
785 mpll->max_feedback_div = 0xff;
786 mpll->best_vco = 0;
787
788 ret = 0;
789 }
790
791 /* if asic is Navi+, the rlc reference clock is used for system clock
792 * from vbios gfx_info table */
793 if (adev->asic_type >= CHIP_NAVI10) {
794 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
795 gfx_info);
796 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
797 frev: &frev, crev: &crev, data_start: &data_offset)) {
798 union gfx_info *gfx_info = (union gfx_info *)
799 (mode_info->atom_context->bios + data_offset);
800 if ((frev == 3) ||
801 (frev == 2 && crev == 6)) {
802 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
803 ret = 0;
804 } else if ((frev == 2) &&
805 (crev >= 2) &&
806 (crev != 6)) {
807 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
808 ret = 0;
809 } else {
810 BUG();
811 }
812 }
813 }
814
815 return ret;
816}
817
818int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
819{
820 struct amdgpu_mode_info *mode_info = &adev->mode_info;
821 int index;
822 uint8_t frev, crev;
823 uint16_t data_offset;
824
825 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
826 gfx_info);
827 if (amdgpu_atom_parse_data_header(ctx: mode_info->atom_context, index, NULL,
828 frev: &frev, crev: &crev, data_start: &data_offset)) {
829 union gfx_info *gfx_info = (union gfx_info *)
830 (mode_info->atom_context->bios + data_offset);
831 if (frev == 2) {
832 switch (crev) {
833 case 4:
834 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
835 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
836 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
837 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
838 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
839 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
840 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
841 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
842 adev->gfx.config.gs_prim_buffer_depth =
843 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
844 adev->gfx.config.double_offchip_lds_buf =
845 gfx_info->v24.gc_double_offchip_lds_buffer;
846 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
847 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
848 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
849 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
850 return 0;
851 case 7:
852 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
853 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
854 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
855 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
856 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
857 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
858 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
859 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
860 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
861 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
862 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
863 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
864 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
865 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
866 return 0;
867 default:
868 return -EINVAL;
869 }
870 } else if (frev == 3) {
871 switch (crev) {
872 case 0:
873 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
874 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
875 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
876 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
877 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
878 return 0;
879 default:
880 return -EINVAL;
881 }
882 } else {
883 return -EINVAL;
884 }
885
886 }
887 return -EINVAL;
888}
889
890/*
891 * Helper function to query two stage mem training capability
892 *
893 * @adev: amdgpu_device pointer
894 *
895 * Return true if two stage mem training is supported or false if not
896 */
897bool amdgpu_atomfirmware_mem_training_supported(struct amdgpu_device *adev)
898{
899 u32 fw_cap;
900
901 fw_cap = adev->mode_info.firmware_flags;
902
903 return (fw_cap & ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING) ? true : false;
904}
905
906int amdgpu_atomfirmware_get_fw_reserved_fb_size(struct amdgpu_device *adev)
907{
908 struct atom_context *ctx = adev->mode_info.atom_context;
909 union firmware_info *firmware_info;
910 int index;
911 u16 data_offset, size;
912 u8 frev, crev;
913 int fw_reserved_fb_size;
914
915 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
916 firmwareinfo);
917
918 if (!amdgpu_atom_parse_data_header(ctx, index, size: &size,
919 frev: &frev, crev: &crev, data_start: &data_offset))
920 /* fail to parse data_header */
921 return 0;
922
923 firmware_info = (union firmware_info *)(ctx->bios + data_offset);
924
925 if (frev != 3)
926 return -EINVAL;
927
928 switch (crev) {
929 case 4:
930 fw_reserved_fb_size =
931 (firmware_info->v34.fw_reserved_size_in_kb << 10);
932 break;
933 case 5:
934 fw_reserved_fb_size =
935 (firmware_info->v35.fw_reserved_size_in_kb << 10);
936 break;
937 default:
938 fw_reserved_fb_size = 0;
939 break;
940 }
941
942 return fw_reserved_fb_size;
943}
944
945/*
946 * Helper function to execute asic_init table
947 *
948 * @adev: amdgpu_device pointer
949 * @fb_reset: flag to indicate whether fb is reset or not
950 *
951 * Return 0 if succeed, otherwise failed
952 */
953int amdgpu_atomfirmware_asic_init(struct amdgpu_device *adev, bool fb_reset)
954{
955 struct amdgpu_mode_info *mode_info = &adev->mode_info;
956 struct atom_context *ctx;
957 uint8_t frev, crev;
958 uint16_t data_offset;
959 uint32_t bootup_sclk_in10khz, bootup_mclk_in10khz;
960 struct asic_init_ps_allocation_v2_1 asic_init_ps_v2_1;
961 int index;
962
963 if (!mode_info)
964 return -EINVAL;
965
966 ctx = mode_info->atom_context;
967 if (!ctx)
968 return -EINVAL;
969
970 /* query bootup sclk/mclk from firmware_info table */
971 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
972 firmwareinfo);
973 if (amdgpu_atom_parse_data_header(ctx, index, NULL,
974 frev: &frev, crev: &crev, data_start: &data_offset)) {
975 union firmware_info *firmware_info =
976 (union firmware_info *)(ctx->bios +
977 data_offset);
978
979 bootup_sclk_in10khz =
980 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
981 bootup_mclk_in10khz =
982 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
983 } else {
984 return -EINVAL;
985 }
986
987 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
988 asic_init);
989 if (amdgpu_atom_parse_cmd_header(ctx: mode_info->atom_context, index, frev: &frev, crev: &crev)) {
990 if (frev == 2 && crev >= 1) {
991 memset(&asic_init_ps_v2_1, 0, sizeof(asic_init_ps_v2_1));
992 asic_init_ps_v2_1.param.engineparam.sclkfreqin10khz = bootup_sclk_in10khz;
993 asic_init_ps_v2_1.param.memparam.mclkfreqin10khz = bootup_mclk_in10khz;
994 asic_init_ps_v2_1.param.engineparam.engineflag = b3NORMAL_ENGINE_INIT;
995 if (!fb_reset)
996 asic_init_ps_v2_1.param.memparam.memflag = b3DRAM_SELF_REFRESH_EXIT;
997 else
998 asic_init_ps_v2_1.param.memparam.memflag = 0;
999 } else {
1000 return -EINVAL;
1001 }
1002 } else {
1003 return -EINVAL;
1004 }
1005
1006 return amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, params: (uint32_t *)&asic_init_ps_v2_1,
1007 params_size: sizeof(asic_init_ps_v2_1));
1008}
1009

source code of linux/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c