1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include <linux/firmware.h> |
24 | #include <linux/pci.h> |
25 | |
26 | #include <drm/drm_cache.h> |
27 | |
28 | #include "amdgpu.h" |
29 | #include "amdgpu_atomfirmware.h" |
30 | #include "gmc_v10_0.h" |
31 | #include "umc_v8_7.h" |
32 | |
33 | #include "athub/athub_2_0_0_sh_mask.h" |
34 | #include "athub/athub_2_0_0_offset.h" |
35 | #include "dcn/dcn_2_0_0_offset.h" |
36 | #include "dcn/dcn_2_0_0_sh_mask.h" |
37 | #include "oss/osssys_5_0_0_offset.h" |
38 | #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" |
39 | #include "navi10_enum.h" |
40 | |
41 | #include "soc15.h" |
42 | #include "soc15d.h" |
43 | #include "soc15_common.h" |
44 | |
45 | #include "nbio_v2_3.h" |
46 | |
47 | #include "gfxhub_v2_0.h" |
48 | #include "gfxhub_v2_1.h" |
49 | #include "mmhub_v2_0.h" |
50 | #include "mmhub_v2_3.h" |
51 | #include "athub_v2_0.h" |
52 | #include "athub_v2_1.h" |
53 | |
54 | static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, |
55 | struct amdgpu_irq_src *src, |
56 | unsigned int type, |
57 | enum amdgpu_interrupt_state state) |
58 | { |
59 | return 0; |
60 | } |
61 | |
62 | static int |
63 | gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
64 | struct amdgpu_irq_src *src, unsigned int type, |
65 | enum amdgpu_interrupt_state state) |
66 | { |
67 | switch (state) { |
68 | case AMDGPU_IRQ_STATE_DISABLE: |
69 | /* MM HUB */ |
70 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), enable: false); |
71 | /* GFX HUB */ |
72 | /* This works because this interrupt is only |
73 | * enabled at init/resume and disabled in |
74 | * fini/suspend, so the overall state doesn't |
75 | * change over the course of suspend/resume. |
76 | */ |
77 | if (!adev->in_s0ix) |
78 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), enable: false); |
79 | break; |
80 | case AMDGPU_IRQ_STATE_ENABLE: |
81 | /* MM HUB */ |
82 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), enable: true); |
83 | /* GFX HUB */ |
84 | /* This works because this interrupt is only |
85 | * enabled at init/resume and disabled in |
86 | * fini/suspend, so the overall state doesn't |
87 | * change over the course of suspend/resume. |
88 | */ |
89 | if (!adev->in_s0ix) |
90 | amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), enable: true); |
91 | break; |
92 | default: |
93 | break; |
94 | } |
95 | |
96 | return 0; |
97 | } |
98 | |
99 | static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, |
100 | struct amdgpu_irq_src *source, |
101 | struct amdgpu_iv_entry *entry) |
102 | { |
103 | uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? |
104 | AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); |
105 | struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; |
106 | bool retry_fault = !!(entry->src_data[1] & 0x80); |
107 | bool write_fault = !!(entry->src_data[1] & 0x20); |
108 | struct amdgpu_task_info *task_info; |
109 | uint32_t status = 0; |
110 | u64 addr; |
111 | |
112 | addr = (u64)entry->src_data[0] << 12; |
113 | addr |= ((u64)entry->src_data[1] & 0xf) << 44; |
114 | |
115 | if (retry_fault) { |
116 | /* Returning 1 here also prevents sending the IV to the KFD */ |
117 | |
118 | /* Process it onyl if it's the first fault for this address */ |
119 | if (entry->ih != &adev->irq.ih_soft && |
120 | amdgpu_gmc_filter_faults(adev, ih: entry->ih, addr, pasid: entry->pasid, |
121 | timestamp: entry->timestamp)) |
122 | return 1; |
123 | |
124 | /* Delegate it to a different ring if the hardware hasn't |
125 | * already done it. |
126 | */ |
127 | if (entry->ih == &adev->irq.ih) { |
128 | amdgpu_irq_delegate(adev, entry, num_dw: 8); |
129 | return 1; |
130 | } |
131 | |
132 | /* Try to handle the recoverable page faults by filling page |
133 | * tables |
134 | */ |
135 | if (amdgpu_vm_handle_fault(adev, pasid: entry->pasid, vmid: 0, node_id: 0, addr, write_fault)) |
136 | return 1; |
137 | } |
138 | |
139 | if (!amdgpu_sriov_vf(adev)) { |
140 | /* |
141 | * Issue a dummy read to wait for the status register to |
142 | * be updated to avoid reading an incorrect value due to |
143 | * the new fast GRBM interface. |
144 | */ |
145 | if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && |
146 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) < |
147 | IP_VERSION(10, 3, 0))) |
148 | RREG32(hub->vm_l2_pro_fault_status); |
149 | |
150 | status = RREG32(hub->vm_l2_pro_fault_status); |
151 | WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); |
152 | |
153 | amdgpu_vm_update_fault_cache(adev, pasid: entry->pasid, addr, status, |
154 | vmhub: entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); |
155 | } |
156 | |
157 | if (!printk_ratelimit()) |
158 | return 0; |
159 | |
160 | dev_err(adev->dev, |
161 | "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n" , |
162 | entry->vmid_src ? "mmhub" : "gfxhub" , |
163 | entry->src_id, entry->ring_id, entry->vmid, entry->pasid); |
164 | task_info = amdgpu_vm_get_task_info_pasid(adev, pasid: entry->pasid); |
165 | if (task_info) { |
166 | dev_err(adev->dev, |
167 | " in process %s pid %d thread %s pid %d\n" , |
168 | task_info->process_name, task_info->tgid, |
169 | task_info->task_name, task_info->pid); |
170 | amdgpu_vm_put_task_info(task_info); |
171 | } |
172 | |
173 | dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n" , |
174 | addr, entry->client_id, |
175 | soc15_ih_clientid_name[entry->client_id]); |
176 | |
177 | if (!amdgpu_sriov_vf(adev)) |
178 | hub->vmhub_funcs->print_l2_protection_fault_status(adev, |
179 | status); |
180 | |
181 | return 0; |
182 | } |
183 | |
184 | static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { |
185 | .set = gmc_v10_0_vm_fault_interrupt_state, |
186 | .process = gmc_v10_0_process_interrupt, |
187 | }; |
188 | |
189 | static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { |
190 | .set = gmc_v10_0_ecc_interrupt_state, |
191 | .process = amdgpu_umc_process_ecc_irq, |
192 | }; |
193 | |
194 | static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) |
195 | { |
196 | adev->gmc.vm_fault.num_types = 1; |
197 | adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; |
198 | |
199 | if (!amdgpu_sriov_vf(adev)) { |
200 | adev->gmc.ecc_irq.num_types = 1; |
201 | adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; |
202 | } |
203 | } |
204 | |
205 | /** |
206 | * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore |
207 | * |
208 | * @adev: amdgpu_device pointer |
209 | * @vmhub: vmhub type |
210 | * |
211 | */ |
212 | static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, |
213 | uint32_t vmhub) |
214 | { |
215 | return ((vmhub == AMDGPU_MMHUB0(0)) && |
216 | (!amdgpu_sriov_vf(adev))); |
217 | } |
218 | |
219 | static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( |
220 | struct amdgpu_device *adev, |
221 | uint8_t vmid, uint16_t *p_pasid) |
222 | { |
223 | uint32_t value; |
224 | |
225 | value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) |
226 | + vmid); |
227 | *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; |
228 | |
229 | return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); |
230 | } |
231 | |
232 | /* |
233 | * GART |
234 | * VMID 0 is the physical GPU addresses as used by the kernel. |
235 | * VMIDs 1-15 are used for userspace clients and are handled |
236 | * by the amdgpu vm/hsa code. |
237 | */ |
238 | |
239 | /** |
240 | * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback |
241 | * |
242 | * @adev: amdgpu_device pointer |
243 | * @vmid: vm instance to flush |
244 | * @vmhub: vmhub type |
245 | * @flush_type: the flush type |
246 | * |
247 | * Flush the TLB for the requested page table. |
248 | */ |
249 | static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
250 | uint32_t vmhub, uint32_t flush_type) |
251 | { |
252 | bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); |
253 | struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; |
254 | u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); |
255 | /* Use register 17 for GART */ |
256 | const unsigned int eng = 17; |
257 | unsigned char hub_ip = 0; |
258 | u32 sem, req, ack; |
259 | unsigned int i; |
260 | u32 tmp; |
261 | |
262 | sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; |
263 | req = hub->vm_inv_eng0_req + hub->eng_distance * eng; |
264 | ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; |
265 | |
266 | /* flush hdp cache */ |
267 | adev->hdp.funcs->flush_hdp(adev, NULL); |
268 | |
269 | /* This is necessary for SRIOV as well as for GFXOFF to function |
270 | * properly under bare metal |
271 | */ |
272 | if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && |
273 | (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { |
274 | amdgpu_gmc_fw_reg_write_reg_wait(adev, reg0: req, reg1: ack, ref: inv_req, |
275 | mask: 1 << vmid, GET_INST(GC, 0)); |
276 | return; |
277 | } |
278 | |
279 | /* This path is needed before KIQ/MES/GFXOFF are set up */ |
280 | hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; |
281 | |
282 | spin_lock(lock: &adev->gmc.invalidate_lock); |
283 | /* |
284 | * It may lose gpuvm invalidate acknowldege state across power-gating |
285 | * off cycle, add semaphore acquire before invalidation and semaphore |
286 | * release after invalidation to avoid entering power gated state |
287 | * to WA the Issue |
288 | */ |
289 | |
290 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
291 | if (use_semaphore) { |
292 | for (i = 0; i < adev->usec_timeout; i++) { |
293 | /* a read return value of 1 means semaphore acuqire */ |
294 | tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); |
295 | if (tmp & 0x1) |
296 | break; |
297 | udelay(1); |
298 | } |
299 | |
300 | if (i >= adev->usec_timeout) |
301 | DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n" ); |
302 | } |
303 | |
304 | WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); |
305 | |
306 | /* |
307 | * Issue a dummy read to wait for the ACK register to be cleared |
308 | * to avoid a false ACK due to the new fast GRBM interface. |
309 | */ |
310 | if ((vmhub == AMDGPU_GFXHUB(0)) && |
311 | (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) < IP_VERSION(10, 3, 0))) |
312 | RREG32_RLC_NO_KIQ(req, hub_ip); |
313 | |
314 | /* Wait for ACK with a delay.*/ |
315 | for (i = 0; i < adev->usec_timeout; i++) { |
316 | tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); |
317 | tmp &= 1 << vmid; |
318 | if (tmp) |
319 | break; |
320 | |
321 | udelay(1); |
322 | } |
323 | |
324 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
325 | if (use_semaphore) |
326 | WREG32_RLC_NO_KIQ(sem, 0, hub_ip); |
327 | |
328 | spin_unlock(lock: &adev->gmc.invalidate_lock); |
329 | |
330 | if (i >= adev->usec_timeout) |
331 | dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n" , |
332 | vmhub); |
333 | } |
334 | |
335 | /** |
336 | * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid |
337 | * |
338 | * @adev: amdgpu_device pointer |
339 | * @pasid: pasid to be flush |
340 | * @flush_type: the flush type |
341 | * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() |
342 | * @inst: is used to select which instance of KIQ to use for the invalidation |
343 | * |
344 | * Flush the TLB for the requested pasid. |
345 | */ |
346 | static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, |
347 | uint16_t pasid, uint32_t flush_type, |
348 | bool all_hub, uint32_t inst) |
349 | { |
350 | uint16_t queried; |
351 | int vmid, i; |
352 | |
353 | for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { |
354 | bool valid; |
355 | |
356 | valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, |
357 | p_pasid: &queried); |
358 | if (!valid || queried != pasid) |
359 | continue; |
360 | |
361 | if (all_hub) { |
362 | for_each_set_bit(i, adev->vmhubs_mask, |
363 | AMDGPU_MAX_VMHUBS) |
364 | gmc_v10_0_flush_gpu_tlb(adev, vmid, vmhub: i, |
365 | flush_type); |
366 | } else { |
367 | gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), |
368 | flush_type); |
369 | } |
370 | } |
371 | } |
372 | |
373 | static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
374 | unsigned int vmid, uint64_t pd_addr) |
375 | { |
376 | bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev: ring->adev, vmhub: ring->vm_hub); |
377 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; |
378 | uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); |
379 | unsigned int eng = ring->vm_inv_eng; |
380 | |
381 | /* |
382 | * It may lose gpuvm invalidate acknowldege state across power-gating |
383 | * off cycle, add semaphore acquire before invalidation and semaphore |
384 | * release after invalidation to avoid entering power gated state |
385 | * to WA the Issue |
386 | */ |
387 | |
388 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
389 | if (use_semaphore) |
390 | /* a read return value of 1 means semaphore acuqire */ |
391 | amdgpu_ring_emit_reg_wait(ring, |
392 | hub->vm_inv_eng0_sem + |
393 | hub->eng_distance * eng, 0x1, 0x1); |
394 | |
395 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + |
396 | (hub->ctx_addr_distance * vmid), |
397 | lower_32_bits(pd_addr)); |
398 | |
399 | amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + |
400 | (hub->ctx_addr_distance * vmid), |
401 | upper_32_bits(pd_addr)); |
402 | |
403 | amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + |
404 | hub->eng_distance * eng, |
405 | hub->vm_inv_eng0_ack + |
406 | hub->eng_distance * eng, |
407 | req, 1 << vmid); |
408 | |
409 | /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ |
410 | if (use_semaphore) |
411 | /* |
412 | * add semaphore release after invalidation, |
413 | * write with 0 means semaphore release |
414 | */ |
415 | amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + |
416 | hub->eng_distance * eng, 0); |
417 | |
418 | return pd_addr; |
419 | } |
420 | |
421 | static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, |
422 | unsigned int pasid) |
423 | { |
424 | struct amdgpu_device *adev = ring->adev; |
425 | uint32_t reg; |
426 | |
427 | /* MES fw manages IH_VMID_x_LUT updating */ |
428 | if (ring->is_mes_queue) |
429 | return; |
430 | |
431 | if (ring->vm_hub == AMDGPU_GFXHUB(0)) |
432 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; |
433 | else |
434 | reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; |
435 | |
436 | amdgpu_ring_emit_wreg(ring, reg, pasid); |
437 | } |
438 | |
439 | /* |
440 | * PTE format on NAVI 10: |
441 | * 63:59 reserved |
442 | * 58 reserved and for sienna_cichlid is used for MALL noalloc |
443 | * 57 reserved |
444 | * 56 F |
445 | * 55 L |
446 | * 54 reserved |
447 | * 53:52 SW |
448 | * 51 T |
449 | * 50:48 mtype |
450 | * 47:12 4k physical page base address |
451 | * 11:7 fragment |
452 | * 6 write |
453 | * 5 read |
454 | * 4 exe |
455 | * 3 Z |
456 | * 2 snooped |
457 | * 1 system |
458 | * 0 valid |
459 | * |
460 | * PDE format on NAVI 10: |
461 | * 63:59 block fragment size |
462 | * 58:55 reserved |
463 | * 54 P |
464 | * 53:48 reserved |
465 | * 47:6 physical base address of PD or PTE |
466 | * 5:3 reserved |
467 | * 2 C |
468 | * 1 system |
469 | * 0 valid |
470 | */ |
471 | |
472 | static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) |
473 | { |
474 | switch (flags) { |
475 | case AMDGPU_VM_MTYPE_DEFAULT: |
476 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
477 | case AMDGPU_VM_MTYPE_NC: |
478 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
479 | case AMDGPU_VM_MTYPE_WC: |
480 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); |
481 | case AMDGPU_VM_MTYPE_CC: |
482 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); |
483 | case AMDGPU_VM_MTYPE_UC: |
484 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); |
485 | default: |
486 | return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); |
487 | } |
488 | } |
489 | |
490 | static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, |
491 | uint64_t *addr, uint64_t *flags) |
492 | { |
493 | if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) |
494 | *addr = amdgpu_gmc_vram_mc2pa(adev, mc_addr: *addr); |
495 | BUG_ON(*addr & 0xFFFF00000000003FULL); |
496 | |
497 | if (!adev->gmc.translate_further) |
498 | return; |
499 | |
500 | if (level == AMDGPU_VM_PDB1) { |
501 | /* Set the block fragment size */ |
502 | if (!(*flags & AMDGPU_PDE_PTE)) |
503 | *flags |= AMDGPU_PDE_BFS(0x9); |
504 | |
505 | } else if (level == AMDGPU_VM_PDB0) { |
506 | if (*flags & AMDGPU_PDE_PTE) |
507 | *flags &= ~AMDGPU_PDE_PTE; |
508 | else |
509 | *flags |= AMDGPU_PTE_TF; |
510 | } |
511 | } |
512 | |
513 | static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, |
514 | struct amdgpu_bo_va_mapping *mapping, |
515 | uint64_t *flags) |
516 | { |
517 | struct amdgpu_bo *bo = mapping->bo_va->base.bo; |
518 | |
519 | *flags &= ~AMDGPU_PTE_EXECUTABLE; |
520 | *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; |
521 | |
522 | *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; |
523 | *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); |
524 | |
525 | *flags &= ~AMDGPU_PTE_NOALLOC; |
526 | *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); |
527 | |
528 | if (mapping->flags & AMDGPU_PTE_PRT) { |
529 | *flags |= AMDGPU_PTE_PRT; |
530 | *flags |= AMDGPU_PTE_SNOOPED; |
531 | *flags |= AMDGPU_PTE_LOG; |
532 | *flags |= AMDGPU_PTE_SYSTEM; |
533 | *flags &= ~AMDGPU_PTE_VALID; |
534 | } |
535 | |
536 | if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | |
537 | AMDGPU_GEM_CREATE_EXT_COHERENT | |
538 | AMDGPU_GEM_CREATE_UNCACHED)) |
539 | *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | |
540 | AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); |
541 | } |
542 | |
543 | static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) |
544 | { |
545 | u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); |
546 | unsigned int size; |
547 | |
548 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { |
549 | size = AMDGPU_VBIOS_VGA_ALLOCATION; |
550 | } else { |
551 | u32 viewport; |
552 | u32 pitch; |
553 | |
554 | viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); |
555 | pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); |
556 | size = (REG_GET_FIELD(viewport, |
557 | HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * |
558 | REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * |
559 | 4); |
560 | } |
561 | |
562 | return size; |
563 | } |
564 | |
565 | static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { |
566 | .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, |
567 | .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, |
568 | .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, |
569 | .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, |
570 | .map_mtype = gmc_v10_0_map_mtype, |
571 | .get_vm_pde = gmc_v10_0_get_vm_pde, |
572 | .get_vm_pte = gmc_v10_0_get_vm_pte, |
573 | .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, |
574 | }; |
575 | |
576 | static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) |
577 | { |
578 | if (adev->gmc.gmc_funcs == NULL) |
579 | adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; |
580 | } |
581 | |
582 | static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) |
583 | { |
584 | switch (amdgpu_ip_version(adev, ip: UMC_HWIP, inst: 0)) { |
585 | case IP_VERSION(8, 7, 0): |
586 | adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; |
587 | adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; |
588 | adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; |
589 | adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; |
590 | adev->umc.retire_unit = 1; |
591 | adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; |
592 | adev->umc.ras = &umc_v8_7_ras; |
593 | break; |
594 | default: |
595 | break; |
596 | } |
597 | } |
598 | |
599 | static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) |
600 | { |
601 | switch (amdgpu_ip_version(adev, ip: MMHUB_HWIP, inst: 0)) { |
602 | case IP_VERSION(2, 3, 0): |
603 | case IP_VERSION(2, 4, 0): |
604 | case IP_VERSION(2, 4, 1): |
605 | adev->mmhub.funcs = &mmhub_v2_3_funcs; |
606 | break; |
607 | default: |
608 | adev->mmhub.funcs = &mmhub_v2_0_funcs; |
609 | break; |
610 | } |
611 | } |
612 | |
613 | static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) |
614 | { |
615 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
616 | case IP_VERSION(10, 3, 0): |
617 | case IP_VERSION(10, 3, 2): |
618 | case IP_VERSION(10, 3, 1): |
619 | case IP_VERSION(10, 3, 4): |
620 | case IP_VERSION(10, 3, 5): |
621 | case IP_VERSION(10, 3, 6): |
622 | case IP_VERSION(10, 3, 3): |
623 | case IP_VERSION(10, 3, 7): |
624 | adev->gfxhub.funcs = &gfxhub_v2_1_funcs; |
625 | break; |
626 | default: |
627 | adev->gfxhub.funcs = &gfxhub_v2_0_funcs; |
628 | break; |
629 | } |
630 | } |
631 | |
632 | |
633 | static int gmc_v10_0_early_init(void *handle) |
634 | { |
635 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
636 | |
637 | gmc_v10_0_set_mmhub_funcs(adev); |
638 | gmc_v10_0_set_gfxhub_funcs(adev); |
639 | gmc_v10_0_set_gmc_funcs(adev); |
640 | gmc_v10_0_set_irq_funcs(adev); |
641 | gmc_v10_0_set_umc_funcs(adev); |
642 | |
643 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; |
644 | adev->gmc.shared_aperture_end = |
645 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; |
646 | adev->gmc.private_aperture_start = 0x1000000000000000ULL; |
647 | adev->gmc.private_aperture_end = |
648 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; |
649 | adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; |
650 | |
651 | return 0; |
652 | } |
653 | |
654 | static int gmc_v10_0_late_init(void *handle) |
655 | { |
656 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
657 | int r; |
658 | |
659 | r = amdgpu_gmc_allocate_vm_inv_eng(adev); |
660 | if (r) |
661 | return r; |
662 | |
663 | r = amdgpu_gmc_ras_late_init(adev); |
664 | if (r) |
665 | return r; |
666 | |
667 | return amdgpu_irq_get(adev, src: &adev->gmc.vm_fault, type: 0); |
668 | } |
669 | |
670 | static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, |
671 | struct amdgpu_gmc *mc) |
672 | { |
673 | u64 base = 0; |
674 | |
675 | base = adev->gfxhub.funcs->get_fb_location(adev); |
676 | |
677 | /* add the xgmi offset of the physical node */ |
678 | base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; |
679 | |
680 | amdgpu_gmc_set_agp_default(adev, mc); |
681 | amdgpu_gmc_vram_location(adev, mc: &adev->gmc, base); |
682 | amdgpu_gmc_gart_location(adev, mc, gart_placement: AMDGPU_GART_PLACEMENT_BEST_FIT); |
683 | if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) |
684 | amdgpu_gmc_agp_location(adev, mc); |
685 | |
686 | /* base offset of vram pages */ |
687 | adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); |
688 | |
689 | /* add the xgmi offset of the physical node */ |
690 | adev->vm_manager.vram_base_offset += |
691 | adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; |
692 | } |
693 | |
694 | /** |
695 | * gmc_v10_0_mc_init - initialize the memory controller driver params |
696 | * |
697 | * @adev: amdgpu_device pointer |
698 | * |
699 | * Look up the amount of vram, vram width, and decide how to place |
700 | * vram and gart within the GPU's physical address space. |
701 | * Returns 0 for success. |
702 | */ |
703 | static int gmc_v10_0_mc_init(struct amdgpu_device *adev) |
704 | { |
705 | int r; |
706 | |
707 | /* size in MB on si */ |
708 | adev->gmc.mc_vram_size = |
709 | adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; |
710 | adev->gmc.real_vram_size = adev->gmc.mc_vram_size; |
711 | |
712 | if (!(adev->flags & AMD_IS_APU)) { |
713 | r = amdgpu_device_resize_fb_bar(adev); |
714 | if (r) |
715 | return r; |
716 | } |
717 | adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); |
718 | adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); |
719 | |
720 | #ifdef CONFIG_X86_64 |
721 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { |
722 | adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); |
723 | adev->gmc.aper_size = adev->gmc.real_vram_size; |
724 | } |
725 | #endif |
726 | |
727 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
728 | |
729 | /* set the gart size */ |
730 | if (amdgpu_gart_size == -1) { |
731 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
732 | default: |
733 | adev->gmc.gart_size = 512ULL << 20; |
734 | break; |
735 | case IP_VERSION(10, 3, 1): /* DCE SG support */ |
736 | case IP_VERSION(10, 3, 3): /* DCE SG support */ |
737 | case IP_VERSION(10, 3, 6): /* DCE SG support */ |
738 | case IP_VERSION(10, 3, 7): /* DCE SG support */ |
739 | adev->gmc.gart_size = 1024ULL << 20; |
740 | break; |
741 | } |
742 | } else { |
743 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
744 | } |
745 | |
746 | gmc_v10_0_vram_gtt_location(adev, mc: &adev->gmc); |
747 | |
748 | return 0; |
749 | } |
750 | |
751 | static int gmc_v10_0_gart_init(struct amdgpu_device *adev) |
752 | { |
753 | int r; |
754 | |
755 | if (adev->gart.bo) { |
756 | WARN(1, "NAVI10 PCIE GART already initialized\n" ); |
757 | return 0; |
758 | } |
759 | |
760 | /* Initialize common gart structure */ |
761 | r = amdgpu_gart_init(adev); |
762 | if (r) |
763 | return r; |
764 | |
765 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; |
766 | adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | |
767 | AMDGPU_PTE_EXECUTABLE; |
768 | |
769 | return amdgpu_gart_table_vram_alloc(adev); |
770 | } |
771 | |
772 | static int gmc_v10_0_sw_init(void *handle) |
773 | { |
774 | int r, vram_width = 0, vram_type = 0, vram_vendor = 0; |
775 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
776 | |
777 | adev->gfxhub.funcs->init(adev); |
778 | |
779 | adev->mmhub.funcs->init(adev); |
780 | |
781 | spin_lock_init(&adev->gmc.invalidate_lock); |
782 | |
783 | if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { |
784 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; |
785 | adev->gmc.vram_width = 64; |
786 | } else if (amdgpu_emu_mode == 1) { |
787 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; |
788 | adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ |
789 | } else { |
790 | r = amdgpu_atomfirmware_get_vram_info(adev, |
791 | vram_width: &vram_width, vram_type: &vram_type, vram_vendor: &vram_vendor); |
792 | adev->gmc.vram_width = vram_width; |
793 | |
794 | adev->gmc.vram_type = vram_type; |
795 | adev->gmc.vram_vendor = vram_vendor; |
796 | } |
797 | |
798 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
799 | case IP_VERSION(10, 3, 0): |
800 | adev->gmc.mall_size = 128 * 1024 * 1024; |
801 | break; |
802 | case IP_VERSION(10, 3, 2): |
803 | adev->gmc.mall_size = 96 * 1024 * 1024; |
804 | break; |
805 | case IP_VERSION(10, 3, 4): |
806 | adev->gmc.mall_size = 32 * 1024 * 1024; |
807 | break; |
808 | case IP_VERSION(10, 3, 5): |
809 | adev->gmc.mall_size = 16 * 1024 * 1024; |
810 | break; |
811 | default: |
812 | adev->gmc.mall_size = 0; |
813 | break; |
814 | } |
815 | |
816 | switch (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0)) { |
817 | case IP_VERSION(10, 1, 10): |
818 | case IP_VERSION(10, 1, 1): |
819 | case IP_VERSION(10, 1, 2): |
820 | case IP_VERSION(10, 1, 3): |
821 | case IP_VERSION(10, 1, 4): |
822 | case IP_VERSION(10, 3, 0): |
823 | case IP_VERSION(10, 3, 2): |
824 | case IP_VERSION(10, 3, 1): |
825 | case IP_VERSION(10, 3, 4): |
826 | case IP_VERSION(10, 3, 5): |
827 | case IP_VERSION(10, 3, 6): |
828 | case IP_VERSION(10, 3, 3): |
829 | case IP_VERSION(10, 3, 7): |
830 | set_bit(AMDGPU_GFXHUB(0), addr: adev->vmhubs_mask); |
831 | set_bit(AMDGPU_MMHUB0(0), addr: adev->vmhubs_mask); |
832 | /* |
833 | * To fulfill 4-level page support, |
834 | * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, |
835 | * block size 512 (9bit) |
836 | */ |
837 | amdgpu_vm_adjust_size(adev, min_vm_size: 256 * 1024, fragment_size_default: 9, max_level: 3, max_bits: 48); |
838 | break; |
839 | default: |
840 | break; |
841 | } |
842 | |
843 | /* This interrupt is VMC page fault.*/ |
844 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_VMC, |
845 | VMC_1_0__SRCID__VM_FAULT, |
846 | source: &adev->gmc.vm_fault); |
847 | |
848 | if (r) |
849 | return r; |
850 | |
851 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_UTCL2, |
852 | UTCL2_1_0__SRCID__FAULT, |
853 | source: &adev->gmc.vm_fault); |
854 | if (r) |
855 | return r; |
856 | |
857 | if (!amdgpu_sriov_vf(adev)) { |
858 | /* interrupt sent to DF. */ |
859 | r = amdgpu_irq_add_id(adev, client_id: SOC15_IH_CLIENTID_DF, src_id: 0, |
860 | source: &adev->gmc.ecc_irq); |
861 | if (r) |
862 | return r; |
863 | } |
864 | |
865 | /* |
866 | * Set the internal MC address mask This is the max address of the GPU's |
867 | * internal address space. |
868 | */ |
869 | adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ |
870 | |
871 | r = dma_set_mask_and_coherent(dev: adev->dev, DMA_BIT_MASK(44)); |
872 | if (r) { |
873 | dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n" ); |
874 | return r; |
875 | } |
876 | |
877 | adev->need_swiotlb = drm_need_swiotlb(dma_bits: 44); |
878 | |
879 | r = gmc_v10_0_mc_init(adev); |
880 | if (r) |
881 | return r; |
882 | |
883 | amdgpu_gmc_get_vbios_allocations(adev); |
884 | |
885 | /* Memory manager */ |
886 | r = amdgpu_bo_init(adev); |
887 | if (r) |
888 | return r; |
889 | |
890 | r = gmc_v10_0_gart_init(adev); |
891 | if (r) |
892 | return r; |
893 | |
894 | /* |
895 | * number of VMs |
896 | * VMID 0 is reserved for System |
897 | * amdgpu graphics/compute will use VMIDs 1-7 |
898 | * amdkfd will use VMIDs 8-15 |
899 | */ |
900 | adev->vm_manager.first_kfd_vmid = 8; |
901 | |
902 | amdgpu_vm_manager_init(adev); |
903 | |
904 | r = amdgpu_gmc_ras_sw_init(adev); |
905 | if (r) |
906 | return r; |
907 | |
908 | return 0; |
909 | } |
910 | |
911 | /** |
912 | * gmc_v10_0_gart_fini - vm fini callback |
913 | * |
914 | * @adev: amdgpu_device pointer |
915 | * |
916 | * Tears down the driver GART/VM setup (CIK). |
917 | */ |
918 | static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) |
919 | { |
920 | amdgpu_gart_table_vram_free(adev); |
921 | } |
922 | |
923 | static int gmc_v10_0_sw_fini(void *handle) |
924 | { |
925 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
926 | |
927 | amdgpu_vm_manager_fini(adev); |
928 | gmc_v10_0_gart_fini(adev); |
929 | amdgpu_gem_force_release(adev); |
930 | amdgpu_bo_fini(adev); |
931 | |
932 | return 0; |
933 | } |
934 | |
935 | static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) |
936 | { |
937 | } |
938 | |
939 | /** |
940 | * gmc_v10_0_gart_enable - gart enable |
941 | * |
942 | * @adev: amdgpu_device pointer |
943 | */ |
944 | static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) |
945 | { |
946 | int r; |
947 | bool value; |
948 | |
949 | if (adev->gart.bo == NULL) { |
950 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n" ); |
951 | return -EINVAL; |
952 | } |
953 | |
954 | amdgpu_gtt_mgr_recover(mgr: &adev->mman.gtt_mgr); |
955 | |
956 | if (!adev->in_s0ix) { |
957 | r = adev->gfxhub.funcs->gart_enable(adev); |
958 | if (r) |
959 | return r; |
960 | } |
961 | |
962 | r = adev->mmhub.funcs->gart_enable(adev); |
963 | if (r) |
964 | return r; |
965 | |
966 | adev->hdp.funcs->init_registers(adev); |
967 | |
968 | /* Flush HDP after it is initialized */ |
969 | adev->hdp.funcs->flush_hdp(adev, NULL); |
970 | |
971 | value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? |
972 | false : true; |
973 | |
974 | if (!adev->in_s0ix) |
975 | adev->gfxhub.funcs->set_fault_enable_default(adev, value); |
976 | adev->mmhub.funcs->set_fault_enable_default(adev, value); |
977 | gmc_v10_0_flush_gpu_tlb(adev, vmid: 0, AMDGPU_MMHUB0(0), flush_type: 0); |
978 | if (!adev->in_s0ix) |
979 | gmc_v10_0_flush_gpu_tlb(adev, vmid: 0, AMDGPU_GFXHUB(0), flush_type: 0); |
980 | |
981 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n" , |
982 | (unsigned int)(adev->gmc.gart_size >> 20), |
983 | (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); |
984 | |
985 | return 0; |
986 | } |
987 | |
988 | static int gmc_v10_0_hw_init(void *handle) |
989 | { |
990 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
991 | int r; |
992 | |
993 | adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; |
994 | |
995 | /* The sequence of these two function calls matters.*/ |
996 | gmc_v10_0_init_golden_registers(adev); |
997 | |
998 | /* |
999 | * harvestable groups in gc_utcl2 need to be programmed before any GFX block |
1000 | * register setup within GMC, or else system hang when harvesting SA. |
1001 | */ |
1002 | if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) |
1003 | adev->gfxhub.funcs->utcl2_harvest(adev); |
1004 | |
1005 | r = gmc_v10_0_gart_enable(adev); |
1006 | if (r) |
1007 | return r; |
1008 | |
1009 | if (amdgpu_emu_mode == 1) { |
1010 | r = amdgpu_gmc_vram_checking(adev); |
1011 | if (r) |
1012 | return r; |
1013 | } |
1014 | |
1015 | if (adev->umc.funcs && adev->umc.funcs->init_registers) |
1016 | adev->umc.funcs->init_registers(adev); |
1017 | |
1018 | return 0; |
1019 | } |
1020 | |
1021 | /** |
1022 | * gmc_v10_0_gart_disable - gart disable |
1023 | * |
1024 | * @adev: amdgpu_device pointer |
1025 | * |
1026 | * This disables all VM page table. |
1027 | */ |
1028 | static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) |
1029 | { |
1030 | if (!adev->in_s0ix) |
1031 | adev->gfxhub.funcs->gart_disable(adev); |
1032 | adev->mmhub.funcs->gart_disable(adev); |
1033 | } |
1034 | |
1035 | static int gmc_v10_0_hw_fini(void *handle) |
1036 | { |
1037 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1038 | |
1039 | gmc_v10_0_gart_disable(adev); |
1040 | |
1041 | if (amdgpu_sriov_vf(adev)) { |
1042 | /* full access mode, so don't touch any GMC register */ |
1043 | DRM_DEBUG("For SRIOV client, shouldn't do anything.\n" ); |
1044 | return 0; |
1045 | } |
1046 | |
1047 | amdgpu_irq_put(adev, src: &adev->gmc.vm_fault, type: 0); |
1048 | |
1049 | if (adev->gmc.ecc_irq.funcs && |
1050 | amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__UMC)) |
1051 | amdgpu_irq_put(adev, src: &adev->gmc.ecc_irq, type: 0); |
1052 | |
1053 | return 0; |
1054 | } |
1055 | |
1056 | static int gmc_v10_0_suspend(void *handle) |
1057 | { |
1058 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1059 | |
1060 | gmc_v10_0_hw_fini(handle: adev); |
1061 | |
1062 | return 0; |
1063 | } |
1064 | |
1065 | static int gmc_v10_0_resume(void *handle) |
1066 | { |
1067 | int r; |
1068 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1069 | |
1070 | r = gmc_v10_0_hw_init(handle: adev); |
1071 | if (r) |
1072 | return r; |
1073 | |
1074 | amdgpu_vmid_reset_all(adev); |
1075 | |
1076 | return 0; |
1077 | } |
1078 | |
1079 | static bool gmc_v10_0_is_idle(void *handle) |
1080 | { |
1081 | /* MC is always ready in GMC v10.*/ |
1082 | return true; |
1083 | } |
1084 | |
1085 | static int gmc_v10_0_wait_for_idle(void *handle) |
1086 | { |
1087 | /* There is no need to wait for MC idle in GMC v10.*/ |
1088 | return 0; |
1089 | } |
1090 | |
1091 | static int gmc_v10_0_soft_reset(void *handle) |
1092 | { |
1093 | return 0; |
1094 | } |
1095 | |
1096 | static int gmc_v10_0_set_clockgating_state(void *handle, |
1097 | enum amd_clockgating_state state) |
1098 | { |
1099 | int r; |
1100 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1101 | |
1102 | /* |
1103 | * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled |
1104 | * is a new problem observed at DF 3.0.3, however with the same suspend sequence not |
1105 | * seen any issue on the DF 3.0.2 series platform. |
1106 | */ |
1107 | if (adev->in_s0ix && |
1108 | amdgpu_ip_version(adev, ip: DF_HWIP, inst: 0) > IP_VERSION(3, 0, 2)) { |
1109 | dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n" ); |
1110 | return 0; |
1111 | } |
1112 | |
1113 | r = adev->mmhub.funcs->set_clockgating(adev, state); |
1114 | if (r) |
1115 | return r; |
1116 | |
1117 | if (amdgpu_ip_version(adev, ip: ATHUB_HWIP, inst: 0) >= IP_VERSION(2, 1, 0)) |
1118 | return athub_v2_1_set_clockgating(adev, state); |
1119 | else |
1120 | return athub_v2_0_set_clockgating(adev, state); |
1121 | } |
1122 | |
1123 | static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) |
1124 | { |
1125 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1126 | |
1127 | if (amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 3) || |
1128 | amdgpu_ip_version(adev, ip: GC_HWIP, inst: 0) == IP_VERSION(10, 1, 4)) |
1129 | return; |
1130 | |
1131 | adev->mmhub.funcs->get_clockgating(adev, flags); |
1132 | |
1133 | if (amdgpu_ip_version(adev, ip: ATHUB_HWIP, inst: 0) >= IP_VERSION(2, 1, 0)) |
1134 | athub_v2_1_get_clockgating(adev, flags); |
1135 | else |
1136 | athub_v2_0_get_clockgating(adev, flags); |
1137 | } |
1138 | |
1139 | static int gmc_v10_0_set_powergating_state(void *handle, |
1140 | enum amd_powergating_state state) |
1141 | { |
1142 | return 0; |
1143 | } |
1144 | |
1145 | const struct amd_ip_funcs gmc_v10_0_ip_funcs = { |
1146 | .name = "gmc_v10_0" , |
1147 | .early_init = gmc_v10_0_early_init, |
1148 | .late_init = gmc_v10_0_late_init, |
1149 | .sw_init = gmc_v10_0_sw_init, |
1150 | .sw_fini = gmc_v10_0_sw_fini, |
1151 | .hw_init = gmc_v10_0_hw_init, |
1152 | .hw_fini = gmc_v10_0_hw_fini, |
1153 | .suspend = gmc_v10_0_suspend, |
1154 | .resume = gmc_v10_0_resume, |
1155 | .is_idle = gmc_v10_0_is_idle, |
1156 | .wait_for_idle = gmc_v10_0_wait_for_idle, |
1157 | .soft_reset = gmc_v10_0_soft_reset, |
1158 | .set_clockgating_state = gmc_v10_0_set_clockgating_state, |
1159 | .set_powergating_state = gmc_v10_0_set_powergating_state, |
1160 | .get_clockgating_state = gmc_v10_0_get_clockgating_state, |
1161 | }; |
1162 | |
1163 | const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { |
1164 | .type = AMD_IP_BLOCK_TYPE_GMC, |
1165 | .major = 10, |
1166 | .minor = 0, |
1167 | .rev = 0, |
1168 | .funcs = &gmc_v10_0_ip_funcs, |
1169 | }; |
1170 | |