1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "dmub_abm.h" |
27 | #include "dmub_abm_lcd.h" |
28 | #include "dce_abm.h" |
29 | #include "dc.h" |
30 | #include "dc_dmub_srv.h" |
31 | #include "dmub/dmub_srv.h" |
32 | #include "core_types.h" |
33 | #include "dm_services.h" |
34 | #include "reg_helper.h" |
35 | #include "fixed31_32.h" |
36 | |
37 | #ifdef _WIN32 |
38 | #include "atombios.h" |
39 | #else |
40 | #include "atom.h" |
41 | #endif |
42 | |
43 | #define TO_DMUB_ABM(abm)\ |
44 | container_of(abm, struct dce_abm, base) |
45 | |
46 | #define REG(reg) \ |
47 | (dce_abm->regs->reg) |
48 | |
49 | #undef FN |
50 | #define FN(reg_name, field_name) \ |
51 | dce_abm->abm_shift->field_name, dce_abm->abm_mask->field_name |
52 | |
53 | #define CTX \ |
54 | dce_abm->base.ctx |
55 | |
56 | #define DISABLE_ABM_IMMEDIATELY 255 |
57 | |
58 | |
59 | |
60 | static void dmub_abm_enable_fractional_pwm(struct dc_context *dc) |
61 | { |
62 | union dmub_rb_cmd cmd; |
63 | uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == false) ? 1 : 0; |
64 | uint32_t edp_id_count = dc->dc_edp_id_count; |
65 | int i; |
66 | uint8_t panel_mask = 0; |
67 | |
68 | for (i = 0; i < edp_id_count; i++) |
69 | panel_mask |= 0x01 << i; |
70 | |
71 | memset(&cmd, 0, sizeof(cmd)); |
72 | cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM; |
73 | cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC; |
74 | cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = fractional_pwm; |
75 | cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; |
76 | cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.panel_mask = panel_mask; |
77 | cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pwm_frac_data); |
78 | |
79 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
80 | } |
81 | |
82 | void dmub_abm_init(struct abm *abm, uint32_t backlight, uint32_t user_level) |
83 | { |
84 | struct dce_abm *dce_abm = TO_DMUB_ABM(abm); |
85 | |
86 | REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x3); |
87 | REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x1); |
88 | REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x3); |
89 | REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x1); |
90 | REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x1); |
91 | |
92 | REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, |
93 | ABM1_HG_NUM_OF_BINS_SEL, 0, |
94 | ABM1_HG_VMAX_SEL, 1, |
95 | ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0); |
96 | |
97 | REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, |
98 | ABM1_IPCSC_COEFF_SEL_R, 2, |
99 | ABM1_IPCSC_COEFF_SEL_G, 4, |
100 | ABM1_IPCSC_COEFF_SEL_B, 2); |
101 | |
102 | REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL, |
103 | BL1_PWM_CURRENT_ABM_LEVEL, backlight); |
104 | |
105 | REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL, |
106 | BL1_PWM_TARGET_ABM_LEVEL, backlight); |
107 | |
108 | REG_UPDATE(BL1_PWM_USER_LEVEL, |
109 | BL1_PWM_USER_LEVEL, user_level); |
110 | |
111 | REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, |
112 | ABM1_LS_MIN_PIXEL_VALUE_THRES, 0, |
113 | ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000); |
114 | |
115 | REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, |
116 | ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1, |
117 | ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1, |
118 | ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1); |
119 | |
120 | dmub_abm_enable_fractional_pwm(dc: abm->ctx); |
121 | } |
122 | |
123 | unsigned int dmub_abm_get_current_backlight(struct abm *abm) |
124 | { |
125 | struct dce_abm *dce_abm = TO_DMUB_ABM(abm); |
126 | unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL); |
127 | |
128 | /* return backlight in hardware format which is unsigned 17 bits, with |
129 | * 1 bit integer and 16 bit fractional |
130 | */ |
131 | return backlight; |
132 | } |
133 | |
134 | unsigned int dmub_abm_get_target_backlight(struct abm *abm) |
135 | { |
136 | struct dce_abm *dce_abm = TO_DMUB_ABM(abm); |
137 | unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL); |
138 | |
139 | /* return backlight in hardware format which is unsigned 17 bits, with |
140 | * 1 bit integer and 16 bit fractional |
141 | */ |
142 | return backlight; |
143 | } |
144 | |
145 | bool dmub_abm_set_level(struct abm *abm, uint32_t level, uint8_t panel_mask) |
146 | { |
147 | union dmub_rb_cmd cmd; |
148 | struct dc_context *dc = abm->ctx; |
149 | |
150 | memset(&cmd, 0, sizeof(cmd)); |
151 | cmd.abm_set_level.header.type = DMUB_CMD__ABM; |
152 | cmd.abm_set_level.header.sub_type = DMUB_CMD__ABM_SET_LEVEL; |
153 | cmd.abm_set_level.abm_set_level_data.level = level; |
154 | cmd.abm_set_level.abm_set_level_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; |
155 | cmd.abm_set_level.abm_set_level_data.panel_mask = panel_mask; |
156 | cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_level_data); |
157 | |
158 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
159 | |
160 | return true; |
161 | } |
162 | |
163 | void dmub_abm_init_config(struct abm *abm, |
164 | const char *src, |
165 | unsigned int bytes, |
166 | unsigned int inst) |
167 | { |
168 | union dmub_rb_cmd cmd; |
169 | struct dc_context *dc = abm->ctx; |
170 | uint8_t panel_mask = 0x01 << inst; |
171 | |
172 | // TODO: Optimize by only reading back final 4 bytes |
173 | dmub_flush_buffer_mem(fb: &dc->dmub_srv->dmub->scratch_mem_fb); |
174 | |
175 | // Copy iramtable into cw7 |
176 | memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes); |
177 | |
178 | memset(&cmd, 0, sizeof(cmd)); |
179 | // Fw will copy from cw7 to fw_state |
180 | cmd.abm_init_config.header.type = DMUB_CMD__ABM; |
181 | cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG; |
182 | cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; |
183 | cmd.abm_init_config.abm_init_config_data.bytes = bytes; |
184 | cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; |
185 | cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask; |
186 | |
187 | cmd.abm_init_config.header.payload_bytes = sizeof(struct dmub_cmd_abm_init_config_data); |
188 | |
189 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
190 | |
191 | } |
192 | |
193 | bool dmub_abm_set_pause(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int stream_inst) |
194 | { |
195 | union dmub_rb_cmd cmd; |
196 | struct dc_context *dc = abm->ctx; |
197 | uint8_t panel_mask = 0x01 << panel_inst; |
198 | |
199 | memset(&cmd, 0, sizeof(cmd)); |
200 | cmd.abm_pause.header.type = DMUB_CMD__ABM; |
201 | cmd.abm_pause.header.sub_type = DMUB_CMD__ABM_PAUSE; |
202 | cmd.abm_pause.abm_pause_data.enable = pause; |
203 | cmd.abm_pause.abm_pause_data.panel_mask = panel_mask; |
204 | cmd.abm_set_level.header.payload_bytes = sizeof(struct dmub_cmd_abm_pause_data); |
205 | |
206 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
207 | |
208 | return true; |
209 | } |
210 | |
211 | |
212 | /***************************************************************************** |
213 | * dmub_abm_save_restore() - dmub interface for abm save+pause and restore+ |
214 | * un-pause |
215 | * @dc: dc context |
216 | * @panel_inst: panel instance index |
217 | * @pData: contains command to pause/un-pause abm and exchange abm parameters |
218 | * |
219 | * When called Pause will get abm data and store in pData, and un-pause will |
220 | * set/apply abm data stored in pData. |
221 | * |
222 | *****************************************************************************/ |
223 | bool dmub_abm_save_restore( |
224 | struct dc_context *dc, |
225 | unsigned int panel_inst, |
226 | struct abm_save_restore *pData) |
227 | { |
228 | union dmub_rb_cmd cmd; |
229 | uint8_t panel_mask = 0x01 << panel_inst; |
230 | unsigned int bytes = sizeof(struct abm_save_restore); |
231 | |
232 | // TODO: Optimize by only reading back final 4 bytes |
233 | dmub_flush_buffer_mem(fb: &dc->dmub_srv->dmub->scratch_mem_fb); |
234 | |
235 | // Copy iramtable into cw7 |
236 | memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)pData, bytes); |
237 | |
238 | memset(&cmd, 0, sizeof(cmd)); |
239 | cmd.abm_save_restore.header.type = DMUB_CMD__ABM; |
240 | cmd.abm_save_restore.header.sub_type = DMUB_CMD__ABM_SAVE_RESTORE; |
241 | |
242 | cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr; |
243 | cmd.abm_save_restore.abm_init_config_data.bytes = bytes; |
244 | cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; |
245 | cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask; |
246 | |
247 | cmd.abm_save_restore.header.payload_bytes = sizeof(struct dmub_rb_cmd_abm_save_restore); |
248 | |
249 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
250 | |
251 | // Copy iramtable data into local structure |
252 | memcpy((void *)pData, dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes); |
253 | |
254 | return true; |
255 | } |
256 | |
257 | bool dmub_abm_set_pipe(struct abm *abm, |
258 | uint32_t otg_inst, |
259 | uint32_t option, |
260 | uint32_t panel_inst, |
261 | uint32_t pwrseq_inst) |
262 | { |
263 | union dmub_rb_cmd cmd; |
264 | struct dc_context *dc = abm->ctx; |
265 | uint32_t ramping_boundary = 0xFFFF; |
266 | |
267 | memset(&cmd, 0, sizeof(cmd)); |
268 | cmd.abm_set_pipe.header.type = DMUB_CMD__ABM; |
269 | cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE; |
270 | cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; |
271 | cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst; |
272 | cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option; |
273 | cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst; |
274 | cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary; |
275 | cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data); |
276 | |
277 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
278 | |
279 | return true; |
280 | } |
281 | |
282 | bool dmub_abm_set_backlight_level(struct abm *abm, |
283 | unsigned int backlight_pwm_u16_16, |
284 | unsigned int frame_ramp, |
285 | unsigned int panel_inst) |
286 | { |
287 | union dmub_rb_cmd cmd; |
288 | struct dc_context *dc = abm->ctx; |
289 | |
290 | memset(&cmd, 0, sizeof(cmd)); |
291 | cmd.abm_set_backlight.header.type = DMUB_CMD__ABM; |
292 | cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT; |
293 | cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp; |
294 | cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16; |
295 | cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1; |
296 | cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_inst); |
297 | cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data); |
298 | |
299 | dc_wake_and_execute_dmub_cmd(ctx: dc, cmd: &cmd, wait_type: DM_DMUB_WAIT_TYPE_WAIT); |
300 | |
301 | return true; |
302 | } |
303 | |
304 | |