1/*
2 * Copyright 2012-17 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_MEM_INPUT_DCN201_H__
27#define __DC_MEM_INPUT_DCN201_H__
28
29#include "../dcn10/dcn10_hubp.h"
30#include "../dcn20/dcn20_hubp.h"
31
32#define TO_DCN201_HUBP(hubp)\
33 container_of(hubp, struct dcn201_hubp, base)
34
35#define HUBP_REG_LIST_DCN201(id)\
36 HUBP_REG_LIST_DCN(id),\
37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
39 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
40 SRI(CURSOR_SETTINGS, HUBPREQ, id), \
41 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
42 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
43 SRI(CURSOR_SIZE, CURSOR0_, id), \
44 SRI(CURSOR_CONTROL, CURSOR0_, id), \
45 SRI(CURSOR_POSITION, CURSOR0_, id), \
46 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
47 SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \
48 SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
49 SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
50 SRI(DMDATA_CNTL, CURSOR0_, id), \
51 SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
52 SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \
53 SRI(DMDATA_SW_DATA, CURSOR0_, id), \
54 SRI(DMDATA_STATUS, CURSOR0_, id),\
55 SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
56 SRI(FLIP_PARAMETERS_2, HUBPREQ, id)
57
58#define HUBP_MASK_SH_LIST_DCN201(mask_sh)\
59 HUBP_MASK_SH_LIST_DCN(mask_sh),\
60 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
61 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
62 HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
63 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
64 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
65 HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
66 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
67 HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
68 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
69 HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
70 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
71 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
72 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
73 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
74 HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
75 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
76 HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
77 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
78 HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
79 HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
80 HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
81 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
82 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
83 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
84 HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
85 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
86 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
87 HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
88 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
89 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
90 HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh),\
91 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
92 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
93 HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
94 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
95 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
96 HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh)
97
98#define DCN201_HUBP_REG_VARIABLE_LIST \
99 DCN2_HUBP_REG_COMMON_VARIABLE_LIST
100
101#define DCN201_HUBP_REG_FIELD_VARIABLE_LIST(type) \
102 DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type)
103
104struct dcn201_hubp_registers {
105 DCN201_HUBP_REG_VARIABLE_LIST;
106};
107
108struct dcn201_hubp_shift {
109 DCN201_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
110};
111
112struct dcn201_hubp_mask {
113 DCN201_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
114};
115
116struct dcn201_hubp {
117 struct hubp base;
118 struct dcn_hubp_state state;
119 const struct dcn201_hubp_registers *hubp_regs;
120 const struct dcn201_hubp_shift *hubp_shift;
121 const struct dcn201_hubp_mask *hubp_mask;
122};
123
124bool dcn201_hubp_construct(
125 struct dcn201_hubp *hubp201,
126 struct dc_context *ctx,
127 uint32_t inst,
128 const struct dcn201_hubp_registers *hubp_regs,
129 const struct dcn201_hubp_shift *hubp_shift,
130 const struct dcn201_hubp_mask *hubp_mask);
131
132#endif /* __DC_HWSS_DCN20_H__ */
133

source code of linux/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h