1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef DAL_DC_DCN21_DCN21_HUBP_H_ |
27 | #define DAL_DC_DCN21_DCN21_HUBP_H_ |
28 | |
29 | #include "../dcn20/dcn20_hubp.h" |
30 | #include "../dcn10/dcn10_hubp.h" |
31 | |
32 | #define TO_DCN21_HUBP(hubp)\ |
33 | container_of(hubp, struct dcn21_hubp, base) |
34 | |
35 | #define HUBP_REG_LIST_DCN21(id)\ |
36 | HUBP_REG_LIST_DCN2_COMMON(id),\ |
37 | SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\ |
38 | SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\ |
39 | SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\ |
40 | SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\ |
41 | SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\ |
42 | SRI(VBLANK_PARAMETERS_6, HUBPREQ, id) |
43 | |
44 | #define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\ |
45 | HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ |
46 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ |
47 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ |
48 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ |
49 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ |
50 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ |
51 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ |
52 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ |
53 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ |
54 | HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ |
55 | HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ |
56 | HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ |
57 | HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ |
58 | HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ |
59 | HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ |
60 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ |
61 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ |
62 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ |
63 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ |
64 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ |
65 | HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ |
66 | HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ |
67 | HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ |
68 | HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ |
69 | HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ |
70 | HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ |
71 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ |
72 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ |
73 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ |
74 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ |
75 | HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ |
76 | HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ |
77 | HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ |
78 | HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ |
79 | HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ |
80 | HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ |
81 | HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ |
82 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ |
83 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ |
84 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ |
85 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ |
86 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ |
87 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ |
88 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ |
89 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ |
90 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ |
91 | HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\ |
92 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\ |
93 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\ |
94 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\ |
95 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ |
96 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ |
97 | HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ |
98 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) |
99 | |
100 | #define HUBP_MASK_SH_LIST_DCN21(mask_sh)\ |
101 | HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\ |
102 | HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh) |
103 | |
104 | |
105 | struct dcn21_hubp { |
106 | struct hubp base; |
107 | struct dcn_hubp_state state; |
108 | const struct dcn_hubp2_registers *hubp_regs; |
109 | const struct dcn_hubp2_shift *hubp_shift; |
110 | const struct dcn_hubp2_mask *hubp_mask; |
111 | int PLAT_54186_wa_chroma_addr_offset; |
112 | }; |
113 | |
114 | bool hubp21_construct( |
115 | struct dcn21_hubp *hubp21, |
116 | struct dc_context *ctx, |
117 | uint32_t inst, |
118 | const struct dcn_hubp2_registers *hubp_regs, |
119 | const struct dcn_hubp2_shift *hubp_shift, |
120 | const struct dcn_hubp2_mask *hubp_mask); |
121 | |
122 | void apply_DEDCN21_142_wa_for_hostvm_deadline( |
123 | struct hubp *hubp, |
124 | struct _vcs_dpi_display_dlg_regs_st *dlg_attr); |
125 | |
126 | void hubp21_program_deadline( |
127 | struct hubp *hubp, |
128 | struct _vcs_dpi_display_dlg_regs_st *dlg_attr, |
129 | struct _vcs_dpi_display_ttu_regs_st *ttu_attr); |
130 | |
131 | void hubp21_program_requestor( |
132 | struct hubp *hubp, |
133 | struct _vcs_dpi_display_rq_regs_st *rq_regs); |
134 | #endif /* DAL_DC_DCN21_DCN21_HUBP_H_ */ |
135 | |