1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | |
27 | #include "reg_helper.h" |
28 | |
29 | #include "core_types.h" |
30 | #include "link_encoder.h" |
31 | #include "dcn31/dcn31_dio_link_encoder.h" |
32 | #include "dcn32_dio_link_encoder.h" |
33 | #include "stream_encoder.h" |
34 | #include "dc_bios_types.h" |
35 | #include "link_enc_cfg.h" |
36 | |
37 | #include "gpio_service_interface.h" |
38 | |
39 | #ifndef MIN |
40 | #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) |
41 | #endif |
42 | |
43 | #define CTX \ |
44 | enc10->base.ctx |
45 | #define DC_LOGGER \ |
46 | enc10->base.ctx->logger |
47 | |
48 | #define REG(reg)\ |
49 | (enc10->link_regs->reg) |
50 | |
51 | #undef FN |
52 | #define FN(reg_name, field_name) \ |
53 | enc10->link_shift->field_name, enc10->link_mask->field_name |
54 | |
55 | #define AUX_REG(reg)\ |
56 | (enc10->aux_regs->reg) |
57 | |
58 | #define AUX_REG_READ(reg_name) \ |
59 | dm_read_reg(CTX, AUX_REG(reg_name)) |
60 | |
61 | #define AUX_REG_WRITE(reg_name, val) \ |
62 | dm_write_reg(CTX, AUX_REG(reg_name), val) |
63 | |
64 | |
65 | void enc32_hw_init(struct link_encoder *enc) |
66 | { |
67 | struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); |
68 | |
69 | /* |
70 | 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 |
71 | 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 |
72 | 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 |
73 | 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 |
74 | 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 |
75 | 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 |
76 | 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 |
77 | 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 |
78 | */ |
79 | |
80 | /* |
81 | AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, |
82 | AUX_RX_START_WINDOW = 1 [6:4] |
83 | AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] |
84 | AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 |
85 | AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 |
86 | AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 |
87 | AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 |
88 | AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 |
89 | AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 |
90 | AUX_RX_DETECTION_THRESHOLD [30:28] = 1 |
91 | */ |
92 | AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); |
93 | |
94 | AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); |
95 | |
96 | //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; |
97 | // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk |
98 | // 27MHz -> 0xd |
99 | // 100MHz -> 0x32 |
100 | // 48MHz -> 0x18 |
101 | |
102 | // Set TMDS_CTL0 to 1. This is a legacy setting. |
103 | REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); |
104 | |
105 | dcn10_aux_initialize(enc10); |
106 | } |
107 | |
108 | |
109 | void dcn32_link_encoder_enable_dp_output( |
110 | struct link_encoder *enc, |
111 | const struct dc_link_settings *link_settings, |
112 | enum clock_source_id clock_source) |
113 | { |
114 | if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { |
115 | dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); |
116 | return; |
117 | } |
118 | } |
119 | |
120 | static bool dcn32_link_encoder_is_in_alt_mode(struct link_encoder *enc) |
121 | { |
122 | struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); |
123 | uint32_t dp_alt_mode_disable = 0; |
124 | bool is_usb_c_alt_mode = false; |
125 | |
126 | if (enc->features.flags.bits.DP_IS_USB_C) { |
127 | /* if value == 1 alt mode is disabled, otherwise it is enabled */ |
128 | REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); |
129 | is_usb_c_alt_mode = (dp_alt_mode_disable == 0); |
130 | } |
131 | |
132 | return is_usb_c_alt_mode; |
133 | } |
134 | |
135 | static void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, |
136 | struct dc_link_settings *link_settings) |
137 | { |
138 | struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); |
139 | uint32_t is_in_usb_c_dp4_mode = 0; |
140 | |
141 | dcn10_link_encoder_get_max_link_cap(enc, link_settings); |
142 | |
143 | /* in usb c dp2 mode, max lane count is 2 */ |
144 | if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { |
145 | REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); |
146 | if (!is_in_usb_c_dp4_mode) |
147 | link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); |
148 | } |
149 | |
150 | } |
151 | |
152 | static const struct link_encoder_funcs dcn32_link_enc_funcs = { |
153 | .read_state = link_enc2_read_state, |
154 | .validate_output_with_stream = |
155 | dcn30_link_encoder_validate_output_with_stream, |
156 | .hw_init = enc32_hw_init, |
157 | .setup = dcn10_link_encoder_setup, |
158 | .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, |
159 | .enable_dp_output = dcn32_link_encoder_enable_dp_output, |
160 | .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, |
161 | .disable_output = dcn10_link_encoder_disable_output, |
162 | .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, |
163 | .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, |
164 | .update_mst_stream_allocation_table = |
165 | dcn10_link_encoder_update_mst_stream_allocation_table, |
166 | .psr_program_dp_dphy_fast_training = |
167 | dcn10_psr_program_dp_dphy_fast_training, |
168 | .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, |
169 | .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, |
170 | .enable_hpd = dcn10_link_encoder_enable_hpd, |
171 | .disable_hpd = dcn10_link_encoder_disable_hpd, |
172 | .is_dig_enabled = dcn10_is_dig_enabled, |
173 | .destroy = dcn10_link_encoder_destroy, |
174 | .fec_set_enable = enc2_fec_set_enable, |
175 | .fec_set_ready = enc2_fec_set_ready, |
176 | .fec_is_active = enc2_fec_is_active, |
177 | .get_dig_frontend = dcn10_get_dig_frontend, |
178 | .get_dig_mode = dcn10_get_dig_mode, |
179 | .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, |
180 | .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, |
181 | .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, |
182 | }; |
183 | |
184 | void dcn32_link_encoder_construct( |
185 | struct dcn20_link_encoder *enc20, |
186 | const struct encoder_init_data *init_data, |
187 | const struct encoder_feature_support *enc_features, |
188 | const struct dcn10_link_enc_registers *link_regs, |
189 | const struct dcn10_link_enc_aux_registers *aux_regs, |
190 | const struct dcn10_link_enc_hpd_registers *hpd_regs, |
191 | const struct dcn10_link_enc_shift *link_shift, |
192 | const struct dcn10_link_enc_mask *link_mask) |
193 | { |
194 | struct bp_connector_speed_cap_info bp_cap_info = {0}; |
195 | const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; |
196 | enum bp_result result = BP_RESULT_OK; |
197 | struct dcn10_link_encoder *enc10 = &enc20->enc10; |
198 | |
199 | enc10->base.funcs = &dcn32_link_enc_funcs; |
200 | enc10->base.ctx = init_data->ctx; |
201 | enc10->base.id = init_data->encoder; |
202 | |
203 | enc10->base.hpd_source = init_data->hpd_source; |
204 | enc10->base.connector = init_data->connector; |
205 | |
206 | if (enc10->base.connector.id == CONNECTOR_ID_USBC) |
207 | enc10->base.features.flags.bits.DP_IS_USB_C = 1; |
208 | |
209 | enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; |
210 | |
211 | enc10->base.features = *enc_features; |
212 | |
213 | enc10->base.transmitter = init_data->transmitter; |
214 | |
215 | /* set the flag to indicate whether driver poll the I2C data pin |
216 | * while doing the DP sink detect |
217 | */ |
218 | |
219 | /* if (dal_adapter_service_is_feature_supported(as, |
220 | FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) |
221 | enc10->base.features.flags.bits. |
222 | DP_SINK_DETECT_POLL_DATA_PIN = true;*/ |
223 | |
224 | enc10->base.output_signals = |
225 | SIGNAL_TYPE_DVI_SINGLE_LINK | |
226 | SIGNAL_TYPE_DVI_DUAL_LINK | |
227 | SIGNAL_TYPE_LVDS | |
228 | SIGNAL_TYPE_DISPLAY_PORT | |
229 | SIGNAL_TYPE_DISPLAY_PORT_MST | |
230 | SIGNAL_TYPE_EDP | |
231 | SIGNAL_TYPE_HDMI_TYPE_A; |
232 | |
233 | enc10->link_regs = link_regs; |
234 | enc10->aux_regs = aux_regs; |
235 | enc10->hpd_regs = hpd_regs; |
236 | enc10->link_shift = link_shift; |
237 | enc10->link_mask = link_mask; |
238 | |
239 | switch (enc10->base.transmitter) { |
240 | case TRANSMITTER_UNIPHY_A: |
241 | enc10->base.preferred_engine = ENGINE_ID_DIGA; |
242 | break; |
243 | case TRANSMITTER_UNIPHY_B: |
244 | enc10->base.preferred_engine = ENGINE_ID_DIGB; |
245 | break; |
246 | case TRANSMITTER_UNIPHY_C: |
247 | enc10->base.preferred_engine = ENGINE_ID_DIGC; |
248 | break; |
249 | case TRANSMITTER_UNIPHY_D: |
250 | enc10->base.preferred_engine = ENGINE_ID_DIGD; |
251 | break; |
252 | case TRANSMITTER_UNIPHY_E: |
253 | enc10->base.preferred_engine = ENGINE_ID_DIGE; |
254 | break; |
255 | default: |
256 | ASSERT_CRITICAL(false); |
257 | enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; |
258 | } |
259 | |
260 | /* default to one to mirror Windows behavior */ |
261 | enc10->base.features.flags.bits.HDMI_6GB_EN = 1; |
262 | |
263 | if (bp_funcs->get_connector_speed_cap_info) |
264 | result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, |
265 | enc10->base.connector, &bp_cap_info); |
266 | |
267 | /* Override features with DCE-specific values */ |
268 | if (result == BP_RESULT_OK) { |
269 | enc10->base.features.flags.bits.IS_HBR2_CAPABLE = |
270 | bp_cap_info.DP_HBR2_EN; |
271 | enc10->base.features.flags.bits.IS_HBR3_CAPABLE = |
272 | bp_cap_info.DP_HBR3_EN; |
273 | enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; |
274 | enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; |
275 | enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; |
276 | enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; |
277 | enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; |
278 | } else { |
279 | DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n" , |
280 | __func__, |
281 | result); |
282 | } |
283 | if (enc10->base.ctx->dc->debug.hdmi20_disable) { |
284 | enc10->base.features.flags.bits.HDMI_6GB_EN = 0; |
285 | } |
286 | } |
287 | |