1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "reg_helper.h"
27#include "dcn30/dcn30_mpc.h"
28#include "dcn30/dcn30_cm_common.h"
29#include "dcn32_mpc.h"
30#include "basics/conversion.h"
31#include "dcn10/dcn10_cm_common.h"
32#include "dc.h"
33
34#define REG(reg)\
35 mpc30->mpc_regs->reg
36
37#define CTX \
38 mpc30->base.ctx
39
40#undef FN
41#define FN(reg_name, field_name) \
42 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
43
44
45void mpc32_mpc_init(struct mpc *mpc)
46{
47 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
48 int mpcc_id;
49
50 mpc1_mpc_init(mpc);
51
52 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
53 if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE) {
54 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) {
55 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);
56 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);
57 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);
58 }
59 }
60 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) {
61 for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++)
62 REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);
63 }
64 }
65}
66
67void mpc32_power_on_blnd_lut(
68 struct mpc *mpc,
69 uint32_t mpcc_id,
70 bool power_on)
71{
72 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
73
74 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {
75 if (power_on) {
76 REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
77 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
78 } else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
79 ASSERT(false);
80 /* TODO: change to mpc
81 * dpp_base->ctx->dc->optimized_required = true;
82 * dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;
83 */
84 }
85 } else {
86 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
87 MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);
88 }
89}
90
91static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)
92{
93 enum dc_lut_mode mode;
94 uint32_t mode_current = 0;
95 uint32_t in_use = 0;
96
97 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
98
99 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
100 MPCC_MCM_1DLUT_MODE_CURRENT, &mode_current);
101 REG_GET(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
102 MPCC_MCM_1DLUT_SELECT_CURRENT, &in_use);
103
104 switch (mode_current) {
105 case 0:
106 case 1:
107 mode = LUT_BYPASS;
108 break;
109
110 case 2:
111 if (in_use == 0)
112 mode = LUT_RAM_A;
113 else
114 mode = LUT_RAM_B;
115 break;
116 default:
117 mode = LUT_BYPASS;
118 break;
119 }
120 return mode;
121}
122
123void mpc32_configure_post1dlut(
124 struct mpc *mpc,
125 uint32_t mpcc_id,
126 bool is_ram_a)
127{
128 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
129
130 //TODO: this
131 REG_UPDATE_2(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id],
132 MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 7,
133 MPCC_MCM_1DLUT_LUT_HOST_SEL, is_ram_a == true ? 0 : 1);
134
135 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
136}
137
138static void mpc32_post1dlut_get_reg_field(
139 struct dcn30_mpc *mpc,
140 struct dcn3_xfer_func_reg *reg)
141{
142 reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
143 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;
144 reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
145 reg->masks.exp_region0_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;
146 reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
147 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;
148 reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
149 reg->masks.exp_region1_num_segments = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS;
150
151 reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
152 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;
153 reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
154 reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;
155 reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
156 reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;
157 reg->shifts.field_region_linear_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
158 reg->masks.field_region_linear_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;
159 reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
160 reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;
161 reg->shifts.exp_resion_start_segment = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
162 reg->masks.exp_resion_start_segment = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;
163}
164
165/*program blnd lut RAM A*/
166void mpc32_program_post1dluta_settings(
167 struct mpc *mpc,
168 uint32_t mpcc_id,
169 const struct pwl_params *params)
170{
171 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
172 struct dcn3_xfer_func_reg gam_regs;
173
174 mpc32_post1dlut_get_reg_field(mpc: mpc30, reg: &gam_regs);
175
176 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
177 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
178 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
179 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
180 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
181 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
182 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
183 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]);
184 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_G[mpcc_id]);
185 gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_G[mpcc_id]);
186 gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_R[mpcc_id]);
187 gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_R[mpcc_id]);
188 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMA_REGION_0_1[mpcc_id]);
189 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMA_REGION_32_33[mpcc_id]);
190
191 cm_helper_program_gamcor_xfer_func(ctx: mpc->ctx, params, reg: &gam_regs);
192}
193
194/*program blnd lut RAM B*/
195void mpc32_program_post1dlutb_settings(
196 struct mpc *mpc,
197 uint32_t mpcc_id,
198 const struct pwl_params *params)
199{
200 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
201 struct dcn3_xfer_func_reg gam_regs;
202
203 mpc32_post1dlut_get_reg_field(mpc: mpc30, reg: &gam_regs);
204
205 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_B[mpcc_id]);
206 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_G[mpcc_id]);
207 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_CNTL_R[mpcc_id]);
208 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B[mpcc_id]);
209 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G[mpcc_id]);
210 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R[mpcc_id]);
211 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_B[mpcc_id]);
212 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_B[mpcc_id]);
213 gam_regs.start_end_cntl1_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_G[mpcc_id]);
214 gam_regs.start_end_cntl2_g = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_G[mpcc_id]);
215 gam_regs.start_end_cntl1_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL1_R[mpcc_id]);
216 gam_regs.start_end_cntl2_r = REG(MPCC_MCM_1DLUT_RAMB_END_CNTL2_R[mpcc_id]);
217 gam_regs.region_start = REG(MPCC_MCM_1DLUT_RAMB_REGION_0_1[mpcc_id]);
218 gam_regs.region_end = REG(MPCC_MCM_1DLUT_RAMB_REGION_32_33[mpcc_id]);
219
220 cm_helper_program_gamcor_xfer_func(ctx: mpc->ctx, params, reg: &gam_regs);
221}
222
223void mpc32_program_post1dlut_pwl(
224 struct mpc *mpc,
225 uint32_t mpcc_id,
226 const struct pwl_result_data *rgb,
227 uint32_t num)
228{
229 uint32_t i;
230 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
231 uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
232 uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
233 uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
234
235 if (is_rgb_equal(rgb, num)) {
236 for (i = 0 ; i < num; i++)
237 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
238 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
239 } else {
240 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
241 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);
242 for (i = 0 ; i < num; i++)
243 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);
244 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);
245
246 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
247 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);
248 for (i = 0 ; i < num; i++)
249 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);
250 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);
251
252 REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);
253 REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);
254 for (i = 0 ; i < num; i++)
255 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);
256 REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);
257 }
258}
259
260bool mpc32_program_post1dlut(
261 struct mpc *mpc,
262 const struct pwl_params *params,
263 uint32_t mpcc_id)
264{
265 enum dc_lut_mode current_mode;
266 enum dc_lut_mode next_mode;
267 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
268
269 if (params == NULL) {
270 REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);
271 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm)
272 mpc32_power_on_blnd_lut(mpc, mpcc_id, power_on: false);
273 return false;
274 }
275
276 current_mode = mpc32_get_post1dlut_current(mpc, mpcc_id);
277 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_B)
278 next_mode = LUT_RAM_A;
279 else
280 next_mode = LUT_RAM_B;
281
282 mpc32_power_on_blnd_lut(mpc, mpcc_id, power_on: true);
283 mpc32_configure_post1dlut(mpc, mpcc_id, is_ram_a: next_mode == LUT_RAM_A);
284
285 if (next_mode == LUT_RAM_A)
286 mpc32_program_post1dluta_settings(mpc, mpcc_id, params);
287 else
288 mpc32_program_post1dlutb_settings(mpc, mpcc_id, params);
289
290 mpc32_program_post1dlut_pwl(
291 mpc, mpcc_id, rgb: params->rgb_resulted, num: params->hw_points_num);
292
293 REG_UPDATE_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id],
294 MPCC_MCM_1DLUT_MODE, 2,
295 MPCC_MCM_1DLUT_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
296
297 return true;
298}
299
300static enum dc_lut_mode mpc32_get_shaper_current(struct mpc *mpc, uint32_t mpcc_id)
301{
302 enum dc_lut_mode mode;
303 uint32_t state_mode;
304 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
305
306 REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_MODE_CURRENT, &state_mode);
307
308 switch (state_mode) {
309 case 0:
310 mode = LUT_BYPASS;
311 break;
312 case 1:
313 mode = LUT_RAM_A;
314 break;
315 case 2:
316 mode = LUT_RAM_B;
317 break;
318 default:
319 mode = LUT_BYPASS;
320 break;
321 }
322
323 return mode;
324}
325
326
327void mpc32_configure_shaper_lut(
328 struct mpc *mpc,
329 bool is_ram_a,
330 uint32_t mpcc_id)
331{
332 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
333
334 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
335 MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, 7);
336 REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],
337 MPCC_MCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
338 REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);
339}
340
341
342void mpc32_program_shaper_luta_settings(
343 struct mpc *mpc,
344 const struct pwl_params *params,
345 uint32_t mpcc_id)
346{
347 const struct gamma_curve *curve;
348 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
349
350 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0,
351 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
352 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
353 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0,
354 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
355 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
356 REG_SET_2(MPCC_MCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0,
357 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
358 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
359
360 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0,
361 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
362 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
363 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0,
364 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
365 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
366 REG_SET_2(MPCC_MCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0,
367 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
368 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
369
370 curve = params->arr_curve_points;
371 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0,
372 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
373 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
374 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
375 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
376
377 curve += 2;
378 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0,
379 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
380 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
381 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
382 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
383
384 curve += 2;
385 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0,
386 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
387 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
388 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
389 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
390
391 curve += 2;
392 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0,
393 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
394 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
395 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
396 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
397
398 curve += 2;
399 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0,
400 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
401 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
402 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
403 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
404
405 curve += 2;
406 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0,
407 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
408 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
409 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
410 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
411
412 curve += 2;
413 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0,
414 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
415 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
416 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
417 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
418
419 curve += 2;
420 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0,
421 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
422 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
423 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
424 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
425
426
427 curve += 2;
428 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0,
429 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
430 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
431 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
432 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
433
434 curve += 2;
435 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0,
436 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
437 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
438 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
439 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
440
441 curve += 2;
442 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0,
443 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
444 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
445 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
446 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
447
448 curve += 2;
449 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0,
450 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
451 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
452 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
453 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
454
455 curve += 2;
456 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0,
457 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
458 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
459 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
460 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
461
462 curve += 2;
463 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0,
464 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
465 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
466 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
467 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
468
469 curve += 2;
470 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0,
471 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
472 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
473 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
474 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
475
476 curve += 2;
477 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0,
478 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
479 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
480 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
481 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
482
483 curve += 2;
484 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0,
485 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
486 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
487 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
488 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
489}
490
491
492void mpc32_program_shaper_lutb_settings(
493 struct mpc *mpc,
494 const struct pwl_params *params,
495 uint32_t mpcc_id)
496{
497 const struct gamma_curve *curve;
498 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
499
500 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0,
501 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x,
502 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
503 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0,
504 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x,
505 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
506 REG_SET_2(MPCC_MCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0,
507 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x,
508 MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0);
509
510 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0,
511 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x,
512 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y);
513 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0,
514 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x,
515 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y);
516 REG_SET_2(MPCC_MCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0,
517 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x,
518 MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y);
519
520 curve = params->arr_curve_points;
521 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0,
522 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
523 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
524 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
525 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
526
527 curve += 2;
528 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0,
529 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
530 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
531 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
532 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
533
534
535 curve += 2;
536 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0,
537 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
538 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
539 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
540 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
541
542 curve += 2;
543 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0,
544 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
545 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
546 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
547 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
548
549 curve += 2;
550 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0,
551 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
552 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
553 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
554 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
555
556 curve += 2;
557 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0,
558 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
559 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
560 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
561 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
562
563 curve += 2;
564 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0,
565 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
566 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
567 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
568 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
569
570 curve += 2;
571 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0,
572 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
573 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
574 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
575 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
576
577
578 curve += 2;
579 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0,
580 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
581 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
582 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
583 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
584
585 curve += 2;
586 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0,
587 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
588 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
589 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
590 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
591
592 curve += 2;
593 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0,
594 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
595 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
596 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
597 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
598
599 curve += 2;
600 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0,
601 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
602 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
603 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
604 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
605
606 curve += 2;
607 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0,
608 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
609 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
610 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
611 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
612
613 curve += 2;
614 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0,
615 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
616 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
617 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
618 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
619
620 curve += 2;
621 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0,
622 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
623 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
624 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
625 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
626
627 curve += 2;
628 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0,
629 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
630 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
631 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
632 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
633
634 curve += 2;
635 REG_SET_4(MPCC_MCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0,
636 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
637 MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
638 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
639 MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
640}
641
642
643void mpc32_program_shaper_lut(
644 struct mpc *mpc,
645 const struct pwl_result_data *rgb,
646 uint32_t num,
647 uint32_t mpcc_id)
648{
649 uint32_t i, red, green, blue;
650 uint32_t red_delta, green_delta, blue_delta;
651 uint32_t red_value, green_value, blue_value;
652
653 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
654
655 for (i = 0 ; i < num; i++) {
656
657 red = rgb[i].red_reg;
658 green = rgb[i].green_reg;
659 blue = rgb[i].blue_reg;
660
661 red_delta = rgb[i].delta_red_reg;
662 green_delta = rgb[i].delta_green_reg;
663 blue_delta = rgb[i].delta_blue_reg;
664
665 red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff);
666 green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff);
667 blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff);
668
669 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);
670 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);
671 REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);
672 }
673
674}
675
676
677void mpc32_power_on_shaper_3dlut(
678 struct mpc *mpc,
679 uint32_t mpcc_id,
680 bool power_on)
681{
682 uint32_t power_status_shaper = 2;
683 uint32_t power_status_3dlut = 2;
684 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
685 int max_retries = 10;
686
687 REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,
688 MPCC_MCM_3DLUT_MEM_PWR_DIS, power_on == true ? 1:0);
689 /* wait for memory to fully power up */
690 if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) {
691 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries);
692 REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries);
693 }
694
695 /*read status is not mandatory, it is just for debugging*/
696 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_PWR_STATE, &power_status_shaper);
697 REG_GET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut);
698
699 if (power_status_shaper != 0 && power_on == true)
700 BREAK_TO_DEBUGGER();
701
702 if (power_status_3dlut != 0 && power_on == true)
703 BREAK_TO_DEBUGGER();
704}
705
706
707bool mpc32_program_shaper(
708 struct mpc *mpc,
709 const struct pwl_params *params,
710 uint32_t mpcc_id)
711{
712 enum dc_lut_mode current_mode;
713 enum dc_lut_mode next_mode;
714
715 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
716
717 if (params == NULL) {
718 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);
719 return false;
720 }
721
722 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
723 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, power_on: true);
724
725 current_mode = mpc32_get_shaper_current(mpc, mpcc_id);
726
727 if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
728 next_mode = LUT_RAM_B;
729 else
730 next_mode = LUT_RAM_A;
731
732 mpc32_configure_shaper_lut(mpc, is_ram_a: next_mode == LUT_RAM_A, mpcc_id);
733
734 if (next_mode == LUT_RAM_A)
735 mpc32_program_shaper_luta_settings(mpc, params, mpcc_id);
736 else
737 mpc32_program_shaper_lutb_settings(mpc, params, mpcc_id);
738
739 mpc32_program_shaper_lut(
740 mpc, rgb: params->rgb_resulted, num: params->hw_points_num, mpcc_id);
741
742 REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);
743 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, power_on: false);
744
745 return true;
746}
747
748
749static enum dc_lut_mode get3dlut_config(
750 struct mpc *mpc,
751 bool *is_17x17x17,
752 bool *is_12bits_color_channel,
753 int mpcc_id)
754{
755 uint32_t i_mode, i_enable_10bits, lut_size;
756 enum dc_lut_mode mode;
757 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
758
759 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id],
760 MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode);
761
762 REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
763 MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits);
764
765 switch (i_mode) {
766 case 0:
767 mode = LUT_BYPASS;
768 break;
769 case 1:
770 mode = LUT_RAM_A;
771 break;
772 case 2:
773 mode = LUT_RAM_B;
774 break;
775 default:
776 mode = LUT_BYPASS;
777 break;
778 }
779 if (i_enable_10bits > 0)
780 *is_12bits_color_channel = false;
781 else
782 *is_12bits_color_channel = true;
783
784 REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size);
785
786 if (lut_size == 0)
787 *is_17x17x17 = true;
788 else
789 *is_17x17x17 = false;
790
791 return mode;
792}
793
794
795void mpc32_select_3dlut_ram(
796 struct mpc *mpc,
797 enum dc_lut_mode mode,
798 bool is_color_channel_12bits,
799 uint32_t mpcc_id)
800{
801 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
802
803 REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id],
804 MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1,
805 MPCC_MCM_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1);
806}
807
808
809void mpc32_select_3dlut_ram_mask(
810 struct mpc *mpc,
811 uint32_t ram_selection_mask,
812 uint32_t mpcc_id)
813{
814 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
815
816 REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,
817 ram_selection_mask);
818 REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);
819}
820
821
822void mpc32_set3dlut_ram12(
823 struct mpc *mpc,
824 const struct dc_rgb *lut,
825 uint32_t entries,
826 uint32_t mpcc_id)
827{
828 uint32_t i, red, green, blue, red1, green1, blue1;
829 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
830
831 for (i = 0 ; i < entries; i += 2) {
832 red = lut[i].red<<4;
833 green = lut[i].green<<4;
834 blue = lut[i].blue<<4;
835 red1 = lut[i+1].red<<4;
836 green1 = lut[i+1].green<<4;
837 blue1 = lut[i+1].blue<<4;
838
839 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
840 MPCC_MCM_3DLUT_DATA0, red,
841 MPCC_MCM_3DLUT_DATA1, red1);
842
843 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
844 MPCC_MCM_3DLUT_DATA0, green,
845 MPCC_MCM_3DLUT_DATA1, green1);
846
847 REG_SET_2(MPCC_MCM_3DLUT_DATA[mpcc_id], 0,
848 MPCC_MCM_3DLUT_DATA0, blue,
849 MPCC_MCM_3DLUT_DATA1, blue1);
850 }
851}
852
853
854void mpc32_set3dlut_ram10(
855 struct mpc *mpc,
856 const struct dc_rgb *lut,
857 uint32_t entries,
858 uint32_t mpcc_id)
859{
860 uint32_t i, red, green, blue, value;
861 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
862
863 for (i = 0; i < entries; i++) {
864 red = lut[i].red;
865 green = lut[i].green;
866 blue = lut[i].blue;
867 //should we shift red 22bit and green 12?
868 value = (red<<20) | (green<<10) | blue;
869
870 REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);
871 }
872
873}
874
875
876static void mpc32_set_3dlut_mode(
877 struct mpc *mpc,
878 enum dc_lut_mode mode,
879 bool is_color_channel_12bits,
880 bool is_lut_size17x17x17,
881 uint32_t mpcc_id)
882{
883 uint32_t lut_mode;
884 struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
885
886 // set default 3DLUT to pre-blend
887 // TODO: implement movable CM location
888 REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);
889
890 if (mode == LUT_BYPASS)
891 lut_mode = 0;
892 else if (mode == LUT_RAM_A)
893 lut_mode = 1;
894 else
895 lut_mode = 2;
896
897 REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id],
898 MPCC_MCM_3DLUT_MODE, lut_mode,
899 MPCC_MCM_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1);
900}
901
902
903bool mpc32_program_3dlut(
904 struct mpc *mpc,
905 const struct tetrahedral_params *params,
906 int mpcc_id)
907{
908 enum dc_lut_mode mode;
909 bool is_17x17x17;
910 bool is_12bits_color_channel;
911 const struct dc_rgb *lut0;
912 const struct dc_rgb *lut1;
913 const struct dc_rgb *lut2;
914 const struct dc_rgb *lut3;
915 int lut_size0;
916 int lut_size;
917
918 if (params == NULL) {
919 mpc32_set_3dlut_mode(mpc, mode: LUT_BYPASS, is_color_channel_12bits: false, is_lut_size17x17x17: false, mpcc_id);
920 return false;
921 }
922 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, power_on: true);
923
924 mode = get3dlut_config(mpc, is_17x17x17: &is_17x17x17, is_12bits_color_channel: &is_12bits_color_channel, mpcc_id);
925
926 if (mode == LUT_BYPASS || mode == LUT_RAM_B)
927 mode = LUT_RAM_A;
928 else
929 mode = LUT_RAM_B;
930
931 is_17x17x17 = !params->use_tetrahedral_9;
932 is_12bits_color_channel = params->use_12bits;
933 if (is_17x17x17) {
934 lut0 = params->tetrahedral_17.lut0;
935 lut1 = params->tetrahedral_17.lut1;
936 lut2 = params->tetrahedral_17.lut2;
937 lut3 = params->tetrahedral_17.lut3;
938 lut_size0 = sizeof(params->tetrahedral_17.lut0)/
939 sizeof(params->tetrahedral_17.lut0[0]);
940 lut_size = sizeof(params->tetrahedral_17.lut1)/
941 sizeof(params->tetrahedral_17.lut1[0]);
942 } else {
943 lut0 = params->tetrahedral_9.lut0;
944 lut1 = params->tetrahedral_9.lut1;
945 lut2 = params->tetrahedral_9.lut2;
946 lut3 = params->tetrahedral_9.lut3;
947 lut_size0 = sizeof(params->tetrahedral_9.lut0)/
948 sizeof(params->tetrahedral_9.lut0[0]);
949 lut_size = sizeof(params->tetrahedral_9.lut1)/
950 sizeof(params->tetrahedral_9.lut1[0]);
951 }
952
953 mpc32_select_3dlut_ram(mpc, mode,
954 is_color_channel_12bits: is_12bits_color_channel, mpcc_id);
955 mpc32_select_3dlut_ram_mask(mpc, ram_selection_mask: 0x1, mpcc_id);
956 if (is_12bits_color_channel)
957 mpc32_set3dlut_ram12(mpc, lut: lut0, entries: lut_size0, mpcc_id);
958 else
959 mpc32_set3dlut_ram10(mpc, lut: lut0, entries: lut_size0, mpcc_id);
960
961 mpc32_select_3dlut_ram_mask(mpc, ram_selection_mask: 0x2, mpcc_id);
962 if (is_12bits_color_channel)
963 mpc32_set3dlut_ram12(mpc, lut: lut1, entries: lut_size, mpcc_id);
964 else
965 mpc32_set3dlut_ram10(mpc, lut: lut1, entries: lut_size, mpcc_id);
966
967 mpc32_select_3dlut_ram_mask(mpc, ram_selection_mask: 0x4, mpcc_id);
968 if (is_12bits_color_channel)
969 mpc32_set3dlut_ram12(mpc, lut: lut2, entries: lut_size, mpcc_id);
970 else
971 mpc32_set3dlut_ram10(mpc, lut: lut2, entries: lut_size, mpcc_id);
972
973 mpc32_select_3dlut_ram_mask(mpc, ram_selection_mask: 0x8, mpcc_id);
974 if (is_12bits_color_channel)
975 mpc32_set3dlut_ram12(mpc, lut: lut3, entries: lut_size, mpcc_id);
976 else
977 mpc32_set3dlut_ram10(mpc, lut: lut3, entries: lut_size, mpcc_id);
978
979 mpc32_set_3dlut_mode(mpc, mode, is_color_channel_12bits: is_12bits_color_channel,
980 is_lut_size17x17x17: is_17x17x17, mpcc_id);
981
982 if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc)
983 mpc32_power_on_shaper_3dlut(mpc, mpcc_id, power_on: false);
984
985 return true;
986}
987
988static const struct mpc_funcs dcn32_mpc_funcs = {
989 .read_mpcc_state = mpc1_read_mpcc_state,
990 .insert_plane = mpc1_insert_plane,
991 .remove_mpcc = mpc1_remove_mpcc,
992 .mpc_init = mpc32_mpc_init,
993 .mpc_init_single_inst = mpc1_mpc_init_single_inst,
994 .update_blending = mpc2_update_blending,
995 .cursor_lock = mpc1_cursor_lock,
996 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
997 .wait_for_idle = mpc2_assert_idle_mpcc,
998 .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect,
999 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
1000 .set_denorm = mpc3_set_denorm,
1001 .set_denorm_clamp = mpc3_set_denorm_clamp,
1002 .set_output_csc = mpc3_set_output_csc,
1003 .set_ocsc_default = mpc3_set_ocsc_default,
1004 .set_output_gamma = mpc3_set_output_gamma,
1005 .insert_plane_to_secondary = NULL,
1006 .remove_mpcc_from_secondary = NULL,
1007 .set_dwb_mux = mpc3_set_dwb_mux,
1008 .disable_dwb_mux = mpc3_disable_dwb_mux,
1009 .is_dwb_idle = mpc3_is_dwb_idle,
1010 .set_out_rate_control = mpc3_set_out_rate_control,
1011 .set_gamut_remap = mpc3_set_gamut_remap,
1012 .program_shaper = mpc32_program_shaper,
1013 .program_3dlut = mpc32_program_3dlut,
1014 .program_1dlut = mpc32_program_post1dlut,
1015 .acquire_rmu = NULL,
1016 .release_rmu = NULL,
1017 .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
1018 .get_mpc_out_mux = mpc1_get_mpc_out_mux,
1019 .set_bg_color = mpc1_set_bg_color,
1020};
1021
1022
1023void dcn32_mpc_construct(struct dcn30_mpc *mpc30,
1024 struct dc_context *ctx,
1025 const struct dcn30_mpc_registers *mpc_regs,
1026 const struct dcn30_mpc_shift *mpc_shift,
1027 const struct dcn30_mpc_mask *mpc_mask,
1028 int num_mpcc,
1029 int num_rmu)
1030{
1031 int i;
1032
1033 mpc30->base.ctx = ctx;
1034
1035 mpc30->base.funcs = &dcn32_mpc_funcs;
1036
1037 mpc30->mpc_regs = mpc_regs;
1038 mpc30->mpc_shift = mpc_shift;
1039 mpc30->mpc_mask = mpc_mask;
1040
1041 mpc30->mpcc_in_use_mask = 0;
1042 mpc30->num_mpcc = num_mpcc;
1043 mpc30->num_rmu = num_rmu;
1044
1045 for (i = 0; i < MAX_MPCC; i++)
1046 mpc3_init_mpcc(mpcc: &mpc30->base.mpcc_array[i], mpcc_inst: i);
1047}
1048

source code of linux/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c