1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright 2022 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | |
27 | #include "clk_mgr.h" |
28 | #include "resource.h" |
29 | #include "dcn31/dcn31_hubbub.h" |
30 | #include "dcn314_fpu.h" |
31 | #include "dml/dcn20/dcn20_fpu.h" |
32 | #include "dml/dcn31/dcn31_fpu.h" |
33 | #include "dml/display_mode_vba.h" |
34 | #include "dml/dml_inline_defs.h" |
35 | |
36 | struct _vcs_dpi_ip_params_st dcn3_14_ip = { |
37 | .VBlankNomDefaultUS = 668, |
38 | .gpuvm_enable = 1, |
39 | .gpuvm_max_page_table_levels = 1, |
40 | .hostvm_enable = 1, |
41 | .hostvm_max_page_table_levels = 2, |
42 | .rob_buffer_size_kbytes = 64, |
43 | .det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE, |
44 | .config_return_buffer_size_in_kbytes = 1792, |
45 | .compressed_buffer_segment_size_in_kbytes = 64, |
46 | .meta_fifo_size_in_kentries = 32, |
47 | .zero_size_buffer_entries = 512, |
48 | .compbuf_reserved_space_64b = 256, |
49 | .compbuf_reserved_space_zs = 64, |
50 | .dpp_output_buffer_pixels = 2560, |
51 | .opp_output_buffer_lines = 1, |
52 | .pixel_chunk_size_kbytes = 8, |
53 | .meta_chunk_size_kbytes = 2, |
54 | .min_meta_chunk_size_bytes = 256, |
55 | .writeback_chunk_size_kbytes = 8, |
56 | .ptoi_supported = false, |
57 | .num_dsc = 4, |
58 | .maximum_dsc_bits_per_component = 10, |
59 | .dsc422_native_support = false, |
60 | .is_line_buffer_bpp_fixed = true, |
61 | .line_buffer_fixed_bpp = 48, |
62 | .line_buffer_size_bits = 789504, |
63 | .max_line_buffer_lines = 12, |
64 | .writeback_interface_buffer_size_kbytes = 90, |
65 | .max_num_dpp = 4, |
66 | .max_num_otg = 4, |
67 | .max_num_hdmi_frl_outputs = 1, |
68 | .max_num_wb = 1, |
69 | .max_dchub_pscl_bw_pix_per_clk = 4, |
70 | .max_pscl_lb_bw_pix_per_clk = 2, |
71 | .max_lb_vscl_bw_pix_per_clk = 4, |
72 | .max_vscl_hscl_bw_pix_per_clk = 4, |
73 | .max_hscl_ratio = 6, |
74 | .max_vscl_ratio = 6, |
75 | .max_hscl_taps = 8, |
76 | .max_vscl_taps = 8, |
77 | .dpte_buffer_size_in_pte_reqs_luma = 64, |
78 | .dpte_buffer_size_in_pte_reqs_chroma = 34, |
79 | .dispclk_ramp_margin_percent = 1, |
80 | .max_inter_dcn_tile_repeaters = 8, |
81 | .cursor_buffer_size = 16, |
82 | .cursor_chunk_size = 2, |
83 | .writeback_line_buffer_buffer_size = 0, |
84 | .writeback_min_hscl_ratio = 1, |
85 | .writeback_min_vscl_ratio = 1, |
86 | .writeback_max_hscl_ratio = 1, |
87 | .writeback_max_vscl_ratio = 1, |
88 | .writeback_max_hscl_taps = 1, |
89 | .writeback_max_vscl_taps = 1, |
90 | .dppclk_delay_subtotal = 46, |
91 | .dppclk_delay_scl = 50, |
92 | .dppclk_delay_scl_lb_only = 16, |
93 | .dppclk_delay_cnvc_formatter = 27, |
94 | .dppclk_delay_cnvc_cursor = 6, |
95 | .dispclk_delay_subtotal = 119, |
96 | .dynamic_metadata_vm_enabled = false, |
97 | .odm_combine_4to1_supported = false, |
98 | .dcc_supported = true, |
99 | }; |
100 | |
101 | static struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { |
102 | /*TODO: correct dispclk/dppclk voltage level determination*/ |
103 | .clock_limits = { |
104 | { |
105 | .state = 0, |
106 | .dispclk_mhz = 1200.0, |
107 | .dppclk_mhz = 1200.0, |
108 | .phyclk_mhz = 600.0, |
109 | .phyclk_d18_mhz = 667.0, |
110 | .dscclk_mhz = 186.0, |
111 | .dtbclk_mhz = 600.0, |
112 | }, |
113 | { |
114 | .state = 1, |
115 | .dispclk_mhz = 1200.0, |
116 | .dppclk_mhz = 1200.0, |
117 | .phyclk_mhz = 810.0, |
118 | .phyclk_d18_mhz = 667.0, |
119 | .dscclk_mhz = 209.0, |
120 | .dtbclk_mhz = 600.0, |
121 | }, |
122 | { |
123 | .state = 2, |
124 | .dispclk_mhz = 1200.0, |
125 | .dppclk_mhz = 1200.0, |
126 | .phyclk_mhz = 810.0, |
127 | .phyclk_d18_mhz = 667.0, |
128 | .dscclk_mhz = 209.0, |
129 | .dtbclk_mhz = 600.0, |
130 | }, |
131 | { |
132 | .state = 3, |
133 | .dispclk_mhz = 1200.0, |
134 | .dppclk_mhz = 1200.0, |
135 | .phyclk_mhz = 810.0, |
136 | .phyclk_d18_mhz = 667.0, |
137 | .dscclk_mhz = 371.0, |
138 | .dtbclk_mhz = 600.0, |
139 | }, |
140 | { |
141 | .state = 4, |
142 | .dispclk_mhz = 1200.0, |
143 | .dppclk_mhz = 1200.0, |
144 | .phyclk_mhz = 810.0, |
145 | .phyclk_d18_mhz = 667.0, |
146 | .dscclk_mhz = 417.0, |
147 | .dtbclk_mhz = 600.0, |
148 | }, |
149 | }, |
150 | .num_states = 5, |
151 | .sr_exit_time_us = 16.5, |
152 | .sr_enter_plus_exit_time_us = 18.5, |
153 | .sr_exit_z8_time_us = 268.0, |
154 | .sr_enter_plus_exit_z8_time_us = 393.0, |
155 | .writeback_latency_us = 12.0, |
156 | .dram_channel_width_bytes = 4, |
157 | .round_trip_ping_latency_dcfclk_cycles = 106, |
158 | .urgent_latency_pixel_data_only_us = 4.0, |
159 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, |
160 | .urgent_latency_vm_data_only_us = 4.0, |
161 | .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, |
162 | .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, |
163 | .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, |
164 | .pct_ideal_sdp_bw_after_urgent = 80.0, |
165 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0, |
166 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, |
167 | .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, |
168 | .max_avg_sdp_bw_use_normal_percent = 60.0, |
169 | .max_avg_dram_bw_use_normal_percent = 60.0, |
170 | .fabric_datapath_to_dcn_data_return_bytes = 32, |
171 | .return_bus_width_bytes = 64, |
172 | .downspread_percent = 0.38, |
173 | .dcn_downspread_percent = 0.5, |
174 | .gpuvm_min_page_size_bytes = 4096, |
175 | .hostvm_min_page_size_bytes = 4096, |
176 | .do_urgent_latency_adjustment = false, |
177 | .urgent_latency_adjustment_fabric_clock_component_us = 0, |
178 | .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, |
179 | }; |
180 | |
181 | |
182 | void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) |
183 | { |
184 | struct clk_limit_table *clk_table = &bw_params->clk_table; |
185 | struct _vcs_dpi_voltage_scaling_st *clock_limits = |
186 | dcn3_14_soc.clock_limits; |
187 | unsigned int i, closest_clk_lvl; |
188 | int max_dispclk_mhz = 0, max_dppclk_mhz = 0; |
189 | int j; |
190 | |
191 | dc_assert_fp_enabled(); |
192 | |
193 | // Default clock levels are used for diags, which may lead to overclocking. |
194 | if (dc->config.use_default_clock_table == false) { |
195 | dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; |
196 | dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; |
197 | |
198 | if (bw_params->dram_channel_width_bytes > 0) |
199 | dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; |
200 | |
201 | if (bw_params->num_channels > 0) |
202 | dcn3_14_soc.num_chans = bw_params->num_channels; |
203 | |
204 | ASSERT(dcn3_14_soc.num_chans); |
205 | ASSERT(clk_table->num_entries); |
206 | |
207 | /* Prepass to find max clocks independent of voltage level. */ |
208 | for (i = 0; i < clk_table->num_entries; ++i) { |
209 | if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) |
210 | max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; |
211 | if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) |
212 | max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; |
213 | } |
214 | |
215 | for (i = 0; i < clk_table->num_entries; i++) { |
216 | /* loop backwards*/ |
217 | for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { |
218 | if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { |
219 | closest_clk_lvl = j; |
220 | break; |
221 | } |
222 | } |
223 | if (clk_table->num_entries == 1) { |
224 | /*smu gives one DPM level, let's take the highest one*/ |
225 | closest_clk_lvl = dcn3_14_soc.num_states - 1; |
226 | } |
227 | |
228 | clock_limits[i].state = i; |
229 | |
230 | /* Clocks dependent on voltage level. */ |
231 | clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; |
232 | if (clk_table->num_entries == 1 && |
233 | clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { |
234 | /*SMU fix not released yet*/ |
235 | clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; |
236 | } |
237 | clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; |
238 | clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; |
239 | |
240 | if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio) |
241 | clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio; |
242 | |
243 | /* Clocks independent of voltage level. */ |
244 | clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : |
245 | dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz; |
246 | |
247 | clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : |
248 | dcn3_14_soc.clock_limits[closest_clk_lvl].dppclk_mhz; |
249 | |
250 | clock_limits[i].dram_bw_per_chan_gbps = dcn3_14_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; |
251 | clock_limits[i].dscclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dscclk_mhz; |
252 | clock_limits[i].dtbclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; |
253 | clock_limits[i].phyclk_d18_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; |
254 | clock_limits[i].phyclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].phyclk_mhz; |
255 | } |
256 | for (i = 0; i < clk_table->num_entries; i++) |
257 | dcn3_14_soc.clock_limits[i] = clock_limits[i]; |
258 | if (clk_table->num_entries) { |
259 | dcn3_14_soc.num_states = clk_table->num_entries; |
260 | } |
261 | } |
262 | |
263 | if (max_dispclk_mhz) { |
264 | dcn3_14_soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; |
265 | dc->dml.soc.dispclk_dppclk_vco_speed_mhz = max_dispclk_mhz * 2; |
266 | } |
267 | |
268 | dcn20_patch_bounding_box(dc, bb: &dcn3_14_soc); |
269 | dml_init_instance(lib: &dc->dml, soc_bb: &dcn3_14_soc, ip_params: &dcn3_14_ip, project: DML_PROJECT_DCN314); |
270 | } |
271 | |
272 | static bool is_dual_plane(enum surface_pixel_format format) |
273 | { |
274 | return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; |
275 | } |
276 | |
277 | /* |
278 | * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing |
279 | * |
280 | * @param: num_us: number of microseconds |
281 | * @return: number of vertical lines. If exact number of vertical lines is not found then |
282 | * it will round up to next number of lines to guarantee num_us |
283 | */ |
284 | static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing) |
285 | { |
286 | unsigned int num_lines = 0; |
287 | unsigned int lines_time_in_ns = 1000.0 * |
288 | (((float)timing->h_total * 1000.0) / |
289 | ((float)timing->pix_clk_100hz / 10.0)); |
290 | |
291 | num_lines = dml_ceil(a: 1000.0 * num_us / lines_time_in_ns, granularity: 1.0); |
292 | |
293 | return num_lines; |
294 | } |
295 | |
296 | static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing) |
297 | { |
298 | unsigned int v_active = 0, v_blank = 0, v_back_porch = 0; |
299 | |
300 | v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; |
301 | v_blank = timing->v_total - v_active; |
302 | v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width; |
303 | |
304 | return v_back_porch; |
305 | } |
306 | |
307 | int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context, |
308 | display_e2e_pipe_params_st *pipes, |
309 | bool fast_validate) |
310 | { |
311 | int i, pipe_cnt; |
312 | struct resource_context *res_ctx = &context->res_ctx; |
313 | struct pipe_ctx *pipe; |
314 | bool upscaled = false; |
315 | const unsigned int max_allowed_vblank_nom = 1023; |
316 | |
317 | dc_assert_fp_enabled(); |
318 | |
319 | dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); |
320 | |
321 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { |
322 | struct dc_crtc_timing *timing; |
323 | unsigned int num_lines = 0; |
324 | unsigned int v_back_porch = 0; |
325 | |
326 | if (!res_ctx->pipe_ctx[i].stream) |
327 | continue; |
328 | pipe = &res_ctx->pipe_ctx[i]; |
329 | timing = &pipe->stream->timing; |
330 | |
331 | num_lines = micro_sec_to_vert_lines(num_us: dcn3_14_ip.VBlankNomDefaultUS, timing); |
332 | |
333 | if (pipe->stream->adjust.v_total_min != 0) |
334 | pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; |
335 | else |
336 | pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; |
337 | |
338 | v_back_porch = get_vertical_back_porch(timing); |
339 | |
340 | pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; |
341 | pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); |
342 | // vblank_nom should not smaller than (VSync (timing->v_sync_width + v_back_porch) + 2) |
343 | // + 2 is because |
344 | // 1 -> VStartup_start should be 1 line before VSync |
345 | // 1 -> always reserve 1 line between start of vblank to vstartup signal |
346 | pipes[pipe_cnt].pipe.dest.vblank_nom = |
347 | max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); |
348 | pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom); |
349 | |
350 | if (pipe->plane_state && |
351 | (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || |
352 | pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width)) |
353 | upscaled = true; |
354 | |
355 | /* Apply HostVM policy - either based on hypervisor globally enabled, or rIOMMU active */ |
356 | if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) |
357 | pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active; |
358 | |
359 | /* |
360 | * Immediate flip can be set dynamically after enabling the plane. |
361 | * We need to require support for immediate flip or underflow can be |
362 | * intermittently experienced depending on peak b/w requirements. |
363 | */ |
364 | pipes[pipe_cnt].pipe.src.immediate_flip = true; |
365 | |
366 | pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; |
367 | pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; |
368 | pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; |
369 | pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; |
370 | pipes[pipe_cnt].pipe.src.dcc_rate = 3; |
371 | pipes[pipe_cnt].dout.dsc_input_bpc = 0; |
372 | |
373 | if (pipes[pipe_cnt].dout.dsc_enable) { |
374 | switch (timing->display_color_depth) { |
375 | case COLOR_DEPTH_888: |
376 | pipes[pipe_cnt].dout.dsc_input_bpc = 8; |
377 | break; |
378 | case COLOR_DEPTH_101010: |
379 | pipes[pipe_cnt].dout.dsc_input_bpc = 10; |
380 | break; |
381 | case COLOR_DEPTH_121212: |
382 | pipes[pipe_cnt].dout.dsc_input_bpc = 12; |
383 | break; |
384 | default: |
385 | ASSERT(0); |
386 | break; |
387 | } |
388 | } |
389 | |
390 | pipe_cnt++; |
391 | } |
392 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; |
393 | |
394 | dc->config.enable_4to1MPC = false; |
395 | if (pipe_cnt == 1 && pipe->plane_state |
396 | && pipe->plane_state->rotation == ROTATION_ANGLE_0 && !dc->debug.disable_z9_mpc) { |
397 | if (is_dual_plane(format: pipe->plane_state->format) |
398 | && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { |
399 | dc->config.enable_4to1MPC = true; |
400 | } else if (!is_dual_plane(format: pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) { |
401 | /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ |
402 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; |
403 | pipes[0].pipe.src.unbounded_req_mode = true; |
404 | } |
405 | } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count |
406 | && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) { |
407 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; |
408 | } else if (context->stream_count >= 3 && upscaled) { |
409 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; |
410 | } |
411 | |
412 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
413 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
414 | |
415 | if (!pipe->stream) |
416 | continue; |
417 | |
418 | if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && |
419 | pipe->stream->apply_seamless_boot_optimization) { |
420 | |
421 | if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { |
422 | context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; |
423 | break; |
424 | } |
425 | } |
426 | } |
427 | |
428 | return pipe_cnt; |
429 | } |
430 | |