1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #include "amdgpu.h" |
24 | #include "soc15.h" |
25 | #include "soc15_hw_ip.h" |
26 | #include "vega10_ip_offset.h" |
27 | #include "soc15_common.h" |
28 | #include "vega10_inc.h" |
29 | #include "smu9_baco.h" |
30 | |
31 | int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) |
32 | { |
33 | struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); |
34 | uint32_t reg, data; |
35 | |
36 | *cap = false; |
37 | if (!phm_cap_enabled(caps: hwmgr->platform_descriptor.platformCaps, c: PHM_PlatformCaps_BACO)) |
38 | return 0; |
39 | |
40 | WREG32(0x12074, 0xFFF0003B); |
41 | data = RREG32(0x12075); |
42 | |
43 | if (data == 0x1) { |
44 | reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); |
45 | |
46 | if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) |
47 | *cap = true; |
48 | } |
49 | |
50 | return 0; |
51 | } |
52 | |
53 | int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) |
54 | { |
55 | struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); |
56 | uint32_t reg; |
57 | |
58 | reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); |
59 | |
60 | if (reg & BACO_CNTL__BACO_MODE_MASK) |
61 | /* gfx has already entered BACO state */ |
62 | *state = BACO_STATE_IN; |
63 | else |
64 | *state = BACO_STATE_OUT; |
65 | return 0; |
66 | } |
67 | |