1	/*
2	* Copyright 2019 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*/
22	#ifndef __AMDGPU_SMU_H__
23	#define __AMDGPU_SMU_H__
24
25	#include <linux/acpi_amd_wbrf.h>
26	#include <linux/units.h>
27
28	#include "amdgpu.h"
29	#include "kgd_pp_interface.h"
30	#include "dm_pp_interface.h"
31	#include "dm_pp_smu.h"
32	#include "smu_types.h"
33	#include "linux/firmware.h"
34
35	#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
36	#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
37	#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
38	#define SMU_FW_NAME_LEN 0x24
39
40	#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
41	#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1)
42	#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2)
43
44	// Power Throttlers
45	#define SMU_THROTTLER_PPT0_BIT 0
46	#define SMU_THROTTLER_PPT1_BIT 1
47	#define SMU_THROTTLER_PPT2_BIT 2
48	#define SMU_THROTTLER_PPT3_BIT 3
49	#define SMU_THROTTLER_SPL_BIT 4
50	#define SMU_THROTTLER_FPPT_BIT 5
51	#define SMU_THROTTLER_SPPT_BIT 6
52	#define SMU_THROTTLER_SPPT_APU_BIT 7
53
54	// Current Throttlers
55	#define SMU_THROTTLER_TDC_GFX_BIT 16
56	#define SMU_THROTTLER_TDC_SOC_BIT 17
57	#define SMU_THROTTLER_TDC_MEM_BIT 18
58	#define SMU_THROTTLER_TDC_VDD_BIT 19
59	#define SMU_THROTTLER_TDC_CVIP_BIT 20
60	#define SMU_THROTTLER_EDC_CPU_BIT 21
61	#define SMU_THROTTLER_EDC_GFX_BIT 22
62	#define SMU_THROTTLER_APCC_BIT 23
63
64	// Temperature
65	#define SMU_THROTTLER_TEMP_GPU_BIT 32
66	#define SMU_THROTTLER_TEMP_CORE_BIT 33
67	#define SMU_THROTTLER_TEMP_MEM_BIT 34
68	#define SMU_THROTTLER_TEMP_EDGE_BIT 35
69	#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
70	#define SMU_THROTTLER_TEMP_SOC_BIT 37
71	#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
72	#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
73	#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
74	#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
75	#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
76	#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
77	#define SMU_THROTTLER_VRHOT0_BIT 44
78	#define SMU_THROTTLER_VRHOT1_BIT 45
79	#define SMU_THROTTLER_PROCHOT_CPU_BIT 46
80	#define SMU_THROTTLER_PROCHOT_GFX_BIT 47
81
82	// Other
83	#define SMU_THROTTLER_PPM_BIT 56
84	#define SMU_THROTTLER_FIT_BIT 57
85
86	struct smu_hw_power_state {
87	unsigned int magic;
88	};
89
90	struct smu_power_state;
91
92	enum smu_state_ui_label {
93	SMU_STATE_UI_LABEL_NONE,
94	SMU_STATE_UI_LABEL_BATTERY,
95	SMU_STATE_UI_TABEL_MIDDLE_LOW,
96	SMU_STATE_UI_LABEL_BALLANCED,
97	SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
98	SMU_STATE_UI_LABEL_PERFORMANCE,
99	SMU_STATE_UI_LABEL_BACO,
100	};
101
102	enum smu_state_classification_flag {
103	SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
104	SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
105	SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
106	SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
107	SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
108	SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
109	SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
110	SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
111	SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
112	SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
113	SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
114	SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
115	SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
116	SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
117	SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
118	SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
119	SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
120	SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
121	SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
122	SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
123	SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
124	};
125
126	struct smu_state_classification_block {
127	enum smu_state_ui_label ui_label;
128	enum smu_state_classification_flag flags;
129	int bios_index;
130	bool temporary_state;
131	bool to_be_deleted;
132	};
133
134	struct smu_state_pcie_block {
135	unsigned int lanes;
136	};
137
138	enum smu_refreshrate_source {
139	SMU_REFRESHRATE_SOURCE_EDID,
140	SMU_REFRESHRATE_SOURCE_EXPLICIT
141	};
142
143	struct smu_state_display_block {
144	bool disable_frame_modulation;
145	bool limit_refreshrate;
146	enum smu_refreshrate_source refreshrate_source;
147	int explicit_refreshrate;
148	int edid_refreshrate_index;
149	bool enable_vari_bright;
150	};
151
152	struct smu_state_memory_block {
153	bool dll_off;
154	uint8_t m3arb;
155	uint8_t unused[3];
156	};
157
158	struct smu_state_software_algorithm_block {
159	bool disable_load_balancing;
160	bool enable_sleep_for_timestamps;
161	};
162
163	struct smu_temperature_range {
164	int min;
165	int max;
166	int edge_emergency_max;
167	int hotspot_min;
168	int hotspot_crit_max;
169	int hotspot_emergency_max;
170	int mem_min;
171	int mem_crit_max;
172	int mem_emergency_max;
173	int software_shutdown_temp;
174	int software_shutdown_temp_offset;
175	};
176
177	struct smu_state_validation_block {
178	bool single_display_only;
179	bool disallow_on_dc;
180	uint8_t supported_power_levels;
181	};
182
183	struct smu_uvd_clocks {
184	uint32_t vclk;
185	uint32_t dclk;
186	};
187
188	/**
189	* Structure to hold a SMU Power State.
190	*/
191	struct smu_power_state {
192	uint32_t id;
193	struct list_head ordered_list;
194	struct list_head all_states_list;
195
196	struct smu_state_classification_block classification;
197	struct smu_state_validation_block validation;
198	struct smu_state_pcie_block pcie;
199	struct smu_state_display_block display;
200	struct smu_state_memory_block memory;
201	struct smu_state_software_algorithm_block software;
202	struct smu_uvd_clocks uvd_clocks;
203	struct smu_hw_power_state hardware;
204	};
205
206	enum smu_power_src_type {
207	SMU_POWER_SOURCE_AC,
208	SMU_POWER_SOURCE_DC,
209	SMU_POWER_SOURCE_COUNT,
210	};
211
212	enum smu_ppt_limit_type {
213	SMU_DEFAULT_PPT_LIMIT = 0,
214	SMU_FAST_PPT_LIMIT,
215	};
216
217	enum smu_ppt_limit_level {
218	SMU_PPT_LIMIT_MIN = -1,
219	SMU_PPT_LIMIT_CURRENT,
220	SMU_PPT_LIMIT_DEFAULT,
221	SMU_PPT_LIMIT_MAX,
222	};
223
224	enum smu_memory_pool_size {
225	SMU_MEMORY_POOL_SIZE_ZERO = 0,
226	SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
227	SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
228	SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
229	SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
230	};
231
232	struct smu_user_dpm_profile {
233	uint32_t fan_mode;
234	uint32_t power_limit;
235	uint32_t fan_speed_pwm;
236	uint32_t fan_speed_rpm;
237	uint32_t flags;
238	uint32_t user_od;
239
240	/* user clock state information */
241	uint32_t clk_mask[SMU_CLK_COUNT];
242	uint32_t clk_dependency;
243	};
244
245	#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
246	do { \
247	tables[table_id].size = s; \
248	tables[table_id].align = a; \
249	tables[table_id].domain = d; \
250	} while (0)
251
252	struct smu_table {
253	uint64_t size;
254	uint32_t align;
255	uint8_t domain;
256	uint64_t mc_address;
257	void *cpu_addr;
258	struct amdgpu_bo *bo;
259	uint32_t version;
260	};
261
262	enum smu_perf_level_designation {
263	PERF_LEVEL_ACTIVITY,
264	PERF_LEVEL_POWER_CONTAINMENT,
265	};
266
267	struct smu_performance_level {
268	uint32_t core_clock;
269	uint32_t memory_clock;
270	uint32_t vddc;
271	uint32_t vddci;
272	uint32_t non_local_mem_freq;
273	uint32_t non_local_mem_width;
274	};
275
276	struct smu_clock_info {
277	uint32_t min_mem_clk;
278	uint32_t max_mem_clk;
279	uint32_t min_eng_clk;
280	uint32_t max_eng_clk;
281	uint32_t min_bus_bandwidth;
282	uint32_t max_bus_bandwidth;
283	};
284
285	struct smu_bios_boot_up_values {
286	uint32_t revision;
287	uint32_t gfxclk;
288	uint32_t uclk;
289	uint32_t socclk;
290	uint32_t dcefclk;
291	uint32_t eclk;
292	uint32_t vclk;
293	uint32_t dclk;
294	uint16_t vddc;
295	uint16_t vddci;
296	uint16_t mvddc;
297	uint16_t vdd_gfx;
298	uint8_t cooling_id;
299	uint32_t pp_table_id;
300	uint32_t format_revision;
301	uint32_t content_revision;
302	uint32_t fclk;
303	uint32_t lclk;
304	uint32_t firmware_caps;
305	};
306
307	enum smu_table_id {
308	SMU_TABLE_PPTABLE = 0,
309	SMU_TABLE_WATERMARKS,
310	SMU_TABLE_CUSTOM_DPM,
311	SMU_TABLE_DPMCLOCKS,
312	SMU_TABLE_AVFS,
313	SMU_TABLE_AVFS_PSM_DEBUG,
314	SMU_TABLE_AVFS_FUSE_OVERRIDE,
315	SMU_TABLE_PMSTATUSLOG,
316	SMU_TABLE_SMU_METRICS,
317	SMU_TABLE_DRIVER_SMU_CONFIG,
318	SMU_TABLE_ACTIVITY_MONITOR_COEFF,
319	SMU_TABLE_OVERDRIVE,
320	SMU_TABLE_I2C_COMMANDS,
321	SMU_TABLE_PACE,
322	SMU_TABLE_ECCINFO,
323	SMU_TABLE_COMBO_PPTABLE,
324	SMU_TABLE_WIFIBAND,
325	SMU_TABLE_COUNT,
326	};
327
328	struct smu_table_context {
329	void *power_play_table;
330	uint32_t power_play_table_size;
331	void *hardcode_pptable;
332	unsigned long metrics_time;
333	void *metrics_table;
334	void *clocks_table;
335	void *watermarks_table;
336
337	void *max_sustainable_clocks;
338	struct smu_bios_boot_up_values boot_values;
339	void *driver_pptable;
340	void *combo_pptable;
341	void *ecc_table;
342	void *driver_smu_config_table;
343	struct smu_table tables[SMU_TABLE_COUNT];
344	/*
345	* The driver table is just a staging buffer for
346	* uploading/downloading content from the SMU.
347	*
348	* And the table_id for SMU_MSG_TransferTableSmu2Dram/
349	* SMU_MSG_TransferTableDram2Smu instructs SMU
350	* which content driver is interested.
351	*/
352	struct smu_table driver_table;
353	struct smu_table memory_pool;
354	struct smu_table dummy_read_1_table;
355	uint8_t thermal_controller_type;
356
357	void *overdrive_table;
358	void *boot_overdrive_table;
359	void *user_overdrive_table;
360
361	uint32_t gpu_metrics_table_size;
362	void *gpu_metrics_table;
363	};
364
365	struct smu_context;
366	struct smu_dpm_policy;
367
368	struct smu_dpm_policy_desc {
369	const char *name;
370	char *(*get_desc)(struct smu_dpm_policy *dpm_policy, int level);
371	};
372
373	struct smu_dpm_policy {
374	struct smu_dpm_policy_desc *desc;
375	enum pp_pm_policy policy_type;
376	unsigned long level_mask;
377	int current_level;
378	int (*set_policy)(struct smu_context *ctxt, int level);
379	};
380
381	struct smu_dpm_policy_ctxt {
382	struct smu_dpm_policy policies[PP_PM_POLICY_NUM];
383	unsigned long policy_mask;
384	};
385
386	struct smu_dpm_context {
387	uint32_t dpm_context_size;
388	void *dpm_context;
389	void *golden_dpm_context;
390	enum amd_dpm_forced_level dpm_level;
391	enum amd_dpm_forced_level saved_dpm_level;
392	enum amd_dpm_forced_level requested_dpm_level;
393	struct smu_power_state *dpm_request_power_state;
394	struct smu_power_state *dpm_current_power_state;
395	struct mclock_latency_table *mclk_latency_table;
396	struct smu_dpm_policy_ctxt *dpm_policies;
397	};
398
399	struct smu_power_gate {
400	bool uvd_gated;
401	bool vce_gated;
402	atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
403	atomic_t jpeg_gated;
404	atomic_t vpe_gated;
405	atomic_t umsch_mm_gated;
406	};
407
408	struct smu_power_context {
409	void *power_context;
410	uint32_t power_context_size;
411	struct smu_power_gate power_gate;
412	};
413
414	#define SMU_FEATURE_MAX (64)
415	struct smu_feature {
416	uint32_t feature_num;
417	DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
418	DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
419	};
420
421	struct smu_clocks {
422	uint32_t engine_clock;
423	uint32_t memory_clock;
424	uint32_t bus_bandwidth;
425	uint32_t engine_clock_in_sr;
426	uint32_t dcef_clock;
427	uint32_t dcef_clock_in_sr;
428	};
429
430	#define MAX_REGULAR_DPM_NUM 16
431	struct mclk_latency_entries {
432	uint32_t frequency;
433	uint32_t latency;
434	};
435	struct mclock_latency_table {
436	uint32_t count;
437	struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
438	};
439
440	enum smu_reset_mode {
441	SMU_RESET_MODE_0,
442	SMU_RESET_MODE_1,
443	SMU_RESET_MODE_2,
444	SMU_RESET_MODE_3,
445	SMU_RESET_MODE_4,
446	};
447
448	enum smu_baco_state {
449	SMU_BACO_STATE_ENTER = 0,
450	SMU_BACO_STATE_EXIT,
451	SMU_BACO_STATE_NONE,
452	};
453
454	struct smu_baco_context {
455	uint32_t state;
456	bool platform_support;
457	bool maco_support;
458	};
459
460	struct smu_freq_info {
461	uint32_t min;
462	uint32_t max;
463	uint32_t freq_level;
464	};
465
466	struct pstates_clk_freq {
467	uint32_t min;
468	uint32_t standard;
469	uint32_t peak;
470	struct smu_freq_info custom;
471	struct smu_freq_info curr;
472	};
473
474	struct smu_umd_pstate_table {
475	struct pstates_clk_freq gfxclk_pstate;
476	struct pstates_clk_freq socclk_pstate;
477	struct pstates_clk_freq uclk_pstate;
478	struct pstates_clk_freq vclk_pstate;
479	struct pstates_clk_freq dclk_pstate;
480	struct pstates_clk_freq fclk_pstate;
481	};
482
483	struct cmn2asic_msg_mapping {
484	int valid_mapping;
485	int map_to;
486	uint32_t flags;
487	};
488
489	struct cmn2asic_mapping {
490	int valid_mapping;
491	int map_to;
492	};
493
494	struct stb_context {
495	uint32_t stb_buf_size;
496	bool enabled;
497	spinlock_t lock;
498	};
499
500	enum smu_fw_status {
501	SMU_FW_INIT = 0,
502	SMU_FW_RUNTIME,
503	SMU_FW_HANG,
504	};
505
506	#define WORKLOAD_POLICY_MAX 7
507
508	/*
509	* Configure wbrf event handling pace as there can be only one
510	* event processed every SMU_WBRF_EVENT_HANDLING_PACE ms.
511	*/
512	#define SMU_WBRF_EVENT_HANDLING_PACE 10
513
514	struct smu_context {
515	struct amdgpu_device *adev;
516	struct amdgpu_irq_src irq_source;
517
518	const struct pptable_funcs *ppt_funcs;
519	const struct cmn2asic_msg_mapping *message_map;
520	const struct cmn2asic_mapping *clock_map;
521	const struct cmn2asic_mapping *feature_map;
522	const struct cmn2asic_mapping *table_map;
523	const struct cmn2asic_mapping *pwr_src_map;
524	const struct cmn2asic_mapping *workload_map;
525	struct mutex message_lock;
526	uint64_t pool_size;
527
528	struct smu_table_context smu_table;
529	struct smu_dpm_context smu_dpm;
530	struct smu_power_context smu_power;
531	struct smu_feature smu_feature;
532	struct amd_pp_display_configuration *display_config;
533	struct smu_baco_context smu_baco;
534	struct smu_temperature_range thermal_range;
535	void *od_settings;
536
537	struct smu_umd_pstate_table pstate_table;
538	uint32_t pstate_sclk;
539	uint32_t pstate_mclk;
540
541	bool od_enabled;
542	uint32_t current_power_limit;
543	uint32_t default_power_limit;
544	uint32_t max_power_limit;
545	uint32_t min_power_limit;
546
547	/* soft pptable */
548	uint32_t ppt_offset_bytes;
549	uint32_t ppt_size_bytes;
550	uint8_t *ppt_start_addr;
551
552	bool support_power_containment;
553	bool disable_watermark;
554
555	#define WATERMARKS_EXIST (1 << 0)
556	#define WATERMARKS_LOADED (1 << 1)
557	uint32_t watermarks_bitmap;
558	uint32_t hard_min_uclk_req_from_dal;
559	bool disable_uclk_switch;
560
561	/* asic agnostic workload mask */
562	uint32_t workload_mask;
563	bool pause_workload;
564	/* default/user workload preference */
565	uint32_t power_profile_mode;
566	uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT];
567	/* backend specific custom workload settings */
568	long *custom_profile_params;
569	bool pm_enabled;
570	bool is_apu;
571
572	uint32_t smc_driver_if_version;
573	uint32_t smc_fw_if_version;
574	uint32_t smc_fw_version;
575	uint32_t smc_fw_caps;
576	uint8_t smc_fw_state;
577
578	bool uploading_custom_pp_table;
579	bool dc_controlled_by_gpio;
580
581	struct work_struct throttling_logging_work;
582	atomic64_t throttle_int_counter;
583	struct work_struct interrupt_work;
584
585	unsigned fan_max_rpm;
586	unsigned manual_fan_speed_pwm;
587
588	uint32_t gfx_default_hard_min_freq;
589	uint32_t gfx_default_soft_max_freq;
590	uint32_t gfx_actual_hard_min_freq;
591	uint32_t gfx_actual_soft_max_freq;
592
593	/* APU only */
594	uint32_t cpu_default_soft_min_freq;
595	uint32_t cpu_default_soft_max_freq;
596	uint32_t cpu_actual_soft_min_freq;
597	uint32_t cpu_actual_soft_max_freq;
598	uint32_t cpu_core_id_select;
599	uint16_t cpu_core_num;
600
601	struct smu_user_dpm_profile user_dpm_profile;
602
603	struct stb_context stb_context;
604
605	struct firmware pptable_firmware;
606
607	u32 param_reg;
608	u32 msg_reg;
609	u32 resp_reg;
610
611	u32 debug_param_reg;
612	u32 debug_msg_reg;
613	u32 debug_resp_reg;
614
615	struct delayed_work swctf_delayed_work;
616
617	/* data structures for wbrf feature support */
618	bool wbrf_supported;
619	struct notifier_block wbrf_notifier;
620	struct delayed_work wbrf_delayed_work;
621	};
622
623	struct i2c_adapter;
624
625	/**
626	* struct pptable_funcs - Callbacks used to interact with the SMU.
627	*/
628	struct pptable_funcs {
629	/**
630	* @run_btc: Calibrate voltage/frequency curve to fit the system's
631	* power delivery and voltage margins. Required for adaptive
632	* voltage frequency scaling (AVFS).
633	*/
634	int (*run_btc)(struct smu_context *smu);
635
636	/**
637	* @get_allowed_feature_mask: Get allowed feature mask.
638	* &feature_mask: Array to store feature mask.
639	* &num: Elements in &feature_mask.
640	*/
641	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
642
643	/**
644	* @get_current_power_state: Get the current power state.
645	*
646	* Return: Current power state on success, negative errno on failure.
647	*/
648	enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
649
650	/**
651	* @set_default_dpm_table: Retrieve the default overdrive settings from
652	* the SMU.
653	*/
654	int (*set_default_dpm_table)(struct smu_context *smu);
655
656	int (*set_power_state)(struct smu_context *smu);
657
658	/**
659	* @populate_umd_state_clk: Populate the UMD power state table with
660	* defaults.
661	*/
662	int (*populate_umd_state_clk)(struct smu_context *smu);
663
664	/**
665	* @print_clk_levels: Print DPM clock levels for a clock domain
666	* to buffer. Star current level.
667	*
668	* Used for sysfs interfaces.
669	* Return: Number of characters written to the buffer
670	*/
671	int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
672
673	/**
674	* @emit_clk_levels: Print DPM clock levels for a clock domain
675	* to buffer using sysfs_emit_at. Star current level.
676	*
677	* Used for sysfs interfaces.
678	* &buf: sysfs buffer
679	* &offset: offset within buffer to start printing, which is updated by the
680	* function.
681	*
682	* Return: 0 on Success or Negative to indicate an error occurred.
683	*/
684	int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
685
686	/**
687	* @force_clk_levels: Set a range of allowed DPM levels for a clock
688	* domain.
689	* &clk_type: Clock domain.
690	* &mask: Range of allowed DPM levels.
691	*/
692	int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
693
694	/**
695	* @od_edit_dpm_table: Edit the custom overdrive DPM table.
696	* &type: Type of edit.
697	* &input: Edit parameters.
698	* &size: Size of &input.
699	*/
700	int (*od_edit_dpm_table)(struct smu_context *smu,
701	enum PP_OD_DPM_TABLE_COMMAND type,
702	long *input, uint32_t size);
703
704	/**
705	* @restore_user_od_settings: Restore the user customized
706	* OD settings on S3/S4/Runpm resume.
707	*/
708	int (*restore_user_od_settings)(struct smu_context *smu);
709
710	/**
711	* @get_clock_by_type_with_latency: Get the speed and latency of a clock
712	* domain.
713	*/
714	int (*get_clock_by_type_with_latency)(struct smu_context *smu,
715	enum smu_clk_type clk_type,
716	struct
717	pp_clock_levels_with_latency
718	*clocks);
719	/**
720	* @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
721	* domain.
722	*/
723	int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
724	enum amd_pp_clock_type type,
725	struct
726	pp_clock_levels_with_voltage
727	*clocks);
728
729	/**
730	* @get_power_profile_mode: Print all power profile modes to
731	* buffer. Star current mode.
732	*/
733	int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
734
735	/**
736	* @set_power_profile_mode: Set a power profile mode. Also used to
737	* create/set custom power profile modes.
738	* &input: Power profile mode parameters.
739	* &workload_mask: mask of workloads to enable
740	* &custom_params: custom profile parameters
741	* &custom_params_max_idx: max valid idx into custom_params
742	*/
743	int (*set_power_profile_mode)(struct smu_context *smu, u32 workload_mask,
744	long *custom_params, u32 custom_params_max_idx);
745
746	/**
747	* @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
748	* management.
749	*/
750	int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);
751
752	/**
753	* @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
754	* management.
755	*/
756	int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
757
758	/**
759	* @set_gfx_power_up_by_imu: Enable GFX engine with IMU
760	*/
761	int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
762
763	/**
764	* @read_sensor: Read data from a sensor.
765	* &sensor: Sensor to read data from.
766	* &data: Sensor reading.
767	* &size: Size of &data.
768	*/
769	int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
770	void *data, uint32_t *size);
771
772	/**
773	* @get_apu_thermal_limit: get apu core limit from smu
774	* &limit: current limit temperature in millidegrees Celsius
775	*/
776	int (*get_apu_thermal_limit)(struct smu_context *smu, uint32_t *limit);
777
778	/**
779	* @set_apu_thermal_limit: update all controllers with new limit
780	* &limit: limit temperature to be setted, in millidegrees Celsius
781	*/
782	int (*set_apu_thermal_limit)(struct smu_context *smu, uint32_t limit);
783
784	/**
785	* @pre_display_config_changed: Prepare GPU for a display configuration
786	* change.
787	*
788	* Disable display tracking and pin memory clock speed to maximum. Used
789	* in display component synchronization.
790	*/
791	int (*pre_display_config_changed)(struct smu_context *smu);
792
793	/**
794	* @display_config_changed: Notify the SMU of the current display
795	* configuration.
796	*
797	* Allows SMU to properly track blanking periods for memory clock
798	* adjustment. Used in display component synchronization.
799	*/
800	int (*display_config_changed)(struct smu_context *smu);
801
802	int (*apply_clocks_adjust_rules)(struct smu_context *smu);
803
804	/**
805	* @notify_smc_display_config: Applies display requirements to the
806	* current power state.
807	*
808	* Optimize deep sleep DCEFclk and mclk for the current display
809	* configuration. Used in display component synchronization.
810	*/
811	int (*notify_smc_display_config)(struct smu_context *smu);
812
813	/**
814	* @is_dpm_running: Check if DPM is running.
815	*
816	* Return: True if DPM is running, false otherwise.
817	*/
818	bool (*is_dpm_running)(struct smu_context *smu);
819
820	/**
821	* @get_fan_speed_pwm: Get the current fan speed in PWM.
822	*/
823	int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);
824
825	/**
826	* @get_fan_speed_rpm: Get the current fan speed in rpm.
827	*/
828	int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
829
830	/**
831	* @set_watermarks_table: Configure and upload the watermarks tables to
832	* the SMU.
833	*/
834	int (*set_watermarks_table)(struct smu_context *smu,
835	struct pp_smu_wm_range_sets *clock_ranges);
836
837	/**
838	* @get_thermal_temperature_range: Get safe thermal limits in Celcius.
839	*/
840	int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
841
842	/**
843	* @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
844	* &clocks_in_khz: Array of DPM levels.
845	* &num_states: Elements in &clocks_in_khz.
846	*/
847	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
848
849	/**
850	* @set_default_od_settings: Set the overdrive tables to defaults.
851	*/
852	int (*set_default_od_settings)(struct smu_context *smu);
853
854	/**
855	* @set_performance_level: Set a performance level.
856	*/
857	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
858
859	/**
860	* @display_disable_memory_clock_switch: Enable/disable dynamic memory
861	* clock switching.
862	*
863	* Disabling this feature forces memory clock speed to maximum.
864	* Enabling sets the minimum memory clock capable of driving the
865	* current display configuration.
866	*/
867	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
868
869	/**
870	* @get_power_limit: Get the device's power limits.
871	*/
872	int (*get_power_limit)(struct smu_context *smu,
873	uint32_t *current_power_limit,
874	uint32_t *default_power_limit,
875	uint32_t *max_power_limit,
876	uint32_t *min_power_limit);
877
878	/**
879	* @get_ppt_limit: Get the device's ppt limits.
880	*/
881	int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
882	enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
883
884	/**
885	* @set_df_cstate: Set data fabric cstate.
886	*/
887	int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
888
889	/**
890	* @update_pcie_parameters: Update and upload the system's PCIe
891	* capabilites to the SMU.
892	* &pcie_gen_cap: Maximum allowed PCIe generation.
893	* &pcie_width_cap: Maximum allowed PCIe width.
894	*/
895	int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap);
896
897	/**
898	* @i2c_init: Initialize i2c.
899	*
900	* The i2c bus is used internally by the SMU voltage regulators and
901	* other devices. The i2c's EEPROM also stores bad page tables on boards
902	* with ECC.
903	*/
904	int (*i2c_init)(struct smu_context *smu);
905
906	/**
907	* @i2c_fini: Tear down i2c.
908	*/
909	void (*i2c_fini)(struct smu_context *smu);
910
911	/**
912	* @get_unique_id: Get the GPU's unique id. Used for asset tracking.
913	*/
914	void (*get_unique_id)(struct smu_context *smu);
915
916	/**
917	* @get_dpm_clock_table: Get a copy of the DPM clock table.
918	*
919	* Used by display component in bandwidth and watermark calculations.
920	*/
921	int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
922
923	/**
924	* @init_microcode: Request the SMU's firmware from the kernel.
925	*/
926	int (*init_microcode)(struct smu_context *smu);
927
928	/**
929	* @load_microcode: Load firmware onto the SMU.
930	*/
931	int (*load_microcode)(struct smu_context *smu);
932
933	/**
934	* @fini_microcode: Release the SMU's firmware.
935	*/
936	void (*fini_microcode)(struct smu_context *smu);
937
938	/**
939	* @init_smc_tables: Initialize the SMU tables.
940	*/
941	int (*init_smc_tables)(struct smu_context *smu);
942
943	/**
944	* @fini_smc_tables: Release the SMU tables.
945	*/
946	int (*fini_smc_tables)(struct smu_context *smu);
947
948	/**
949	* @init_power: Initialize the power gate table context.
950	*/
951	int (*init_power)(struct smu_context *smu);
952
953	/**
954	* @fini_power: Release the power gate table context.
955	*/
956	int (*fini_power)(struct smu_context *smu);
957
958	/**
959	* @check_fw_status: Check the SMU's firmware status.
960	*
961	* Return: Zero if check passes, negative errno on failure.
962	*/
963	int (*check_fw_status)(struct smu_context *smu);
964
965	/**
966	* @set_mp1_state: put SMU into a correct state for comming
967	* resume from runpm or gpu reset.
968	*/
969	int (*set_mp1_state)(struct smu_context *smu,
970	enum pp_mp1_state mp1_state);
971
972	/**
973	* @setup_pptable: Initialize the power play table and populate it with
974	* default values.
975	*/
976	int (*setup_pptable)(struct smu_context *smu);
977
978	/**
979	* @get_vbios_bootup_values: Get default boot values from the VBIOS.
980	*/
981	int (*get_vbios_bootup_values)(struct smu_context *smu);
982
983	/**
984	* @check_fw_version: Print driver and SMU interface versions to the
985	* system log.
986	*
987	* Interface mismatch is not a critical failure.
988	*/
989	int (*check_fw_version)(struct smu_context *smu);
990
991	/**
992	* @powergate_sdma: Power up/down system direct memory access.
993	*/
994	int (*powergate_sdma)(struct smu_context *smu, bool gate);
995
996	/**
997	* @set_gfx_cgpg: Enable/disable graphics engine course grain power
998	* gating.
999	*/
1000	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
1001
1002	/**
1003	* @write_pptable: Write the power play table to the SMU.
1004	*/
1005	int (*write_pptable)(struct smu_context *smu);
1006
1007	/**
1008	* @set_driver_table_location: Send the location of the driver table to
1009	* the SMU.
1010	*/
1011	int (*set_driver_table_location)(struct smu_context *smu);
1012
1013	/**
1014	* @set_tool_table_location: Send the location of the tool table to the
1015	* SMU.
1016	*/
1017	int (*set_tool_table_location)(struct smu_context *smu);
1018
1019	/**
1020	* @notify_memory_pool_location: Send the location of the memory pool to
1021	* the SMU.
1022	*/
1023	int (*notify_memory_pool_location)(struct smu_context *smu);
1024
1025	/**
1026	* @system_features_control: Enable/disable all SMU features.
1027	*/
1028	int (*system_features_control)(struct smu_context *smu, bool en);
1029
1030	/**
1031	* @send_smc_msg_with_param: Send a message with a parameter to the SMU.
1032	* &msg: Type of message.
1033	* &param: Message parameter.
1034	* &read_arg: SMU response (optional).
1035	*/
1036	int (*send_smc_msg_with_param)(struct smu_context *smu,
1037	enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
1038
1039	/**
1040	* @send_smc_msg: Send a message to the SMU.
1041	* &msg: Type of message.
1042	* &read_arg: SMU response (optional).
1043	*/
1044	int (*send_smc_msg)(struct smu_context *smu,
1045	enum smu_message_type msg,
1046	uint32_t *read_arg);
1047
1048	/**
1049	* @init_display_count: Notify the SMU of the number of display
1050	* components in current display configuration.
1051	*/
1052	int (*init_display_count)(struct smu_context *smu, uint32_t count);
1053
1054	/**
1055	* @set_allowed_mask: Notify the SMU of the features currently allowed
1056	* by the driver.
1057	*/
1058	int (*set_allowed_mask)(struct smu_context *smu);
1059
1060	/**
1061	* @get_enabled_mask: Get a mask of features that are currently enabled
1062	* on the SMU.
1063	* &feature_mask: Enabled feature mask.
1064	*/
1065	int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
1066
1067	/**
1068	* @feature_is_enabled: Test if a feature is enabled.
1069	*
1070	* Return: One if enabled, zero if disabled.
1071	*/
1072	int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
1073
1074	/**
1075	* @disable_all_features_with_exception: Disable all features with
1076	* exception to those in &mask.
1077	*/
1078	int (*disable_all_features_with_exception)(struct smu_context *smu,
1079	enum smu_feature_mask mask);
1080
1081	/**
1082	* @notify_display_change: General interface call to let SMU know about DC change
1083	*/
1084	int (*notify_display_change)(struct smu_context *smu);
1085
1086	/**
1087	* @set_power_limit: Set power limit in watts.
1088	*/
1089	int (*set_power_limit)(struct smu_context *smu,
1090	enum smu_ppt_limit_type limit_type,
1091	uint32_t limit);
1092
1093	/**
1094	* @init_max_sustainable_clocks: Populate max sustainable clock speed
1095	* table with values from the SMU.
1096	*/
1097	int (*init_max_sustainable_clocks)(struct smu_context *smu);
1098
1099	/**
1100	* @enable_thermal_alert: Enable thermal alert interrupts.
1101	*/
1102	int (*enable_thermal_alert)(struct smu_context *smu);
1103
1104	/**
1105	* @disable_thermal_alert: Disable thermal alert interrupts.
1106	*/
1107	int (*disable_thermal_alert)(struct smu_context *smu);
1108
1109	/**
1110	* @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
1111	* clock speed in MHz.
1112	*/
1113	int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
1114
1115	/**
1116	* @display_clock_voltage_request: Set a hard minimum frequency
1117	* for a clock domain.
1118	*/
1119	int (*display_clock_voltage_request)(struct smu_context *smu, struct
1120	pp_display_clock_request
1121	*clock_req);
1122
1123	/**
1124	* @get_fan_control_mode: Get the current fan control mode.
1125	*/
1126	uint32_t (*get_fan_control_mode)(struct smu_context *smu);
1127
1128	/**
1129	* @set_fan_control_mode: Set the fan control mode.
1130	*/
1131	int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
1132
1133	/**
1134	* @set_fan_speed_pwm: Set a static fan speed in PWM.
1135	*/
1136	int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);
1137
1138	/**
1139	* @set_fan_speed_rpm: Set a static fan speed in rpm.
1140	*/
1141	int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
1142
1143	/**
1144	* @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
1145	* &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
1146	*/
1147	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
1148
1149	/**
1150	* @gfx_off_control: Enable/disable graphics engine poweroff.
1151	*/
1152	int (*gfx_off_control)(struct smu_context *smu, bool enable);
1153
1154
1155	/**
1156	* @get_gfx_off_status: Get graphics engine poweroff status.
1157	*
1158	* Return:
1159	* 0 - GFXOFF(default).
1160	* 1 - Transition out of GFX State.
1161	* 2 - Not in GFXOFF.
1162	* 3 - Transition into GFXOFF.
1163	*/
1164	uint32_t (*get_gfx_off_status)(struct smu_context *smu);
1165
1166	/**
1167	* @gfx_off_entrycount: total GFXOFF entry count at the time of
1168	* query since system power-up
1169	*/
1170	u32 (*get_gfx_off_entrycount)(struct smu_context *smu, uint64_t *entrycount);
1171
1172	/**
1173	* @set_gfx_off_residency: set 1 to start logging, 0 to stop logging
1174	*/
1175	u32 (*set_gfx_off_residency)(struct smu_context *smu, bool start);
1176
1177	/**
1178	* @get_gfx_off_residency: Average GFXOFF residency % during the logging interval
1179	*/
1180	u32 (*get_gfx_off_residency)(struct smu_context *smu, uint32_t *residency);
1181
1182	/**
1183	* @register_irq_handler: Register interupt request handlers.
1184	*/
1185	int (*register_irq_handler)(struct smu_context *smu);
1186
1187	/**
1188	* @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
1189	*/
1190	int (*set_azalia_d3_pme)(struct smu_context *smu);
1191
1192	/**
1193	* @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
1194	* clock speeds table.
1195	*
1196	* Provides a way for the display component (DC) to get the max
1197	* sustainable clocks from the SMU.
1198	*/
1199	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
1200
1201	/**
1202	* @get_bamaco_support: Check if GPU supports BACO/MACO
1203	* BACO: Bus Active, Chip Off
1204	* MACO: Memory Active, Chip Off
1205	*/
1206	int (*get_bamaco_support)(struct smu_context *smu);
1207
1208	/**
1209	* @baco_get_state: Get the current BACO state.
1210	*
1211	* Return: Current BACO state.
1212	*/
1213	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
1214
1215	/**
1216	* @baco_set_state: Enter/exit BACO.
1217	*/
1218	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
1219
1220	/**
1221	* @baco_enter: Enter BACO.
1222	*/
1223	int (*baco_enter)(struct smu_context *smu);
1224
1225	/**
1226	* @baco_exit: Exit Baco.
1227	*/
1228	int (*baco_exit)(struct smu_context *smu);
1229
1230	/**
1231	* @mode1_reset_is_support: Check if GPU supports mode1 reset.
1232	*/
1233	bool (*mode1_reset_is_support)(struct smu_context *smu);
1234
1235	/**
1236	* @link_reset_is_support: Check if GPU supports link reset.
1237	*/
1238	bool (*link_reset_is_support)(struct smu_context *smu);
1239
1240	/**
1241	* @mode1_reset: Perform mode1 reset.
1242	*
1243	* Complete GPU reset.
1244	*/
1245	int (*mode1_reset)(struct smu_context *smu);
1246
1247	/**
1248	* @mode2_reset: Perform mode2 reset.
1249	*
1250	* Mode2 reset generally does not reset as many IPs as mode1 reset. The
1251	* IPs reset varies by asic.
1252	*/
1253	int (*mode2_reset)(struct smu_context *smu);
1254	/* for gfx feature enablement after mode2 reset */
1255	int (*enable_gfx_features)(struct smu_context *smu);
1256
1257	/**
1258	* @link_reset: Perform link reset.
1259	*
1260	* The gfx device driver reset
1261	*/
1262	int (*link_reset)(struct smu_context *smu);
1263
1264	/**
1265	* @get_dpm_ultimate_freq: Get the hard frequency range of a clock
1266	* domain in MHz.
1267	*/
1268	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
1269
1270	/**
1271	* @set_soft_freq_limited_range: Set the soft frequency range of a clock
1272	* domain in MHz.
1273	*/
1274	int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max,
1275	bool automatic);
1276
1277	/**
1278	* @set_power_source: Notify the SMU of the current power source.
1279	*/
1280	int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
1281
1282	/**
1283	* @log_thermal_throttling_event: Print a thermal throttling warning to
1284	* the system's log.
1285	*/
1286	void (*log_thermal_throttling_event)(struct smu_context *smu);
1287
1288	/**
1289	* @get_pp_feature_mask: Print a human readable table of enabled
1290	* features to buffer.
1291	*/
1292	size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
1293
1294	/**
1295	* @set_pp_feature_mask: Request the SMU enable/disable features to
1296	* match those enabled in &new_mask.
1297	*/
1298	int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
1299
1300	/**
1301	* @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
1302	*
1303	* Return: Size of &table
1304	*/
1305	ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
1306
1307	/**
1308	* @get_pm_metrics: Get one snapshot of power management metrics from
1309	* PMFW.
1310	*
1311	* Return: Size of the metrics sample
1312	*/
1313	ssize_t (*get_pm_metrics)(struct smu_context *smu, void *pm_metrics,
1314	size_t size);
1315
1316	/**
1317	* @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
1318	*/
1319	int (*enable_mgpu_fan_boost)(struct smu_context *smu);
1320
1321	/**
1322	* @gfx_ulv_control: Enable/disable ultra low voltage.
1323	*/
1324	int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
1325
1326	/**
1327	* @deep_sleep_control: Enable/disable deep sleep.
1328	*/
1329	int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
1330
1331	/**
1332	* @get_fan_parameters: Get fan parameters.
1333	*
1334	* Get maximum fan speed from the power play table.
1335	*/
1336	int (*get_fan_parameters)(struct smu_context *smu);
1337
1338	/**
1339	* @post_init: Helper function for asic specific workarounds.
1340	*/
1341	int (*post_init)(struct smu_context *smu);
1342
1343	/**
1344	* @interrupt_work: Work task scheduled from SMU interrupt handler.
1345	*/
1346	void (*interrupt_work)(struct smu_context *smu);
1347
1348	/**
1349	* @gpo_control: Enable/disable graphics power optimization if supported.
1350	*/
1351	int (*gpo_control)(struct smu_context *smu, bool enablement);
1352
1353	/**
1354	* @gfx_state_change_set: Send the current graphics state to the SMU.
1355	*/
1356	int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
1357
1358	/**
1359	* @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
1360	* parameters to defaults.
1361	*/
1362	int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
1363
1364	/**
1365	* @smu_handle_passthrough_sbr: Send message to SMU about special handling for SBR.
1366	*/
1367	int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
1368
1369	/**
1370	* @wait_for_event: Wait for events from SMU.
1371	*/
1372	int (*wait_for_event)(struct smu_context *smu,
1373	enum smu_event_type event, uint64_t event_arg);
1374
1375	/**
1376	* @sned_hbm_bad_pages_num: message SMU to update bad page number
1377	* of SMUBUS table.
1378	*/
1379	int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
1380
1381	/**
1382	* @send_rma_reason: message rma reason event to SMU.
1383	*/
1384	int (*send_rma_reason)(struct smu_context *smu);
1385
1386	/**
1387	* @reset_sdma: message SMU to soft reset sdma instance.
1388	*/
1389	int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask);
1390	/**
1391	* @reset_sdma_is_supported: Check if support resets the SDMA engine.
1392	*/
1393	bool (*reset_sdma_is_supported)(struct smu_context *smu);
1394
1395	/**
1396	* @reset_vcn: message SMU to soft reset vcn instance.
1397	*/
1398	int (*dpm_reset_vcn)(struct smu_context *smu, uint32_t inst_mask);
1399
1400	/**
1401	* @get_ecc_table: message SMU to get ECC INFO table.
1402	*/
1403	ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
1404
1405
1406	/**
1407	* @stb_collect_info: Collects Smart Trace Buffers data.
1408	*/
1409	int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);
1410
1411	/**
1412	* @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings.
1413	*/
1414	int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table);
1415
1416	/**
1417	* @set_config_table: Apply the input DriverSmuConfig table settings.
1418	*/
1419	int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table);
1420
1421	/**
1422	* @sned_hbm_bad_channel_flag: message SMU to update bad channel info
1423	* of SMUBUS table.
1424	*/
1425	int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);
1426
1427	/**
1428	* @init_pptable_microcode: Prepare the pptable microcode to upload via PSP
1429	*/
1430	int (*init_pptable_microcode)(struct smu_context *smu);
1431
1432	/**
1433	* @dpm_set_vpe_enable: Enable/disable VPE engine dynamic power
1434	* management.
1435	*/
1436	int (*dpm_set_vpe_enable)(struct smu_context *smu, bool enable);
1437
1438	/**
1439	* @dpm_set_umsch_mm_enable: Enable/disable UMSCH engine dynamic power
1440	* management.
1441	*/
1442	int (*dpm_set_umsch_mm_enable)(struct smu_context *smu, bool enable);
1443
1444	/**
1445	* @set_mall_enable: Init MALL power gating control.
1446	*/
1447	int (*set_mall_enable)(struct smu_context *smu);
1448
1449	/**
1450	* @notify_rlc_state: Notify RLC power state to SMU.
1451	*/
1452	int (*notify_rlc_state)(struct smu_context *smu, bool en);
1453
1454	/**
1455	* @is_asic_wbrf_supported: check whether PMFW supports the wbrf feature
1456	*/
1457	bool (*is_asic_wbrf_supported)(struct smu_context *smu);
1458
1459	/**
1460	* @enable_uclk_shadow: Enable the uclk shadow feature on wbrf supported
1461	*/
1462	int (*enable_uclk_shadow)(struct smu_context *smu, bool enable);
1463
1464	/**
1465	* @set_wbrf_exclusion_ranges: notify SMU the wifi bands occupied
1466	*/
1467	int (*set_wbrf_exclusion_ranges)(struct smu_context *smu,
1468	struct freq_band_range *exclusion_ranges);
1469	/**
1470	* @get_xcp_metrics: Get a copy of the partition metrics table from SMU.
1471	* Return: Size of table
1472	*/
1473	ssize_t (*get_xcp_metrics)(struct smu_context *smu, int xcp_id,
1474	void *table);
1475	};
1476
1477	typedef enum {
1478	METRICS_CURR_GFXCLK,
1479	METRICS_CURR_SOCCLK,
1480	METRICS_CURR_UCLK,
1481	METRICS_CURR_VCLK,
1482	METRICS_CURR_VCLK1,
1483	METRICS_CURR_DCLK,
1484	METRICS_CURR_DCLK1,
1485	METRICS_CURR_FCLK,
1486	METRICS_CURR_DCEFCLK,
1487	METRICS_AVERAGE_CPUCLK,
1488	METRICS_AVERAGE_GFXCLK,
1489	METRICS_AVERAGE_SOCCLK,
1490	METRICS_AVERAGE_FCLK,
1491	METRICS_AVERAGE_UCLK,
1492	METRICS_AVERAGE_VCLK,
1493	METRICS_AVERAGE_DCLK,
1494	METRICS_AVERAGE_VCLK1,
1495	METRICS_AVERAGE_DCLK1,
1496	METRICS_AVERAGE_GFXACTIVITY,
1497	METRICS_AVERAGE_MEMACTIVITY,
1498	METRICS_AVERAGE_VCNACTIVITY,
1499	METRICS_AVERAGE_SOCKETPOWER,
1500	METRICS_TEMPERATURE_EDGE,
1501	METRICS_TEMPERATURE_HOTSPOT,
1502	METRICS_TEMPERATURE_MEM,
1503	METRICS_TEMPERATURE_VRGFX,
1504	METRICS_TEMPERATURE_VRSOC,
1505	METRICS_TEMPERATURE_VRMEM,
1506	METRICS_THROTTLER_STATUS,
1507	METRICS_CURR_FANSPEED,
1508	METRICS_VOLTAGE_VDDSOC,
1509	METRICS_VOLTAGE_VDDGFX,
1510	METRICS_SS_APU_SHARE,
1511	METRICS_SS_DGPU_SHARE,
1512	METRICS_UNIQUE_ID_UPPER32,
1513	METRICS_UNIQUE_ID_LOWER32,
1514	METRICS_PCIE_RATE,
1515	METRICS_PCIE_WIDTH,
1516	METRICS_CURR_FANPWM,
1517	METRICS_CURR_SOCKETPOWER,
1518	METRICS_AVERAGE_VPECLK,
1519	METRICS_AVERAGE_IPUCLK,
1520	METRICS_AVERAGE_MPIPUCLK,
1521	METRICS_THROTTLER_RESIDENCY_PROCHOT,
1522	METRICS_THROTTLER_RESIDENCY_SPL,
1523	METRICS_THROTTLER_RESIDENCY_FPPT,
1524	METRICS_THROTTLER_RESIDENCY_SPPT,
1525	METRICS_THROTTLER_RESIDENCY_THM_CORE,
1526	METRICS_THROTTLER_RESIDENCY_THM_GFX,
1527	METRICS_THROTTLER_RESIDENCY_THM_SOC,
1528	} MetricsMember_t;
1529
1530	enum smu_cmn2asic_mapping_type {
1531	CMN2ASIC_MAPPING_MSG,
1532	CMN2ASIC_MAPPING_CLK,
1533	CMN2ASIC_MAPPING_FEATURE,
1534	CMN2ASIC_MAPPING_TABLE,
1535	CMN2ASIC_MAPPING_PWR,
1536	CMN2ASIC_MAPPING_WORKLOAD,
1537	};
1538
1539	enum smu_baco_seq {
1540	BACO_SEQ_BACO = 0,
1541	BACO_SEQ_MSR,
1542	BACO_SEQ_BAMACO,
1543	BACO_SEQ_ULPS,
1544	BACO_SEQ_COUNT,
1545	};
1546
1547	#define MSG_MAP(msg, index, flags) \
1548	[SMU_MSG_##msg] = {1, (index), (flags)}
1549
1550	#define CLK_MAP(clk, index) \
1551	[SMU_##clk] = {1, (index)}
1552
1553	#define FEA_MAP(fea) \
1554	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
1555
1556	#define FEA_MAP_REVERSE(fea) \
1557	[SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1558
1559	#define FEA_MAP_HALF_REVERSE(fea) \
1560	[SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1561
1562	#define TAB_MAP(tab) \
1563	[SMU_TABLE_##tab] = {1, TABLE_##tab}
1564
1565	#define TAB_MAP_VALID(tab) \
1566	[SMU_TABLE_##tab] = {1, TABLE_##tab}
1567
1568	#define TAB_MAP_INVALID(tab) \
1569	[SMU_TABLE_##tab] = {0, TABLE_##tab}
1570
1571	#define PWR_MAP(tab) \
1572	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
1573
1574	#define WORKLOAD_MAP(profile, workload) \
1575	[profile] = {1, (workload)}
1576
1577	/**
1578	* smu_memcpy_trailing - Copy the end of one structure into the middle of another
1579	*
1580	* @dst: Pointer to destination struct
1581	* @first_dst_member: The member name in @dst where the overwrite begins
1582	* @last_dst_member: The member name in @dst where the overwrite ends after
1583	* @src: Pointer to the source struct
1584	* @first_src_member: The member name in @src where the copy begins
1585	*
1586	*/
1587	#define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \
1588	src, first_src_member) \
1589	({ \
1590	size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \
1591	size_t __src_size = sizeof(*(src)) - __src_offset; \
1592	size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \
1593	size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
1594	__dst_offset; \
1595	BUILD_BUG_ON(__src_size != __dst_size); \
1596	__builtin_memcpy((u8 *)(dst) + __dst_offset, \
1597	(u8 *)(src) + __src_offset, \
1598	__dst_size); \
1599	})
1600
1601	typedef struct {
1602	uint16_t LowFreq;
1603	uint16_t HighFreq;
1604	} WifiOneBand_t;
1605
1606	typedef struct {
1607	uint32_t WifiBandEntryNum;
1608	WifiOneBand_t WifiBandEntry[11];
1609	uint32_t MmHubPadding[8];
1610	} WifiBandEntryTable_t;
1611
1612	#define STR_SOC_PSTATE_POLICY "soc_pstate"
1613	#define STR_XGMI_PLPD_POLICY "xgmi_plpd"
1614
1615	struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu,
1616	enum pp_pm_policy p_type);
1617
1618	#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1619	int smu_get_power_limit(void *handle,
1620	uint32_t *limit,
1621	enum pp_power_limit_level pp_limit_level,
1622	enum pp_power_type pp_power_type);
1623
1624	bool smu_mode1_reset_is_support(struct smu_context *smu);
1625	bool smu_link_reset_is_support(struct smu_context *smu);
1626	int smu_mode1_reset(struct smu_context *smu);
1627	int smu_link_reset(struct smu_context *smu);
1628
1629	extern const struct amd_ip_funcs smu_ip_funcs;
1630
1631	bool is_support_sw_smu(struct amdgpu_device *adev);
1632	bool is_support_cclk_dpm(struct amdgpu_device *adev);
1633	int smu_write_watermarks_table(struct smu_context *smu);
1634
1635	int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1636	uint32_t *min, uint32_t *max);
1637
1638	int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1639	uint32_t min, uint32_t max);
1640
1641	int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
1642
1643	int smu_set_ac_dc(struct smu_context *smu);
1644
1645	int smu_set_xgmi_plpd_mode(struct smu_context *smu,
1646	enum pp_xgmi_plpd_mode mode);
1647
1648	int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value);
1649
1650	int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value);
1651
1652	int smu_set_residency_gfxoff(struct smu_context *smu, bool value);
1653
1654	int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
1655
1656	int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
1657
1658	int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1659	uint64_t event_arg);
1660	int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc);
1661	int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);
1662	void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
1663	int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
1664	int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
1665	int smu_send_rma_reason(struct smu_context *smu);
1666	int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask);
1667	bool smu_reset_sdma_is_supported(struct smu_context *smu);
1668	int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask);
1669	int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type,
1670	int level);
1671	ssize_t smu_get_pm_policy_info(struct smu_context *smu,
1672	enum pp_pm_policy p_type, char *sysbuf);
1673
1674	#endif
1675	#endif
1676