1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright: 2017 Cadence Design Systems, Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <drm/drm_atomic_helper.h>
9#include <drm/drm_drv.h>
10#include <drm/drm_probe_helper.h>
11#include <video/mipi_display.h>
12
13#include <linux/clk.h>
14#include <linux/interrupt.h>
15#include <linux/iopoll.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_graph.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22
23#include <linux/phy/phy-mipi-dphy.h>
24
25#include "cdns-dsi-core.h"
26#ifdef CONFIG_DRM_CDNS_DSI_J721E
27#include "cdns-dsi-j721e.h"
28#endif
29
30#define IP_CONF 0x0
31#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
32#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
33#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
34#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
35#define SDI_IFACE_32 BIT(12)
36#define INTERNAL_DATAPATH_32 (0 << 10)
37#define INTERNAL_DATAPATH_16 (1 << 10)
38#define INTERNAL_DATAPATH_8 (3 << 10)
39#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
40#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
41#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
42#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
43
44#define MCTL_MAIN_DATA_CTL 0x4
45#define TE_MIPI_POLLING_EN BIT(25)
46#define TE_HW_POLLING_EN BIT(24)
47#define DISP_EOT_GEN BIT(18)
48#define HOST_EOT_GEN BIT(17)
49#define DISP_GEN_CHECKSUM BIT(16)
50#define DISP_GEN_ECC BIT(15)
51#define BTA_EN BIT(14)
52#define READ_EN BIT(13)
53#define REG_TE_EN BIT(12)
54#define IF_TE_EN(x) BIT(8 + (x))
55#define TVG_SEL BIT(6)
56#define VID_EN BIT(5)
57#define IF_VID_SELECT(x) ((x) << 2)
58#define IF_VID_SELECT_MASK GENMASK(3, 2)
59#define IF_VID_MODE BIT(1)
60#define LINK_EN BIT(0)
61
62#define MCTL_MAIN_PHY_CTL 0x8
63#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
64#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
65#define HS_INVERT_CLK BIT(17)
66#define SWAP_PINS_CLK BIT(16)
67#define HS_SKEWCAL_EN BIT(15)
68#define WAIT_BURST_TIME(x) ((x) << 10)
69#define DATA_ULPM_EN(x) BIT(6 + (x))
70#define CLK_ULPM_EN BIT(5)
71#define CLK_CONTINUOUS BIT(4)
72#define DATA_LANE_EN(x) BIT((x) - 1)
73
74#define MCTL_MAIN_EN 0xc
75#define DATA_FORCE_STOP BIT(17)
76#define CLK_FORCE_STOP BIT(16)
77#define IF_EN(x) BIT(13 + (x))
78#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
79#define CLK_LANE_ULPM_REQ BIT(8)
80#define DATA_LANE_START(x) BIT(4 + (x))
81#define CLK_LANE_EN BIT(3)
82#define PLL_START BIT(0)
83
84#define MCTL_DPHY_CFG0 0x10
85#define DPHY_C_RSTB BIT(20)
86#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
87#define DPHY_PLL_PDN BIT(10)
88#define DPHY_CMN_PDN BIT(9)
89#define DPHY_C_PDN BIT(8)
90#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
91#define DPHY_ALL_D_PDN GENMASK(7, 4)
92#define DPHY_PLL_PSO BIT(1)
93#define DPHY_CMN_PSO BIT(0)
94
95#define MCTL_DPHY_TIMEOUT1 0x14
96#define HSTX_TIMEOUT(x) ((x) << 4)
97#define HSTX_TIMEOUT_MAX GENMASK(17, 0)
98#define CLK_DIV(x) (x)
99#define CLK_DIV_MAX GENMASK(3, 0)
100
101#define MCTL_DPHY_TIMEOUT2 0x18
102#define LPRX_TIMEOUT(x) (x)
103
104#define MCTL_ULPOUT_TIME 0x1c
105#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
106#define CLK_LANE_ULPOUT_TIME(x) (x)
107
108#define MCTL_3DVIDEO_CTL 0x20
109#define VID_VSYNC_3D_EN BIT(7)
110#define VID_VSYNC_3D_LR BIT(5)
111#define VID_VSYNC_3D_SECOND_EN BIT(4)
112#define VID_VSYNC_3DFORMAT_LINE (0 << 2)
113#define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
114#define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
115#define VID_VSYNC_3DMODE_OFF 0
116#define VID_VSYNC_3DMODE_PORTRAIT 1
117#define VID_VSYNC_3DMODE_LANDSCAPE 2
118
119#define MCTL_MAIN_STS 0x24
120#define MCTL_MAIN_STS_CTL 0x130
121#define MCTL_MAIN_STS_CLR 0x150
122#define MCTL_MAIN_STS_FLAG 0x170
123#define HS_SKEWCAL_DONE BIT(11)
124#define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
125#define LPRX_TIMEOUT_ERR BIT(7)
126#define HSTX_TIMEOUT_ERR BIT(6)
127#define DATA_LANE_RDY(l) BIT(2 + (l))
128#define CLK_LANE_RDY BIT(1)
129#define PLL_LOCKED BIT(0)
130
131#define MCTL_DPHY_ERR 0x28
132#define MCTL_DPHY_ERR_CTL1 0x148
133#define MCTL_DPHY_ERR_CLR 0x168
134#define MCTL_DPHY_ERR_FLAG 0x188
135#define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
136#define ERR_CONTROL(l) BIT(14 + (l))
137#define ERR_SYNESC(l) BIT(10 + (l))
138#define ERR_ESC(l) BIT(6 + (l))
139
140#define MCTL_DPHY_ERR_CTL2 0x14c
141#define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
142#define ERR_CONTROL_EDGE(l) BIT(8 + (l))
143#define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
144#define ERR_ESC_EDGE(l) BIT(0 + (l))
145
146#define MCTL_LANE_STS 0x2c
147#define PPI_C_TX_READY_HS BIT(18)
148#define DPHY_PLL_LOCK BIT(17)
149#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
150#define LANE_STATE_START 0
151#define LANE_STATE_IDLE 1
152#define LANE_STATE_WRITE 2
153#define LANE_STATE_ULPM 3
154#define LANE_STATE_READ 4
155#define DATA_LANE_STATE(l, val) \
156 (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
157#define CLK_LANE_STATE_HS 2
158#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
159
160#define DSC_MODE_CTL 0x30
161#define DSC_MODE_EN BIT(0)
162
163#define DSC_CMD_SEND 0x34
164#define DSC_SEND_PPS BIT(0)
165#define DSC_EXECUTE_QUEUE BIT(1)
166
167#define DSC_PPS_WRDAT 0x38
168
169#define DSC_MODE_STS 0x3c
170#define DSC_PPS_DONE BIT(1)
171#define DSC_EXEC_DONE BIT(2)
172
173#define CMD_MODE_CTL 0x70
174#define IF_LP_EN(x) BIT(9 + (x))
175#define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
176
177#define CMD_MODE_CTL2 0x74
178#define TE_TIMEOUT(x) ((x) << 11)
179#define FILL_VALUE(x) ((x) << 3)
180#define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
181#define ARB_ROUND_ROBIN_MODE BIT(0)
182
183#define CMD_MODE_STS 0x78
184#define CMD_MODE_STS_CTL 0x134
185#define CMD_MODE_STS_CLR 0x154
186#define CMD_MODE_STS_FLAG 0x174
187#define ERR_IF_UNDERRUN(x) BIT(4 + (x))
188#define ERR_UNWANTED_READ BIT(3)
189#define ERR_TE_MISS BIT(2)
190#define ERR_NO_TE BIT(1)
191#define CSM_RUNNING BIT(0)
192
193#define DIRECT_CMD_SEND 0x80
194
195#define DIRECT_CMD_MAIN_SETTINGS 0x84
196#define TRIGGER_VAL(x) ((x) << 25)
197#define CMD_LP_EN BIT(24)
198#define CMD_SIZE(x) ((x) << 16)
199#define CMD_VCHAN_ID(x) ((x) << 14)
200#define CMD_DATATYPE(x) ((x) << 8)
201#define CMD_LONG BIT(3)
202#define WRITE_CMD 0
203#define READ_CMD 1
204#define TE_REQ 4
205#define TRIGGER_REQ 5
206#define BTA_REQ 6
207
208#define DIRECT_CMD_STS 0x88
209#define DIRECT_CMD_STS_CTL 0x138
210#define DIRECT_CMD_STS_CLR 0x158
211#define DIRECT_CMD_STS_FLAG 0x178
212#define RCVD_ACK_VAL(val) ((val) >> 16)
213#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
214#define READ_COMPLETED_WITH_ERR BIT(10)
215#define BTA_FINISHED BIT(9)
216#define BTA_COMPLETED BIT(8)
217#define TE_RCVD BIT(7)
218#define TRIGGER_RCVD BIT(6)
219#define ACK_WITH_ERR_RCVD BIT(5)
220#define ACK_RCVD BIT(4)
221#define READ_COMPLETED BIT(3)
222#define TRIGGER_COMPLETED BIT(2)
223#define WRITE_COMPLETED BIT(1)
224#define SENDING_CMD BIT(0)
225
226#define DIRECT_CMD_STOP_READ 0x8c
227
228#define DIRECT_CMD_WRDATA 0x90
229
230#define DIRECT_CMD_FIFO_RST 0x94
231
232#define DIRECT_CMD_RDDATA 0xa0
233
234#define DIRECT_CMD_RD_PROPS 0xa4
235#define RD_DCS BIT(18)
236#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
237#define RD_SIZE(val) ((val) & GENMASK(15, 0))
238
239#define DIRECT_CMD_RD_STS 0xa8
240#define DIRECT_CMD_RD_STS_CTL 0x13c
241#define DIRECT_CMD_RD_STS_CLR 0x15c
242#define DIRECT_CMD_RD_STS_FLAG 0x17c
243#define ERR_EOT_WITH_ERR BIT(8)
244#define ERR_MISSING_EOT BIT(7)
245#define ERR_WRONG_LENGTH BIT(6)
246#define ERR_OVERSIZE BIT(5)
247#define ERR_RECEIVE BIT(4)
248#define ERR_UNDECODABLE BIT(3)
249#define ERR_CHECKSUM BIT(2)
250#define ERR_UNCORRECTABLE BIT(1)
251#define ERR_FIXED BIT(0)
252
253#define VID_MAIN_CTL 0xb0
254#define VID_IGNORE_MISS_VSYNC BIT(31)
255#define VID_FIELD_SW BIT(28)
256#define VID_INTERLACED_EN BIT(27)
257#define RECOVERY_MODE(x) ((x) << 25)
258#define RECOVERY_MODE_NEXT_HSYNC 0
259#define RECOVERY_MODE_NEXT_STOP_POINT 2
260#define RECOVERY_MODE_NEXT_VSYNC 3
261#define REG_BLKEOL_MODE(x) ((x) << 23)
262#define REG_BLKLINE_MODE(x) ((x) << 21)
263#define REG_BLK_MODE_NULL_PKT 0
264#define REG_BLK_MODE_BLANKING_PKT 1
265#define REG_BLK_MODE_LP 2
266#define SYNC_PULSE_HORIZONTAL BIT(20)
267#define SYNC_PULSE_ACTIVE BIT(19)
268#define BURST_MODE BIT(18)
269#define VID_PIXEL_MODE_MASK GENMASK(17, 14)
270#define VID_PIXEL_MODE_RGB565 (0 << 14)
271#define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
272#define VID_PIXEL_MODE_RGB666 (2 << 14)
273#define VID_PIXEL_MODE_RGB888 (3 << 14)
274#define VID_PIXEL_MODE_RGB101010 (4 << 14)
275#define VID_PIXEL_MODE_RGB121212 (5 << 14)
276#define VID_PIXEL_MODE_YUV420 (8 << 14)
277#define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
278#define VID_PIXEL_MODE_YUV422 (10 << 14)
279#define VID_PIXEL_MODE_YUV422_24B (11 << 14)
280#define VID_PIXEL_MODE_DSC_COMP (12 << 14)
281#define VID_DATATYPE(x) ((x) << 8)
282#define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
283#define STOP_MODE(x) ((x) << 2)
284#define START_MODE(x) (x)
285
286#define VID_VSIZE1 0xb4
287#define VFP_LEN(x) ((x) << 12)
288#define VBP_LEN(x) ((x) << 6)
289#define VSA_LEN(x) (x)
290
291#define VID_VSIZE2 0xb8
292#define VACT_LEN(x) (x)
293
294#define VID_HSIZE1 0xc0
295#define HBP_LEN(x) ((x) << 16)
296#define HSA_LEN(x) (x)
297
298#define VID_HSIZE2 0xc4
299#define HFP_LEN(x) ((x) << 16)
300#define HACT_LEN(x) (x)
301
302#define VID_BLKSIZE1 0xcc
303#define BLK_EOL_PKT_LEN(x) ((x) << 15)
304#define BLK_LINE_EVENT_PKT_LEN(x) (x)
305
306#define VID_BLKSIZE2 0xd0
307#define BLK_LINE_PULSE_PKT_LEN(x) (x)
308
309#define VID_PKT_TIME 0xd8
310#define BLK_EOL_DURATION(x) (x)
311
312#define VID_DPHY_TIME 0xdc
313#define REG_WAKEUP_TIME(x) ((x) << 17)
314#define REG_LINE_DURATION(x) (x)
315
316#define VID_ERR_COLOR1 0xe0
317#define COL_GREEN(x) ((x) << 12)
318#define COL_RED(x) (x)
319
320#define VID_ERR_COLOR2 0xe4
321#define PAD_VAL(x) ((x) << 12)
322#define COL_BLUE(x) (x)
323
324#define VID_VPOS 0xe8
325#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
326#define LINE_POS(val) ((val) & GENMASK(1, 0))
327
328#define VID_HPOS 0xec
329#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
330#define HORIZ_POS(val) ((val) & GENMASK(2, 0))
331
332#define VID_MODE_STS 0xf0
333#define VID_MODE_STS_CTL 0x140
334#define VID_MODE_STS_CLR 0x160
335#define VID_MODE_STS_FLAG 0x180
336#define VSG_RECOVERY BIT(10)
337#define ERR_VRS_WRONG_LEN BIT(9)
338#define ERR_LONG_READ BIT(8)
339#define ERR_LINE_WRITE BIT(7)
340#define ERR_BURST_WRITE BIT(6)
341#define ERR_SMALL_HEIGHT BIT(5)
342#define ERR_SMALL_LEN BIT(4)
343#define ERR_MISSING_VSYNC BIT(3)
344#define ERR_MISSING_HSYNC BIT(2)
345#define ERR_MISSING_DATA BIT(1)
346#define VSG_RUNNING BIT(0)
347
348#define VID_VCA_SETTING1 0xf4
349#define BURST_LP BIT(16)
350#define MAX_BURST_LIMIT(x) (x)
351
352#define VID_VCA_SETTING2 0xf8
353#define MAX_LINE_LIMIT(x) ((x) << 16)
354#define EXACT_BURST_LIMIT(x) (x)
355
356#define TVG_CTL 0xfc
357#define TVG_STRIPE_SIZE(x) ((x) << 5)
358#define TVG_MODE_MASK GENMASK(4, 3)
359#define TVG_MODE_SINGLE_COLOR (0 << 3)
360#define TVG_MODE_VSTRIPES (2 << 3)
361#define TVG_MODE_HSTRIPES (3 << 3)
362#define TVG_STOPMODE_MASK GENMASK(2, 1)
363#define TVG_STOPMODE_EOF (0 << 1)
364#define TVG_STOPMODE_EOL (1 << 1)
365#define TVG_STOPMODE_NOW (2 << 1)
366#define TVG_RUN BIT(0)
367
368#define TVG_IMG_SIZE 0x100
369#define TVG_NBLINES(x) ((x) << 16)
370#define TVG_LINE_SIZE(x) (x)
371
372#define TVG_COLOR1 0x104
373#define TVG_COL1_GREEN(x) ((x) << 12)
374#define TVG_COL1_RED(x) (x)
375
376#define TVG_COLOR1_BIS 0x108
377#define TVG_COL1_BLUE(x) (x)
378
379#define TVG_COLOR2 0x10c
380#define TVG_COL2_GREEN(x) ((x) << 12)
381#define TVG_COL2_RED(x) (x)
382
383#define TVG_COLOR2_BIS 0x110
384#define TVG_COL2_BLUE(x) (x)
385
386#define TVG_STS 0x114
387#define TVG_STS_CTL 0x144
388#define TVG_STS_CLR 0x164
389#define TVG_STS_FLAG 0x184
390#define TVG_STS_RUNNING BIT(0)
391
392#define STS_CTL_EDGE(e) ((e) << 16)
393
394#define DPHY_LANES_MAP 0x198
395#define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
396
397#define DPI_IRQ_EN 0x1a0
398#define DPI_IRQ_CLR 0x1a4
399#define DPI_IRQ_STS 0x1a8
400#define PIXEL_BUF_OVERFLOW BIT(0)
401
402#define DPI_CFG 0x1ac
403#define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
404#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
405
406#define TEST_GENERIC 0x1f0
407#define TEST_STATUS(x) ((x) >> 16)
408#define TEST_CTRL(x) (x)
409
410#define ID_REG 0x1fc
411#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
412#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
413#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
414#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
415#define REV_MINOR(x) ((x) & GENMASK(3, 0))
416
417#define DSI_OUTPUT_PORT 0
418#define DSI_INPUT_PORT(inputid) (1 + (inputid))
419
420#define DSI_HBP_FRAME_OVERHEAD 12
421#define DSI_HSA_FRAME_OVERHEAD 14
422#define DSI_HFP_FRAME_OVERHEAD 6
423#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
424#define DSI_BLANKING_FRAME_OVERHEAD 6
425#define DSI_NULL_FRAME_OVERHEAD 6
426#define DSI_EOT_PKT_SIZE 4
427
428struct cdns_dsi_bridge_state {
429 struct drm_bridge_state base;
430 struct cdns_dsi_cfg dsi_cfg;
431};
432
433static inline struct cdns_dsi_bridge_state *
434to_cdns_dsi_bridge_state(struct drm_bridge_state *bridge_state)
435{
436 return container_of(bridge_state, struct cdns_dsi_bridge_state, base);
437}
438
439static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
440{
441 return container_of(input, struct cdns_dsi, input);
442}
443
444static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host)
445{
446 return container_of(host, struct cdns_dsi, base);
447}
448
449static inline struct cdns_dsi_input *
450bridge_to_cdns_dsi_input(struct drm_bridge *bridge)
451{
452 return container_of(bridge, struct cdns_dsi_input, bridge);
453}
454
455static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,
456 bool mode_valid_check)
457{
458 if (mode_valid_check)
459 return mode->hsync_start - mode->hdisplay;
460
461 return mode->crtc_hsync_start - mode->crtc_hdisplay;
462}
463
464static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,
465 unsigned int dpi_bpp,
466 unsigned int dsi_pkt_overhead)
467{
468 unsigned int dsi_timing = DIV_ROUND_UP(dpi_timing * dpi_bpp, 8);
469
470 if (dsi_timing < dsi_pkt_overhead)
471 dsi_timing = 0;
472 else
473 dsi_timing -= dsi_pkt_overhead;
474
475 return dsi_timing;
476}
477
478static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
479 const struct drm_display_mode *mode,
480 struct cdns_dsi_cfg *dsi_cfg,
481 bool mode_valid_check)
482{
483 struct cdns_dsi_output *output = &dsi->output;
484 unsigned int tmp;
485 bool sync_pulse = false;
486 int bpp;
487
488 memset(dsi_cfg, 0, sizeof(*dsi_cfg));
489
490 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
491 sync_pulse = true;
492
493 bpp = mipi_dsi_pixel_format_to_bpp(fmt: output->dev->format);
494
495 if (mode_valid_check)
496 tmp = mode->htotal -
497 (sync_pulse ? mode->hsync_end : mode->hsync_start);
498 else
499 tmp = mode->crtc_htotal -
500 (sync_pulse ?
501 mode->crtc_hsync_end : mode->crtc_hsync_start);
502
503 dsi_cfg->hbp = dpi_to_dsi_timing(dpi_timing: tmp, dpi_bpp: bpp, DSI_HBP_FRAME_OVERHEAD);
504
505 if (sync_pulse) {
506 if (mode_valid_check)
507 tmp = mode->hsync_end - mode->hsync_start;
508 else
509 tmp = mode->crtc_hsync_end - mode->crtc_hsync_start;
510
511 dsi_cfg->hsa = dpi_to_dsi_timing(dpi_timing: tmp, dpi_bpp: bpp,
512 DSI_HSA_FRAME_OVERHEAD);
513 }
514
515 dsi_cfg->hact = dpi_to_dsi_timing(dpi_timing: mode_valid_check ?
516 mode->hdisplay : mode->crtc_hdisplay,
517 dpi_bpp: bpp, dsi_pkt_overhead: 0);
518 dsi_cfg->hfp = dpi_to_dsi_timing(dpi_timing: mode_to_dpi_hfp(mode, mode_valid_check),
519 dpi_bpp: bpp, DSI_HFP_FRAME_OVERHEAD);
520
521 return 0;
522}
523
524static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,
525 struct cdns_dsi_cfg *dsi_cfg,
526 struct phy_configure_opts_mipi_dphy *phy_cfg,
527 const struct drm_display_mode *mode,
528 bool mode_valid_check)
529{
530 struct cdns_dsi_output *output = &dsi->output;
531 unsigned long long dlane_bps;
532 unsigned long adj_dsi_htotal;
533 unsigned long dsi_htotal;
534 unsigned long dpi_htotal;
535 unsigned long dpi_hz;
536 unsigned int dsi_hfp_ext;
537 unsigned int lanes = output->dev->lanes;
538
539 dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
540 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
541 dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
542
543 dsi_htotal += dsi_cfg->hact;
544 dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD;
545
546 /*
547 * Make sure DSI htotal is aligned on a lane boundary when calculating
548 * the expected data rate. This is done by extending HFP in case of
549 * misalignment.
550 */
551 adj_dsi_htotal = dsi_htotal;
552 if (dsi_htotal % lanes)
553 adj_dsi_htotal += lanes - (dsi_htotal % lanes);
554
555 dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000;
556 dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;
557
558 /* data rate in bytes/sec is not an integer, refuse the mode. */
559 dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal;
560 if (do_div(dlane_bps, lanes * dpi_htotal))
561 return -EINVAL;
562
563 /* data rate was in bytes/sec, convert to bits/sec. */
564 phy_cfg->hs_clk_rate = dlane_bps * 8;
565
566 dsi_hfp_ext = adj_dsi_htotal - dsi_htotal;
567 dsi_cfg->hfp += dsi_hfp_ext;
568 dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext;
569
570 return 0;
571}
572
573static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
574 const struct drm_display_mode *mode,
575 struct cdns_dsi_cfg *dsi_cfg,
576 bool mode_valid_check)
577{
578 struct cdns_dsi_output *output = &dsi->output;
579 struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
580 unsigned long dsi_hss_hsa_hse_hbp;
581 unsigned int nlanes = output->dev->lanes;
582 int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);
583 int ret;
584
585 ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);
586 if (ret)
587 return ret;
588
589 ret = phy_mipi_dphy_get_default_config(pixel_clock: mode_clock * 1000,
590 bpp: mipi_dsi_pixel_format_to_bpp(fmt: output->dev->format),
591 lanes: nlanes, cfg: phy_cfg);
592 if (ret)
593 return ret;
594
595 ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check);
596 if (ret)
597 return ret;
598
599 ret = phy_validate(phy: dsi->dphy, mode: PHY_MODE_MIPI_DPHY, submode: 0, opts: &output->phy_opts);
600 if (ret)
601 return ret;
602
603 dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
604 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
605 dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
606
607 /*
608 * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO
609 * is empty before we start a receiving a new line on the DPI
610 * interface.
611 */
612 if ((u64)phy_cfg->hs_clk_rate *
613 mode_to_dpi_hfp(mode, mode_valid_check) * nlanes <
614 (u64)dsi_hss_hsa_hse_hbp *
615 (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000)
616 return -EINVAL;
617
618 return 0;
619}
620
621static int cdns_dsi_bridge_attach(struct drm_bridge *bridge,
622 struct drm_encoder *encoder,
623 enum drm_bridge_attach_flags flags)
624{
625 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
626 struct cdns_dsi *dsi = input_to_dsi(input);
627 struct cdns_dsi_output *output = &dsi->output;
628
629 if (!drm_core_check_feature(dev: bridge->dev, feature: DRIVER_ATOMIC)) {
630 dev_err(dsi->base.dev,
631 "cdns-dsi driver is only compatible with DRM devices supporting atomic updates");
632 return -ENOTSUPP;
633 }
634
635 return drm_bridge_attach(encoder, bridge: output->bridge, previous: bridge,
636 flags);
637}
638
639static enum drm_mode_status
640cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge,
641 const struct drm_display_info *info,
642 const struct drm_display_mode *mode)
643{
644 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
645 struct cdns_dsi *dsi = input_to_dsi(input);
646 struct cdns_dsi_output *output = &dsi->output;
647 struct cdns_dsi_cfg dsi_cfg;
648 int bpp, ret;
649
650 /*
651 * VFP_DSI should be less than VFP_DPI and VFP_DSI should be at
652 * least 1.
653 */
654 if (mode->vtotal - mode->vsync_end < 2)
655 return MODE_V_ILLEGAL;
656
657 /* VSA_DSI = VSA_DPI and must be at least 2. */
658 if (mode->vsync_end - mode->vsync_start < 2)
659 return MODE_V_ILLEGAL;
660
661 /* HACT must be 32-bits aligned. */
662 bpp = mipi_dsi_pixel_format_to_bpp(fmt: output->dev->format);
663 if ((mode->hdisplay * bpp) % 32)
664 return MODE_H_ILLEGAL;
665
666 ret = cdns_dsi_check_conf(dsi, mode, dsi_cfg: &dsi_cfg, mode_valid_check: true);
667 if (ret)
668 return MODE_BAD;
669
670 return MODE_OK;
671}
672
673static void cdns_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
674 struct drm_atomic_state *state)
675{
676 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
677 struct cdns_dsi *dsi = input_to_dsi(input);
678 u32 val;
679
680 val = readl(addr: dsi->regs + MCTL_MAIN_DATA_CTL);
681 val &= ~(IF_VID_SELECT_MASK | IF_VID_MODE | VID_EN | HOST_EOT_GEN |
682 DISP_EOT_GEN);
683 writel(val, addr: dsi->regs + MCTL_MAIN_DATA_CTL);
684
685 val = readl(addr: dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
686 writel(val, addr: dsi->regs + MCTL_MAIN_EN);
687
688 if (dsi->platform_ops && dsi->platform_ops->disable)
689 dsi->platform_ops->disable(dsi);
690
691 pm_runtime_put(dev: dsi->base.dev);
692}
693
694static void cdns_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
695 struct drm_atomic_state *state)
696{
697 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
698 struct cdns_dsi *dsi = input_to_dsi(input);
699
700 dsi->phy_initialized = false;
701 dsi->link_initialized = false;
702 phy_power_off(phy: dsi->dphy);
703 phy_exit(phy: dsi->dphy);
704
705 pm_runtime_put(dev: dsi->base.dev);
706}
707
708static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
709{
710 struct cdns_dsi_output *output = &dsi->output;
711 u32 status;
712
713 if (dsi->phy_initialized)
714 return;
715 /*
716 * Power all internal DPHY blocks down and maintain their reset line
717 * asserted before changing the DPHY config.
718 */
719 writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN |
720 DPHY_CMN_PDN | DPHY_PLL_PDN,
721 addr: dsi->regs + MCTL_DPHY_CFG0);
722
723 phy_init(phy: dsi->dphy);
724 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
725 phy_configure(phy: dsi->dphy, opts: &output->phy_opts);
726 phy_power_on(phy: dsi->dphy);
727
728 /* Activate the PLL and wait until it's locked. */
729 writel(PLL_LOCKED, addr: dsi->regs + MCTL_MAIN_STS_CLR);
730 writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN,
731 addr: dsi->regs + MCTL_DPHY_CFG0);
732 WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
733 status & PLL_LOCKED, 100, 100));
734 /* De-assert data and clock reset lines. */
735 writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN |
736 DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB,
737 addr: dsi->regs + MCTL_DPHY_CFG0);
738 dsi->phy_initialized = true;
739}
740
741static void cdns_dsi_init_link(struct cdns_dsi *dsi)
742{
743 struct cdns_dsi_output *output = &dsi->output;
744 unsigned long sysclk_period, ulpout;
745 u32 val;
746 int i;
747
748 if (dsi->link_initialized)
749 return;
750
751 val = 0;
752 for (i = 1; i < output->dev->lanes; i++)
753 val |= DATA_LANE_EN(i);
754
755 if (!(output->dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
756 val |= CLK_CONTINUOUS;
757
758 writel(val, addr: dsi->regs + MCTL_MAIN_PHY_CTL);
759
760 /* ULPOUT should be set to 1ms and is expressed in sysclk cycles. */
761 sysclk_period = NSEC_PER_SEC / clk_get_rate(clk: dsi->dsi_sys_clk);
762 ulpout = DIV_ROUND_UP(NSEC_PER_MSEC, sysclk_period);
763 writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
764 addr: dsi->regs + MCTL_ULPOUT_TIME);
765
766 writel(LINK_EN, addr: dsi->regs + MCTL_MAIN_DATA_CTL);
767
768 val = CLK_LANE_EN | PLL_START;
769 for (i = 0; i < output->dev->lanes; i++)
770 val |= DATA_LANE_START(i);
771
772 writel(val, addr: dsi->regs + MCTL_MAIN_EN);
773
774 dsi->link_initialized = true;
775}
776
777static void cdns_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
778 struct drm_atomic_state *state)
779{
780 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
781 struct cdns_dsi *dsi = input_to_dsi(input);
782 struct cdns_dsi_output *output = &dsi->output;
783 struct drm_connector_state *conn_state;
784 struct drm_crtc_state *crtc_state;
785 struct cdns_dsi_bridge_state *dsi_state;
786 struct drm_bridge_state *new_bridge_state;
787 struct drm_display_mode *mode;
788 struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
789 struct drm_connector *connector;
790 unsigned long tx_byte_period;
791 struct cdns_dsi_cfg dsi_cfg;
792 u32 tmp, reg_wakeup, div, status;
793 int nlanes;
794
795 if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
796 return;
797
798 new_bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
799 if (WARN_ON(!new_bridge_state))
800 return;
801
802 dsi_state = to_cdns_dsi_bridge_state(bridge_state: new_bridge_state);
803 dsi_cfg = dsi_state->dsi_cfg;
804
805 if (dsi->platform_ops && dsi->platform_ops->enable)
806 dsi->platform_ops->enable(dsi);
807
808 connector = drm_atomic_get_new_connector_for_encoder(state, encoder: bridge->encoder);
809 conn_state = drm_atomic_get_new_connector_state(state, connector);
810 crtc_state = drm_atomic_get_new_crtc_state(state, crtc: conn_state->crtc);
811 mode = &crtc_state->adjusted_mode;
812 nlanes = output->dev->lanes;
813
814 cdns_dsi_hs_init(dsi);
815 cdns_dsi_init_link(dsi);
816
817 /*
818 * Now that the DSI Link and DSI Phy are initialized,
819 * wait for the CLK and Data Lanes to be ready.
820 */
821 tmp = CLK_LANE_RDY;
822 for (int i = 0; i < nlanes; i++)
823 tmp |= DATA_LANE_RDY(i);
824
825 if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
826 (tmp == (status & tmp)), 100, 500000))
827 dev_err(dsi->base.dev,
828 "Timed Out: DSI-DPhy Clock and Data Lanes not ready.\n");
829
830 writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
831 addr: dsi->regs + VID_HSIZE1);
832 writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),
833 addr: dsi->regs + VID_HSIZE2);
834
835 writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) |
836 VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay) |
837 VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start + 1),
838 addr: dsi->regs + VID_VSIZE1);
839 writel(val: mode->crtc_vdisplay, addr: dsi->regs + VID_VSIZE2);
840
841 tmp = dsi_cfg.htotal -
842 (dsi_cfg.hsa + DSI_BLANKING_FRAME_OVERHEAD +
843 DSI_HSA_FRAME_OVERHEAD);
844 writel(BLK_LINE_PULSE_PKT_LEN(tmp), addr: dsi->regs + VID_BLKSIZE2);
845 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
846 writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
847 addr: dsi->regs + VID_VCA_SETTING2);
848
849 tmp = dsi_cfg.htotal -
850 (DSI_HSS_VSS_VSE_FRAME_OVERHEAD + DSI_BLANKING_FRAME_OVERHEAD);
851 writel(BLK_LINE_EVENT_PKT_LEN(tmp), addr: dsi->regs + VID_BLKSIZE1);
852 if (!(output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
853 writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
854 addr: dsi->regs + VID_VCA_SETTING2);
855
856 tmp = DIV_ROUND_UP(dsi_cfg.htotal, nlanes) -
857 DIV_ROUND_UP(dsi_cfg.hsa, nlanes);
858
859 if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
860 tmp -= DIV_ROUND_UP(DSI_EOT_PKT_SIZE, nlanes);
861
862 tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,
863 phy_cfg->hs_clk_rate);
864 reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;
865 writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
866 addr: dsi->regs + VID_DPHY_TIME);
867
868 /*
869 * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and
870 * both should be set to at least the time it takes to transmit a
871 * frame.
872 */
873 tmp = NSEC_PER_SEC / drm_mode_vrefresh(mode);
874 tmp /= tx_byte_period;
875
876 for (div = 0; div <= CLK_DIV_MAX; div++) {
877 if (tmp <= HSTX_TIMEOUT_MAX)
878 break;
879
880 tmp >>= 1;
881 }
882
883 if (tmp > HSTX_TIMEOUT_MAX)
884 tmp = HSTX_TIMEOUT_MAX;
885
886 writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp),
887 addr: dsi->regs + MCTL_DPHY_TIMEOUT1);
888
889 writel(LPRX_TIMEOUT(tmp), addr: dsi->regs + MCTL_DPHY_TIMEOUT2);
890
891 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) {
892 switch (output->dev->format) {
893 case MIPI_DSI_FMT_RGB888:
894 tmp = VID_PIXEL_MODE_RGB888 |
895 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_24);
896 break;
897
898 case MIPI_DSI_FMT_RGB666:
899 tmp = VID_PIXEL_MODE_RGB666 |
900 VID_DATATYPE(MIPI_DSI_PIXEL_STREAM_3BYTE_18);
901 break;
902
903 case MIPI_DSI_FMT_RGB666_PACKED:
904 tmp = VID_PIXEL_MODE_RGB666_PACKED |
905 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_18);
906 break;
907
908 case MIPI_DSI_FMT_RGB565:
909 tmp = VID_PIXEL_MODE_RGB565 |
910 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_16);
911 break;
912
913 default:
914 dev_err(dsi->base.dev, "Unsupported DSI format\n");
915 return;
916 }
917
918 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
919 tmp |= SYNC_PULSE_ACTIVE | SYNC_PULSE_HORIZONTAL;
920
921 tmp |= REG_BLKLINE_MODE(REG_BLK_MODE_BLANKING_PKT) |
922 REG_BLKEOL_MODE(REG_BLK_MODE_BLANKING_PKT) |
923 RECOVERY_MODE(RECOVERY_MODE_NEXT_HSYNC) |
924 VID_IGNORE_MISS_VSYNC;
925
926 writel(val: tmp, addr: dsi->regs + VID_MAIN_CTL);
927 }
928
929 tmp = readl(addr: dsi->regs + MCTL_MAIN_DATA_CTL);
930 tmp &= ~(IF_VID_SELECT_MASK | HOST_EOT_GEN | IF_VID_MODE);
931
932 if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
933 tmp |= HOST_EOT_GEN;
934
935 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO)
936 tmp |= IF_VID_MODE | IF_VID_SELECT(input->id) | VID_EN;
937
938 writel(val: tmp, addr: dsi->regs + MCTL_MAIN_DATA_CTL);
939
940 tmp = readl(addr: dsi->regs + MCTL_MAIN_EN) | IF_EN(input->id);
941 writel(val: tmp, addr: dsi->regs + MCTL_MAIN_EN);
942}
943
944static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
945 struct drm_atomic_state *state)
946{
947 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
948 struct cdns_dsi *dsi = input_to_dsi(input);
949
950 if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
951 return;
952
953 cdns_dsi_init_link(dsi);
954 cdns_dsi_hs_init(dsi);
955}
956
957static u32 *cdns_dsi_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
958 struct drm_bridge_state *bridge_state,
959 struct drm_crtc_state *crtc_state,
960 struct drm_connector_state *conn_state,
961 u32 output_fmt,
962 unsigned int *num_input_fmts)
963{
964 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
965 struct cdns_dsi *dsi = input_to_dsi(input);
966 struct cdns_dsi_output *output = &dsi->output;
967 u32 *input_fmts;
968
969 *num_input_fmts = 0;
970
971 input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL);
972 if (!input_fmts)
973 return NULL;
974
975 input_fmts[0] = drm_mipi_dsi_get_input_bus_fmt(dsi_format: output->dev->format);
976 if (!input_fmts[0])
977 return NULL;
978
979 *num_input_fmts = 1;
980
981 return input_fmts;
982}
983
984static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,
985 struct drm_bridge_state *bridge_state,
986 struct drm_crtc_state *crtc_state,
987 struct drm_connector_state *conn_state)
988{
989 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
990 struct cdns_dsi *dsi = input_to_dsi(input);
991 struct cdns_dsi_bridge_state *dsi_state = to_cdns_dsi_bridge_state(bridge_state);
992 const struct drm_display_mode *mode = &crtc_state->mode;
993 struct cdns_dsi_cfg *dsi_cfg = &dsi_state->dsi_cfg;
994
995 return cdns_dsi_check_conf(dsi, mode, dsi_cfg, mode_valid_check: false);
996}
997
998static struct drm_bridge_state *
999cdns_dsi_bridge_atomic_duplicate_state(struct drm_bridge *bridge)
1000{
1001 struct cdns_dsi_bridge_state *dsi_state, *old_dsi_state;
1002 struct drm_bridge_state *bridge_state;
1003
1004 if (WARN_ON(!bridge->base.state))
1005 return NULL;
1006
1007 bridge_state = drm_priv_to_bridge_state(priv: bridge->base.state);
1008 old_dsi_state = to_cdns_dsi_bridge_state(bridge_state);
1009
1010 dsi_state = kzalloc(sizeof(*dsi_state), GFP_KERNEL);
1011 if (!dsi_state)
1012 return NULL;
1013
1014 __drm_atomic_helper_bridge_duplicate_state(bridge, state: &dsi_state->base);
1015
1016 memcpy(&dsi_state->dsi_cfg, &old_dsi_state->dsi_cfg,
1017 sizeof(dsi_state->dsi_cfg));
1018
1019 return &dsi_state->base;
1020}
1021
1022static void
1023cdns_dsi_bridge_atomic_destroy_state(struct drm_bridge *bridge,
1024 struct drm_bridge_state *state)
1025{
1026 struct cdns_dsi_bridge_state *dsi_state;
1027
1028 dsi_state = to_cdns_dsi_bridge_state(bridge_state: state);
1029
1030 kfree(objp: dsi_state);
1031}
1032
1033static struct drm_bridge_state *
1034cdns_dsi_bridge_atomic_reset(struct drm_bridge *bridge)
1035{
1036 struct cdns_dsi_bridge_state *dsi_state;
1037
1038 dsi_state = kzalloc(sizeof(*dsi_state), GFP_KERNEL);
1039 if (!dsi_state)
1040 return NULL;
1041
1042 memset(dsi_state, 0, sizeof(*dsi_state));
1043 dsi_state->base.bridge = bridge;
1044
1045 return &dsi_state->base;
1046}
1047
1048static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = {
1049 .attach = cdns_dsi_bridge_attach,
1050 .mode_valid = cdns_dsi_bridge_mode_valid,
1051 .atomic_disable = cdns_dsi_bridge_atomic_disable,
1052 .atomic_pre_enable = cdns_dsi_bridge_atomic_pre_enable,
1053 .atomic_enable = cdns_dsi_bridge_atomic_enable,
1054 .atomic_post_disable = cdns_dsi_bridge_atomic_post_disable,
1055 .atomic_check = cdns_dsi_bridge_atomic_check,
1056 .atomic_reset = cdns_dsi_bridge_atomic_reset,
1057 .atomic_duplicate_state = cdns_dsi_bridge_atomic_duplicate_state,
1058 .atomic_destroy_state = cdns_dsi_bridge_atomic_destroy_state,
1059 .atomic_get_input_bus_fmts = cdns_dsi_bridge_get_input_bus_fmts,
1060};
1061
1062static int cdns_dsi_attach(struct mipi_dsi_host *host,
1063 struct mipi_dsi_device *dev)
1064{
1065 struct cdns_dsi *dsi = to_cdns_dsi(host);
1066 struct cdns_dsi_output *output = &dsi->output;
1067 struct cdns_dsi_input *input = &dsi->input;
1068 struct drm_bridge *bridge;
1069 int ret;
1070
1071 /*
1072 * We currently do not support connecting several DSI devices to the
1073 * same host. In order to support that we'd need the DRM bridge
1074 * framework to allow dynamic reconfiguration of the bridge chain.
1075 */
1076 if (output->dev)
1077 return -EBUSY;
1078
1079 /* We do not support burst mode yet. */
1080 if (dev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
1081 return -ENOTSUPP;
1082
1083 /*
1084 * The host <-> device link might be described using an OF-graph
1085 * representation, in this case we extract the device of_node from
1086 * this representation.
1087 */
1088 bridge = devm_drm_of_get_bridge(dev: dsi->base.dev, node: dsi->base.dev->of_node,
1089 DSI_OUTPUT_PORT, endpoint: dev->channel);
1090 if (IS_ERR(ptr: bridge)) {
1091 ret = PTR_ERR(ptr: bridge);
1092 dev_err(host->dev, "failed to add DSI device %s (err = %d)",
1093 dev->name, ret);
1094 return ret;
1095 }
1096
1097 output->dev = dev;
1098 output->bridge = bridge;
1099
1100 /*
1101 * The DSI output has been properly configured, we can now safely
1102 * register the input to the bridge framework so that it can take place
1103 * in a display pipeline.
1104 */
1105 drm_bridge_add(bridge: &input->bridge);
1106
1107 return 0;
1108}
1109
1110static int cdns_dsi_detach(struct mipi_dsi_host *host,
1111 struct mipi_dsi_device *dev)
1112{
1113 struct cdns_dsi *dsi = to_cdns_dsi(host);
1114 struct cdns_dsi_input *input = &dsi->input;
1115
1116 drm_bridge_remove(bridge: &input->bridge);
1117
1118 return 0;
1119}
1120
1121static irqreturn_t cdns_dsi_interrupt(int irq, void *data)
1122{
1123 struct cdns_dsi *dsi = data;
1124 irqreturn_t ret = IRQ_NONE;
1125 u32 flag, ctl;
1126
1127 flag = readl(addr: dsi->regs + DIRECT_CMD_STS_FLAG);
1128 if (flag) {
1129 ctl = readl(addr: dsi->regs + DIRECT_CMD_STS_CTL);
1130 ctl &= ~flag;
1131 writel(val: ctl, addr: dsi->regs + DIRECT_CMD_STS_CTL);
1132 complete(&dsi->direct_cmd_comp);
1133 ret = IRQ_HANDLED;
1134 }
1135
1136 return ret;
1137}
1138
1139static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
1140 const struct mipi_dsi_msg *msg)
1141{
1142 struct cdns_dsi *dsi = to_cdns_dsi(host);
1143 u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0;
1144 struct mipi_dsi_packet packet;
1145 int ret, i, tx_len, rx_len;
1146
1147 ret = pm_runtime_resume_and_get(dev: host->dev);
1148 if (ret < 0)
1149 return ret;
1150
1151 cdns_dsi_init_link(dsi);
1152
1153 ret = mipi_dsi_create_packet(packet: &packet, msg);
1154 if (ret)
1155 goto out;
1156
1157 tx_len = msg->tx_buf ? msg->tx_len : 0;
1158 rx_len = msg->rx_buf ? msg->rx_len : 0;
1159
1160 /* For read operations, the maximum TX len is 2. */
1161 if (rx_len && tx_len > 2) {
1162 ret = -ENOTSUPP;
1163 goto out;
1164 }
1165
1166 /* TX len is limited by the CMD FIFO depth. */
1167 if (tx_len > dsi->direct_cmd_fifo_depth) {
1168 ret = -ENOTSUPP;
1169 goto out;
1170 }
1171
1172 /* RX len is limited by the RX FIFO depth. */
1173 if (rx_len > dsi->rx_fifo_depth) {
1174 ret = -ENOTSUPP;
1175 goto out;
1176 }
1177
1178 cmd = CMD_SIZE(tx_len) | CMD_VCHAN_ID(msg->channel) |
1179 CMD_DATATYPE(msg->type);
1180
1181 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1182 cmd |= CMD_LP_EN;
1183
1184 if (mipi_dsi_packet_format_is_long(type: msg->type))
1185 cmd |= CMD_LONG;
1186
1187 if (rx_len) {
1188 cmd |= READ_CMD;
1189 wait = READ_COMPLETED_WITH_ERR | READ_COMPLETED;
1190 ctl = READ_EN | BTA_EN;
1191 } else if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
1192 cmd |= BTA_REQ;
1193 wait = ACK_WITH_ERR_RCVD | ACK_RCVD;
1194 ctl = BTA_EN;
1195 }
1196
1197 writel(readl(addr: dsi->regs + MCTL_MAIN_DATA_CTL) | ctl,
1198 addr: dsi->regs + MCTL_MAIN_DATA_CTL);
1199
1200 writel(val: cmd, addr: dsi->regs + DIRECT_CMD_MAIN_SETTINGS);
1201
1202 for (i = 0; i < tx_len; i += 4) {
1203 const u8 *buf = msg->tx_buf;
1204 int j;
1205
1206 val = 0;
1207 for (j = 0; j < 4 && j + i < tx_len; j++)
1208 val |= (u32)buf[i + j] << (8 * j);
1209
1210 writel(val, addr: dsi->regs + DIRECT_CMD_WRDATA);
1211 }
1212
1213 /* Clear status flags before sending the command. */
1214 writel(val: wait, addr: dsi->regs + DIRECT_CMD_STS_CLR);
1215 writel(val: wait, addr: dsi->regs + DIRECT_CMD_STS_CTL);
1216 reinit_completion(x: &dsi->direct_cmd_comp);
1217 writel(val: 0, addr: dsi->regs + DIRECT_CMD_SEND);
1218
1219 wait_for_completion_timeout(x: &dsi->direct_cmd_comp,
1220 timeout: msecs_to_jiffies(m: 1000));
1221
1222 sts = readl(addr: dsi->regs + DIRECT_CMD_STS);
1223 writel(val: wait, addr: dsi->regs + DIRECT_CMD_STS_CLR);
1224 writel(val: 0, addr: dsi->regs + DIRECT_CMD_STS_CTL);
1225
1226 writel(readl(addr: dsi->regs + MCTL_MAIN_DATA_CTL) & ~ctl,
1227 addr: dsi->regs + MCTL_MAIN_DATA_CTL);
1228
1229 /* We did not receive the events we were waiting for. */
1230 if (!(sts & wait)) {
1231 ret = -ETIMEDOUT;
1232 goto out;
1233 }
1234
1235 /* 'READ' or 'WRITE with ACK' failed. */
1236 if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) {
1237 ret = -EIO;
1238 goto out;
1239 }
1240
1241 for (i = 0; i < rx_len; i += 4) {
1242 u8 *buf = msg->rx_buf;
1243 int j;
1244
1245 val = readl(addr: dsi->regs + DIRECT_CMD_RDDATA);
1246 for (j = 0; j < 4 && j + i < rx_len; j++)
1247 buf[i + j] = val >> (8 * j);
1248 }
1249
1250out:
1251 pm_runtime_put(dev: host->dev);
1252 return ret;
1253}
1254
1255static const struct mipi_dsi_host_ops cdns_dsi_ops = {
1256 .attach = cdns_dsi_attach,
1257 .detach = cdns_dsi_detach,
1258 .transfer = cdns_dsi_transfer,
1259};
1260
1261static int __maybe_unused cdns_dsi_resume(struct device *dev)
1262{
1263 struct cdns_dsi *dsi = dev_get_drvdata(dev);
1264
1265 reset_control_deassert(rstc: dsi->dsi_p_rst);
1266 clk_prepare_enable(clk: dsi->dsi_p_clk);
1267 clk_prepare_enable(clk: dsi->dsi_sys_clk);
1268
1269 return 0;
1270}
1271
1272static int __maybe_unused cdns_dsi_suspend(struct device *dev)
1273{
1274 struct cdns_dsi *dsi = dev_get_drvdata(dev);
1275
1276 clk_disable_unprepare(clk: dsi->dsi_sys_clk);
1277 clk_disable_unprepare(clk: dsi->dsi_p_clk);
1278 reset_control_assert(rstc: dsi->dsi_p_rst);
1279 return 0;
1280}
1281
1282static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume,
1283 NULL);
1284
1285static int cdns_dsi_drm_probe(struct platform_device *pdev)
1286{
1287 struct cdns_dsi *dsi;
1288 struct cdns_dsi_input *input;
1289 int ret, irq;
1290 u32 val;
1291
1292 dsi = devm_kzalloc(dev: &pdev->dev, size: sizeof(*dsi), GFP_KERNEL);
1293 if (!dsi)
1294 return -ENOMEM;
1295
1296 platform_set_drvdata(pdev, data: dsi);
1297
1298 input = &dsi->input;
1299
1300 dsi->regs = devm_platform_ioremap_resource(pdev, index: 0);
1301 if (IS_ERR(ptr: dsi->regs))
1302 return PTR_ERR(ptr: dsi->regs);
1303
1304 dsi->dsi_p_clk = devm_clk_get(dev: &pdev->dev, id: "dsi_p_clk");
1305 if (IS_ERR(ptr: dsi->dsi_p_clk))
1306 return PTR_ERR(ptr: dsi->dsi_p_clk);
1307
1308 dsi->dsi_p_rst = devm_reset_control_get_optional_exclusive(dev: &pdev->dev,
1309 id: "dsi_p_rst");
1310 if (IS_ERR(ptr: dsi->dsi_p_rst))
1311 return PTR_ERR(ptr: dsi->dsi_p_rst);
1312
1313 dsi->dsi_sys_clk = devm_clk_get(dev: &pdev->dev, id: "dsi_sys_clk");
1314 if (IS_ERR(ptr: dsi->dsi_sys_clk))
1315 return PTR_ERR(ptr: dsi->dsi_sys_clk);
1316
1317 irq = platform_get_irq(pdev, 0);
1318 if (irq < 0)
1319 return irq;
1320
1321 dsi->dphy = devm_phy_get(dev: &pdev->dev, string: "dphy");
1322 if (IS_ERR(ptr: dsi->dphy))
1323 return PTR_ERR(ptr: dsi->dphy);
1324
1325 ret = clk_prepare_enable(clk: dsi->dsi_p_clk);
1326 if (ret)
1327 return ret;
1328
1329 val = readl(addr: dsi->regs + ID_REG);
1330 if (REV_VENDOR_ID(val) != 0xcad) {
1331 dev_err(&pdev->dev, "invalid vendor id\n");
1332 ret = -EINVAL;
1333 goto err_disable_pclk;
1334 }
1335
1336 dsi->platform_ops = of_device_get_match_data(dev: &pdev->dev);
1337
1338 val = readl(addr: dsi->regs + IP_CONF);
1339 dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
1340 dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
1341 init_completion(x: &dsi->direct_cmd_comp);
1342
1343 writel(val: 0, addr: dsi->regs + MCTL_MAIN_DATA_CTL);
1344 writel(val: 0, addr: dsi->regs + MCTL_MAIN_EN);
1345 writel(val: 0, addr: dsi->regs + MCTL_MAIN_PHY_CTL);
1346
1347 /*
1348 * We only support the DPI input, so force input->id to
1349 * CDNS_DPI_INPUT.
1350 */
1351 input->id = CDNS_DPI_INPUT;
1352 input->bridge.funcs = &cdns_dsi_bridge_funcs;
1353 input->bridge.of_node = pdev->dev.of_node;
1354
1355 /* Mask all interrupts before registering the IRQ handler. */
1356 writel(val: 0, addr: dsi->regs + MCTL_MAIN_STS_CTL);
1357 writel(val: 0, addr: dsi->regs + MCTL_DPHY_ERR_CTL1);
1358 writel(val: 0, addr: dsi->regs + CMD_MODE_STS_CTL);
1359 writel(val: 0, addr: dsi->regs + DIRECT_CMD_STS_CTL);
1360 writel(val: 0, addr: dsi->regs + DIRECT_CMD_RD_STS_CTL);
1361 writel(val: 0, addr: dsi->regs + VID_MODE_STS_CTL);
1362 writel(val: 0, addr: dsi->regs + TVG_STS_CTL);
1363 writel(val: 0, addr: dsi->regs + DPI_IRQ_EN);
1364 ret = devm_request_irq(dev: &pdev->dev, irq, handler: cdns_dsi_interrupt, irqflags: 0,
1365 devname: dev_name(dev: &pdev->dev), dev_id: dsi);
1366 if (ret)
1367 goto err_disable_pclk;
1368
1369 pm_runtime_enable(dev: &pdev->dev);
1370 dsi->base.dev = &pdev->dev;
1371 dsi->base.ops = &cdns_dsi_ops;
1372
1373 if (dsi->platform_ops && dsi->platform_ops->init) {
1374 ret = dsi->platform_ops->init(dsi);
1375 if (ret != 0) {
1376 dev_err(&pdev->dev, "platform initialization failed: %d\n",
1377 ret);
1378 goto err_disable_runtime_pm;
1379 }
1380 }
1381
1382 ret = mipi_dsi_host_register(host: &dsi->base);
1383 if (ret)
1384 goto err_deinit_platform;
1385
1386 clk_disable_unprepare(clk: dsi->dsi_p_clk);
1387
1388 return 0;
1389
1390err_deinit_platform:
1391 if (dsi->platform_ops && dsi->platform_ops->deinit)
1392 dsi->platform_ops->deinit(dsi);
1393
1394err_disable_runtime_pm:
1395 pm_runtime_disable(dev: &pdev->dev);
1396
1397err_disable_pclk:
1398 clk_disable_unprepare(clk: dsi->dsi_p_clk);
1399
1400 return ret;
1401}
1402
1403static void cdns_dsi_drm_remove(struct platform_device *pdev)
1404{
1405 struct cdns_dsi *dsi = platform_get_drvdata(pdev);
1406
1407 mipi_dsi_host_unregister(host: &dsi->base);
1408
1409 if (dsi->platform_ops && dsi->platform_ops->deinit)
1410 dsi->platform_ops->deinit(dsi);
1411
1412 pm_runtime_disable(dev: &pdev->dev);
1413}
1414
1415static const struct of_device_id cdns_dsi_of_match[] = {
1416 { .compatible = "cdns,dsi" },
1417#ifdef CONFIG_DRM_CDNS_DSI_J721E
1418 { .compatible = "ti,j721e-dsi", .data = &dsi_ti_j721e_ops, },
1419#endif
1420 { },
1421};
1422MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
1423
1424static struct platform_driver cdns_dsi_platform_driver = {
1425 .probe = cdns_dsi_drm_probe,
1426 .remove = cdns_dsi_drm_remove,
1427 .driver = {
1428 .name = "cdns-dsi",
1429 .of_match_table = cdns_dsi_of_match,
1430 .pm = &cdns_dsi_pm_ops,
1431 },
1432};
1433module_platform_driver(cdns_dsi_platform_driver);
1434
1435MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
1436MODULE_DESCRIPTION("Cadence DSI driver");
1437MODULE_LICENSE("GPL");
1438MODULE_ALIAS("platform:cdns-dsi");
1439
1440

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source code of linux/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c