1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2	/*
3	* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4	*/
5	#include <linux/bits.h>
6	#include <linux/delay.h>
7	#include <linux/device.h>
8	#include <linux/err.h>
9	#include <linux/extcon.h>
10	#include <linux/fs.h>
11	#include <linux/gpio/consumer.h>
12	#include <linux/i2c.h>
13	#include <linux/interrupt.h>
14	#include <linux/kernel.h>
15	#include <linux/module.h>
16	#include <linux/pm_runtime.h>
17	#include <linux/regmap.h>
18	#include <linux/regulator/consumer.h>
19	#include <linux/types.h>
20	#include <linux/wait.h>
21
22	#include <crypto/hash.h>
23
24	#include <drm/display/drm_dp_helper.h>
25	#include <drm/display/drm_hdcp_helper.h>
26	#include <drm/drm_atomic_helper.h>
27	#include <drm/drm_bridge.h>
28	#include <drm/drm_crtc.h>
29	#include <drm/drm_edid.h>
30	#include <drm/drm_print.h>
31	#include <drm/drm_probe_helper.h>
32
33	#include <sound/hdmi-codec.h>
34
35	#define REG_IC_VER 0x04
36
37	#define REG_RESET_CTRL 0x05
38	#define VIDEO_RESET BIT(0)
39	#define AUDIO_RESET BIT(1)
40	#define ALL_LOGIC_RESET BIT(2)
41	#define AUX_RESET BIT(3)
42	#define HDCP_RESET BIT(4)
43
44	#define INT_STATUS_01 0x06
45	#define INT_MASK_01 0x09
46	#define INT_HPD_CHANGE 0
47	#define INT_RECEIVE_HPD_IRQ 1
48	#define INT_SCDT_CHANGE 2
49	#define INT_HDCP_FAIL 3
50	#define INT_HDCP_DONE 4
51	#define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
52	#define BIT_INT_HPD INT_HPD_CHANGE
53	#define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
54	#define BIT_INT_SCDT INT_SCDT_CHANGE
55	#define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
56	#define BIT_INT_HDCP_DONE INT_HDCP_DONE
57
58	#define INT_STATUS_02 0x07
59	#define INT_MASK_02 0x0A
60	#define INT_AUX_CMD_FAIL 0
61	#define INT_HDCP_KSV_CHECK 1
62	#define INT_AUDIO_FIFO_ERROR 2
63	#define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
64	#define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
65	#define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
66
67	#define INT_STATUS_03 0x08
68	#define INT_MASK_03 0x0B
69	#define INT_LINK_TRAIN_FAIL 4
70	#define INT_VID_FIFO_ERROR 5
71	#define INT_IO_LATCH_FIFO_OVERFLOW 7
72	#define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
73	#define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
74	#define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
75
76	#define REG_SYSTEM_STS 0x0D
77	#define INT_STS BIT(0)
78	#define HPD_STS BIT(1)
79	#define VIDEO_STB BIT(2)
80
81	#define REG_LINK_TRAIN_STS 0x0E
82	#define LINK_STATE_CR BIT(2)
83	#define LINK_STATE_EQ BIT(3)
84	#define LINK_STATE_NORP BIT(4)
85
86	#define REG_BANK_SEL 0x0F
87	#define REG_CLK_CTRL0 0x10
88	#define M_PCLK_DELAY 0x03
89
90	#define REG_AUX_OPT 0x11
91	#define AUX_AUTO_RST BIT(0)
92	#define AUX_FIX_FREQ BIT(3)
93
94	#define REG_DATA_CTRL0 0x12
95	#define VIDEO_LATCH_EDGE BIT(4)
96	#define ENABLE_PCLK_COUNTER BIT(7)
97
98	#define REG_PCLK_COUNTER_VALUE 0x13
99
100	#define REG_501_FIFO_CTRL 0x15
101	#define RST_501_FIFO BIT(1)
102
103	#define REG_TRAIN_CTRL0 0x16
104	#define FORCE_LBR BIT(0)
105	#define LANE_COUNT_MASK 0x06
106	#define LANE_SWAP BIT(3)
107	#define SPREAD_AMP_5 BIT(4)
108	#define FORCE_CR_DONE BIT(5)
109	#define FORCE_EQ_DONE BIT(6)
110
111	#define REG_TRAIN_CTRL1 0x17
112	#define AUTO_TRAIN BIT(0)
113	#define MANUAL_TRAIN BIT(1)
114	#define FORCE_RETRAIN BIT(2)
115
116	#define REG_AUX_CTRL 0x23
117	#define CLR_EDID_FIFO BIT(0)
118	#define AUX_USER_MODE BIT(1)
119	#define AUX_NO_SEGMENT_WR BIT(6)
120	#define AUX_EN_FIFO_READ BIT(7)
121
122	#define REG_AUX_ADR_0_7 0x24
123	#define REG_AUX_ADR_8_15 0x25
124	#define REG_AUX_ADR_16_19 0x26
125	#define REG_AUX_OUT_DATA0 0x27
126
127	#define REG_AUX_CMD_REQ 0x2B
128	#define AUX_BUSY BIT(5)
129
130	#define REG_AUX_DATA_0_7 0x2C
131	#define REG_AUX_DATA_8_15 0x2D
132	#define REG_AUX_DATA_16_23 0x2E
133	#define REG_AUX_DATA_24_31 0x2F
134
135	#define REG_AUX_DATA_FIFO 0x2F
136
137	#define REG_AUX_ERROR_STS 0x9F
138	#define M_AUX_REQ_FAIL 0x03
139
140	#define REG_HDCP_CTRL1 0x38
141	#define HDCP_CP_ENABLE BIT(0)
142
143	#define REG_HDCP_TRIGGER 0x39
144	#define HDCP_TRIGGER_START BIT(0)
145	#define HDCP_TRIGGER_CPIRQ BIT(1)
146	#define HDCP_TRIGGER_KSV_DONE BIT(4)
147	#define HDCP_TRIGGER_KSV_FAIL BIT(5)
148
149	#define REG_HDCP_CTRL2 0x3A
150	#define HDCP_AN_SEL BIT(0)
151	#define HDCP_AN_GEN BIT(1)
152	#define HDCP_HW_HPDIRQ_ACT BIT(2)
153	#define HDCP_EN_M0_READ BIT(5)
154
155	#define REG_M0_0_7 0x4C
156	#define REG_AN_0_7 0x4C
157	#define REG_SP_CTRL0 0x58
158	#define REG_IP_CTRL1 0x59
159	#define REG_IP_CTRL2 0x5A
160
161	#define REG_LINK_DRV 0x5C
162	#define DRV_HS BIT(1)
163
164	#define REG_DRV_LN_DATA_SEL 0x5D
165
166	#define REG_AUX 0x5E
167
168	#define REG_VID_BUS_CTRL0 0x60
169	#define IN_DDR BIT(2)
170	#define DDR_CD (0x01 << 6)
171
172	#define REG_VID_BUS_CTRL1 0x61
173	#define TX_FIFO_RESET BIT(1)
174
175	#define REG_INPUT_CTRL 0xA0
176	#define INPUT_HSYNC_POL BIT(0)
177	#define INPUT_VSYNC_POL BIT(2)
178	#define INPUT_INTERLACED BIT(4)
179
180	#define REG_INPUT_HTOTAL 0xA1
181	#define REG_INPUT_HACTIVE_START 0xA3
182	#define REG_INPUT_HACTIVE_WIDTH 0xA5
183	#define REG_INPUT_HFRONT_PORCH 0xA7
184	#define REG_INPUT_HSYNC_WIDTH 0xA9
185	#define REG_INPUT_VTOTAL 0xAB
186	#define REG_INPUT_VACTIVE_START 0xAD
187	#define REG_INPUT_VACTIVE_WIDTH 0xAF
188	#define REG_INPUT_VFRONT_PORCH 0xB1
189	#define REG_INPUT_VSYNC_WIDTH 0xB3
190
191	#define REG_AUDIO_SRC_CTRL 0xB8
192	#define M_AUDIO_I2S_EN 0x0F
193	#define EN_I2S0 BIT(0)
194	#define EN_I2S1 BIT(1)
195	#define EN_I2S2 BIT(2)
196	#define EN_I2S3 BIT(3)
197	#define AUDIO_FIFO_RESET BIT(7)
198
199	#define REG_AUDIO_FMT 0xB9
200	#define REG_AUDIO_FIFO_SEL 0xBA
201
202	#define REG_AUDIO_CTRL0 0xBB
203	#define AUDIO_FULL_PKT BIT(4)
204	#define AUDIO_16B_BOUND BIT(5)
205
206	#define REG_AUDIO_CTRL1 0xBC
207	#define REG_AUDIO_INPUT_FREQ 0xBE
208
209	#define REG_IEC958_STS0 0xBF
210	#define REG_IEC958_STS1 0xC0
211	#define REG_IEC958_STS2 0xC1
212	#define REG_IEC958_STS3 0xC2
213	#define REG_IEC958_STS4 0xC3
214
215	#define REG_HPD_IRQ_TIME 0xC9
216	#define REG_AUX_DEBUG_MODE 0xCA
217	#define REG_AUX_OPT2 0xCB
218	#define REG_HDCP_OPT 0xCE
219	#define REG_USER_DRV_PRE 0xCF
220
221	#define REG_DATA_MUTE_CTRL 0xD3
222	#define ENABLE_ENHANCED_FRAME BIT(0)
223	#define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
224	#define EN_VID_MUTE BIT(4)
225	#define EN_AUD_MUTE BIT(5)
226
227	#define REG_TIME_STMP_CTRL 0xD4
228	#define EN_ENHANCE_VID_STMP BIT(0)
229	#define EN_ENHANCE_AUD_STMP BIT(2)
230	#define M_STAMP_STEP 0x30
231	#define EN_SSC_GAT BIT(6)
232
233	#define REG_INFOFRAME_CTRL 0xE8
234	#define EN_AVI_PKT BIT(0)
235	#define EN_AUD_PKT BIT(1)
236	#define EN_MPG_PKT BIT(2)
237	#define EN_GEN_PKT BIT(3)
238	#define EN_VID_TIME_STMP BIT(4)
239	#define EN_AUD_TIME_STMP BIT(5)
240	#define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
241	#define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
242
243	#define REG_AUDIO_N_0_7 0xDE
244	#define REG_AUDIO_N_8_15 0xDF
245	#define REG_AUDIO_N_16_23 0xE0
246
247	#define REG_AVI_INFO_DB1 0xE9
248	#define REG_AVI_INFO_DB2 0xEA
249	#define REG_AVI_INFO_DB3 0xEB
250	#define REG_AVI_INFO_DB4 0xEC
251	#define REG_AVI_INFO_DB5 0xED
252	#define REG_AVI_INFO_SUM 0xF6
253
254	#define REG_AUD_INFOFRAM_DB1 0xF7
255	#define REG_AUD_INFOFRAM_DB2 0xF8
256	#define REG_AUD_INFOFRAM_DB3 0xF9
257	#define REG_AUD_INFOFRAM_DB4 0xFA
258	#define REG_AUD_INFOFRAM_SUM 0xFB
259
260	/* the following six registers are in bank1 */
261	#define REG_DRV_0_DB_800_MV 0x17E
262	#define REG_PRE_0_DB_800_MV 0x17F
263	#define REG_PRE_3P5_DB_800_MV 0x181
264	#define REG_SSC_CTRL0 0x188
265	#define REG_SSC_CTRL1 0x189
266	#define REG_SSC_CTRL2 0x18A
267
268	#define RBR DP_LINK_BW_1_62
269	#define HBR DP_LINK_BW_2_7
270	#define HBR2 DP_LINK_BW_5_4
271	#define HBR3 DP_LINK_BW_8_1
272
273	#define DPCD_V_1_1 0x11
274	#define MISC_VERB 0xF0
275	#define MISC_VERC 0x70
276	#define I2S_INPUT_FORMAT_STANDARD 0
277	#define I2S_INPUT_FORMAT_32BIT 1
278	#define I2S_INPUT_LEFT_JUSTIFIED 0
279	#define I2S_INPUT_RIGHT_JUSTIFIED 1
280	#define I2S_DATA_1T_DELAY 0
281	#define I2S_DATA_NO_DELAY 1
282	#define I2S_WS_LEFT_CHANNEL 0
283	#define I2S_WS_RIGHT_CHANNEL 1
284	#define I2S_DATA_MSB_FIRST 0
285	#define I2S_DATA_LSB_FIRST 1
286	#define WORD_LENGTH_16BIT 0
287	#define WORD_LENGTH_18BIT 1
288	#define WORD_LENGTH_20BIT 2
289	#define WORD_LENGTH_24BIT 3
290	#define DEBUGFS_DIR_NAME "it6505-debugfs"
291	#define READ_BUFFER_SIZE 400
292
293	/* Vendor option */
294	#define HDCP_DESIRED 1
295	#define MAX_LANE_COUNT 4
296	#define MAX_LINK_RATE HBR
297	#define AUTO_TRAIN_RETRY 3
298	#define MAX_HDCP_DOWN_STREAM_COUNT 10
299	#define MAX_CR_LEVEL 0x03
300	#define MAX_EQ_LEVEL 0x03
301	#define AUX_WAIT_TIMEOUT_MS 15
302	#define AUX_FIFO_MAX_SIZE 32
303	#define PIXEL_CLK_DELAY 1
304	#define PIXEL_CLK_INVERSE 0
305	#define ADJUST_PHASE_THRESHOLD 80000
306	#define DPI_PIXEL_CLK_MAX 95000
307	#define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
308	#define DEFAULT_PWR_ON 0
309	#define DEFAULT_DRV_HOLD 0
310
311	#define AUDIO_SELECT I2S
312	#define AUDIO_TYPE LPCM
313	#define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
314	#define AUDIO_CHANNEL_COUNT 2
315	#define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
316	#define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
317	#define I2S_DATA_DELAY I2S_DATA_1T_DELAY
318	#define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
319	#define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
320	#define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
321
322	enum aux_cmd_type {
323	CMD_AUX_NATIVE_READ = 0x0,
324	CMD_AUX_NATIVE_WRITE = 0x5,
325	CMD_AUX_I2C_EDID_READ = 0xB,
326	};
327
328	enum aux_cmd_reply {
329	REPLY_ACK,
330	REPLY_NACK,
331	REPLY_DEFER,
332	};
333
334	enum link_train_status {
335	LINK_IDLE,
336	LINK_BUSY,
337	LINK_OK,
338	};
339
340	enum hdcp_state {
341	HDCP_AUTH_IDLE,
342	HDCP_AUTH_GOING,
343	HDCP_AUTH_DONE,
344	};
345
346	struct it6505_platform_data {
347	struct regulator *pwr18;
348	struct regulator *ovdd;
349	struct gpio_desc *gpiod_reset;
350	};
351
352	enum it6505_audio_select {
353	I2S = 0,
354	SPDIF,
355	};
356
357	enum it6505_audio_sample_rate {
358	SAMPLE_RATE_24K = 0x6,
359	SAMPLE_RATE_32K = 0x3,
360	SAMPLE_RATE_48K = 0x2,
361	SAMPLE_RATE_96K = 0xA,
362	SAMPLE_RATE_192K = 0xE,
363	SAMPLE_RATE_44_1K = 0x0,
364	SAMPLE_RATE_88_2K = 0x8,
365	SAMPLE_RATE_176_4K = 0xC,
366	};
367
368	enum it6505_audio_type {
369	LPCM = 0,
370	NLPCM,
371	DSS,
372	};
373
374	struct it6505_audio_data {
375	enum it6505_audio_select select;
376	enum it6505_audio_sample_rate sample_rate;
377	enum it6505_audio_type type;
378	u8 word_length;
379	u8 channel_count;
380	u8 i2s_input_format;
381	u8 i2s_justified;
382	u8 i2s_data_delay;
383	u8 i2s_ws_channel;
384	u8 i2s_data_sequence;
385	};
386
387	struct it6505_audio_sample_rate_map {
388	enum it6505_audio_sample_rate rate;
389	int sample_rate_value;
390	};
391
392	struct it6505_drm_dp_link {
393	unsigned char revision;
394	unsigned int rate;
395	unsigned int num_lanes;
396	unsigned long capabilities;
397	};
398
399	struct debugfs_entries {
400	char *name;
401	const struct file_operations *fops;
402	};
403
404	struct it6505 {
405	struct drm_dp_aux aux;
406	struct drm_bridge bridge;
407	struct device *dev;
408	struct it6505_drm_dp_link link;
409	struct it6505_platform_data pdata;
410	/*
411	* Mutex protects extcon and interrupt functions from interfering
412	* each other.
413	*/
414	struct mutex extcon_lock;
415	struct mutex mode_lock; /* used to bridge_detect */
416	struct mutex aux_lock; /* used to aux data transfers */
417	struct regmap *regmap;
418	struct drm_display_mode source_output_mode;
419	struct drm_display_mode video_info;
420	struct notifier_block event_nb;
421	struct extcon_dev *extcon;
422	struct work_struct extcon_wq;
423	int extcon_state;
424	enum drm_connector_status connector_status;
425	enum link_train_status link_state;
426	struct work_struct link_works;
427	u8 dpcd[DP_RECEIVER_CAP_SIZE];
428	u8 lane_count;
429	u8 link_rate_bw_code;
430	u8 sink_count;
431	bool step_train;
432	bool branch_device;
433	bool enable_ssc;
434	bool lane_swap_disabled;
435	bool lane_swap;
436	bool powered;
437	bool hpd_state;
438	u32 afe_setting;
439	u32 max_dpi_pixel_clock;
440	u32 max_lane_count;
441	enum hdcp_state hdcp_status;
442	struct delayed_work hdcp_work;
443	struct work_struct hdcp_wait_ksv_list;
444	struct completion extcon_completion;
445	u8 auto_train_retry;
446	bool hdcp_desired;
447	bool is_repeater;
448	u8 hdcp_down_stream_count;
449	u8 bksvs[DRM_HDCP_KSV_LEN];
450	u8 sha1_input[HDCP_SHA1_FIFO_LEN];
451	bool enable_enhanced_frame;
452	hdmi_codec_plugged_cb plugged_cb;
453	struct device *codec_dev;
454	struct delayed_work delayed_audio;
455	struct it6505_audio_data audio;
456	struct dentry *debugfs;
457
458	/* it6505 driver hold option */
459	bool enable_drv_hold;
460
461	struct edid *cached_edid;
462	};
463
464	struct it6505_step_train_para {
465	u8 voltage_swing[MAX_LANE_COUNT];
466	u8 pre_emphasis[MAX_LANE_COUNT];
467	};
468
469	/*
470	* Vendor option afe settings for different platforms
471	* 0: without FPC cable
472	* 1: with FPC cable
473	*/
474
475	static const u8 afe_setting_table[][3] = {
476	{0x82, 0x00, 0x45},
477	{0x93, 0x2A, 0x85}
478	};
479
480	static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
481	{SAMPLE_RATE_24K, 24000},
482	{SAMPLE_RATE_32K, 32000},
483	{SAMPLE_RATE_48K, 48000},
484	{SAMPLE_RATE_96K, 96000},
485	{SAMPLE_RATE_192K, 192000},
486	{SAMPLE_RATE_44_1K, 44100},
487	{SAMPLE_RATE_88_2K, 88200},
488	{SAMPLE_RATE_176_4K, 176400},
489	};
490
491	static const struct regmap_range it6505_bridge_volatile_ranges[] = {
492	{ .range_min = 0, .range_max = 0x1FF },
493	};
494
495	static const struct regmap_access_table it6505_bridge_volatile_table = {
496	.yes_ranges = it6505_bridge_volatile_ranges,
497	.n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
498	};
499
500	static const struct regmap_range_cfg it6505_regmap_banks[] = {
501	{
502	.name = "it6505",
503	.range_min = 0x00,
504	.range_max = 0x1FF,
505	.selector_reg = REG_BANK_SEL,
506	.selector_mask = 0x1,
507	.selector_shift = 0,
508	.window_start = 0x00,
509	.window_len = 0x100,
510	},
511	};
512
513	static const struct regmap_config it6505_regmap_config = {
514	.reg_bits = 8,
515	.val_bits = 8,
516	.volatile_table = &it6505_bridge_volatile_table,
517	.cache_type = REGCACHE_NONE,
518	.ranges = it6505_regmap_banks,
519	.num_ranges = ARRAY_SIZE(it6505_regmap_banks),
520	.max_register = 0x1FF,
521	};
522
523	static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
524	{
525	unsigned int value;
526	int err;
527	struct device *dev = it6505->dev;
528
529	if (!it6505->powered)
530	return -ENODEV;
531
532	err = regmap_read(map: it6505->regmap, reg: reg_addr, val: &value);
533	if (err < 0) {
534	dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
535	return err;
536	}
537
538	return value;
539	}
540
541	static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
542	unsigned int reg_val)
543	{
544	int err;
545	struct device *dev = it6505->dev;
546
547	if (!it6505->powered)
548	return -ENODEV;
549
550	err = regmap_write(map: it6505->regmap, reg: reg_addr, val: reg_val);
551
552	if (err < 0) {
553	dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
554	reg_addr, reg_val, err);
555	return err;
556	}
557
558	return 0;
559	}
560
561	static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
562	unsigned int mask, unsigned int value)
563	{
564	int err;
565	struct device *dev = it6505->dev;
566
567	if (!it6505->powered)
568	return -ENODEV;
569
570	err = regmap_update_bits(map: it6505->regmap, reg, mask, val: value);
571	if (err < 0) {
572	dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
573	reg, value, mask, err);
574	return err;
575	}
576
577	return 0;
578	}
579
580	static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
581	const char *prefix)
582	{
583	struct device *dev = it6505->dev;
584	int val;
585
586	if (!drm_debug_enabled(DRM_UT_DRIVER))
587	return;
588
589	val = it6505_read(it6505, reg_addr: reg);
590	if (val < 0)
591	DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
592	prefix, reg, val);
593	else
594	DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
595	val);
596	}
597
598	static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
599	{
600	u8 value;
601	int ret;
602	struct device *dev = it6505->dev;
603
604	ret = drm_dp_dpcd_readb(aux: &it6505->aux, offset, valuep: &value);
605	if (ret < 0) {
606	dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
607	return ret;
608	}
609	return value;
610	}
611
612	static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
613	u8 datain)
614	{
615	int ret;
616	struct device *dev = it6505->dev;
617
618	ret = drm_dp_dpcd_writeb(aux: &it6505->aux, offset, value: datain);
619	if (ret < 0) {
620	dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
621	return ret;
622	}
623	return 0;
624	}
625
626	static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
627	{
628	int ret;
629	struct device *dev = it6505->dev;
630
631	ret = drm_dp_dpcd_read(aux: &it6505->aux, offset, buffer: dpcd, size: num);
632
633	if (ret < 0)
634	return ret;
635
636	DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
637	num, dpcd);
638
639	return 0;
640	}
641
642	static void it6505_dump(struct it6505 *it6505)
643	{
644	unsigned int i, j;
645	u8 regs[16];
646	struct device *dev = it6505->dev;
647
648	for (i = 0; i <= 0xff; i += 16) {
649	for (j = 0; j < 16; j++)
650	regs[j] = it6505_read(it6505, reg_addr: i + j);
651
652	DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
653	}
654	}
655
656	static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
657	{
658	int reg_0d;
659
660	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
661
662	if (reg_0d < 0)
663	return false;
664
665	return reg_0d & HPD_STS;
666	}
667
668	static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
669	{
670	int val0, val1;
671
672	val0 = it6505_read(it6505, reg_addr: reg);
673	if (val0 < 0)
674	return val0;
675
676	val1 = it6505_read(it6505, reg_addr: reg + 1);
677	if (val1 < 0)
678	return val1;
679
680	return (val1 << 8) | val0;
681	}
682
683	static void it6505_calc_video_info(struct it6505 *it6505)
684	{
685	struct device *dev = it6505->dev;
686	int hsync_pol, vsync_pol, interlaced;
687	int htotal, hdes, hdew, hfph, hsyncw;
688	int vtotal, vdes, vdew, vfph, vsyncw;
689	int rddata, i, pclk, sum = 0;
690
691	usleep_range(min: 10000, max: 15000);
692	rddata = it6505_read(it6505, REG_INPUT_CTRL);
693	hsync_pol = rddata & INPUT_HSYNC_POL;
694	vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
695	interlaced = (rddata & INPUT_INTERLACED) >> 4;
696
697	htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
698	hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
699	hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
700	hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
701	hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
702
703	vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
704	vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
705	vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
706	vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
707	vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
708
709	DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
710	hsync_pol, vsync_pol, interlaced);
711	DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
712	hdes, vdes);
713
714	for (i = 0; i < 3; i++) {
715	it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
716	ENABLE_PCLK_COUNTER);
717	usleep_range(min: 10000, max: 15000);
718	it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
719	value: 0x00);
720	rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
721	0xFFF;
722
723	sum += rddata;
724	}
725
726	if (sum == 0) {
727	DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
728	return;
729	}
730
731	sum /= 3;
732	pclk = 13500 * 2048 / sum;
733	it6505->video_info.clock = pclk;
734	it6505->video_info.hdisplay = hdew;
735	it6505->video_info.hsync_start = hdew + hfph;
736	it6505->video_info.hsync_end = hdew + hfph + hsyncw;
737	it6505->video_info.htotal = htotal;
738	it6505->video_info.vdisplay = vdew;
739	it6505->video_info.vsync_start = vdew + vfph;
740	it6505->video_info.vsync_end = vdew + vfph + vsyncw;
741	it6505->video_info.vtotal = vtotal;
742
743	DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
744	DRM_MODE_ARG(&it6505->video_info));
745	}
746
747	static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
748	struct it6505_drm_dp_link *link,
749	u8 mode)
750	{
751	u8 value;
752	int err;
753
754	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
755	if (link->revision < DPCD_V_1_1)
756	return 0;
757
758	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, valuep: &value);
759	if (err < 0)
760	return err;
761
762	value &= ~DP_SET_POWER_MASK;
763	value |= mode;
764
765	err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
766	if (err < 0)
767	return err;
768
769	if (mode == DP_SET_POWER_D0) {
770	/*
771	* According to the DP 1.1 specification, a "Sink Device must
772	* exit the power saving state within 1 ms" (Section 2.5.3.1,
773	* Table 5-52, "Sink Control Field" (register 0x600).
774	*/
775	usleep_range(min: 1000, max: 2000);
776	}
777
778	return 0;
779	}
780
781	static void it6505_clear_int(struct it6505 *it6505)
782	{
783	it6505_write(it6505, INT_STATUS_01, reg_val: 0xFF);
784	it6505_write(it6505, INT_STATUS_02, reg_val: 0xFF);
785	it6505_write(it6505, INT_STATUS_03, reg_val: 0xFF);
786	}
787
788	static void it6505_int_mask_enable(struct it6505 *it6505)
789	{
790	it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
791	BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
792	BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
793
794	it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
795	BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
796
797	it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
798	BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
799	}
800
801	static void it6505_int_mask_disable(struct it6505 *it6505)
802	{
803	it6505_write(it6505, INT_MASK_01, reg_val: 0x00);
804	it6505_write(it6505, INT_MASK_02, reg_val: 0x00);
805	it6505_write(it6505, INT_MASK_03, reg_val: 0x00);
806	}
807
808	static void it6505_lane_termination_on(struct it6505 *it6505)
809	{
810	int regcf;
811
812	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
813
814	if (regcf == MISC_VERB)
815	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x80, value: 0x00);
816
817	if (regcf == MISC_VERC) {
818	if (it6505->lane_swap) {
819	switch (it6505->lane_count) {
820	case 1:
821	case 2:
822	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
823	mask: 0x0C, value: 0x08);
824	break;
825	default:
826	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
827	mask: 0x0C, value: 0x0C);
828	break;
829	}
830	} else {
831	switch (it6505->lane_count) {
832	case 1:
833	case 2:
834	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
835	mask: 0x0C, value: 0x04);
836	break;
837	default:
838	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
839	mask: 0x0C, value: 0x0C);
840	break;
841	}
842	}
843	}
844	}
845
846	static void it6505_lane_termination_off(struct it6505 *it6505)
847	{
848	int regcf;
849
850	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
851
852	if (regcf == MISC_VERB)
853	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x80, value: 0x80);
854
855	if (regcf == MISC_VERC)
856	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x0C, value: 0x00);
857	}
858
859	static void it6505_lane_power_on(struct it6505 *it6505)
860	{
861	it6505_set_bits(it6505, REG_LINK_DRV, mask: 0xF1,
862	value: (it6505->lane_swap ?
863	GENMASK(7, 8 - it6505->lane_count) :
864	GENMASK(3 + it6505->lane_count, 4)) |
865	0x01);
866	}
867
868	static void it6505_lane_power_off(struct it6505 *it6505)
869	{
870	it6505_set_bits(it6505, REG_LINK_DRV, mask: 0xF0, value: 0x00);
871	}
872
873	static void it6505_lane_off(struct it6505 *it6505)
874	{
875	it6505_lane_power_off(it6505);
876	it6505_lane_termination_off(it6505);
877	}
878
879	static void it6505_aux_termination_on(struct it6505 *it6505)
880	{
881	int regcf;
882
883	regcf = it6505_read(it6505, REG_USER_DRV_PRE);
884
885	if (regcf == MISC_VERB)
886	it6505_lane_termination_on(it6505);
887
888	if (regcf == MISC_VERC)
889	it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, mask: 0x80, value: 0x80);
890	}
891
892	static void it6505_aux_power_on(struct it6505 *it6505)
893	{
894	it6505_set_bits(it6505, REG_AUX, mask: 0x02, value: 0x02);
895	}
896
897	static void it6505_aux_on(struct it6505 *it6505)
898	{
899	it6505_aux_power_on(it6505);
900	it6505_aux_termination_on(it6505);
901	}
902
903	static void it6505_aux_reset(struct it6505 *it6505)
904	{
905	it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
906	it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, value: 0x00);
907	}
908
909	static void it6505_reset_logic(struct it6505 *it6505)
910	{
911	regmap_write(map: it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
912	usleep_range(min: 1000, max: 1500);
913	}
914
915	static bool it6505_aux_op_finished(struct it6505 *it6505)
916	{
917	int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
918
919	if (reg2b < 0)
920	return false;
921
922	return (reg2b & AUX_BUSY) == 0;
923	}
924
925	static int it6505_aux_wait(struct it6505 *it6505)
926	{
927	int status;
928	unsigned long timeout;
929	struct device *dev = it6505->dev;
930
931	timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
932
933	while (!it6505_aux_op_finished(it6505)) {
934	if (time_after(jiffies, timeout)) {
935	dev_err(dev, "Timed out waiting AUX to finish");
936	return -ETIMEDOUT;
937	}
938	usleep_range(min: 1000, max: 2000);
939	}
940
941	status = it6505_read(it6505, REG_AUX_ERROR_STS);
942	if (status < 0) {
943	dev_err(dev, "Failed to read AUX channel: %d", status);
944	return status;
945	}
946
947	return 0;
948	}
949
950	static ssize_t it6505_aux_operation(struct it6505 *it6505,
951	enum aux_cmd_type cmd,
952	unsigned int address, u8 *buffer,
953	size_t size, enum aux_cmd_reply *reply)
954	{
955	int i, ret;
956	bool aux_write_check = false;
957
958	if (!it6505_get_sink_hpd_status(it6505))
959	return -EIO;
960
961	/* set AUX user mode */
962	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
963
964	aux_op_start:
965	if (cmd == CMD_AUX_I2C_EDID_READ) {
966	/* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
967	size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
968	/* Enable AUX FIFO read back and clear FIFO */
969	it6505_set_bits(it6505, REG_AUX_CTRL,
970	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
971	AUX_EN_FIFO_READ | CLR_EDID_FIFO);
972
973	it6505_set_bits(it6505, REG_AUX_CTRL,
974	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
975	AUX_EN_FIFO_READ);
976	} else {
977	/* The DP AUX transmit buffer has 4 bytes. */
978	size = min_t(size_t, size, 4);
979	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
980	AUX_NO_SEGMENT_WR);
981	}
982
983	/* Start Address[7:0] */
984	it6505_write(it6505, REG_AUX_ADR_0_7, reg_val: (address >> 0) & 0xFF);
985	/* Start Address[15:8] */
986	it6505_write(it6505, REG_AUX_ADR_8_15, reg_val: (address >> 8) & 0xFF);
987	/* WriteNum[3:0]+StartAdr[19:16] */
988	it6505_write(it6505, REG_AUX_ADR_16_19,
989	reg_val: ((address >> 16) & 0x0F) | ((size - 1) << 4));
990
991	if (cmd == CMD_AUX_NATIVE_WRITE)
992	regmap_bulk_write(map: it6505->regmap, REG_AUX_OUT_DATA0, val: buffer,
993	val_count: size);
994
995	/* Aux Fire */
996	it6505_write(it6505, REG_AUX_CMD_REQ, reg_val: cmd);
997
998	ret = it6505_aux_wait(it6505);
999	if (ret < 0)
1000	goto aux_op_err;
1001
1002	ret = it6505_read(it6505, REG_AUX_ERROR_STS);
1003	if (ret < 0)
1004	goto aux_op_err;
1005
1006	switch ((ret >> 6) & 0x3) {
1007	case 0:
1008	*reply = REPLY_ACK;
1009	break;
1010	case 1:
1011	*reply = REPLY_DEFER;
1012	ret = -EAGAIN;
1013	goto aux_op_err;
1014	case 2:
1015	*reply = REPLY_NACK;
1016	ret = -EIO;
1017	goto aux_op_err;
1018	case 3:
1019	ret = -ETIMEDOUT;
1020	goto aux_op_err;
1021	}
1022
1023	/* Read back Native Write data */
1024	if (cmd == CMD_AUX_NATIVE_WRITE) {
1025	aux_write_check = true;
1026	cmd = CMD_AUX_NATIVE_READ;
1027	goto aux_op_start;
1028	}
1029
1030	if (cmd == CMD_AUX_I2C_EDID_READ) {
1031	for (i = 0; i < size; i++) {
1032	ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1033	if (ret < 0)
1034	goto aux_op_err;
1035	buffer[i] = ret;
1036	}
1037	} else {
1038	for (i = 0; i < size; i++) {
1039	ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1040	if (ret < 0)
1041	goto aux_op_err;
1042
1043	if (aux_write_check && buffer[size - 1 - i] != ret) {
1044	ret = -EINVAL;
1045	goto aux_op_err;
1046	}
1047
1048	buffer[size - 1 - i] = ret;
1049	}
1050	}
1051
1052	ret = i;
1053
1054	aux_op_err:
1055	if (cmd == CMD_AUX_I2C_EDID_READ) {
1056	/* clear AUX FIFO */
1057	it6505_set_bits(it6505, REG_AUX_CTRL,
1058	AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1059	AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1060	it6505_set_bits(it6505, REG_AUX_CTRL,
1061	AUX_EN_FIFO_READ | CLR_EDID_FIFO, value: 0x00);
1062	}
1063
1064	/* Leave AUX user mode */
1065	it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, value: 0);
1066
1067	return ret;
1068	}
1069
1070	static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1071	enum aux_cmd_type cmd,
1072	unsigned int address, u8 *buffer,
1073	size_t size, enum aux_cmd_reply *reply)
1074	{
1075	int i, ret_size, ret = 0, request_size;
1076
1077	mutex_lock(&it6505->aux_lock);
1078	for (i = 0; i < size; i += 4) {
1079	request_size = min((int)size - i, 4);
1080	ret_size = it6505_aux_operation(it6505, cmd, address: address + i,
1081	buffer: buffer + i, size: request_size,
1082	reply);
1083	if (ret_size < 0) {
1084	ret = ret_size;
1085	goto aux_op_err;
1086	}
1087
1088	ret += ret_size;
1089	}
1090
1091	aux_op_err:
1092	mutex_unlock(lock: &it6505->aux_lock);
1093	return ret;
1094	}
1095
1096	static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1097	struct drm_dp_aux_msg *msg)
1098	{
1099	struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1100	u8 cmd;
1101	bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1102	int ret;
1103	enum aux_cmd_reply reply;
1104
1105	/* IT6505 doesn't support arbitrary I2C read / write. */
1106	if (is_i2c)
1107	return -EINVAL;
1108
1109	switch (msg->request) {
1110	case DP_AUX_NATIVE_READ:
1111	cmd = CMD_AUX_NATIVE_READ;
1112	break;
1113	case DP_AUX_NATIVE_WRITE:
1114	cmd = CMD_AUX_NATIVE_WRITE;
1115	break;
1116	default:
1117	return -EINVAL;
1118	}
1119
1120	ret = it6505_aux_do_transfer(it6505, cmd, address: msg->address, buffer: msg->buffer,
1121	size: msg->size, reply: &reply);
1122	if (ret < 0)
1123	return ret;
1124
1125	switch (reply) {
1126	case REPLY_ACK:
1127	msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1128	break;
1129	case REPLY_NACK:
1130	msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1131	break;
1132	case REPLY_DEFER:
1133	msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1134	break;
1135	}
1136
1137	return ret;
1138	}
1139
1140	static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1141	size_t len)
1142	{
1143	struct it6505 *it6505 = data;
1144	struct device *dev = it6505->dev;
1145	enum aux_cmd_reply reply;
1146	int offset, ret, aux_retry = 100;
1147
1148	it6505_aux_reset(it6505);
1149	DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1150
1151	for (offset = 0; offset < EDID_LENGTH;) {
1152	ret = it6505_aux_do_transfer(it6505, cmd: CMD_AUX_I2C_EDID_READ,
1153	address: block * EDID_LENGTH + offset,
1154	buffer: buf + offset, size: 8, reply: &reply);
1155
1156	if (ret < 0 && ret != -EAGAIN)
1157	return ret;
1158
1159	switch (reply) {
1160	case REPLY_ACK:
1161	DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1162	buf + offset);
1163	offset += 8;
1164	aux_retry = 100;
1165	break;
1166	case REPLY_NACK:
1167	return -EIO;
1168	case REPLY_DEFER:
1169	msleep(msecs: 20);
1170	if (!(--aux_retry))
1171	return -EIO;
1172	}
1173	}
1174
1175	return 0;
1176	}
1177
1178	static void it6505_variable_config(struct it6505 *it6505)
1179	{
1180	it6505->link_rate_bw_code = HBR;
1181	it6505->lane_count = MAX_LANE_COUNT;
1182	it6505->link_state = LINK_IDLE;
1183	it6505->hdcp_desired = HDCP_DESIRED;
1184	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1185	it6505->audio.select = AUDIO_SELECT;
1186	it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1187	it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1188	it6505->audio.type = AUDIO_TYPE;
1189	it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1190	it6505->audio.i2s_justified = I2S_JUSTIFIED;
1191	it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1192	it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1193	it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1194	it6505->audio.word_length = AUDIO_WORD_LENGTH;
1195	memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1196	memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1197	}
1198
1199	static int it6505_send_video_infoframe(struct it6505 *it6505,
1200	struct hdmi_avi_infoframe *frame)
1201	{
1202	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1203	int err;
1204	struct device *dev = it6505->dev;
1205
1206	err = hdmi_avi_infoframe_pack(frame, buffer, size: sizeof(buffer));
1207	if (err < 0) {
1208	dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1209	return err;
1210	}
1211
1212	err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, value: 0x00);
1213	if (err)
1214	return err;
1215
1216	err = regmap_bulk_write(map: it6505->regmap, REG_AVI_INFO_DB1,
1217	val: buffer + HDMI_INFOFRAME_HEADER_SIZE,
1218	val_count: frame->length);
1219	if (err)
1220	return err;
1221
1222	err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1223	EN_AVI_PKT);
1224	if (err)
1225	return err;
1226
1227	return 0;
1228	}
1229
1230	static void it6505_get_extcon_property(struct it6505 *it6505)
1231	{
1232	int err;
1233	union extcon_property_value property;
1234	struct device *dev = it6505->dev;
1235
1236	if (it6505->extcon && !it6505->lane_swap_disabled) {
1237	err = extcon_get_property(edev: it6505->extcon, EXTCON_DISP_DP,
1238	EXTCON_PROP_USB_TYPEC_POLARITY,
1239	prop_val: &property);
1240	if (err) {
1241	dev_err(dev, "get property fail!");
1242	return;
1243	}
1244	it6505->lane_swap = property.intval;
1245	}
1246	}
1247
1248	static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1249	const struct drm_display_mode *mode)
1250	{
1251	int clock = mode->clock;
1252
1253	it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1254	value: clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1255	it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1256	PIXEL_CLK_INVERSE << 4);
1257	}
1258
1259	static void it6505_link_reset_step_train(struct it6505 *it6505)
1260	{
1261	it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1262	FORCE_CR_DONE | FORCE_EQ_DONE, value: 0x00);
1263	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1264	DP_TRAINING_PATTERN_DISABLE);
1265	}
1266
1267	static void it6505_init(struct it6505 *it6505)
1268	{
1269	it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1270	it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1271	it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1272	it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1273	it6505_write(it6505, REG_VID_BUS_CTRL1, reg_val: 0x01);
1274	it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1275
1276	/* chip internal setting, don't modify */
1277	it6505_write(it6505, REG_HPD_IRQ_TIME, reg_val: 0xF5);
1278	it6505_write(it6505, REG_AUX_DEBUG_MODE, reg_val: 0x4D);
1279	it6505_write(it6505, REG_AUX_OPT2, reg_val: 0x17);
1280	it6505_write(it6505, REG_HDCP_OPT, reg_val: 0x60);
1281	it6505_write(it6505, REG_DATA_MUTE_CTRL,
1282	EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1283	it6505_write(it6505, REG_TIME_STMP_CTRL,
1284	EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1285	it6505_write(it6505, REG_INFOFRAME_CTRL, reg_val: 0x00);
1286	it6505_write(it6505, REG_DRV_0_DB_800_MV,
1287	reg_val: afe_setting_table[it6505->afe_setting][0]);
1288	it6505_write(it6505, REG_PRE_0_DB_800_MV,
1289	reg_val: afe_setting_table[it6505->afe_setting][1]);
1290	it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1291	reg_val: afe_setting_table[it6505->afe_setting][2]);
1292	it6505_write(it6505, REG_SSC_CTRL0, reg_val: 0x9E);
1293	it6505_write(it6505, REG_SSC_CTRL1, reg_val: 0x1C);
1294	it6505_write(it6505, REG_SSC_CTRL2, reg_val: 0x42);
1295	}
1296
1297	static void it6505_video_disable(struct it6505 *it6505)
1298	{
1299	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1300	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, value: 0x00);
1301	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1302	}
1303
1304	static void it6505_video_reset(struct it6505 *it6505)
1305	{
1306	it6505_link_reset_step_train(it6505);
1307	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1308	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, value: 0x00);
1309	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1310	it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1311	it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, value: 0x00);
1312	it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, value: 0x00);
1313	}
1314
1315	static void it6505_update_video_parameter(struct it6505 *it6505,
1316	const struct drm_display_mode *mode)
1317	{
1318	it6505_clk_phase_adjustment(it6505, mode);
1319	it6505_video_disable(it6505);
1320	}
1321
1322	static bool it6505_audio_input(struct it6505 *it6505)
1323	{
1324	int reg05, regbe;
1325
1326	reg05 = it6505_read(it6505, REG_RESET_CTRL);
1327	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, value: 0x00);
1328	usleep_range(min: 3000, max: 4000);
1329	regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1330	it6505_write(it6505, REG_RESET_CTRL, reg_val: reg05);
1331
1332	return regbe != 0xFF;
1333	}
1334
1335	static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1336	{
1337	enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1338	u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1339
1340	/* Channel Status */
1341	it6505_write(it6505, REG_IEC958_STS0, reg_val: it6505->audio.type << 1);
1342	it6505_write(it6505, REG_IEC958_STS1, reg_val: 0x00);
1343	it6505_write(it6505, REG_IEC958_STS2, reg_val: 0x00);
1344	it6505_write(it6505, REG_IEC958_STS3, reg_val: sample_rate);
1345	it6505_write(it6505, REG_IEC958_STS4, reg_val: (~sample_rate << 4) |
1346	audio_word_length_map[it6505->audio.word_length]);
1347	}
1348
1349	static void it6505_setup_audio_format(struct it6505 *it6505)
1350	{
1351	/* I2S MODE */
1352	it6505_write(it6505, REG_AUDIO_FMT,
1353	reg_val: (it6505->audio.word_length << 5) |
1354	(it6505->audio.i2s_data_sequence << 4) |
1355	(it6505->audio.i2s_ws_channel << 3) |
1356	(it6505->audio.i2s_data_delay << 2) |
1357	(it6505->audio.i2s_justified << 1) |
1358	it6505->audio.i2s_input_format);
1359	if (it6505->audio.select == SPDIF) {
1360	it6505_write(it6505, REG_AUDIO_FIFO_SEL, reg_val: 0x00);
1361	/* 0x30 = 128*FS */
1362	it6505_set_bits(it6505, REG_AUX_OPT, mask: 0xF0, value: 0x30);
1363	} else {
1364	it6505_write(it6505, REG_AUDIO_FIFO_SEL, reg_val: 0xE4);
1365	}
1366
1367	it6505_write(it6505, REG_AUDIO_CTRL0, reg_val: 0x20);
1368	it6505_write(it6505, REG_AUDIO_CTRL1, reg_val: 0x00);
1369	}
1370
1371	static void it6505_enable_audio_source(struct it6505 *it6505)
1372	{
1373	unsigned int audio_source_count;
1374
1375	audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1376	- 1;
1377
1378	audio_source_count |= it6505->audio.select << 4;
1379
1380	it6505_write(it6505, REG_AUDIO_SRC_CTRL, reg_val: audio_source_count);
1381	}
1382
1383	static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1384	{
1385	struct device *dev = it6505->dev;
1386	u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1387
1388	DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1389	audio_info_ca[it6505->audio.channel_count - 1]);
1390
1391	it6505_write(it6505, REG_AUD_INFOFRAM_DB1, reg_val: it6505->audio.channel_count
1392	- 1);
1393	it6505_write(it6505, REG_AUD_INFOFRAM_DB2, reg_val: 0x00);
1394	it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1395	reg_val: audio_info_ca[it6505->audio.channel_count - 1]);
1396	it6505_write(it6505, REG_AUD_INFOFRAM_DB4, reg_val: 0x00);
1397	it6505_write(it6505, REG_AUD_INFOFRAM_SUM, reg_val: 0x00);
1398
1399	/* Enable Audio InfoFrame */
1400	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1401	EN_AUD_CTRL_PKT);
1402	}
1403
1404	static void it6505_disable_audio(struct it6505 *it6505)
1405	{
1406	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1407	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, value: 0x00);
1408	it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, value: 0x00);
1409	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1410	}
1411
1412	static void it6505_enable_audio(struct it6505 *it6505)
1413	{
1414	struct device *dev = it6505->dev;
1415	int regbe;
1416
1417	DRM_DEV_DEBUG_DRIVER(dev, "start");
1418	it6505_disable_audio(it6505);
1419
1420	it6505_setup_audio_channel_status(it6505);
1421	it6505_setup_audio_format(it6505);
1422	it6505_enable_audio_source(it6505);
1423	it6505_enable_audio_infoframe(it6505);
1424
1425	it6505_write(it6505, REG_AUDIO_N_0_7, reg_val: 0x00);
1426	it6505_write(it6505, REG_AUDIO_N_8_15, reg_val: 0x80);
1427	it6505_write(it6505, REG_AUDIO_N_16_23, reg_val: 0x00);
1428
1429	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1430	AUDIO_FIFO_RESET);
1431	it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, value: 0x00);
1432	it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, value: 0x00);
1433	regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1434	DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1435	regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1436	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, value: 0x00);
1437	}
1438
1439	static bool it6505_use_step_train_check(struct it6505 *it6505)
1440	{
1441	if (it6505->link.revision >= 0x12)
1442	return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1443
1444	return true;
1445	}
1446
1447	static void it6505_parse_link_capabilities(struct it6505 *it6505)
1448	{
1449	struct device *dev = it6505->dev;
1450	struct it6505_drm_dp_link *link = &it6505->link;
1451	int bcaps;
1452
1453	if (it6505->dpcd[0] == 0) {
1454	dev_err(dev, "DPCD is not initialized");
1455	return;
1456	}
1457
1458	memset(link, 0, sizeof(*link));
1459
1460	link->revision = it6505->dpcd[0];
1461	link->rate = drm_dp_bw_code_to_link_rate(link_bw: it6505->dpcd[1]);
1462	link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1463
1464	if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1465	link->capabilities = DP_ENHANCED_FRAME_CAP;
1466
1467	DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1468	link->revision >> 4, link->revision & 0x0F);
1469
1470	DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1471	link->rate / 100000, link->rate / 1000 % 100);
1472
1473	it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link_rate: link->rate);
1474	DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1475	it6505->link_rate_bw_code);
1476	it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1477	MAX_LINK_RATE);
1478
1479	it6505->lane_count = link->num_lanes;
1480	DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1481	it6505->lane_count);
1482	it6505->lane_count = min_t(int, it6505->lane_count,
1483	it6505->max_lane_count);
1484
1485	it6505->branch_device = drm_dp_is_branch(dpcd: it6505->dpcd);
1486	DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1487	it6505->branch_device ? "" : "Not ");
1488
1489	it6505->enable_enhanced_frame = link->capabilities;
1490	DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1491	it6505->enable_enhanced_frame ? "" : "Not ");
1492
1493	it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1494	DP_MAX_DOWNSPREAD_0_5);
1495	DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1496	it6505->enable_ssc ? "0.5" : "0",
1497	it6505->enable_ssc ? "" : "Not ");
1498
1499	it6505->step_train = it6505_use_step_train_check(it6505);
1500	if (it6505->step_train)
1501	DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1502
1503	bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1504	DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1505	if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1506	it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1507	DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1508	it6505->is_repeater ? "repeater" :
1509	"receiver");
1510	} else {
1511	DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1512	it6505->hdcp_desired = false;
1513	}
1514	DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1515	it6505->hdcp_desired ? "desired" : "undesired");
1516	}
1517
1518	static void it6505_setup_ssc(struct it6505 *it6505)
1519	{
1520	it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1521	value: it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1522	if (it6505->enable_ssc) {
1523	it6505_write(it6505, REG_SSC_CTRL0, reg_val: 0x9E);
1524	it6505_write(it6505, REG_SSC_CTRL1, reg_val: 0x1C);
1525	it6505_write(it6505, REG_SSC_CTRL2, reg_val: 0x42);
1526	it6505_write(it6505, REG_SP_CTRL0, reg_val: 0x07);
1527	it6505_write(it6505, REG_IP_CTRL1, reg_val: 0x29);
1528	it6505_write(it6505, REG_IP_CTRL2, reg_val: 0x03);
1529	/* Stamp Interrupt Step */
1530	it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1531	value: 0x10);
1532	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1533	DP_SPREAD_AMP_0_5);
1534	} else {
1535	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, datain: 0x00);
1536	it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1537	value: 0x00);
1538	}
1539	}
1540
1541	static inline void it6505_link_rate_setup(struct it6505 *it6505)
1542	{
1543	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1544	value: (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1545	it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1546	value: (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1547	}
1548
1549	static void it6505_lane_count_setup(struct it6505 *it6505)
1550	{
1551	it6505_get_extcon_property(it6505);
1552	it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1553	value: it6505->lane_swap ? LANE_SWAP : 0x00);
1554	it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1555	value: (it6505->lane_count - 1) << 1);
1556	}
1557
1558	static void it6505_link_training_setup(struct it6505 *it6505)
1559	{
1560	struct device *dev = it6505->dev;
1561
1562	if (it6505->enable_enhanced_frame)
1563	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1564	ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1565
1566	it6505_link_rate_setup(it6505);
1567	it6505_lane_count_setup(it6505);
1568	it6505_setup_ssc(it6505);
1569	DRM_DEV_DEBUG_DRIVER(dev,
1570	"%s, %d lanes, %sable ssc, %sable enhanced frame",
1571	it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1572	it6505->lane_count,
1573	it6505->enable_ssc ? "en" : "dis",
1574	it6505->enable_enhanced_frame ? "en" : "dis");
1575	}
1576
1577	static bool it6505_link_start_auto_train(struct it6505 *it6505)
1578	{
1579	int timeout = 500, link_training_state;
1580	bool state = false;
1581
1582	mutex_lock(&it6505->aux_lock);
1583	it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1584	FORCE_CR_DONE | FORCE_EQ_DONE, value: 0x00);
1585	it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1586	it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1587
1588	while (timeout > 0) {
1589	usleep_range(min: 1000, max: 2000);
1590	link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1591
1592	if (link_training_state > 0 &&
1593	(link_training_state & LINK_STATE_NORP)) {
1594	state = true;
1595	goto unlock;
1596	}
1597
1598	timeout--;
1599	}
1600	unlock:
1601	mutex_unlock(lock: &it6505->aux_lock);
1602
1603	return state;
1604	}
1605
1606	static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1607	{
1608	u8 values[2];
1609	int err;
1610	struct drm_dp_aux *aux = &it6505->aux;
1611
1612	values[0] = it6505->link_rate_bw_code;
1613	values[1] = it6505->lane_count;
1614
1615	if (it6505->enable_enhanced_frame)
1616	values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1617
1618	err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, buffer: values, size: sizeof(values));
1619	if (err < 0)
1620	return err;
1621
1622	return 0;
1623	}
1624
1625	static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1626	{
1627	return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1628	}
1629
1630	static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1631	{
1632	return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1633	}
1634
1635	static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1636	u8 lane_count)
1637	{
1638	u8 i;
1639
1640	for (i = 0; i < lane_count; i++) {
1641	if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1642	return true;
1643	}
1644
1645	return false;
1646	}
1647
1648	static bool
1649	step_train_lane_voltage_para_set(struct it6505 *it6505,
1650	struct it6505_step_train_para
1651	*lane_voltage_pre_emphasis,
1652	u8 *lane_voltage_pre_emphasis_set)
1653	{
1654	u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1655	u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1656	u8 i;
1657
1658	for (i = 0; i < it6505->lane_count; i++) {
1659	voltage_swing[i] &= 0x03;
1660	lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1661	if (it6505_check_voltage_swing_max(lane_voltage_swing_pre_emphasis: voltage_swing[i]))
1662	lane_voltage_pre_emphasis_set[i] |=
1663	DP_TRAIN_MAX_SWING_REACHED;
1664
1665	pre_emphasis[i] &= 0x03;
1666	lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1667	<< DP_TRAIN_PRE_EMPHASIS_SHIFT;
1668	if (it6505_check_pre_emphasis_max(lane_voltage_swing_pre_emphasis: pre_emphasis[i]))
1669	lane_voltage_pre_emphasis_set[i] |=
1670	DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1671	it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1672	datain: lane_voltage_pre_emphasis_set[i]);
1673
1674	if (lane_voltage_pre_emphasis_set[i] !=
1675	it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1676	return false;
1677	}
1678
1679	return true;
1680	}
1681
1682	static bool
1683	it6505_step_cr_train(struct it6505 *it6505,
1684	struct it6505_step_train_para *lane_voltage_pre_emphasis)
1685	{
1686	u8 loop_count = 0, i = 0, j;
1687	u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1688	u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1689	int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1690	const struct drm_dp_aux *aux = &it6505->aux;
1691
1692	it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1693	datain: it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1694	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1695	DP_TRAINING_PATTERN_1);
1696
1697	while (loop_count < 5 && i < 10) {
1698	i++;
1699	if (!step_train_lane_voltage_para_set(it6505,
1700	lane_voltage_pre_emphasis,
1701	lane_voltage_pre_emphasis_set: lane_level_config))
1702	continue;
1703	drm_dp_link_train_clock_recovery_delay(aux, dpcd: it6505->dpcd);
1704	drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
1705
1706	if (drm_dp_clock_recovery_ok(link_status, lane_count: it6505->lane_count)) {
1707	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1708	FORCE_CR_DONE);
1709	return true;
1710	}
1711	DRM_DEV_DEBUG_DRIVER(it6505->dev, "cr not done");
1712
1713	if (it6505_check_max_voltage_swing_reached(lane_voltage_swing: lane_level_config,
1714	lane_count: it6505->lane_count))
1715	goto cr_train_fail;
1716
1717	for (j = 0; j < it6505->lane_count; j++) {
1718	lane_voltage_pre_emphasis->voltage_swing[j] =
1719	drm_dp_get_adjust_request_voltage(link_status,
1720	lane: j) >>
1721	DP_TRAIN_VOLTAGE_SWING_SHIFT;
1722	lane_voltage_pre_emphasis->pre_emphasis[j] =
1723	drm_dp_get_adjust_request_pre_emphasis(link_status,
1724	lane: j) >>
1725	DP_TRAIN_PRE_EMPHASIS_SHIFT;
1726	if (voltage_swing_adjust ==
1727	lane_voltage_pre_emphasis->voltage_swing[j] &&
1728	pre_emphasis_adjust ==
1729	lane_voltage_pre_emphasis->pre_emphasis[j]) {
1730	loop_count++;
1731	continue;
1732	}
1733
1734	voltage_swing_adjust =
1735	lane_voltage_pre_emphasis->voltage_swing[j];
1736	pre_emphasis_adjust =
1737	lane_voltage_pre_emphasis->pre_emphasis[j];
1738	loop_count = 0;
1739
1740	if (voltage_swing_adjust + pre_emphasis_adjust >
1741	MAX_EQ_LEVEL)
1742	lane_voltage_pre_emphasis->voltage_swing[j] =
1743	MAX_EQ_LEVEL -
1744	lane_voltage_pre_emphasis
1745	->pre_emphasis[j];
1746	}
1747	}
1748
1749	cr_train_fail:
1750	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1751	DP_TRAINING_PATTERN_DISABLE);
1752
1753	return false;
1754	}
1755
1756	static bool
1757	it6505_step_eq_train(struct it6505 *it6505,
1758	struct it6505_step_train_para *lane_voltage_pre_emphasis)
1759	{
1760	u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1761	u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1762	const struct drm_dp_aux *aux = &it6505->aux;
1763
1764	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1765	DP_TRAINING_PATTERN_2);
1766
1767	while (loop_count < 6) {
1768	loop_count++;
1769
1770	if (!step_train_lane_voltage_para_set(it6505,
1771	lane_voltage_pre_emphasis,
1772	lane_voltage_pre_emphasis_set: lane_level_config))
1773	continue;
1774
1775	drm_dp_link_train_channel_eq_delay(aux, dpcd: it6505->dpcd);
1776	drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
1777
1778	if (!drm_dp_clock_recovery_ok(link_status, lane_count: it6505->lane_count))
1779	goto eq_train_fail;
1780
1781	if (drm_dp_channel_eq_ok(link_status, lane_count: it6505->lane_count)) {
1782	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1783	DP_TRAINING_PATTERN_DISABLE);
1784	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1785	FORCE_EQ_DONE);
1786	return true;
1787	}
1788	DRM_DEV_DEBUG_DRIVER(it6505->dev, "eq not done");
1789
1790	for (i = 0; i < it6505->lane_count; i++) {
1791	lane_voltage_pre_emphasis->voltage_swing[i] =
1792	drm_dp_get_adjust_request_voltage(link_status,
1793	lane: i) >>
1794	DP_TRAIN_VOLTAGE_SWING_SHIFT;
1795	lane_voltage_pre_emphasis->pre_emphasis[i] =
1796	drm_dp_get_adjust_request_pre_emphasis(link_status,
1797	lane: i) >>
1798	DP_TRAIN_PRE_EMPHASIS_SHIFT;
1799
1800	if (lane_voltage_pre_emphasis->voltage_swing[i] +
1801	lane_voltage_pre_emphasis->pre_emphasis[i] >
1802	MAX_EQ_LEVEL)
1803	lane_voltage_pre_emphasis->voltage_swing[i] =
1804	0x03 - lane_voltage_pre_emphasis
1805	->pre_emphasis[i];
1806	}
1807	}
1808
1809	eq_train_fail:
1810	it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1811	DP_TRAINING_PATTERN_DISABLE);
1812	return false;
1813	}
1814
1815	static bool it6505_link_start_step_train(struct it6505 *it6505)
1816	{
1817	int err;
1818	struct it6505_step_train_para lane_voltage_pre_emphasis = {
1819	.voltage_swing = { 0 },
1820	.pre_emphasis = { 0 },
1821	};
1822
1823	DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
1824	err = it6505_drm_dp_link_configure(it6505);
1825
1826	if (err < 0)
1827	return false;
1828	if (!it6505_step_cr_train(it6505, lane_voltage_pre_emphasis: &lane_voltage_pre_emphasis))
1829	return false;
1830	if (!it6505_step_eq_train(it6505, lane_voltage_pre_emphasis: &lane_voltage_pre_emphasis))
1831	return false;
1832	return true;
1833	}
1834
1835	static bool it6505_get_video_status(struct it6505 *it6505)
1836	{
1837	int reg_0d;
1838
1839	reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1840
1841	if (reg_0d < 0)
1842	return false;
1843
1844	return reg_0d & VIDEO_STB;
1845	}
1846
1847	static void it6505_reset_hdcp(struct it6505 *it6505)
1848	{
1849	it6505->hdcp_status = HDCP_AUTH_IDLE;
1850	/* Disable CP_Desired */
1851	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, value: 0x00);
1852	it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1853	}
1854
1855	static void it6505_start_hdcp(struct it6505 *it6505)
1856	{
1857	struct device *dev = it6505->dev;
1858
1859	DRM_DEV_DEBUG_DRIVER(dev, "start");
1860	it6505_reset_hdcp(it6505);
1861	queue_delayed_work(wq: system_wq, dwork: &it6505->hdcp_work,
1862	delay: msecs_to_jiffies(m: 2400));
1863	}
1864
1865	static void it6505_stop_hdcp(struct it6505 *it6505)
1866	{
1867	it6505_reset_hdcp(it6505);
1868	cancel_delayed_work(dwork: &it6505->hdcp_work);
1869	}
1870
1871	static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1872	{
1873	int i, ones = 0;
1874
1875	/* KSV has 20 1's and 20 0's */
1876	for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1877	ones += hweight8(ksv[i]);
1878	if (ones != 20)
1879	return false;
1880	return true;
1881	}
1882
1883	static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1884	{
1885	struct device *dev = it6505->dev;
1886	u8 hdcp_bcaps;
1887
1888	it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, value: 0x00);
1889	/* Disable CP_Desired */
1890	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, value: 0x00);
1891
1892	usleep_range(min: 1000, max: 1500);
1893	hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1894	DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1895	hdcp_bcaps);
1896
1897	if (!hdcp_bcaps)
1898	return;
1899
1900	/* clear the repeater List Chk Done and fail bit */
1901	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1902	HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1903	value: 0x00);
1904
1905	/* Enable An Generator */
1906	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1907	/* delay1ms(10);*/
1908	usleep_range(min: 10000, max: 15000);
1909	/* Stop An Generator */
1910	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, value: 0x00);
1911
1912	it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1913
1914	it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1915	HDCP_TRIGGER_START);
1916
1917	it6505->hdcp_status = HDCP_AUTH_GOING;
1918	}
1919
1920	static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1921	unsigned int size, u8 *output_av)
1922	{
1923	struct shash_desc *desc;
1924	struct crypto_shash *tfm;
1925	int err;
1926	struct device *dev = it6505->dev;
1927
1928	tfm = crypto_alloc_shash(alg_name: "sha1", type: 0, mask: 0);
1929	if (IS_ERR(ptr: tfm)) {
1930	dev_err(dev, "crypto_alloc_shash sha1 failed");
1931	return PTR_ERR(ptr: tfm);
1932	}
1933	desc = kzalloc(size: sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1934	if (!desc) {
1935	crypto_free_shash(tfm);
1936	return -ENOMEM;
1937	}
1938
1939	desc->tfm = tfm;
1940	err = crypto_shash_digest(desc, data: sha1_input, len: size, out: output_av);
1941	if (err)
1942	dev_err(dev, "crypto_shash_digest sha1 failed");
1943
1944	crypto_free_shash(tfm);
1945	kfree(objp: desc);
1946	return err;
1947	}
1948
1949	static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1950	{
1951	struct device *dev = it6505->dev;
1952	u8 binfo[2];
1953	int down_stream_count, i, err, msg_count = 0;
1954
1955	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, dpcd: binfo,
1956	ARRAY_SIZE(binfo));
1957
1958	if (err < 0) {
1959	dev_err(dev, "Read binfo value Fail");
1960	return err;
1961	}
1962
1963	down_stream_count = binfo[0] & 0x7F;
1964	DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1965	binfo);
1966
1967	if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1968	dev_err(dev, "HDCP max cascade device exceed");
1969	return 0;
1970	}
1971
1972	if (!down_stream_count ||
1973	down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1974	dev_err(dev, "HDCP down stream count Error %d",
1975	down_stream_count);
1976	return 0;
1977	}
1978
1979	for (i = 0; i < down_stream_count; i++) {
1980	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1981	(i % 3) * DRM_HDCP_KSV_LEN,
1982	dpcd: sha1_input + msg_count,
1983	DRM_HDCP_KSV_LEN);
1984
1985	if (err < 0)
1986	return err;
1987
1988	msg_count += 5;
1989	}
1990
1991	it6505->hdcp_down_stream_count = down_stream_count;
1992	sha1_input[msg_count++] = binfo[0];
1993	sha1_input[msg_count++] = binfo[1];
1994
1995	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
1996	HDCP_EN_M0_READ);
1997
1998	err = regmap_bulk_read(map: it6505->regmap, REG_M0_0_7,
1999	val: sha1_input + msg_count, val_count: 8);
2000
2001	it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, value: 0x00);
2002
2003	if (err < 0) {
2004	dev_err(dev, " Warning, Read M value Fail");
2005	return err;
2006	}
2007
2008	msg_count += 8;
2009
2010	return msg_count;
2011	}
2012
2013	static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2014	{
2015	struct device *dev = it6505->dev;
2016	u8 av[5][4], bv[5][4];
2017	int i, err;
2018
2019	i = it6505_setup_sha1_input(it6505, sha1_input: it6505->sha1_input);
2020	if (i <= 0) {
2021	dev_err(dev, "SHA-1 Input length error %d", i);
2022	return false;
2023	}
2024
2025	it6505_sha1_digest(it6505, sha1_input: it6505->sha1_input, size: i, output_av: (u8 *)av);
2026
2027	err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), dpcd: (u8 *)bv,
2028	num: sizeof(bv));
2029
2030	if (err < 0) {
2031	dev_err(dev, "Read V' value Fail");
2032	return false;
2033	}
2034
2035	for (i = 0; i < 5; i++)
2036	if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2037	bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2038	return false;
2039
2040	DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2041	return true;
2042	}
2043
2044	static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2045	{
2046	struct it6505 *it6505 = container_of(work, struct it6505,
2047	hdcp_wait_ksv_list);
2048	struct device *dev = it6505->dev;
2049	unsigned int timeout = 5000;
2050	u8 bstatus = 0;
2051	bool ksv_list_check;
2052
2053	timeout /= 20;
2054	while (timeout > 0) {
2055	if (!it6505_get_sink_hpd_status(it6505))
2056	return;
2057
2058	bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2059
2060	if (bstatus & DP_BSTATUS_READY)
2061	break;
2062
2063	msleep(msecs: 20);
2064	timeout--;
2065	}
2066
2067	if (timeout == 0) {
2068	DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2069	goto timeout;
2070	}
2071
2072	ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2073	DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2074	ksv_list_check ? "pass" : "fail");
2075	if (ksv_list_check) {
2076	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2077	HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2078	return;
2079	}
2080	timeout:
2081	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2082	HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2083	HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2084	}
2085
2086	static void it6505_hdcp_work(struct work_struct *work)
2087	{
2088	struct it6505 *it6505 = container_of(work, struct it6505,
2089	hdcp_work.work);
2090	struct device *dev = it6505->dev;
2091	int ret;
2092	u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2093
2094	DRM_DEV_DEBUG_DRIVER(dev, "start");
2095
2096	if (!it6505_get_sink_hpd_status(it6505))
2097	return;
2098
2099	ret = drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
2100	DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2101	(int)sizeof(link_status), link_status);
2102
2103	if (ret < 0 || !drm_dp_channel_eq_ok(link_status, lane_count: it6505->lane_count) ||
2104	!it6505_get_video_status(it6505)) {
2105	DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2106	return;
2107	}
2108
2109	ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, dpcd: it6505->bksvs,
2110	ARRAY_SIZE(it6505->bksvs));
2111	if (ret < 0) {
2112	dev_err(dev, "fail to get bksv ret: %d", ret);
2113	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2114	HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2115	}
2116
2117	DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2118	(int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2119
2120	if (!it6505_hdcp_is_ksv_valid(ksv: it6505->bksvs)) {
2121	dev_err(dev, "Display Port bksv not valid");
2122	it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2123	HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2124	}
2125
2126	it6505_hdcp_part1_auth(it6505);
2127	}
2128
2129	static void it6505_show_hdcp_info(struct it6505 *it6505)
2130	{
2131	struct device *dev = it6505->dev;
2132	int i;
2133	u8 *sha1 = it6505->sha1_input;
2134
2135	DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2136	it6505->hdcp_status, it6505->is_repeater);
2137	DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2138	(int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2139
2140	if (it6505->is_repeater) {
2141	DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2142	it6505->hdcp_down_stream_count);
2143	DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2144	(int)ARRAY_SIZE(it6505->sha1_input),
2145	it6505->sha1_input);
2146	for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2147	DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2148	DRM_HDCP_KSV_LEN, sha1);
2149	sha1 += DRM_HDCP_KSV_LEN;
2150	}
2151	DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2152	sha1, sha1 + 2);
2153	}
2154	}
2155
2156	static void it6505_stop_link_train(struct it6505 *it6505)
2157	{
2158	it6505->link_state = LINK_IDLE;
2159	cancel_work_sync(work: &it6505->link_works);
2160	it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2161	}
2162
2163	static void it6505_link_train_ok(struct it6505 *it6505)
2164	{
2165	struct device *dev = it6505->dev;
2166
2167	it6505->link_state = LINK_OK;
2168	/* disalbe mute enable avi info frame */
2169	it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, value: 0x00);
2170	it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2171	EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2172
2173	if (it6505_audio_input(it6505)) {
2174	DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2175	it6505_enable_audio(it6505);
2176	}
2177
2178	if (it6505->hdcp_desired)
2179	it6505_start_hdcp(it6505);
2180	}
2181
2182	static void it6505_link_step_train_process(struct it6505 *it6505)
2183	{
2184	struct device *dev = it6505->dev;
2185	int ret, i, step_retry = 3;
2186
2187	DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2188
2189	if (it6505->sink_count == 0) {
2190	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2191	it6505->sink_count);
2192	it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2193	FORCE_EQ_DONE);
2194	return;
2195	}
2196
2197	if (!it6505->step_train) {
2198	DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2199	return;
2200	}
2201
2202	/* step training start here */
2203	for (i = 0; i < step_retry; i++) {
2204	it6505_link_reset_step_train(it6505);
2205	ret = it6505_link_start_step_train(it6505);
2206	DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2207	ret ? "pass" : "failed", i + 1);
2208	if (ret) {
2209	it6505_link_train_ok(it6505);
2210	return;
2211	}
2212	}
2213
2214	DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2215	it6505->link_state = LINK_IDLE;
2216	it6505_video_reset(it6505);
2217	}
2218
2219	static void it6505_link_training_work(struct work_struct *work)
2220	{
2221	struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2222	struct device *dev = it6505->dev;
2223	int ret;
2224
2225	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2226	it6505->sink_count);
2227
2228	if (!it6505_get_sink_hpd_status(it6505))
2229	return;
2230
2231	it6505_link_training_setup(it6505);
2232	it6505_reset_hdcp(it6505);
2233	it6505_aux_reset(it6505);
2234
2235	if (it6505->auto_train_retry < 1) {
2236	it6505_link_step_train_process(it6505);
2237	return;
2238	}
2239
2240	ret = it6505_link_start_auto_train(it6505);
2241	DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2242	ret ? "pass" : "failed", it6505->auto_train_retry);
2243	it6505->auto_train_retry--;
2244
2245	if (ret) {
2246	it6505_link_train_ok(it6505);
2247	return;
2248	}
2249
2250	it6505_dump(it6505);
2251	}
2252
2253	static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2254	{
2255	enum drm_connector_status status = it6505->connector_status;
2256
2257	if (it6505->plugged_cb && it6505->codec_dev)
2258	it6505->plugged_cb(it6505->codec_dev,
2259	status == connector_status_connected);
2260	}
2261
2262	static void it6505_remove_edid(struct it6505 *it6505)
2263	{
2264	kfree(objp: it6505->cached_edid);
2265	it6505->cached_edid = NULL;
2266	}
2267
2268	static int it6505_process_hpd_irq(struct it6505 *it6505)
2269	{
2270	struct device *dev = it6505->dev;
2271	int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2272	u8 link_status[DP_LINK_STATUS_SIZE];
2273
2274	if (!it6505_get_sink_hpd_status(it6505)) {
2275	DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2276	it6505->sink_count = 0;
2277	return 0;
2278	}
2279
2280	ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2281	if (ret < 0)
2282	return ret;
2283
2284	dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2285	DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2286	dpcd_sink_count, it6505->sink_count);
2287
2288	if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2289	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2290	it6505->sink_count = dpcd_sink_count;
2291	it6505_reset_logic(it6505);
2292	it6505_int_mask_enable(it6505);
2293	it6505_init(it6505);
2294	it6505_remove_edid(it6505);
2295	return 0;
2296	}
2297
2298	dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2299	if (dp_irq_vector < 0)
2300	return dp_irq_vector;
2301
2302	DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2303
2304	if (dp_irq_vector & DP_CP_IRQ) {
2305	it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2306	HDCP_TRIGGER_CPIRQ);
2307
2308	bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2309	if (bstatus < 0)
2310	return bstatus;
2311
2312	DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2313	}
2314
2315	ret = drm_dp_dpcd_read_link_status(aux: &it6505->aux, status: link_status);
2316	if (ret < 0) {
2317	dev_err(dev, "Fail to read link status ret: %d", ret);
2318	return ret;
2319	}
2320
2321	DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2322	(int)ARRAY_SIZE(link_status), link_status);
2323
2324	if (!drm_dp_channel_eq_ok(link_status, lane_count: it6505->lane_count)) {
2325	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2326	it6505_video_reset(it6505);
2327	}
2328
2329	return 0;
2330	}
2331
2332	static void it6505_irq_hpd(struct it6505 *it6505)
2333	{
2334	struct device *dev = it6505->dev;
2335	int dp_sink_count;
2336
2337	it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2338	DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2339	it6505->hpd_state ? "high" : "low");
2340
2341	if (it6505->hpd_state) {
2342	wait_for_completion_timeout(x: &it6505->extcon_completion,
2343	timeout: msecs_to_jiffies(m: 1000));
2344	it6505_aux_on(it6505);
2345	if (it6505->dpcd[0] == 0) {
2346	it6505_get_dpcd(it6505, DP_DPCD_REV, dpcd: it6505->dpcd,
2347	ARRAY_SIZE(it6505->dpcd));
2348	it6505_variable_config(it6505);
2349	it6505_parse_link_capabilities(it6505);
2350	}
2351	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2352
2353	it6505_drm_dp_link_set_power(aux: &it6505->aux, link: &it6505->link,
2354	DP_SET_POWER_D0);
2355	dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2356	it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2357
2358	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2359	it6505->sink_count);
2360
2361	it6505_lane_termination_on(it6505);
2362	it6505_lane_power_on(it6505);
2363
2364	/*
2365	* for some dongle which issue HPD_irq
2366	* when sink count change from 0->1
2367	* it6505 not able to receive HPD_IRQ
2368	* if HW never go into trainig done
2369	*/
2370
2371	if (it6505->branch_device && it6505->sink_count == 0)
2372	schedule_work(work: &it6505->link_works);
2373
2374	if (!it6505_get_video_status(it6505))
2375	it6505_video_reset(it6505);
2376	} else {
2377	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2378	it6505_remove_edid(it6505);
2379
2380	if (it6505->hdcp_desired)
2381	it6505_stop_hdcp(it6505);
2382
2383	it6505_video_disable(it6505);
2384	it6505_disable_audio(it6505);
2385	it6505_stop_link_train(it6505);
2386	it6505_lane_off(it6505);
2387	it6505_link_reset_step_train(it6505);
2388	}
2389
2390	if (it6505->bridge.dev)
2391	drm_helper_hpd_irq_event(dev: it6505->bridge.dev);
2392	}
2393
2394	static void it6505_irq_hpd_irq(struct it6505 *it6505)
2395	{
2396	struct device *dev = it6505->dev;
2397
2398	DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2399
2400	if (it6505_process_hpd_irq(it6505) < 0)
2401	DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2402	}
2403
2404	static void it6505_irq_scdt(struct it6505 *it6505)
2405	{
2406	struct device *dev = it6505->dev;
2407	bool data;
2408
2409	data = it6505_get_video_status(it6505);
2410	DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2411	data ? "stable" : "unstable");
2412	it6505_calc_video_info(it6505);
2413	it6505_link_reset_step_train(it6505);
2414
2415	if (data)
2416	schedule_work(work: &it6505->link_works);
2417	}
2418
2419	static void it6505_irq_hdcp_done(struct it6505 *it6505)
2420	{
2421	struct device *dev = it6505->dev;
2422
2423	DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2424	it6505->hdcp_status = HDCP_AUTH_DONE;
2425	it6505_show_hdcp_info(it6505);
2426	}
2427
2428	static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2429	{
2430	struct device *dev = it6505->dev;
2431
2432	DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2433	it6505->hdcp_status = HDCP_AUTH_IDLE;
2434	it6505_show_hdcp_info(it6505);
2435	it6505_start_hdcp(it6505);
2436	}
2437
2438	static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2439	{
2440	struct device *dev = it6505->dev;
2441
2442	DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2443	}
2444
2445	static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2446	{
2447	struct device *dev = it6505->dev;
2448
2449	DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2450	schedule_work(work: &it6505->hdcp_wait_ksv_list);
2451	}
2452
2453	static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2454	{
2455	struct device *dev = it6505->dev;
2456
2457	DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2458
2459	if (it6505_audio_input(it6505))
2460	it6505_enable_audio(it6505);
2461	}
2462
2463	static void it6505_irq_link_train_fail(struct it6505 *it6505)
2464	{
2465	struct device *dev = it6505->dev;
2466
2467	DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2468	schedule_work(work: &it6505->link_works);
2469	}
2470
2471	static void it6505_irq_video_fifo_error(struct it6505 *it6505)
2472	{
2473	struct device *dev = it6505->dev;
2474
2475	DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2476	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2477	flush_work(work: &it6505->link_works);
2478	it6505_stop_hdcp(it6505);
2479	it6505_video_reset(it6505);
2480	}
2481
2482	static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)
2483	{
2484	struct device *dev = it6505->dev;
2485
2486	DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");
2487	it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2488	flush_work(work: &it6505->link_works);
2489	it6505_stop_hdcp(it6505);
2490	it6505_video_reset(it6505);
2491	}
2492
2493	static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2494	{
2495	return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2496	}
2497
2498	static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2499	{
2500	struct it6505 *it6505 = data;
2501	struct device *dev = it6505->dev;
2502	static const struct {
2503	int bit;
2504	void (*handler)(struct it6505 *it6505);
2505	} irq_vec[] = {
2506	{ BIT_INT_HPD, it6505_irq_hpd },
2507	{ BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2508	{ BIT_INT_SCDT, it6505_irq_scdt },
2509	{ BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2510	{ BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2511	{ BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2512	{ BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2513	{ BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2514	{ BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2515	{ BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2516	{ BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2517	};
2518	int int_status[3], i;
2519
2520	if (it6505->enable_drv_hold || !it6505->powered)
2521	return IRQ_HANDLED;
2522
2523	pm_runtime_get_sync(dev);
2524
2525	int_status[0] = it6505_read(it6505, INT_STATUS_01);
2526	int_status[1] = it6505_read(it6505, INT_STATUS_02);
2527	int_status[2] = it6505_read(it6505, INT_STATUS_03);
2528
2529	it6505_write(it6505, INT_STATUS_01, reg_val: int_status[0]);
2530	it6505_write(it6505, INT_STATUS_02, reg_val: int_status[1]);
2531	it6505_write(it6505, INT_STATUS_03, reg_val: int_status[2]);
2532
2533	DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2534	DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2535	DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2536	it6505_debug_print(it6505, REG_SYSTEM_STS, prefix: "");
2537
2538	if (it6505_test_bit(bit: irq_vec[0].bit, addr: (unsigned int *)int_status))
2539	irq_vec[0].handler(it6505);
2540
2541	if (it6505->hpd_state) {
2542	for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2543	if (it6505_test_bit(bit: irq_vec[i].bit, addr: (unsigned int *)int_status))
2544	irq_vec[i].handler(it6505);
2545	}
2546	}
2547
2548	pm_runtime_put_sync(dev);
2549
2550	return IRQ_HANDLED;
2551	}
2552
2553	static int it6505_poweron(struct it6505 *it6505)
2554	{
2555	struct device *dev = it6505->dev;
2556	struct it6505_platform_data *pdata = &it6505->pdata;
2557	int err;
2558
2559	DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2560
2561	if (it6505->powered) {
2562	DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2563	return 0;
2564	}
2565
2566	if (pdata->pwr18) {
2567	err = regulator_enable(regulator: pdata->pwr18);
2568	if (err) {
2569	DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2570	err);
2571	return err;
2572	}
2573	}
2574
2575	if (pdata->ovdd) {
2576	/* time interval between IVDD and OVDD at least be 1ms */
2577	usleep_range(min: 1000, max: 2000);
2578	err = regulator_enable(regulator: pdata->ovdd);
2579	if (err) {
2580	regulator_disable(regulator: pdata->pwr18);
2581	return err;
2582	}
2583	}
2584	/* time interval between OVDD and SYSRSTN at least be 10ms */
2585	if (pdata->gpiod_reset) {
2586	usleep_range(min: 10000, max: 20000);
2587	gpiod_set_value_cansleep(desc: pdata->gpiod_reset, value: 0);
2588	usleep_range(min: 1000, max: 2000);
2589	gpiod_set_value_cansleep(desc: pdata->gpiod_reset, value: 1);
2590	usleep_range(min: 10000, max: 20000);
2591	}
2592
2593	it6505->powered = true;
2594	it6505_reset_logic(it6505);
2595	it6505_int_mask_enable(it6505);
2596	it6505_init(it6505);
2597	it6505_lane_off(it6505);
2598
2599	return 0;
2600	}
2601
2602	static int it6505_poweroff(struct it6505 *it6505)
2603	{
2604	struct device *dev = it6505->dev;
2605	struct it6505_platform_data *pdata = &it6505->pdata;
2606	int err;
2607
2608	DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2609
2610	if (!it6505->powered) {
2611	DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2612	return 0;
2613	}
2614
2615	if (pdata->gpiod_reset)
2616	gpiod_set_value_cansleep(desc: pdata->gpiod_reset, value: 0);
2617
2618	if (pdata->pwr18) {
2619	err = regulator_disable(regulator: pdata->pwr18);
2620	if (err)
2621	return err;
2622	}
2623
2624	if (pdata->ovdd) {
2625	err = regulator_disable(regulator: pdata->ovdd);
2626	if (err)
2627	return err;
2628	}
2629
2630	it6505->powered = false;
2631	it6505->sink_count = 0;
2632
2633	return 0;
2634	}
2635
2636	static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2637	{
2638	struct device *dev = it6505->dev;
2639	enum drm_connector_status status = connector_status_disconnected;
2640	int dp_sink_count;
2641
2642	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2643	it6505->sink_count, it6505->powered);
2644
2645	mutex_lock(&it6505->mode_lock);
2646
2647	if (!it6505->powered)
2648	goto unlock;
2649
2650	if (it6505->enable_drv_hold) {
2651	status = it6505->hpd_state ? connector_status_connected :
2652	connector_status_disconnected;
2653	goto unlock;
2654	}
2655
2656	if (it6505->hpd_state) {
2657	it6505_drm_dp_link_set_power(aux: &it6505->aux, link: &it6505->link,
2658	DP_SET_POWER_D0);
2659	dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2660	it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2661	DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2662	it6505->sink_count, it6505->branch_device);
2663
2664	if (it6505->branch_device) {
2665	status = (it6505->sink_count != 0) ?
2666	connector_status_connected :
2667	connector_status_disconnected;
2668	} else {
2669	status = connector_status_connected;
2670	}
2671	} else {
2672	it6505->sink_count = 0;
2673	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2674	}
2675
2676	unlock:
2677	if (it6505->connector_status != status) {
2678	it6505->connector_status = status;
2679	it6505_plugged_status_to_codec(it6505);
2680	}
2681
2682	mutex_unlock(lock: &it6505->mode_lock);
2683
2684	return status;
2685	}
2686
2687	static int it6505_extcon_notifier(struct notifier_block *self,
2688	unsigned long event, void *ptr)
2689	{
2690	struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2691
2692	schedule_work(work: &it6505->extcon_wq);
2693	return NOTIFY_DONE;
2694	}
2695
2696	static void it6505_extcon_work(struct work_struct *work)
2697	{
2698	struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2699	struct device *dev = it6505->dev;
2700	int state, ret;
2701
2702	if (it6505->enable_drv_hold)
2703	return;
2704
2705	mutex_lock(&it6505->extcon_lock);
2706
2707	state = extcon_get_state(edev: it6505->extcon, EXTCON_DISP_DP);
2708	DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2709
2710	if (state == it6505->extcon_state || unlikely(state < 0))
2711	goto unlock;
2712	it6505->extcon_state = state;
2713	if (state) {
2714	DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2715	msleep(msecs: 100);
2716	ret = pm_runtime_get_sync(dev);
2717
2718	/*
2719	* On system resume, extcon_work can be triggered before
2720	* pm_runtime_force_resume re-enables runtime power management.
2721	* Handling the error here to make sure the bridge is powered on.
2722	*/
2723	if (ret < 0)
2724	it6505_poweron(it6505);
2725
2726	complete_all(&it6505->extcon_completion);
2727	} else {
2728	DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2729	pm_runtime_put_sync(dev);
2730	reinit_completion(x: &it6505->extcon_completion);
2731
2732	drm_helper_hpd_irq_event(dev: it6505->bridge.dev);
2733	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2734	DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2735	}
2736
2737	unlock:
2738	mutex_unlock(lock: &it6505->extcon_lock);
2739	}
2740
2741	static int it6505_use_notifier_module(struct it6505 *it6505)
2742	{
2743	int ret;
2744	struct device *dev = it6505->dev;
2745
2746	it6505->event_nb.notifier_call = it6505_extcon_notifier;
2747	INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2748	ret = devm_extcon_register_notifier(dev: it6505->dev,
2749	edev: it6505->extcon, EXTCON_DISP_DP,
2750	nb: &it6505->event_nb);
2751	if (ret) {
2752	dev_err(dev, "failed to register notifier for DP");
2753	return ret;
2754	}
2755
2756	schedule_work(work: &it6505->extcon_wq);
2757
2758	return 0;
2759	}
2760
2761	static void it6505_remove_notifier_module(struct it6505 *it6505)
2762	{
2763	if (it6505->extcon) {
2764	devm_extcon_unregister_notifier(dev: it6505->dev,
2765	edev: it6505->extcon, EXTCON_DISP_DP,
2766	nb: &it6505->event_nb);
2767
2768	flush_work(work: &it6505->extcon_wq);
2769	}
2770	}
2771
2772	static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2773	{
2774	struct it6505 *it6505 = container_of(work, struct it6505,
2775	delayed_audio.work);
2776
2777	DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
2778
2779	if (!it6505->powered)
2780	return;
2781
2782	if (!it6505->enable_drv_hold)
2783	it6505_enable_audio(it6505);
2784	}
2785
2786	static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2787	struct hdmi_codec_params
2788	*params)
2789	{
2790	struct device *dev = it6505->dev;
2791	int i = 0;
2792
2793	DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2794	params->sample_rate, params->sample_width,
2795	params->cea.channels);
2796
2797	if (!it6505->bridge.encoder)
2798	return -ENODEV;
2799
2800	if (params->cea.channels <= 1 || params->cea.channels > 8) {
2801	DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2802	it6505->audio.channel_count);
2803	return -EINVAL;
2804	}
2805
2806	it6505->audio.channel_count = params->cea.channels;
2807
2808	while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2809	params->sample_rate !=
2810	audio_sample_rate_map[i].sample_rate_value) {
2811	i++;
2812	}
2813	if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2814	DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2815	params->sample_rate);
2816	return -EINVAL;
2817	}
2818	it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2819
2820	switch (params->sample_width) {
2821	case 16:
2822	it6505->audio.word_length = WORD_LENGTH_16BIT;
2823	break;
2824	case 18:
2825	it6505->audio.word_length = WORD_LENGTH_18BIT;
2826	break;
2827	case 20:
2828	it6505->audio.word_length = WORD_LENGTH_20BIT;
2829	break;
2830	case 24:
2831	case 32:
2832	it6505->audio.word_length = WORD_LENGTH_24BIT;
2833	break;
2834	default:
2835	DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2836	params->sample_width);
2837	return -EINVAL;
2838	}
2839
2840	return 0;
2841	}
2842
2843	static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2844	{
2845	struct it6505 *it6505 = dev_get_drvdata(dev);
2846
2847	if (it6505->powered)
2848	it6505_disable_audio(it6505);
2849	}
2850
2851	static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2852	void *data,
2853	hdmi_codec_plugged_cb fn,
2854	struct device *codec_dev)
2855	{
2856	struct it6505 *it6505 = data;
2857
2858	it6505->plugged_cb = fn;
2859	it6505->codec_dev = codec_dev;
2860	it6505_plugged_status_to_codec(it6505);
2861
2862	return 0;
2863	}
2864
2865	static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2866	{
2867	return container_of(bridge, struct it6505, bridge);
2868	}
2869
2870	static int it6505_bridge_attach(struct drm_bridge *bridge,
2871	enum drm_bridge_attach_flags flags)
2872	{
2873	struct it6505 *it6505 = bridge_to_it6505(bridge);
2874	struct device *dev = it6505->dev;
2875	int ret;
2876
2877	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2878	DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2879	return -EINVAL;
2880	}
2881
2882	if (!bridge->encoder) {
2883	dev_err(dev, "Parent encoder object not found");
2884	return -ENODEV;
2885	}
2886
2887	/* Register aux channel */
2888	it6505->aux.drm_dev = bridge->dev;
2889
2890	ret = drm_dp_aux_register(aux: &it6505->aux);
2891
2892	if (ret < 0) {
2893	dev_err(dev, "Failed to register aux: %d", ret);
2894	return ret;
2895	}
2896
2897	if (it6505->extcon) {
2898	ret = it6505_use_notifier_module(it6505);
2899	if (ret < 0) {
2900	dev_err(dev, "use notifier module failed");
2901	return ret;
2902	}
2903	}
2904
2905	return 0;
2906	}
2907
2908	static void it6505_bridge_detach(struct drm_bridge *bridge)
2909	{
2910	struct it6505 *it6505 = bridge_to_it6505(bridge);
2911
2912	flush_work(work: &it6505->link_works);
2913	it6505_remove_notifier_module(it6505);
2914	}
2915
2916	static enum drm_mode_status
2917	it6505_bridge_mode_valid(struct drm_bridge *bridge,
2918	const struct drm_display_info *info,
2919	const struct drm_display_mode *mode)
2920	{
2921	struct it6505 *it6505 = bridge_to_it6505(bridge);
2922
2923	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2924	return MODE_NO_INTERLACE;
2925
2926	if (mode->clock > it6505->max_dpi_pixel_clock)
2927	return MODE_CLOCK_HIGH;
2928
2929	it6505->video_info.clock = mode->clock;
2930
2931	return MODE_OK;
2932	}
2933
2934	static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2935	struct drm_bridge_state *old_state)
2936	{
2937	struct it6505 *it6505 = bridge_to_it6505(bridge);
2938	struct device *dev = it6505->dev;
2939	struct drm_atomic_state *state = old_state->base.state;
2940	struct hdmi_avi_infoframe frame;
2941	struct drm_crtc_state *crtc_state;
2942	struct drm_connector_state *conn_state;
2943	struct drm_display_mode *mode;
2944	struct drm_connector *connector;
2945	int ret;
2946
2947	DRM_DEV_DEBUG_DRIVER(dev, "start");
2948
2949	connector = drm_atomic_get_new_connector_for_encoder(state,
2950	encoder: bridge->encoder);
2951
2952	if (WARN_ON(!connector))
2953	return;
2954
2955	conn_state = drm_atomic_get_new_connector_state(state, connector);
2956
2957	if (WARN_ON(!conn_state))
2958	return;
2959
2960	crtc_state = drm_atomic_get_new_crtc_state(state, crtc: conn_state->crtc);
2961
2962	if (WARN_ON(!crtc_state))
2963	return;
2964
2965	mode = &crtc_state->adjusted_mode;
2966
2967	if (WARN_ON(!mode))
2968	return;
2969
2970	ret = drm_hdmi_avi_infoframe_from_display_mode(frame: &frame,
2971	connector,
2972	mode);
2973	if (ret)
2974	dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2975
2976	it6505_update_video_parameter(it6505, mode);
2977
2978	ret = it6505_send_video_infoframe(it6505, frame: &frame);
2979
2980	if (ret)
2981	dev_err(dev, "Failed to send AVI infoframe: %d", ret);
2982
2983	it6505_int_mask_enable(it6505);
2984	it6505_video_reset(it6505);
2985
2986	it6505_drm_dp_link_set_power(aux: &it6505->aux, link: &it6505->link,
2987	DP_SET_POWER_D0);
2988	}
2989
2990	static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
2991	struct drm_bridge_state *old_state)
2992	{
2993	struct it6505 *it6505 = bridge_to_it6505(bridge);
2994	struct device *dev = it6505->dev;
2995
2996	DRM_DEV_DEBUG_DRIVER(dev, "start");
2997
2998	if (it6505->powered) {
2999	it6505_drm_dp_link_set_power(aux: &it6505->aux, link: &it6505->link,
3000	DP_SET_POWER_D3);
3001	it6505_video_disable(it6505);
3002	}
3003	}
3004
3005	static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
3006	struct drm_bridge_state *old_state)
3007	{
3008	struct it6505 *it6505 = bridge_to_it6505(bridge);
3009	struct device *dev = it6505->dev;
3010
3011	DRM_DEV_DEBUG_DRIVER(dev, "start");
3012
3013	pm_runtime_get_sync(dev);
3014	}
3015
3016	static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
3017	struct drm_bridge_state *old_state)
3018	{
3019	struct it6505 *it6505 = bridge_to_it6505(bridge);
3020	struct device *dev = it6505->dev;
3021
3022	DRM_DEV_DEBUG_DRIVER(dev, "start");
3023
3024	pm_runtime_put_sync(dev);
3025	}
3026
3027	static enum drm_connector_status
3028	it6505_bridge_detect(struct drm_bridge *bridge)
3029	{
3030	struct it6505 *it6505 = bridge_to_it6505(bridge);
3031
3032	return it6505_detect(it6505);
3033	}
3034
3035	static struct edid *it6505_bridge_get_edid(struct drm_bridge *bridge,
3036	struct drm_connector *connector)
3037	{
3038	struct it6505 *it6505 = bridge_to_it6505(bridge);
3039	struct device *dev = it6505->dev;
3040
3041	if (!it6505->cached_edid) {
3042	it6505->cached_edid = drm_do_get_edid(connector, get_edid_block: it6505_get_edid_block,
3043	data: it6505);
3044
3045	if (!it6505->cached_edid) {
3046	DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3047	return NULL;
3048	}
3049	}
3050
3051	return drm_edid_duplicate(edid: it6505->cached_edid);
3052	}
3053
3054	static const struct drm_bridge_funcs it6505_bridge_funcs = {
3055	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3056	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3057	.atomic_reset = drm_atomic_helper_bridge_reset,
3058	.attach = it6505_bridge_attach,
3059	.detach = it6505_bridge_detach,
3060	.mode_valid = it6505_bridge_mode_valid,
3061	.atomic_enable = it6505_bridge_atomic_enable,
3062	.atomic_disable = it6505_bridge_atomic_disable,
3063	.atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3064	.atomic_post_disable = it6505_bridge_atomic_post_disable,
3065	.detect = it6505_bridge_detect,
3066	.get_edid = it6505_bridge_get_edid,
3067	};
3068
3069	static __maybe_unused int it6505_bridge_resume(struct device *dev)
3070	{
3071	struct it6505 *it6505 = dev_get_drvdata(dev);
3072
3073	return it6505_poweron(it6505);
3074	}
3075
3076	static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3077	{
3078	struct it6505 *it6505 = dev_get_drvdata(dev);
3079
3080	return it6505_poweroff(it6505);
3081	}
3082
3083	static const struct dev_pm_ops it6505_bridge_pm_ops = {
3084	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3085	SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3086	};
3087
3088	static int it6505_init_pdata(struct it6505 *it6505)
3089	{
3090	struct it6505_platform_data *pdata = &it6505->pdata;
3091	struct device *dev = it6505->dev;
3092
3093	/* 1.0V digital core power regulator */
3094	pdata->pwr18 = devm_regulator_get(dev, id: "pwr18");
3095	if (IS_ERR(ptr: pdata->pwr18)) {
3096	dev_err(dev, "pwr18 regulator not found");
3097	return PTR_ERR(ptr: pdata->pwr18);
3098	}
3099
3100	pdata->ovdd = devm_regulator_get(dev, id: "ovdd");
3101	if (IS_ERR(ptr: pdata->ovdd)) {
3102	dev_err(dev, "ovdd regulator not found");
3103	return PTR_ERR(ptr: pdata->ovdd);
3104	}
3105
3106	pdata->gpiod_reset = devm_gpiod_get(dev, con_id: "reset", flags: GPIOD_OUT_LOW);
3107	if (IS_ERR(ptr: pdata->gpiod_reset)) {
3108	dev_err(dev, "gpiod_reset gpio not found");
3109	return PTR_ERR(ptr: pdata->gpiod_reset);
3110	}
3111
3112	return 0;
3113	}
3114
3115	static int it6505_get_data_lanes_count(const struct device_node *endpoint,
3116	const unsigned int min,
3117	const unsigned int max)
3118	{
3119	int ret;
3120
3121	ret = of_property_count_u32_elems(np: endpoint, propname: "data-lanes");
3122	if (ret < 0)
3123	return ret;
3124
3125	if (ret < min || ret > max)
3126	return -EINVAL;
3127
3128	return ret;
3129	}
3130
3131	static void it6505_parse_dt(struct it6505 *it6505)
3132	{
3133	struct device *dev = it6505->dev;
3134	struct device_node *np = dev->of_node, *ep = NULL;
3135	int len;
3136	u64 link_frequencies;
3137	u32 data_lanes[4];
3138	u32 *afe_setting = &it6505->afe_setting;
3139	u32 *max_lane_count = &it6505->max_lane_count;
3140	u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
3141
3142	it6505->lane_swap_disabled =
3143	device_property_read_bool(dev, propname: "no-laneswap");
3144
3145	if (it6505->lane_swap_disabled)
3146	it6505->lane_swap = false;
3147
3148	if (device_property_read_u32(dev, propname: "afe-setting", val: afe_setting) == 0) {
3149	if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3150	dev_err(dev, "afe setting error, use default");
3151	*afe_setting = 0;
3152	}
3153	} else {
3154	*afe_setting = 0;
3155	}
3156
3157	ep = of_graph_get_endpoint_by_regs(parent: np, port_reg: 1, reg: 0);
3158	of_node_put(node: ep);
3159
3160	if (ep) {
3161	len = it6505_get_data_lanes_count(endpoint: ep, min: 1, max: 4);
3162
3163	if (len > 0 && len != 3) {
3164	of_property_read_u32_array(np: ep, propname: "data-lanes",
3165	out_values: data_lanes, sz: len);
3166	*max_lane_count = len;
3167	} else {
3168	*max_lane_count = MAX_LANE_COUNT;
3169	dev_err(dev, "error data-lanes, use default");
3170	}
3171	} else {
3172	*max_lane_count = MAX_LANE_COUNT;
3173	dev_err(dev, "error endpoint, use default");
3174	}
3175
3176	ep = of_graph_get_endpoint_by_regs(parent: np, port_reg: 0, reg: 0);
3177	of_node_put(node: ep);
3178
3179	if (ep) {
3180	len = of_property_read_variable_u64_array(np: ep,
3181	propname: "link-frequencies",
3182	out_values: &link_frequencies, sz_min: 0,
3183	sz_max: 1);
3184	if (len >= 0) {
3185	do_div(link_frequencies, 1000);
3186	if (link_frequencies > 297000) {
3187	dev_err(dev,
3188	"max pixel clock error, use default");
3189	*max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3190	} else {
3191	*max_dpi_pixel_clock = link_frequencies;
3192	}
3193	} else {
3194	dev_err(dev, "error link frequencies, use default");
3195	*max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3196	}
3197	} else {
3198	dev_err(dev, "error endpoint, use default");
3199	*max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3200	}
3201
3202	DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
3203	it6505->afe_setting, it6505->max_lane_count);
3204	DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
3205	it6505->max_dpi_pixel_clock);
3206	}
3207
3208	static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3209	size_t len, loff_t *ppos)
3210	{
3211	struct it6505 *it6505 = file->private_data;
3212	struct drm_display_mode *vid;
3213	u8 read_buf[READ_BUFFER_SIZE];
3214	u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3215	ssize_t ret, count;
3216
3217	if (!it6505)
3218	return -ENODEV;
3219
3220	it6505_calc_video_info(it6505);
3221	vid = &it6505->video_info;
3222	str += scnprintf(buf: str, size: end - str, fmt: "---video timing---\n");
3223	str += scnprintf(buf: str, size: end - str, fmt: "PCLK:%d.%03dMHz\n",
3224	vid->clock / 1000, vid->clock % 1000);
3225	str += scnprintf(buf: str, size: end - str, fmt: "HTotal:%d\n", vid->htotal);
3226	str += scnprintf(buf: str, size: end - str, fmt: "HActive:%d\n", vid->hdisplay);
3227	str += scnprintf(buf: str, size: end - str, fmt: "HFrontPorch:%d\n",
3228	vid->hsync_start - vid->hdisplay);
3229	str += scnprintf(buf: str, size: end - str, fmt: "HSyncWidth:%d\n",
3230	vid->hsync_end - vid->hsync_start);
3231	str += scnprintf(buf: str, size: end - str, fmt: "HBackPorch:%d\n",
3232	vid->htotal - vid->hsync_end);
3233	str += scnprintf(buf: str, size: end - str, fmt: "VTotal:%d\n", vid->vtotal);
3234	str += scnprintf(buf: str, size: end - str, fmt: "VActive:%d\n", vid->vdisplay);
3235	str += scnprintf(buf: str, size: end - str, fmt: "VFrontPorch:%d\n",
3236	vid->vsync_start - vid->vdisplay);
3237	str += scnprintf(buf: str, size: end - str, fmt: "VSyncWidth:%d\n",
3238	vid->vsync_end - vid->vsync_start);
3239	str += scnprintf(buf: str, size: end - str, fmt: "VBackPorch:%d\n",
3240	vid->vtotal - vid->vsync_end);
3241
3242	count = str - read_buf;
3243	ret = simple_read_from_buffer(to: buf, count: len, ppos, from: read_buf, available: count);
3244
3245	return ret;
3246	}
3247
3248	static int force_power_on_off_debugfs_write(void *data, u64 value)
3249	{
3250	struct it6505 *it6505 = data;
3251
3252	if (!it6505)
3253	return -ENODEV;
3254
3255	if (value)
3256	it6505_poweron(it6505);
3257	else
3258	it6505_poweroff(it6505);
3259
3260	return 0;
3261	}
3262
3263	static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3264	{
3265	struct it6505 *it6505 = data;
3266
3267	if (!it6505)
3268	return -ENODEV;
3269
3270	*buf = it6505->enable_drv_hold;
3271
3272	return 0;
3273	}
3274
3275	static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3276	{
3277	struct it6505 *it6505 = data;
3278
3279	if (!it6505)
3280	return -ENODEV;
3281
3282	it6505->enable_drv_hold = drv_hold;
3283
3284	if (it6505->enable_drv_hold) {
3285	it6505_int_mask_disable(it6505);
3286	} else {
3287	it6505_clear_int(it6505);
3288	it6505_int_mask_enable(it6505);
3289
3290	if (it6505->powered) {
3291	it6505->connector_status =
3292	it6505_get_sink_hpd_status(it6505) ?
3293	connector_status_connected :
3294	connector_status_disconnected;
3295	} else {
3296	it6505->connector_status =
3297	connector_status_disconnected;
3298	}
3299	}
3300
3301	return 0;
3302	}
3303
3304	static const struct file_operations receive_timing_fops = {
3305	.owner = THIS_MODULE,
3306	.open = simple_open,
3307	.read = receive_timing_debugfs_show,
3308	.llseek = default_llseek,
3309	};
3310
3311	DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3312	force_power_on_off_debugfs_write, "%llu\n");
3313
3314	DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3315	enable_drv_hold_debugfs_write, "%llu\n");
3316
3317	static const struct debugfs_entries debugfs_entry[] = {
3318	{ "receive_timing", &receive_timing_fops },
3319	{ "force_power_on_off", &fops_force_power },
3320	{ "enable_drv_hold", &fops_enable_drv_hold },
3321	{ NULL, NULL },
3322	};
3323
3324	static void debugfs_create_files(struct it6505 *it6505)
3325	{
3326	int i = 0;
3327
3328	while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3329	debugfs_create_file(name: debugfs_entry[i].name, mode: 0644,
3330	parent: it6505->debugfs, data: it6505,
3331	fops: debugfs_entry[i].fops);
3332	i++;
3333	}
3334	}
3335
3336	static void debugfs_init(struct it6505 *it6505)
3337	{
3338	struct device *dev = it6505->dev;
3339
3340	it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3341
3342	if (IS_ERR(ptr: it6505->debugfs)) {
3343	dev_err(dev, "failed to create debugfs root");
3344	return;
3345	}
3346
3347	debugfs_create_files(it6505);
3348	}
3349
3350	static void it6505_debugfs_remove(struct it6505 *it6505)
3351	{
3352	debugfs_remove_recursive(dentry: it6505->debugfs);
3353	}
3354
3355	static void it6505_shutdown(struct i2c_client *client)
3356	{
3357	struct it6505 *it6505 = dev_get_drvdata(dev: &client->dev);
3358
3359	if (it6505->powered)
3360	it6505_lane_off(it6505);
3361	}
3362
3363	static int it6505_i2c_probe(struct i2c_client *client)
3364	{
3365	struct it6505 *it6505;
3366	struct device *dev = &client->dev;
3367	struct extcon_dev *extcon;
3368	int err, intp_irq;
3369
3370	it6505 = devm_kzalloc(dev: &client->dev, size: sizeof(*it6505), GFP_KERNEL);
3371	if (!it6505)
3372	return -ENOMEM;
3373
3374	mutex_init(&it6505->extcon_lock);
3375	mutex_init(&it6505->mode_lock);
3376	mutex_init(&it6505->aux_lock);
3377
3378	it6505->bridge.of_node = client->dev.of_node;
3379	it6505->connector_status = connector_status_disconnected;
3380	it6505->dev = &client->dev;
3381	i2c_set_clientdata(client, data: it6505);
3382
3383	/* get extcon device from DTS */
3384	extcon = extcon_get_edev_by_phandle(dev, index: 0);
3385	if (PTR_ERR(ptr: extcon) == -EPROBE_DEFER)
3386	return -EPROBE_DEFER;
3387	if (IS_ERR(ptr: extcon)) {
3388	dev_err(dev, "can not get extcon device!");
3389	return PTR_ERR(ptr: extcon);
3390	}
3391
3392	it6505->extcon = extcon;
3393
3394	it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3395	if (IS_ERR(ptr: it6505->regmap)) {
3396	dev_err(dev, "regmap i2c init failed");
3397	err = PTR_ERR(ptr: it6505->regmap);
3398	return err;
3399	}
3400
3401	err = it6505_init_pdata(it6505);
3402	if (err) {
3403	dev_err(dev, "Failed to initialize pdata: %d", err);
3404	return err;
3405	}
3406
3407	it6505_parse_dt(it6505);
3408
3409	intp_irq = client->irq;
3410
3411	if (!intp_irq) {
3412	dev_err(dev, "Failed to get INTP IRQ");
3413	err = -ENODEV;
3414	return err;
3415	}
3416
3417	err = devm_request_threaded_irq(dev: &client->dev, irq: intp_irq, NULL,
3418	thread_fn: it6505_int_threaded_handler,
3419	IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3420	devname: "it6505-intp", dev_id: it6505);
3421	if (err) {
3422	dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3423	return err;
3424	}
3425
3426	INIT_WORK(&it6505->link_works, it6505_link_training_work);
3427	INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3428	INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3429	init_completion(x: &it6505->extcon_completion);
3430	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3431	it6505->powered = false;
3432	it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3433
3434	if (DEFAULT_PWR_ON)
3435	it6505_poweron(it6505);
3436
3437	DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3438	debugfs_init(it6505);
3439	pm_runtime_enable(dev);
3440
3441	it6505->aux.name = "DP-AUX";
3442	it6505->aux.dev = dev;
3443	it6505->aux.transfer = it6505_aux_transfer;
3444	drm_dp_aux_init(aux: &it6505->aux);
3445
3446	it6505->bridge.funcs = &it6505_bridge_funcs;
3447	it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3448	it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3449	DRM_BRIDGE_OP_HPD;
3450	drm_bridge_add(bridge: &it6505->bridge);
3451
3452	return 0;
3453	}
3454
3455	static void it6505_i2c_remove(struct i2c_client *client)
3456	{
3457	struct it6505 *it6505 = i2c_get_clientdata(client);
3458
3459	drm_bridge_remove(bridge: &it6505->bridge);
3460	drm_dp_aux_unregister(aux: &it6505->aux);
3461	it6505_debugfs_remove(it6505);
3462	it6505_poweroff(it6505);
3463	it6505_remove_edid(it6505);
3464	}
3465
3466	static const struct i2c_device_id it6505_id[] = {
3467	{ "it6505", 0 },
3468	{ }
3469	};
3470
3471	MODULE_DEVICE_TABLE(i2c, it6505_id);
3472
3473	static const struct of_device_id it6505_of_match[] = {
3474	{ .compatible = "ite,it6505" },
3475	{ }
3476	};
3477
3478	static struct i2c_driver it6505_i2c_driver = {
3479	.driver = {
3480	.name = "it6505",
3481	.of_match_table = it6505_of_match,
3482	.pm = &it6505_bridge_pm_ops,
3483	},
3484	.probe = it6505_i2c_probe,
3485	.remove = it6505_i2c_remove,
3486	.shutdown = it6505_shutdown,
3487	.id_table = it6505_id,
3488	};
3489
3490	module_i2c_driver(it6505_i2c_driver);
3491
3492	MODULE_AUTHOR("Allen Chen <allen.chen@ite.com.tw>");
3493	MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3494	MODULE_LICENSE("GPL v2");
3495