1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Samsung MIPI DSIM bridge driver. |
4 | * |
5 | * Copyright (C) 2021 Amarula Solutions(India) |
6 | * Copyright (c) 2014 Samsung Electronics Co., Ltd |
7 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
8 | * |
9 | * Based on exynos_drm_dsi from |
10 | * Tomasz Figa <t.figa@samsung.com> |
11 | */ |
12 | |
13 | #include <asm/unaligned.h> |
14 | |
15 | #include <linux/clk.h> |
16 | #include <linux/delay.h> |
17 | #include <linux/irq.h> |
18 | #include <linux/media-bus-format.h> |
19 | #include <linux/of.h> |
20 | #include <linux/phy/phy.h> |
21 | #include <linux/platform_device.h> |
22 | |
23 | #include <video/mipi_display.h> |
24 | |
25 | #include <drm/bridge/samsung-dsim.h> |
26 | #include <drm/drm_panel.h> |
27 | #include <drm/drm_print.h> |
28 | |
29 | /* returns true iff both arguments logically differs */ |
30 | #define NEQV(a, b) (!(a) ^ !(b)) |
31 | |
32 | /* DSIM_STATUS */ |
33 | #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) |
34 | #define DSIM_STOP_STATE_CLK BIT(8) |
35 | #define DSIM_TX_READY_HS_CLK BIT(10) |
36 | #define DSIM_PLL_STABLE BIT(31) |
37 | |
38 | /* DSIM_SWRST */ |
39 | #define DSIM_FUNCRST BIT(16) |
40 | #define DSIM_SWRST BIT(0) |
41 | |
42 | /* DSIM_TIMEOUT */ |
43 | #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) |
44 | #define DSIM_BTA_TIMEOUT(x) ((x) << 16) |
45 | |
46 | /* DSIM_CLKCTRL */ |
47 | #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) |
48 | #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) |
49 | #define DSIM_LANE_ESC_CLK_EN_CLK BIT(19) |
50 | #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) |
51 | #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) |
52 | #define DSIM_BYTE_CLKEN BIT(24) |
53 | #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) |
54 | #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) |
55 | #define DSIM_PLL_BYPASS BIT(27) |
56 | #define DSIM_ESC_CLKEN BIT(28) |
57 | #define DSIM_TX_REQUEST_HSCLK BIT(31) |
58 | |
59 | /* DSIM_CONFIG */ |
60 | #define DSIM_LANE_EN_CLK BIT(0) |
61 | #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) |
62 | #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) |
63 | #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) |
64 | #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) |
65 | #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) |
66 | #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) |
67 | #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) |
68 | #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) |
69 | #define DSIM_SUB_VC (((x) & 0x3) << 16) |
70 | #define DSIM_MAIN_VC (((x) & 0x3) << 18) |
71 | #define DSIM_HSA_DISABLE_MODE BIT(20) |
72 | #define DSIM_HBP_DISABLE_MODE BIT(21) |
73 | #define DSIM_HFP_DISABLE_MODE BIT(22) |
74 | /* |
75 | * The i.MX 8M Mini Applications Processor Reference Manual, |
76 | * Rev. 3, 11/2020 Page 4091 |
77 | * The i.MX 8M Nano Applications Processor Reference Manual, |
78 | * Rev. 2, 07/2022 Page 3058 |
79 | * The i.MX 8M Plus Applications Processor Reference Manual, |
80 | * Rev. 1, 06/2021 Page 5436 |
81 | * all claims this bit is 'HseDisableMode' with the definition |
82 | * 0 = Disables transfer |
83 | * 1 = Enables transfer |
84 | * |
85 | * This clearly states that HSE is not a disabled bit. |
86 | * |
87 | * The naming convention follows as per the manual and the |
88 | * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag. |
89 | */ |
90 | #define DSIM_HSE_DISABLE_MODE BIT(23) |
91 | #define DSIM_AUTO_MODE BIT(24) |
92 | #define DSIM_VIDEO_MODE BIT(25) |
93 | #define DSIM_BURST_MODE BIT(26) |
94 | #define DSIM_SYNC_INFORM BIT(27) |
95 | #define DSIM_EOT_DISABLE BIT(28) |
96 | #define DSIM_MFLUSH_VS BIT(29) |
97 | /* This flag is valid only for exynos3250/3472/5260/5430 */ |
98 | #define DSIM_CLKLANE_STOP BIT(30) |
99 | |
100 | /* DSIM_ESCMODE */ |
101 | #define DSIM_TX_TRIGGER_RST BIT(4) |
102 | #define DSIM_TX_LPDT_LP BIT(6) |
103 | #define DSIM_CMD_LPDT_LP BIT(7) |
104 | #define DSIM_FORCE_BTA BIT(16) |
105 | #define DSIM_FORCE_STOP_STATE BIT(20) |
106 | #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) |
107 | #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) |
108 | |
109 | /* DSIM_MDRESOL */ |
110 | #define DSIM_MAIN_STAND_BY BIT(31) |
111 | #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) |
112 | #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) |
113 | |
114 | /* DSIM_MVPORCH */ |
115 | #define DSIM_CMD_ALLOW(x) ((x) << 28) |
116 | #define DSIM_STABLE_VFP(x) ((x) << 16) |
117 | #define DSIM_MAIN_VBP(x) ((x) << 0) |
118 | #define DSIM_CMD_ALLOW_MASK (0xf << 28) |
119 | #define DSIM_STABLE_VFP_MASK (0x7ff << 16) |
120 | #define DSIM_MAIN_VBP_MASK (0x7ff << 0) |
121 | |
122 | /* DSIM_MHPORCH */ |
123 | #define DSIM_MAIN_HFP(x) ((x) << 16) |
124 | #define DSIM_MAIN_HBP(x) ((x) << 0) |
125 | #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) |
126 | #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) |
127 | |
128 | /* DSIM_MSYNC */ |
129 | #define DSIM_MAIN_VSA(x) ((x) << 22) |
130 | #define DSIM_MAIN_HSA(x) ((x) << 0) |
131 | #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) |
132 | #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) |
133 | |
134 | /* DSIM_SDRESOL */ |
135 | #define DSIM_SUB_STANDY(x) ((x) << 31) |
136 | #define DSIM_SUB_VRESOL(x) ((x) << 16) |
137 | #define DSIM_SUB_HRESOL(x) ((x) << 0) |
138 | #define DSIM_SUB_STANDY_MASK ((0x1) << 31) |
139 | #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) |
140 | #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) |
141 | |
142 | /* DSIM_INTSRC */ |
143 | #define DSIM_INT_PLL_STABLE BIT(31) |
144 | #define DSIM_INT_SW_RST_RELEASE BIT(30) |
145 | #define DSIM_INT_SFR_FIFO_EMPTY BIT(29) |
146 | #define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28) |
147 | #define DSIM_INT_BTA BIT(25) |
148 | #define DSIM_INT_FRAME_DONE BIT(24) |
149 | #define DSIM_INT_RX_TIMEOUT BIT(21) |
150 | #define DSIM_INT_BTA_TIMEOUT BIT(20) |
151 | #define DSIM_INT_RX_DONE BIT(18) |
152 | #define DSIM_INT_RX_TE BIT(17) |
153 | #define DSIM_INT_RX_ACK BIT(16) |
154 | #define DSIM_INT_RX_ECC_ERR BIT(15) |
155 | #define DSIM_INT_RX_CRC_ERR BIT(14) |
156 | |
157 | /* DSIM_FIFOCTRL */ |
158 | #define DSIM_RX_DATA_FULL BIT(25) |
159 | #define DSIM_RX_DATA_EMPTY BIT(24) |
160 | #define BIT(23) |
161 | #define BIT(22) |
162 | #define DSIM_SFR_PAYLOAD_FULL BIT(21) |
163 | #define DSIM_SFR_PAYLOAD_EMPTY BIT(20) |
164 | #define BIT(19) |
165 | #define BIT(18) |
166 | #define DSIM_I80_PAYLOAD_FULL BIT(17) |
167 | #define DSIM_I80_PAYLOAD_EMPTY BIT(16) |
168 | #define BIT(15) |
169 | #define BIT(14) |
170 | #define DSIM_SD_PAYLOAD_FULL BIT(13) |
171 | #define DSIM_SD_PAYLOAD_EMPTY BIT(12) |
172 | #define BIT(11) |
173 | #define BIT(10) |
174 | #define DSIM_MD_PAYLOAD_FULL BIT(9) |
175 | #define DSIM_MD_PAYLOAD_EMPTY BIT(8) |
176 | #define DSIM_RX_FIFO BIT(4) |
177 | #define DSIM_SFR_FIFO BIT(3) |
178 | #define DSIM_I80_FIFO BIT(2) |
179 | #define DSIM_SD_FIFO BIT(1) |
180 | #define DSIM_MD_FIFO BIT(0) |
181 | |
182 | /* DSIM_PHYACCHR */ |
183 | #define DSIM_AFC_EN BIT(14) |
184 | #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) |
185 | |
186 | /* DSIM_PLLCTRL */ |
187 | #define DSIM_PLL_DPDNSWAP_CLK (1 << 25) |
188 | #define DSIM_PLL_DPDNSWAP_DAT (1 << 24) |
189 | #define DSIM_FREQ_BAND(x) ((x) << 24) |
190 | #define DSIM_PLL_EN BIT(23) |
191 | #define DSIM_PLL_P(x, offset) ((x) << (offset)) |
192 | #define DSIM_PLL_M(x) ((x) << 4) |
193 | #define DSIM_PLL_S(x) ((x) << 1) |
194 | |
195 | /* DSIM_PHYCTRL */ |
196 | #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) |
197 | #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30) |
198 | #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14) |
199 | |
200 | /* DSIM_PHYTIMING */ |
201 | #define DSIM_PHYTIMING_LPX(x) ((x) << 8) |
202 | #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) |
203 | |
204 | /* DSIM_PHYTIMING1 */ |
205 | #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) |
206 | #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) |
207 | #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) |
208 | #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) |
209 | |
210 | /* DSIM_PHYTIMING2 */ |
211 | #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) |
212 | #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) |
213 | #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) |
214 | |
215 | #define DSI_MAX_BUS_WIDTH 4 |
216 | #define DSI_NUM_VIRTUAL_CHANNELS 4 |
217 | #define DSI_TX_FIFO_SIZE 2048 |
218 | #define DSI_RX_FIFO_SIZE 256 |
219 | #define DSI_XFER_TIMEOUT_MS 100 |
220 | #define DSI_RX_FIFO_EMPTY 0x30800002 |
221 | |
222 | #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" |
223 | |
224 | #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL) |
225 | |
226 | static const char *const clk_names[5] = { |
227 | "bus_clk" , |
228 | "sclk_mipi" , |
229 | "phyclk_mipidphy0_bitclkdiv8" , |
230 | "phyclk_mipidphy0_rxclkesc0" , |
231 | "sclk_rgb_vclk_to_dsim0" |
232 | }; |
233 | |
234 | enum samsung_dsim_transfer_type { |
235 | EXYNOS_DSI_TX, |
236 | EXYNOS_DSI_RX, |
237 | }; |
238 | |
239 | enum reg_idx { |
240 | DSIM_STATUS_REG, /* Status register */ |
241 | DSIM_SWRST_REG, /* Software reset register */ |
242 | DSIM_CLKCTRL_REG, /* Clock control register */ |
243 | DSIM_TIMEOUT_REG, /* Time out register */ |
244 | DSIM_CONFIG_REG, /* Configuration register */ |
245 | DSIM_ESCMODE_REG, /* Escape mode register */ |
246 | DSIM_MDRESOL_REG, |
247 | DSIM_MVPORCH_REG, /* Main display Vporch register */ |
248 | DSIM_MHPORCH_REG, /* Main display Hporch register */ |
249 | DSIM_MSYNC_REG, /* Main display sync area register */ |
250 | DSIM_INTSRC_REG, /* Interrupt source register */ |
251 | DSIM_INTMSK_REG, /* Interrupt mask register */ |
252 | DSIM_PKTHDR_REG, /* Packet Header FIFO register */ |
253 | DSIM_PAYLOAD_REG, /* Payload FIFO register */ |
254 | DSIM_RXFIFO_REG, /* Read FIFO register */ |
255 | DSIM_FIFOCTRL_REG, /* FIFO status and control register */ |
256 | DSIM_PLLCTRL_REG, /* PLL control register */ |
257 | DSIM_PHYCTRL_REG, |
258 | DSIM_PHYTIMING_REG, |
259 | DSIM_PHYTIMING1_REG, |
260 | DSIM_PHYTIMING2_REG, |
261 | NUM_REGS |
262 | }; |
263 | |
264 | static const unsigned int exynos_reg_ofs[] = { |
265 | [DSIM_STATUS_REG] = 0x00, |
266 | [DSIM_SWRST_REG] = 0x04, |
267 | [DSIM_CLKCTRL_REG] = 0x08, |
268 | [DSIM_TIMEOUT_REG] = 0x0c, |
269 | [DSIM_CONFIG_REG] = 0x10, |
270 | [DSIM_ESCMODE_REG] = 0x14, |
271 | [DSIM_MDRESOL_REG] = 0x18, |
272 | [DSIM_MVPORCH_REG] = 0x1c, |
273 | [DSIM_MHPORCH_REG] = 0x20, |
274 | [DSIM_MSYNC_REG] = 0x24, |
275 | [DSIM_INTSRC_REG] = 0x2c, |
276 | [DSIM_INTMSK_REG] = 0x30, |
277 | [DSIM_PKTHDR_REG] = 0x34, |
278 | [DSIM_PAYLOAD_REG] = 0x38, |
279 | [DSIM_RXFIFO_REG] = 0x3c, |
280 | [DSIM_FIFOCTRL_REG] = 0x44, |
281 | [DSIM_PLLCTRL_REG] = 0x4c, |
282 | [DSIM_PHYCTRL_REG] = 0x5c, |
283 | [DSIM_PHYTIMING_REG] = 0x64, |
284 | [DSIM_PHYTIMING1_REG] = 0x68, |
285 | [DSIM_PHYTIMING2_REG] = 0x6c, |
286 | }; |
287 | |
288 | static const unsigned int exynos5433_reg_ofs[] = { |
289 | [DSIM_STATUS_REG] = 0x04, |
290 | [DSIM_SWRST_REG] = 0x0C, |
291 | [DSIM_CLKCTRL_REG] = 0x10, |
292 | [DSIM_TIMEOUT_REG] = 0x14, |
293 | [DSIM_CONFIG_REG] = 0x18, |
294 | [DSIM_ESCMODE_REG] = 0x1C, |
295 | [DSIM_MDRESOL_REG] = 0x20, |
296 | [DSIM_MVPORCH_REG] = 0x24, |
297 | [DSIM_MHPORCH_REG] = 0x28, |
298 | [DSIM_MSYNC_REG] = 0x2C, |
299 | [DSIM_INTSRC_REG] = 0x34, |
300 | [DSIM_INTMSK_REG] = 0x38, |
301 | [DSIM_PKTHDR_REG] = 0x3C, |
302 | [DSIM_PAYLOAD_REG] = 0x40, |
303 | [DSIM_RXFIFO_REG] = 0x44, |
304 | [DSIM_FIFOCTRL_REG] = 0x4C, |
305 | [DSIM_PLLCTRL_REG] = 0x94, |
306 | [DSIM_PHYCTRL_REG] = 0xA4, |
307 | [DSIM_PHYTIMING_REG] = 0xB4, |
308 | [DSIM_PHYTIMING1_REG] = 0xB8, |
309 | [DSIM_PHYTIMING2_REG] = 0xBC, |
310 | }; |
311 | |
312 | enum reg_value_idx { |
313 | RESET_TYPE, |
314 | PLL_TIMER, |
315 | STOP_STATE_CNT, |
316 | PHYCTRL_ULPS_EXIT, |
317 | PHYCTRL_VREG_LP, |
318 | PHYCTRL_SLEW_UP, |
319 | PHYTIMING_LPX, |
320 | PHYTIMING_HS_EXIT, |
321 | PHYTIMING_CLK_PREPARE, |
322 | PHYTIMING_CLK_ZERO, |
323 | PHYTIMING_CLK_POST, |
324 | PHYTIMING_CLK_TRAIL, |
325 | PHYTIMING_HS_PREPARE, |
326 | PHYTIMING_HS_ZERO, |
327 | PHYTIMING_HS_TRAIL |
328 | }; |
329 | |
330 | static const unsigned int reg_values[] = { |
331 | [RESET_TYPE] = DSIM_SWRST, |
332 | [PLL_TIMER] = 500, |
333 | [STOP_STATE_CNT] = 0xf, |
334 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), |
335 | [PHYCTRL_VREG_LP] = 0, |
336 | [PHYCTRL_SLEW_UP] = 0, |
337 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), |
338 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), |
339 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), |
340 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), |
341 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), |
342 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), |
343 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), |
344 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), |
345 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), |
346 | }; |
347 | |
348 | static const unsigned int exynos5422_reg_values[] = { |
349 | [RESET_TYPE] = DSIM_SWRST, |
350 | [PLL_TIMER] = 500, |
351 | [STOP_STATE_CNT] = 0xf, |
352 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), |
353 | [PHYCTRL_VREG_LP] = 0, |
354 | [PHYCTRL_SLEW_UP] = 0, |
355 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), |
356 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), |
357 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), |
358 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), |
359 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), |
360 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), |
361 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), |
362 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), |
363 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), |
364 | }; |
365 | |
366 | static const unsigned int exynos5433_reg_values[] = { |
367 | [RESET_TYPE] = DSIM_FUNCRST, |
368 | [PLL_TIMER] = 22200, |
369 | [STOP_STATE_CNT] = 0xa, |
370 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), |
371 | [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, |
372 | [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, |
373 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), |
374 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), |
375 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), |
376 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), |
377 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), |
378 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), |
379 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), |
380 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), |
381 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), |
382 | }; |
383 | |
384 | static const unsigned int imx8mm_dsim_reg_values[] = { |
385 | [RESET_TYPE] = DSIM_SWRST, |
386 | [PLL_TIMER] = 500, |
387 | [STOP_STATE_CNT] = 0xf, |
388 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), |
389 | [PHYCTRL_VREG_LP] = 0, |
390 | [PHYCTRL_SLEW_UP] = 0, |
391 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), |
392 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), |
393 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), |
394 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), |
395 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), |
396 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), |
397 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), |
398 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), |
399 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), |
400 | }; |
401 | |
402 | static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { |
403 | .reg_ofs = exynos_reg_ofs, |
404 | .plltmr_reg = 0x50, |
405 | .has_freqband = 1, |
406 | .has_clklane_stop = 1, |
407 | .num_clks = 2, |
408 | .max_freq = 1000, |
409 | .wait_for_reset = 1, |
410 | .num_bits_resol = 11, |
411 | .pll_p_offset = 13, |
412 | .reg_values = reg_values, |
413 | .pll_fin_min = 6, |
414 | .pll_fin_max = 12, |
415 | .m_min = 41, |
416 | .m_max = 125, |
417 | .min_freq = 500, |
418 | .has_broken_fifoctrl_emptyhdr = 1, |
419 | }; |
420 | |
421 | static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { |
422 | .reg_ofs = exynos_reg_ofs, |
423 | .plltmr_reg = 0x50, |
424 | .has_freqband = 1, |
425 | .has_clklane_stop = 1, |
426 | .num_clks = 2, |
427 | .max_freq = 1000, |
428 | .wait_for_reset = 1, |
429 | .num_bits_resol = 11, |
430 | .pll_p_offset = 13, |
431 | .reg_values = reg_values, |
432 | .pll_fin_min = 6, |
433 | .pll_fin_max = 12, |
434 | .m_min = 41, |
435 | .m_max = 125, |
436 | .min_freq = 500, |
437 | .has_broken_fifoctrl_emptyhdr = 1, |
438 | }; |
439 | |
440 | static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { |
441 | .reg_ofs = exynos_reg_ofs, |
442 | .plltmr_reg = 0x58, |
443 | .num_clks = 2, |
444 | .max_freq = 1000, |
445 | .wait_for_reset = 1, |
446 | .num_bits_resol = 11, |
447 | .pll_p_offset = 13, |
448 | .reg_values = reg_values, |
449 | .pll_fin_min = 6, |
450 | .pll_fin_max = 12, |
451 | .m_min = 41, |
452 | .m_max = 125, |
453 | .min_freq = 500, |
454 | }; |
455 | |
456 | static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { |
457 | .reg_ofs = exynos5433_reg_ofs, |
458 | .plltmr_reg = 0xa0, |
459 | .has_clklane_stop = 1, |
460 | .num_clks = 5, |
461 | .max_freq = 1500, |
462 | .wait_for_reset = 0, |
463 | .num_bits_resol = 12, |
464 | .pll_p_offset = 13, |
465 | .reg_values = exynos5433_reg_values, |
466 | .pll_fin_min = 6, |
467 | .pll_fin_max = 12, |
468 | .m_min = 41, |
469 | .m_max = 125, |
470 | .min_freq = 500, |
471 | }; |
472 | |
473 | static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { |
474 | .reg_ofs = exynos5433_reg_ofs, |
475 | .plltmr_reg = 0xa0, |
476 | .has_clklane_stop = 1, |
477 | .num_clks = 2, |
478 | .max_freq = 1500, |
479 | .wait_for_reset = 1, |
480 | .num_bits_resol = 12, |
481 | .pll_p_offset = 13, |
482 | .reg_values = exynos5422_reg_values, |
483 | .pll_fin_min = 6, |
484 | .pll_fin_max = 12, |
485 | .m_min = 41, |
486 | .m_max = 125, |
487 | .min_freq = 500, |
488 | }; |
489 | |
490 | static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { |
491 | .reg_ofs = exynos5433_reg_ofs, |
492 | .plltmr_reg = 0xa0, |
493 | .has_clklane_stop = 1, |
494 | .num_clks = 2, |
495 | .max_freq = 2100, |
496 | .wait_for_reset = 0, |
497 | .num_bits_resol = 12, |
498 | /* |
499 | * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus |
500 | * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c |
501 | */ |
502 | .pll_p_offset = 14, |
503 | .reg_values = imx8mm_dsim_reg_values, |
504 | .pll_fin_min = 2, |
505 | .pll_fin_max = 30, |
506 | .m_min = 64, |
507 | .m_max = 1023, |
508 | .min_freq = 1050, |
509 | }; |
510 | |
511 | static const struct samsung_dsim_driver_data * |
512 | samsung_dsim_types[DSIM_TYPE_COUNT] = { |
513 | [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, |
514 | [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, |
515 | [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, |
516 | [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, |
517 | [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, |
518 | [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, |
519 | [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data, |
520 | }; |
521 | |
522 | static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) |
523 | { |
524 | return container_of(h, struct samsung_dsim, dsi_host); |
525 | } |
526 | |
527 | static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b) |
528 | { |
529 | return container_of(b, struct samsung_dsim, bridge); |
530 | } |
531 | |
532 | static inline void samsung_dsim_write(struct samsung_dsim *dsi, |
533 | enum reg_idx idx, u32 val) |
534 | { |
535 | writel(val, addr: dsi->reg_base + dsi->driver_data->reg_ofs[idx]); |
536 | } |
537 | |
538 | static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) |
539 | { |
540 | return readl(addr: dsi->reg_base + dsi->driver_data->reg_ofs[idx]); |
541 | } |
542 | |
543 | static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) |
544 | { |
545 | if (wait_for_completion_timeout(x: &dsi->completed, timeout: msecs_to_jiffies(m: 300))) |
546 | return; |
547 | |
548 | dev_err(dsi->dev, "timeout waiting for reset\n" ); |
549 | } |
550 | |
551 | static void samsung_dsim_reset(struct samsung_dsim *dsi) |
552 | { |
553 | u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; |
554 | |
555 | reinit_completion(x: &dsi->completed); |
556 | samsung_dsim_write(dsi, idx: DSIM_SWRST_REG, val: reset_val); |
557 | } |
558 | |
559 | #ifndef MHZ |
560 | #define MHZ (1000 * 1000) |
561 | #endif |
562 | |
563 | static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, |
564 | unsigned long fin, |
565 | unsigned long fout, |
566 | u8 *p, u16 *m, u8 *s) |
567 | { |
568 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
569 | unsigned long best_freq = 0; |
570 | u32 min_delta = 0xffffffff; |
571 | u8 p_min, p_max; |
572 | u8 _p, best_p; |
573 | u16 _m, best_m; |
574 | u8 _s, best_s; |
575 | |
576 | p_min = DIV_ROUND_UP(fin, (12 * MHZ)); |
577 | p_max = fin / (6 * MHZ); |
578 | |
579 | for (_p = p_min; _p <= p_max; ++_p) { |
580 | for (_s = 0; _s <= 5; ++_s) { |
581 | u64 tmp; |
582 | u32 delta; |
583 | |
584 | tmp = (u64)fout * (_p << _s); |
585 | do_div(tmp, fin); |
586 | _m = tmp; |
587 | if (_m < driver_data->m_min || _m > driver_data->m_max) |
588 | continue; |
589 | |
590 | tmp = (u64)_m * fin; |
591 | do_div(tmp, _p); |
592 | if (tmp < driver_data->min_freq * MHZ || |
593 | tmp > driver_data->max_freq * MHZ) |
594 | continue; |
595 | |
596 | tmp = (u64)_m * fin; |
597 | do_div(tmp, _p << _s); |
598 | |
599 | delta = abs(fout - tmp); |
600 | if (delta < min_delta) { |
601 | best_p = _p; |
602 | best_m = _m; |
603 | best_s = _s; |
604 | min_delta = delta; |
605 | best_freq = tmp; |
606 | } |
607 | } |
608 | } |
609 | |
610 | if (best_freq) { |
611 | *p = best_p; |
612 | *m = best_m; |
613 | *s = best_s; |
614 | } |
615 | |
616 | return best_freq; |
617 | } |
618 | |
619 | static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, |
620 | unsigned long freq) |
621 | { |
622 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
623 | unsigned long fin, fout; |
624 | int timeout; |
625 | u8 p, s; |
626 | u16 m; |
627 | u32 reg; |
628 | |
629 | if (dsi->pll_clk) { |
630 | /* |
631 | * Ensure that the reference clock is generated with a power of |
632 | * two divider from its parent, but close to the PLLs upper |
633 | * limit. |
634 | */ |
635 | fin = clk_get_rate(clk: clk_get_parent(clk: dsi->pll_clk)); |
636 | while (fin > driver_data->pll_fin_max * MHZ) |
637 | fin /= 2; |
638 | clk_set_rate(clk: dsi->pll_clk, rate: fin); |
639 | |
640 | fin = clk_get_rate(clk: dsi->pll_clk); |
641 | } else { |
642 | fin = dsi->pll_clk_rate; |
643 | } |
644 | dev_dbg(dsi->dev, "PLL ref clock freq %lu\n" , fin); |
645 | |
646 | fout = samsung_dsim_pll_find_pms(dsi, fin, fout: freq, p: &p, m: &m, s: &s); |
647 | if (!fout) { |
648 | dev_err(dsi->dev, |
649 | "failed to find PLL PMS for requested frequency\n" ); |
650 | return 0; |
651 | } |
652 | dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n" , fout, p, m, s); |
653 | |
654 | writel(val: driver_data->reg_values[PLL_TIMER], |
655 | addr: dsi->reg_base + driver_data->plltmr_reg); |
656 | |
657 | reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | |
658 | DSIM_PLL_M(m) | DSIM_PLL_S(s); |
659 | |
660 | if (driver_data->has_freqband) { |
661 | static const unsigned long freq_bands[] = { |
662 | 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, |
663 | 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, |
664 | 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, |
665 | 770 * MHZ, 870 * MHZ, 950 * MHZ, |
666 | }; |
667 | int band; |
668 | |
669 | for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) |
670 | if (fout < freq_bands[band]) |
671 | break; |
672 | |
673 | dev_dbg(dsi->dev, "band %d\n" , band); |
674 | |
675 | reg |= DSIM_FREQ_BAND(band); |
676 | } |
677 | |
678 | if (dsi->swap_dn_dp_clk) |
679 | reg |= DSIM_PLL_DPDNSWAP_CLK; |
680 | if (dsi->swap_dn_dp_data) |
681 | reg |= DSIM_PLL_DPDNSWAP_DAT; |
682 | |
683 | samsung_dsim_write(dsi, idx: DSIM_PLLCTRL_REG, val: reg); |
684 | |
685 | timeout = 1000; |
686 | do { |
687 | if (timeout-- == 0) { |
688 | dev_err(dsi->dev, "PLL failed to stabilize\n" ); |
689 | return 0; |
690 | } |
691 | reg = samsung_dsim_read(dsi, idx: DSIM_STATUS_REG); |
692 | } while ((reg & DSIM_PLL_STABLE) == 0); |
693 | |
694 | dsi->hs_clock = fout; |
695 | |
696 | return fout; |
697 | } |
698 | |
699 | static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) |
700 | { |
701 | unsigned long hs_clk, byte_clk, esc_clk, pix_clk; |
702 | unsigned long esc_div; |
703 | u32 reg; |
704 | struct drm_display_mode *m = &dsi->mode; |
705 | int bpp = mipi_dsi_pixel_format_to_bpp(fmt: dsi->format); |
706 | |
707 | /* m->clock is in KHz */ |
708 | pix_clk = m->clock * 1000; |
709 | |
710 | /* Use burst_clk_rate if available, otherwise use the pix_clk */ |
711 | if (dsi->burst_clk_rate) |
712 | hs_clk = samsung_dsim_set_pll(dsi, freq: dsi->burst_clk_rate); |
713 | else |
714 | hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); |
715 | |
716 | if (!hs_clk) { |
717 | dev_err(dsi->dev, "failed to configure DSI PLL\n" ); |
718 | return -EFAULT; |
719 | } |
720 | |
721 | byte_clk = hs_clk / 8; |
722 | esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); |
723 | esc_clk = byte_clk / esc_div; |
724 | |
725 | if (esc_clk > 20 * MHZ) { |
726 | ++esc_div; |
727 | esc_clk = byte_clk / esc_div; |
728 | } |
729 | |
730 | dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n" , |
731 | hs_clk, byte_clk, esc_clk); |
732 | |
733 | reg = samsung_dsim_read(dsi, idx: DSIM_CLKCTRL_REG); |
734 | reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK |
735 | | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS |
736 | | DSIM_BYTE_CLK_SRC_MASK); |
737 | reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN |
738 | | DSIM_ESC_PRESCALER(esc_div) |
739 | | DSIM_LANE_ESC_CLK_EN_CLK |
740 | | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) |
741 | | DSIM_BYTE_CLK_SRC(0) |
742 | | DSIM_TX_REQUEST_HSCLK; |
743 | samsung_dsim_write(dsi, idx: DSIM_CLKCTRL_REG, val: reg); |
744 | |
745 | return 0; |
746 | } |
747 | |
748 | static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) |
749 | { |
750 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
751 | const unsigned int *reg_values = driver_data->reg_values; |
752 | u32 reg; |
753 | struct phy_configure_opts_mipi_dphy cfg; |
754 | int clk_prepare, lpx, clk_zero, clk_post, clk_trail; |
755 | int hs_exit, hs_prepare, hs_zero, hs_trail; |
756 | unsigned long long byte_clock = dsi->hs_clock / 8; |
757 | |
758 | if (driver_data->has_freqband) |
759 | return; |
760 | |
761 | phy_mipi_dphy_get_default_config_for_hsclk(hs_clk_rate: dsi->hs_clock, |
762 | lanes: dsi->lanes, cfg: &cfg); |
763 | |
764 | /* |
765 | * TODO: |
766 | * The tech Applications Processor manuals for i.MX8M Mini, Nano, |
767 | * and Plus don't state what the definition of the PHYTIMING |
768 | * bits are beyond their address and bit position. |
769 | * After reviewing NXP's downstream code, it appears |
770 | * that the various PHYTIMING registers take the number |
771 | * of cycles and use various dividers on them. This |
772 | * calculation does not result in an exact match to the |
773 | * downstream code, but it is very close to the values |
774 | * generated by their lookup table, and it appears |
775 | * to sync at a variety of resolutions. If someone |
776 | * can get a more accurate mathematical equation needed |
777 | * for these registers, this should be updated. |
778 | */ |
779 | |
780 | lpx = PS_TO_CYCLE(cfg.lpx, byte_clock); |
781 | hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock); |
782 | clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock); |
783 | clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); |
784 | clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); |
785 | clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock); |
786 | hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock); |
787 | hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock); |
788 | hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock); |
789 | |
790 | /* B D-PHY: D-PHY Master & Slave Analog Block control */ |
791 | reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | |
792 | reg_values[PHYCTRL_SLEW_UP]; |
793 | |
794 | samsung_dsim_write(dsi, idx: DSIM_PHYCTRL_REG, val: reg); |
795 | |
796 | /* |
797 | * T LPX: Transmitted length of any Low-Power state period |
798 | * T HS-EXIT: Time that the transmitter drives LP-11 following a HS |
799 | * burst |
800 | */ |
801 | |
802 | reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); |
803 | |
804 | samsung_dsim_write(dsi, idx: DSIM_PHYTIMING_REG, val: reg); |
805 | |
806 | /* |
807 | * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 |
808 | * Line state immediately before the HS-0 Line state starting the |
809 | * HS transmission |
810 | * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to |
811 | * transmitting the Clock. |
812 | * T CLK_POST: Time that the transmitter continues to send HS clock |
813 | * after the last associated Data Lane has transitioned to LP Mode |
814 | * Interval is defined as the period from the end of T HS-TRAIL to |
815 | * the beginning of T CLK-TRAIL |
816 | * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after |
817 | * the last payload clock bit of a HS transmission burst |
818 | */ |
819 | |
820 | reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | |
821 | DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | |
822 | DSIM_PHYTIMING1_CLK_POST(clk_post) | |
823 | DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); |
824 | |
825 | samsung_dsim_write(dsi, idx: DSIM_PHYTIMING1_REG, val: reg); |
826 | |
827 | /* |
828 | * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 |
829 | * Line state immediately before the HS-0 Line state starting the |
830 | * HS transmission |
831 | * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to |
832 | * transmitting the Sync sequence. |
833 | * T HS-TRAIL: Time that the transmitter drives the flipped differential |
834 | * state after last payload data bit of a HS transmission burst |
835 | */ |
836 | |
837 | reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | |
838 | DSIM_PHYTIMING2_HS_ZERO(hs_zero) | |
839 | DSIM_PHYTIMING2_HS_TRAIL(hs_trail); |
840 | |
841 | samsung_dsim_write(dsi, idx: DSIM_PHYTIMING2_REG, val: reg); |
842 | } |
843 | |
844 | static void samsung_dsim_disable_clock(struct samsung_dsim *dsi) |
845 | { |
846 | u32 reg; |
847 | |
848 | reg = samsung_dsim_read(dsi, idx: DSIM_CLKCTRL_REG); |
849 | reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK |
850 | | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); |
851 | samsung_dsim_write(dsi, idx: DSIM_CLKCTRL_REG, val: reg); |
852 | |
853 | reg = samsung_dsim_read(dsi, idx: DSIM_PLLCTRL_REG); |
854 | reg &= ~DSIM_PLL_EN; |
855 | samsung_dsim_write(dsi, idx: DSIM_PLLCTRL_REG, val: reg); |
856 | } |
857 | |
858 | static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane) |
859 | { |
860 | u32 reg = samsung_dsim_read(dsi, idx: DSIM_CONFIG_REG); |
861 | |
862 | reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | |
863 | DSIM_LANE_EN(lane)); |
864 | samsung_dsim_write(dsi, idx: DSIM_CONFIG_REG, val: reg); |
865 | } |
866 | |
867 | static int samsung_dsim_init_link(struct samsung_dsim *dsi) |
868 | { |
869 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
870 | int timeout; |
871 | u32 reg; |
872 | u32 lanes_mask; |
873 | |
874 | /* Initialize FIFO pointers */ |
875 | reg = samsung_dsim_read(dsi, idx: DSIM_FIFOCTRL_REG); |
876 | reg &= ~0x1f; |
877 | samsung_dsim_write(dsi, idx: DSIM_FIFOCTRL_REG, val: reg); |
878 | |
879 | usleep_range(min: 9000, max: 11000); |
880 | |
881 | reg |= 0x1f; |
882 | samsung_dsim_write(dsi, idx: DSIM_FIFOCTRL_REG, val: reg); |
883 | usleep_range(min: 9000, max: 11000); |
884 | |
885 | /* DSI configuration */ |
886 | reg = 0; |
887 | |
888 | /* |
889 | * The first bit of mode_flags specifies display configuration. |
890 | * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video |
891 | * mode, otherwise it will support command mode. |
892 | */ |
893 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
894 | reg |= DSIM_VIDEO_MODE; |
895 | |
896 | /* |
897 | * The user manual describes that following bits are ignored in |
898 | * command mode. |
899 | */ |
900 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) |
901 | reg |= DSIM_MFLUSH_VS; |
902 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
903 | reg |= DSIM_SYNC_INFORM; |
904 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) |
905 | reg |= DSIM_BURST_MODE; |
906 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) |
907 | reg |= DSIM_AUTO_MODE; |
908 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) |
909 | reg |= DSIM_HSE_DISABLE_MODE; |
910 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) |
911 | reg |= DSIM_HFP_DISABLE_MODE; |
912 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) |
913 | reg |= DSIM_HBP_DISABLE_MODE; |
914 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) |
915 | reg |= DSIM_HSA_DISABLE_MODE; |
916 | } |
917 | |
918 | if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) |
919 | reg |= DSIM_EOT_DISABLE; |
920 | |
921 | switch (dsi->format) { |
922 | case MIPI_DSI_FMT_RGB888: |
923 | reg |= DSIM_MAIN_PIX_FORMAT_RGB888; |
924 | break; |
925 | case MIPI_DSI_FMT_RGB666: |
926 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666; |
927 | break; |
928 | case MIPI_DSI_FMT_RGB666_PACKED: |
929 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; |
930 | break; |
931 | case MIPI_DSI_FMT_RGB565: |
932 | reg |= DSIM_MAIN_PIX_FORMAT_RGB565; |
933 | break; |
934 | default: |
935 | dev_err(dsi->dev, "invalid pixel format\n" ); |
936 | return -EINVAL; |
937 | } |
938 | |
939 | /* |
940 | * Use non-continuous clock mode if the periparal wants and |
941 | * host controller supports |
942 | * |
943 | * In non-continous clock mode, host controller will turn off |
944 | * the HS clock between high-speed transmissions to reduce |
945 | * power consumption. |
946 | */ |
947 | if (driver_data->has_clklane_stop && |
948 | dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) |
949 | reg |= DSIM_CLKLANE_STOP; |
950 | samsung_dsim_write(dsi, idx: DSIM_CONFIG_REG, val: reg); |
951 | |
952 | lanes_mask = BIT(dsi->lanes) - 1; |
953 | samsung_dsim_enable_lane(dsi, lane: lanes_mask); |
954 | |
955 | /* Check clock and data lane state are stop state */ |
956 | timeout = 100; |
957 | do { |
958 | if (timeout-- == 0) { |
959 | dev_err(dsi->dev, "waiting for bus lanes timed out\n" ); |
960 | return -EFAULT; |
961 | } |
962 | |
963 | reg = samsung_dsim_read(dsi, idx: DSIM_STATUS_REG); |
964 | if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) |
965 | != DSIM_STOP_STATE_DAT(lanes_mask)) |
966 | continue; |
967 | } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); |
968 | |
969 | reg = samsung_dsim_read(dsi, idx: DSIM_ESCMODE_REG); |
970 | reg &= ~DSIM_STOP_STATE_CNT_MASK; |
971 | reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); |
972 | |
973 | if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) |
974 | reg |= DSIM_FORCE_STOP_STATE; |
975 | |
976 | samsung_dsim_write(dsi, idx: DSIM_ESCMODE_REG, val: reg); |
977 | |
978 | reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); |
979 | samsung_dsim_write(dsi, idx: DSIM_TIMEOUT_REG, val: reg); |
980 | |
981 | return 0; |
982 | } |
983 | |
984 | static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) |
985 | { |
986 | struct drm_display_mode *m = &dsi->mode; |
987 | unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; |
988 | u32 reg; |
989 | |
990 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
991 | u64 byte_clk = dsi->hs_clock / 8; |
992 | u64 pix_clk = m->clock * 1000; |
993 | |
994 | int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); |
995 | int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); |
996 | int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); |
997 | |
998 | /* remove packet overhead when possible */ |
999 | hfp = max(hfp - 6, 0); |
1000 | hbp = max(hbp - 6, 0); |
1001 | hsa = max(hsa - 6, 0); |
1002 | |
1003 | dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u" , |
1004 | hfp, hbp, hsa); |
1005 | |
1006 | reg = DSIM_CMD_ALLOW(0xf) |
1007 | | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) |
1008 | | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); |
1009 | samsung_dsim_write(dsi, idx: DSIM_MVPORCH_REG, val: reg); |
1010 | |
1011 | reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); |
1012 | samsung_dsim_write(dsi, idx: DSIM_MHPORCH_REG, val: reg); |
1013 | |
1014 | reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) |
1015 | | DSIM_MAIN_HSA(hsa); |
1016 | samsung_dsim_write(dsi, idx: DSIM_MSYNC_REG, val: reg); |
1017 | } |
1018 | reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | |
1019 | DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); |
1020 | |
1021 | samsung_dsim_write(dsi, idx: DSIM_MDRESOL_REG, val: reg); |
1022 | |
1023 | dev_dbg(dsi->dev, "LCD size = %dx%d\n" , m->hdisplay, m->vdisplay); |
1024 | } |
1025 | |
1026 | static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable) |
1027 | { |
1028 | u32 reg; |
1029 | |
1030 | reg = samsung_dsim_read(dsi, idx: DSIM_MDRESOL_REG); |
1031 | if (enable) |
1032 | reg |= DSIM_MAIN_STAND_BY; |
1033 | else |
1034 | reg &= ~DSIM_MAIN_STAND_BY; |
1035 | samsung_dsim_write(dsi, idx: DSIM_MDRESOL_REG, val: reg); |
1036 | } |
1037 | |
1038 | static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi) |
1039 | { |
1040 | int timeout = 2000; |
1041 | |
1042 | do { |
1043 | u32 reg = samsung_dsim_read(dsi, idx: DSIM_FIFOCTRL_REG); |
1044 | |
1045 | if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) { |
1046 | if (reg & DSIM_SFR_HEADER_EMPTY) |
1047 | return 0; |
1048 | } else { |
1049 | if (!(reg & DSIM_SFR_HEADER_FULL)) { |
1050 | /* |
1051 | * Wait a little bit, so the pending data can |
1052 | * actually leave the FIFO to avoid overflow. |
1053 | */ |
1054 | if (!cond_resched()) |
1055 | usleep_range(min: 950, max: 1050); |
1056 | return 0; |
1057 | } |
1058 | } |
1059 | |
1060 | if (!cond_resched()) |
1061 | usleep_range(min: 950, max: 1050); |
1062 | } while (--timeout); |
1063 | |
1064 | return -ETIMEDOUT; |
1065 | } |
1066 | |
1067 | static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm) |
1068 | { |
1069 | u32 v = samsung_dsim_read(dsi, idx: DSIM_ESCMODE_REG); |
1070 | |
1071 | if (lpm) |
1072 | v |= DSIM_CMD_LPDT_LP; |
1073 | else |
1074 | v &= ~DSIM_CMD_LPDT_LP; |
1075 | |
1076 | samsung_dsim_write(dsi, idx: DSIM_ESCMODE_REG, val: v); |
1077 | } |
1078 | |
1079 | static void samsung_dsim_force_bta(struct samsung_dsim *dsi) |
1080 | { |
1081 | u32 v = samsung_dsim_read(dsi, idx: DSIM_ESCMODE_REG); |
1082 | |
1083 | v |= DSIM_FORCE_BTA; |
1084 | samsung_dsim_write(dsi, idx: DSIM_ESCMODE_REG, val: v); |
1085 | } |
1086 | |
1087 | static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi, |
1088 | struct samsung_dsim_transfer *xfer) |
1089 | { |
1090 | struct device *dev = dsi->dev; |
1091 | struct mipi_dsi_packet *pkt = &xfer->packet; |
1092 | const u8 *payload = pkt->payload + xfer->tx_done; |
1093 | u16 length = pkt->payload_length - xfer->tx_done; |
1094 | bool first = !xfer->tx_done; |
1095 | u32 reg; |
1096 | |
1097 | dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n" , |
1098 | xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); |
1099 | |
1100 | if (length > DSI_TX_FIFO_SIZE) |
1101 | length = DSI_TX_FIFO_SIZE; |
1102 | |
1103 | xfer->tx_done += length; |
1104 | |
1105 | /* Send payload */ |
1106 | while (length >= 4) { |
1107 | reg = get_unaligned_le32(p: payload); |
1108 | samsung_dsim_write(dsi, idx: DSIM_PAYLOAD_REG, val: reg); |
1109 | payload += 4; |
1110 | length -= 4; |
1111 | } |
1112 | |
1113 | reg = 0; |
1114 | switch (length) { |
1115 | case 3: |
1116 | reg |= payload[2] << 16; |
1117 | fallthrough; |
1118 | case 2: |
1119 | reg |= payload[1] << 8; |
1120 | fallthrough; |
1121 | case 1: |
1122 | reg |= payload[0]; |
1123 | samsung_dsim_write(dsi, idx: DSIM_PAYLOAD_REG, val: reg); |
1124 | break; |
1125 | } |
1126 | |
1127 | /* Send packet header */ |
1128 | if (!first) |
1129 | return; |
1130 | |
1131 | reg = get_unaligned_le32(p: pkt->header); |
1132 | if (samsung_dsim_wait_for_hdr_fifo(dsi)) { |
1133 | dev_err(dev, "waiting for header FIFO timed out\n" ); |
1134 | return; |
1135 | } |
1136 | |
1137 | if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, |
1138 | dsi->state & DSIM_STATE_CMD_LPM)) { |
1139 | samsung_dsim_set_cmd_lpm(dsi, lpm: xfer->flags & MIPI_DSI_MSG_USE_LPM); |
1140 | dsi->state ^= DSIM_STATE_CMD_LPM; |
1141 | } |
1142 | |
1143 | samsung_dsim_write(dsi, idx: DSIM_PKTHDR_REG, val: reg); |
1144 | |
1145 | if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) |
1146 | samsung_dsim_force_bta(dsi); |
1147 | } |
1148 | |
1149 | static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi, |
1150 | struct samsung_dsim_transfer *xfer) |
1151 | { |
1152 | u8 *payload = xfer->rx_payload + xfer->rx_done; |
1153 | bool first = !xfer->rx_done; |
1154 | struct device *dev = dsi->dev; |
1155 | u16 length; |
1156 | u32 reg; |
1157 | |
1158 | if (first) { |
1159 | reg = samsung_dsim_read(dsi, idx: DSIM_RXFIFO_REG); |
1160 | |
1161 | switch (reg & 0x3f) { |
1162 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: |
1163 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: |
1164 | if (xfer->rx_len >= 2) { |
1165 | payload[1] = reg >> 16; |
1166 | ++xfer->rx_done; |
1167 | } |
1168 | fallthrough; |
1169 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: |
1170 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: |
1171 | payload[0] = reg >> 8; |
1172 | ++xfer->rx_done; |
1173 | xfer->rx_len = xfer->rx_done; |
1174 | xfer->result = 0; |
1175 | goto clear_fifo; |
1176 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: |
1177 | dev_err(dev, "DSI Error Report: 0x%04x\n" , (reg >> 8) & 0xffff); |
1178 | xfer->result = 0; |
1179 | goto clear_fifo; |
1180 | } |
1181 | |
1182 | length = (reg >> 8) & 0xffff; |
1183 | if (length > xfer->rx_len) { |
1184 | dev_err(dev, |
1185 | "response too long (%u > %u bytes), stripping\n" , |
1186 | xfer->rx_len, length); |
1187 | length = xfer->rx_len; |
1188 | } else if (length < xfer->rx_len) { |
1189 | xfer->rx_len = length; |
1190 | } |
1191 | } |
1192 | |
1193 | length = xfer->rx_len - xfer->rx_done; |
1194 | xfer->rx_done += length; |
1195 | |
1196 | /* Receive payload */ |
1197 | while (length >= 4) { |
1198 | reg = samsung_dsim_read(dsi, idx: DSIM_RXFIFO_REG); |
1199 | payload[0] = (reg >> 0) & 0xff; |
1200 | payload[1] = (reg >> 8) & 0xff; |
1201 | payload[2] = (reg >> 16) & 0xff; |
1202 | payload[3] = (reg >> 24) & 0xff; |
1203 | payload += 4; |
1204 | length -= 4; |
1205 | } |
1206 | |
1207 | if (length) { |
1208 | reg = samsung_dsim_read(dsi, idx: DSIM_RXFIFO_REG); |
1209 | switch (length) { |
1210 | case 3: |
1211 | payload[2] = (reg >> 16) & 0xff; |
1212 | fallthrough; |
1213 | case 2: |
1214 | payload[1] = (reg >> 8) & 0xff; |
1215 | fallthrough; |
1216 | case 1: |
1217 | payload[0] = reg & 0xff; |
1218 | } |
1219 | } |
1220 | |
1221 | if (xfer->rx_done == xfer->rx_len) |
1222 | xfer->result = 0; |
1223 | |
1224 | clear_fifo: |
1225 | length = DSI_RX_FIFO_SIZE / 4; |
1226 | do { |
1227 | reg = samsung_dsim_read(dsi, idx: DSIM_RXFIFO_REG); |
1228 | if (reg == DSI_RX_FIFO_EMPTY) |
1229 | break; |
1230 | } while (--length); |
1231 | } |
1232 | |
1233 | static void samsung_dsim_transfer_start(struct samsung_dsim *dsi) |
1234 | { |
1235 | unsigned long flags; |
1236 | struct samsung_dsim_transfer *xfer; |
1237 | bool start = false; |
1238 | |
1239 | again: |
1240 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
1241 | |
1242 | if (list_empty(head: &dsi->transfer_list)) { |
1243 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1244 | return; |
1245 | } |
1246 | |
1247 | xfer = list_first_entry(&dsi->transfer_list, |
1248 | struct samsung_dsim_transfer, list); |
1249 | |
1250 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1251 | |
1252 | if (xfer->packet.payload_length && |
1253 | xfer->tx_done == xfer->packet.payload_length) |
1254 | /* waiting for RX */ |
1255 | return; |
1256 | |
1257 | samsung_dsim_send_to_fifo(dsi, xfer); |
1258 | |
1259 | if (xfer->packet.payload_length || xfer->rx_len) |
1260 | return; |
1261 | |
1262 | xfer->result = 0; |
1263 | complete(&xfer->completed); |
1264 | |
1265 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
1266 | |
1267 | list_del_init(entry: &xfer->list); |
1268 | start = !list_empty(head: &dsi->transfer_list); |
1269 | |
1270 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1271 | |
1272 | if (start) |
1273 | goto again; |
1274 | } |
1275 | |
1276 | static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi) |
1277 | { |
1278 | struct samsung_dsim_transfer *xfer; |
1279 | unsigned long flags; |
1280 | bool start = true; |
1281 | |
1282 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
1283 | |
1284 | if (list_empty(head: &dsi->transfer_list)) { |
1285 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1286 | return false; |
1287 | } |
1288 | |
1289 | xfer = list_first_entry(&dsi->transfer_list, |
1290 | struct samsung_dsim_transfer, list); |
1291 | |
1292 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1293 | |
1294 | dev_dbg(dsi->dev, |
1295 | "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n" , |
1296 | xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, |
1297 | xfer->rx_done); |
1298 | |
1299 | if (xfer->tx_done != xfer->packet.payload_length) |
1300 | return true; |
1301 | |
1302 | if (xfer->rx_done != xfer->rx_len) |
1303 | samsung_dsim_read_from_fifo(dsi, xfer); |
1304 | |
1305 | if (xfer->rx_done != xfer->rx_len) |
1306 | return true; |
1307 | |
1308 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
1309 | |
1310 | list_del_init(entry: &xfer->list); |
1311 | start = !list_empty(head: &dsi->transfer_list); |
1312 | |
1313 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1314 | |
1315 | if (!xfer->rx_len) |
1316 | xfer->result = 0; |
1317 | complete(&xfer->completed); |
1318 | |
1319 | return start; |
1320 | } |
1321 | |
1322 | static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi, |
1323 | struct samsung_dsim_transfer *xfer) |
1324 | { |
1325 | unsigned long flags; |
1326 | bool start; |
1327 | |
1328 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
1329 | |
1330 | if (!list_empty(head: &dsi->transfer_list) && |
1331 | xfer == list_first_entry(&dsi->transfer_list, |
1332 | struct samsung_dsim_transfer, list)) { |
1333 | list_del_init(entry: &xfer->list); |
1334 | start = !list_empty(head: &dsi->transfer_list); |
1335 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1336 | if (start) |
1337 | samsung_dsim_transfer_start(dsi); |
1338 | return; |
1339 | } |
1340 | |
1341 | list_del_init(entry: &xfer->list); |
1342 | |
1343 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1344 | } |
1345 | |
1346 | static int samsung_dsim_transfer(struct samsung_dsim *dsi, |
1347 | struct samsung_dsim_transfer *xfer) |
1348 | { |
1349 | unsigned long flags; |
1350 | bool stopped; |
1351 | |
1352 | xfer->tx_done = 0; |
1353 | xfer->rx_done = 0; |
1354 | xfer->result = -ETIMEDOUT; |
1355 | init_completion(x: &xfer->completed); |
1356 | |
1357 | spin_lock_irqsave(&dsi->transfer_lock, flags); |
1358 | |
1359 | stopped = list_empty(head: &dsi->transfer_list); |
1360 | list_add_tail(new: &xfer->list, head: &dsi->transfer_list); |
1361 | |
1362 | spin_unlock_irqrestore(lock: &dsi->transfer_lock, flags); |
1363 | |
1364 | if (stopped) |
1365 | samsung_dsim_transfer_start(dsi); |
1366 | |
1367 | wait_for_completion_timeout(x: &xfer->completed, |
1368 | timeout: msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); |
1369 | if (xfer->result == -ETIMEDOUT) { |
1370 | struct mipi_dsi_packet *pkt = &xfer->packet; |
1371 | |
1372 | samsung_dsim_remove_transfer(dsi, xfer); |
1373 | dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n" , 4, pkt->header, |
1374 | (int)pkt->payload_length, pkt->payload); |
1375 | return -ETIMEDOUT; |
1376 | } |
1377 | |
1378 | /* Also covers hardware timeout condition */ |
1379 | return xfer->result; |
1380 | } |
1381 | |
1382 | static irqreturn_t samsung_dsim_irq(int irq, void *dev_id) |
1383 | { |
1384 | struct samsung_dsim *dsi = dev_id; |
1385 | u32 status; |
1386 | |
1387 | status = samsung_dsim_read(dsi, idx: DSIM_INTSRC_REG); |
1388 | if (!status) { |
1389 | static unsigned long j; |
1390 | |
1391 | if (printk_timed_ratelimit(caller_jiffies: &j, interval_msec: 500)) |
1392 | dev_warn(dsi->dev, "spurious interrupt\n" ); |
1393 | return IRQ_HANDLED; |
1394 | } |
1395 | samsung_dsim_write(dsi, idx: DSIM_INTSRC_REG, val: status); |
1396 | |
1397 | if (status & DSIM_INT_SW_RST_RELEASE) { |
1398 | unsigned long mask = ~(DSIM_INT_RX_DONE | |
1399 | DSIM_INT_SFR_FIFO_EMPTY | |
1400 | DSIM_INT_SFR_HDR_FIFO_EMPTY | |
1401 | DSIM_INT_RX_ECC_ERR | |
1402 | DSIM_INT_SW_RST_RELEASE); |
1403 | samsung_dsim_write(dsi, idx: DSIM_INTMSK_REG, val: mask); |
1404 | complete(&dsi->completed); |
1405 | return IRQ_HANDLED; |
1406 | } |
1407 | |
1408 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
1409 | DSIM_INT_PLL_STABLE))) |
1410 | return IRQ_HANDLED; |
1411 | |
1412 | if (samsung_dsim_transfer_finish(dsi)) |
1413 | samsung_dsim_transfer_start(dsi); |
1414 | |
1415 | return IRQ_HANDLED; |
1416 | } |
1417 | |
1418 | static void samsung_dsim_enable_irq(struct samsung_dsim *dsi) |
1419 | { |
1420 | enable_irq(irq: dsi->irq); |
1421 | |
1422 | if (dsi->te_gpio) |
1423 | enable_irq(irq: gpiod_to_irq(desc: dsi->te_gpio)); |
1424 | } |
1425 | |
1426 | static void samsung_dsim_disable_irq(struct samsung_dsim *dsi) |
1427 | { |
1428 | if (dsi->te_gpio) |
1429 | disable_irq(irq: gpiod_to_irq(desc: dsi->te_gpio)); |
1430 | |
1431 | disable_irq(irq: dsi->irq); |
1432 | } |
1433 | |
1434 | static void samsung_dsim_set_stop_state(struct samsung_dsim *dsi, bool enable) |
1435 | { |
1436 | u32 reg = samsung_dsim_read(dsi, idx: DSIM_ESCMODE_REG); |
1437 | |
1438 | if (enable) |
1439 | reg |= DSIM_FORCE_STOP_STATE; |
1440 | else |
1441 | reg &= ~DSIM_FORCE_STOP_STATE; |
1442 | |
1443 | samsung_dsim_write(dsi, idx: DSIM_ESCMODE_REG, val: reg); |
1444 | } |
1445 | |
1446 | static int samsung_dsim_init(struct samsung_dsim *dsi) |
1447 | { |
1448 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
1449 | |
1450 | if (dsi->state & DSIM_STATE_INITIALIZED) |
1451 | return 0; |
1452 | |
1453 | samsung_dsim_reset(dsi); |
1454 | samsung_dsim_enable_irq(dsi); |
1455 | |
1456 | if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) |
1457 | samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1); |
1458 | |
1459 | samsung_dsim_enable_clock(dsi); |
1460 | if (driver_data->wait_for_reset) |
1461 | samsung_dsim_wait_for_reset(dsi); |
1462 | samsung_dsim_set_phy_ctrl(dsi); |
1463 | samsung_dsim_init_link(dsi); |
1464 | |
1465 | dsi->state |= DSIM_STATE_INITIALIZED; |
1466 | |
1467 | return 0; |
1468 | } |
1469 | |
1470 | static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, |
1471 | struct drm_bridge_state *old_bridge_state) |
1472 | { |
1473 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1474 | int ret; |
1475 | |
1476 | if (dsi->state & DSIM_STATE_ENABLED) |
1477 | return; |
1478 | |
1479 | ret = pm_runtime_resume_and_get(dev: dsi->dev); |
1480 | if (ret < 0) { |
1481 | dev_err(dsi->dev, "failed to enable DSI device.\n" ); |
1482 | return; |
1483 | } |
1484 | |
1485 | dsi->state |= DSIM_STATE_ENABLED; |
1486 | |
1487 | /* |
1488 | * For Exynos-DSIM the downstream bridge, or panel are expecting |
1489 | * the host initialization during DSI transfer. |
1490 | */ |
1491 | if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { |
1492 | ret = samsung_dsim_init(dsi); |
1493 | if (ret) |
1494 | return; |
1495 | |
1496 | samsung_dsim_set_display_mode(dsi); |
1497 | samsung_dsim_set_display_enable(dsi, enable: true); |
1498 | } |
1499 | } |
1500 | |
1501 | static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, |
1502 | struct drm_bridge_state *old_bridge_state) |
1503 | { |
1504 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1505 | |
1506 | if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { |
1507 | samsung_dsim_set_display_mode(dsi); |
1508 | samsung_dsim_set_display_enable(dsi, enable: true); |
1509 | } else { |
1510 | samsung_dsim_set_stop_state(dsi, enable: false); |
1511 | } |
1512 | |
1513 | dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; |
1514 | } |
1515 | |
1516 | static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, |
1517 | struct drm_bridge_state *old_bridge_state) |
1518 | { |
1519 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1520 | |
1521 | if (!(dsi->state & DSIM_STATE_ENABLED)) |
1522 | return; |
1523 | |
1524 | if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) |
1525 | samsung_dsim_set_stop_state(dsi, enable: true); |
1526 | |
1527 | dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; |
1528 | } |
1529 | |
1530 | static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, |
1531 | struct drm_bridge_state *old_bridge_state) |
1532 | { |
1533 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1534 | |
1535 | samsung_dsim_set_display_enable(dsi, enable: false); |
1536 | |
1537 | dsi->state &= ~DSIM_STATE_ENABLED; |
1538 | pm_runtime_put_sync(dev: dsi->dev); |
1539 | } |
1540 | |
1541 | /* |
1542 | * This pixel output formats list referenced from, |
1543 | * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 |
1544 | * 3.7.4 Pixel formats |
1545 | * Table 14. DSI pixel packing formats |
1546 | */ |
1547 | static const u32 samsung_dsim_pixel_output_fmts[] = { |
1548 | MEDIA_BUS_FMT_YUYV10_1X20, |
1549 | MEDIA_BUS_FMT_YUYV12_1X24, |
1550 | MEDIA_BUS_FMT_UYVY8_1X16, |
1551 | MEDIA_BUS_FMT_RGB101010_1X30, |
1552 | MEDIA_BUS_FMT_RGB121212_1X36, |
1553 | MEDIA_BUS_FMT_RGB565_1X16, |
1554 | MEDIA_BUS_FMT_RGB666_1X18, |
1555 | MEDIA_BUS_FMT_RGB888_1X24, |
1556 | }; |
1557 | |
1558 | static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt) |
1559 | { |
1560 | int i; |
1561 | |
1562 | if (fmt == MEDIA_BUS_FMT_FIXED) |
1563 | return false; |
1564 | |
1565 | for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) { |
1566 | if (samsung_dsim_pixel_output_fmts[i] == fmt) |
1567 | return true; |
1568 | } |
1569 | |
1570 | return false; |
1571 | } |
1572 | |
1573 | static u32 * |
1574 | samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge, |
1575 | struct drm_bridge_state *bridge_state, |
1576 | struct drm_crtc_state *crtc_state, |
1577 | struct drm_connector_state *conn_state, |
1578 | u32 output_fmt, |
1579 | unsigned int *num_input_fmts) |
1580 | { |
1581 | u32 *input_fmts; |
1582 | |
1583 | input_fmts = kmalloc(size: sizeof(*input_fmts), GFP_KERNEL); |
1584 | if (!input_fmts) |
1585 | return NULL; |
1586 | |
1587 | if (!samsung_dsim_pixel_output_fmt_supported(fmt: output_fmt)) |
1588 | /* |
1589 | * Some bridge/display drivers are still not able to pass the |
1590 | * correct format, so handle those pipelines by falling back |
1591 | * to the default format till the supported formats finalized. |
1592 | */ |
1593 | output_fmt = MEDIA_BUS_FMT_RGB888_1X24; |
1594 | |
1595 | input_fmts[0] = output_fmt; |
1596 | *num_input_fmts = 1; |
1597 | |
1598 | return input_fmts; |
1599 | } |
1600 | |
1601 | static int samsung_dsim_atomic_check(struct drm_bridge *bridge, |
1602 | struct drm_bridge_state *bridge_state, |
1603 | struct drm_crtc_state *crtc_state, |
1604 | struct drm_connector_state *conn_state) |
1605 | { |
1606 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1607 | struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; |
1608 | |
1609 | /* |
1610 | * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM |
1611 | * inverts HS/VS/DE sync signals polarity, therefore, while |
1612 | * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 |
1613 | * 13.6.3.5.2 RGB interface |
1614 | * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 |
1615 | * 13.6.2.7.2 RGB interface |
1616 | * both claim "Vsync, Hsync, and VDEN are active high signals.", the |
1617 | * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. |
1618 | * |
1619 | * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not |
1620 | * implement the same behavior, therefore LCDIFv3 must generate |
1621 | * HS/VS/DE signals active HIGH. |
1622 | */ |
1623 | if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { |
1624 | adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); |
1625 | adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
1626 | } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) { |
1627 | adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); |
1628 | adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
1629 | } |
1630 | |
1631 | return 0; |
1632 | } |
1633 | |
1634 | static void samsung_dsim_mode_set(struct drm_bridge *bridge, |
1635 | const struct drm_display_mode *mode, |
1636 | const struct drm_display_mode *adjusted_mode) |
1637 | { |
1638 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1639 | |
1640 | drm_mode_copy(dst: &dsi->mode, src: adjusted_mode); |
1641 | } |
1642 | |
1643 | static int samsung_dsim_attach(struct drm_bridge *bridge, |
1644 | enum drm_bridge_attach_flags flags) |
1645 | { |
1646 | struct samsung_dsim *dsi = bridge_to_dsi(b: bridge); |
1647 | |
1648 | return drm_bridge_attach(encoder: bridge->encoder, bridge: dsi->out_bridge, previous: bridge, |
1649 | flags); |
1650 | } |
1651 | |
1652 | static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = { |
1653 | .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, |
1654 | .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, |
1655 | .atomic_reset = drm_atomic_helper_bridge_reset, |
1656 | .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts, |
1657 | .atomic_check = samsung_dsim_atomic_check, |
1658 | .atomic_pre_enable = samsung_dsim_atomic_pre_enable, |
1659 | .atomic_enable = samsung_dsim_atomic_enable, |
1660 | .atomic_disable = samsung_dsim_atomic_disable, |
1661 | .atomic_post_disable = samsung_dsim_atomic_post_disable, |
1662 | .mode_set = samsung_dsim_mode_set, |
1663 | .attach = samsung_dsim_attach, |
1664 | }; |
1665 | |
1666 | static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id) |
1667 | { |
1668 | struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id; |
1669 | const struct samsung_dsim_plat_data *pdata = dsi->plat_data; |
1670 | |
1671 | if (pdata->host_ops && pdata->host_ops->te_irq_handler) |
1672 | return pdata->host_ops->te_irq_handler(dsi); |
1673 | |
1674 | return IRQ_HANDLED; |
1675 | } |
1676 | |
1677 | static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev) |
1678 | { |
1679 | int te_gpio_irq; |
1680 | int ret; |
1681 | |
1682 | dsi->te_gpio = devm_gpiod_get_optional(dev, con_id: "te" , flags: GPIOD_IN); |
1683 | if (!dsi->te_gpio) |
1684 | return 0; |
1685 | else if (IS_ERR(ptr: dsi->te_gpio)) |
1686 | return dev_err_probe(dev, err: PTR_ERR(ptr: dsi->te_gpio), fmt: "failed to get te GPIO\n" ); |
1687 | |
1688 | te_gpio_irq = gpiod_to_irq(desc: dsi->te_gpio); |
1689 | |
1690 | ret = request_threaded_irq(irq: te_gpio_irq, handler: samsung_dsim_te_irq_handler, NULL, |
1691 | IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, name: "TE" , dev: dsi); |
1692 | if (ret) { |
1693 | dev_err(dsi->dev, "request interrupt failed with %d\n" , ret); |
1694 | gpiod_put(desc: dsi->te_gpio); |
1695 | return ret; |
1696 | } |
1697 | |
1698 | return 0; |
1699 | } |
1700 | |
1701 | static int samsung_dsim_host_attach(struct mipi_dsi_host *host, |
1702 | struct mipi_dsi_device *device) |
1703 | { |
1704 | struct samsung_dsim *dsi = host_to_dsi(h: host); |
1705 | const struct samsung_dsim_plat_data *pdata = dsi->plat_data; |
1706 | struct device *dev = dsi->dev; |
1707 | struct device_node *np = dev->of_node; |
1708 | struct device_node *remote; |
1709 | struct drm_panel *panel; |
1710 | int ret; |
1711 | |
1712 | /* |
1713 | * Devices can also be child nodes when we also control that device |
1714 | * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). |
1715 | * |
1716 | * Lookup for a child node of the given parent that isn't either port |
1717 | * or ports. |
1718 | */ |
1719 | for_each_available_child_of_node(np, remote) { |
1720 | if (of_node_name_eq(np: remote, name: "port" ) || |
1721 | of_node_name_eq(np: remote, name: "ports" )) |
1722 | continue; |
1723 | |
1724 | goto of_find_panel_or_bridge; |
1725 | } |
1726 | |
1727 | /* |
1728 | * of_graph_get_remote_node() produces a noisy error message if port |
1729 | * node isn't found and the absence of the port is a legit case here, |
1730 | * so at first we silently check whether graph presents in the |
1731 | * device-tree node. |
1732 | */ |
1733 | if (!of_graph_is_present(node: np)) |
1734 | return -ENODEV; |
1735 | |
1736 | remote = of_graph_get_remote_node(node: np, port: 1, endpoint: 0); |
1737 | |
1738 | of_find_panel_or_bridge: |
1739 | if (!remote) |
1740 | return -ENODEV; |
1741 | |
1742 | panel = of_drm_find_panel(np: remote); |
1743 | if (!IS_ERR(ptr: panel)) { |
1744 | dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); |
1745 | } else { |
1746 | dsi->out_bridge = of_drm_find_bridge(np: remote); |
1747 | if (!dsi->out_bridge) |
1748 | dsi->out_bridge = ERR_PTR(error: -EINVAL); |
1749 | } |
1750 | |
1751 | of_node_put(node: remote); |
1752 | |
1753 | if (IS_ERR(ptr: dsi->out_bridge)) { |
1754 | ret = PTR_ERR(ptr: dsi->out_bridge); |
1755 | DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n" , ret); |
1756 | return ret; |
1757 | } |
1758 | |
1759 | DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n" , |
1760 | device->name, device->lanes, |
1761 | mipi_dsi_pixel_format_to_bpp(device->format), |
1762 | device->mode_flags); |
1763 | |
1764 | drm_bridge_add(bridge: &dsi->bridge); |
1765 | |
1766 | /* |
1767 | * This is a temporary solution and should be made by more generic way. |
1768 | * |
1769 | * If attached panel device is for command mode one, dsi should register |
1770 | * TE interrupt handler. |
1771 | */ |
1772 | if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { |
1773 | ret = samsung_dsim_register_te_irq(dsi, dev: &device->dev); |
1774 | if (ret) |
1775 | return ret; |
1776 | } |
1777 | |
1778 | if (pdata->host_ops && pdata->host_ops->attach) { |
1779 | ret = pdata->host_ops->attach(dsi, device); |
1780 | if (ret) |
1781 | return ret; |
1782 | } |
1783 | |
1784 | dsi->lanes = device->lanes; |
1785 | dsi->format = device->format; |
1786 | dsi->mode_flags = device->mode_flags; |
1787 | |
1788 | return 0; |
1789 | } |
1790 | |
1791 | static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi) |
1792 | { |
1793 | if (dsi->te_gpio) { |
1794 | free_irq(gpiod_to_irq(desc: dsi->te_gpio), dsi); |
1795 | gpiod_put(desc: dsi->te_gpio); |
1796 | } |
1797 | } |
1798 | |
1799 | static int samsung_dsim_host_detach(struct mipi_dsi_host *host, |
1800 | struct mipi_dsi_device *device) |
1801 | { |
1802 | struct samsung_dsim *dsi = host_to_dsi(h: host); |
1803 | const struct samsung_dsim_plat_data *pdata = dsi->plat_data; |
1804 | |
1805 | dsi->out_bridge = NULL; |
1806 | |
1807 | if (pdata->host_ops && pdata->host_ops->detach) |
1808 | pdata->host_ops->detach(dsi, device); |
1809 | |
1810 | samsung_dsim_unregister_te_irq(dsi); |
1811 | |
1812 | drm_bridge_remove(bridge: &dsi->bridge); |
1813 | |
1814 | return 0; |
1815 | } |
1816 | |
1817 | static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host, |
1818 | const struct mipi_dsi_msg *msg) |
1819 | { |
1820 | struct samsung_dsim *dsi = host_to_dsi(h: host); |
1821 | struct samsung_dsim_transfer xfer; |
1822 | int ret; |
1823 | |
1824 | if (!(dsi->state & DSIM_STATE_ENABLED)) |
1825 | return -EINVAL; |
1826 | |
1827 | ret = samsung_dsim_init(dsi); |
1828 | if (ret) |
1829 | return ret; |
1830 | |
1831 | samsung_dsim_set_stop_state(dsi, enable: false); |
1832 | |
1833 | ret = mipi_dsi_create_packet(packet: &xfer.packet, msg); |
1834 | if (ret < 0) |
1835 | return ret; |
1836 | |
1837 | xfer.rx_len = msg->rx_len; |
1838 | xfer.rx_payload = msg->rx_buf; |
1839 | xfer.flags = msg->flags; |
1840 | |
1841 | ret = samsung_dsim_transfer(dsi, xfer: &xfer); |
1842 | return (ret < 0) ? ret : xfer.rx_done; |
1843 | } |
1844 | |
1845 | static const struct mipi_dsi_host_ops samsung_dsim_ops = { |
1846 | .attach = samsung_dsim_host_attach, |
1847 | .detach = samsung_dsim_host_detach, |
1848 | .transfer = samsung_dsim_host_transfer, |
1849 | }; |
1850 | |
1851 | static int samsung_dsim_of_read_u32(const struct device_node *np, |
1852 | const char *propname, u32 *out_value, bool optional) |
1853 | { |
1854 | int ret = of_property_read_u32(np, propname, out_value); |
1855 | |
1856 | if (ret < 0 && !optional) |
1857 | pr_err("%pOF: failed to get '%s' property\n" , np, propname); |
1858 | |
1859 | return ret; |
1860 | } |
1861 | |
1862 | static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) |
1863 | { |
1864 | struct device *dev = dsi->dev; |
1865 | struct device_node *node = dev->of_node; |
1866 | u32 lane_polarities[5] = { 0 }; |
1867 | struct device_node *endpoint; |
1868 | int i, nr_lanes, ret; |
1869 | |
1870 | ret = samsung_dsim_of_read_u32(np: node, propname: "samsung,pll-clock-frequency" , |
1871 | out_value: &dsi->pll_clk_rate, optional: 1); |
1872 | /* If it doesn't exist, read it from the clock instead of failing */ |
1873 | if (ret < 0) { |
1874 | dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n" ); |
1875 | dsi->pll_clk = devm_clk_get(dev, id: "sclk_mipi" ); |
1876 | if (IS_ERR(ptr: dsi->pll_clk)) |
1877 | return PTR_ERR(ptr: dsi->pll_clk); |
1878 | } |
1879 | |
1880 | /* If it doesn't exist, use pixel clock instead of failing */ |
1881 | ret = samsung_dsim_of_read_u32(np: node, propname: "samsung,burst-clock-frequency" , |
1882 | out_value: &dsi->burst_clk_rate, optional: 1); |
1883 | if (ret < 0) { |
1884 | dev_dbg(dev, "Using pixel clock for HS clock frequency\n" ); |
1885 | dsi->burst_clk_rate = 0; |
1886 | } |
1887 | |
1888 | ret = samsung_dsim_of_read_u32(np: node, propname: "samsung,esc-clock-frequency" , |
1889 | out_value: &dsi->esc_clk_rate, optional: 0); |
1890 | if (ret < 0) |
1891 | return ret; |
1892 | |
1893 | endpoint = of_graph_get_endpoint_by_regs(parent: node, port_reg: 1, reg: -1); |
1894 | nr_lanes = of_property_count_u32_elems(np: endpoint, propname: "data-lanes" ); |
1895 | if (nr_lanes > 0 && nr_lanes <= 4) { |
1896 | /* Polarity 0 is clock lane, 1..4 are data lanes. */ |
1897 | of_property_read_u32_array(np: endpoint, propname: "lane-polarities" , |
1898 | out_values: lane_polarities, sz: nr_lanes + 1); |
1899 | for (i = 1; i <= nr_lanes; i++) { |
1900 | if (lane_polarities[1] != lane_polarities[i]) |
1901 | DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match" ); |
1902 | } |
1903 | if (lane_polarities[0]) |
1904 | dsi->swap_dn_dp_clk = true; |
1905 | if (lane_polarities[1]) |
1906 | dsi->swap_dn_dp_data = true; |
1907 | } |
1908 | |
1909 | return 0; |
1910 | } |
1911 | |
1912 | static int generic_dsim_register_host(struct samsung_dsim *dsi) |
1913 | { |
1914 | return mipi_dsi_host_register(host: &dsi->dsi_host); |
1915 | } |
1916 | |
1917 | static void generic_dsim_unregister_host(struct samsung_dsim *dsi) |
1918 | { |
1919 | mipi_dsi_host_unregister(host: &dsi->dsi_host); |
1920 | } |
1921 | |
1922 | static const struct samsung_dsim_host_ops generic_dsim_host_ops = { |
1923 | .register_host = generic_dsim_register_host, |
1924 | .unregister_host = generic_dsim_unregister_host, |
1925 | }; |
1926 | |
1927 | static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = { |
1928 | .input_bus_flags = DRM_BUS_FLAG_DE_HIGH, |
1929 | }; |
1930 | |
1931 | static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = { |
1932 | .input_bus_flags = DRM_BUS_FLAG_DE_LOW, |
1933 | }; |
1934 | |
1935 | int samsung_dsim_probe(struct platform_device *pdev) |
1936 | { |
1937 | struct device *dev = &pdev->dev; |
1938 | struct samsung_dsim *dsi; |
1939 | int ret, i; |
1940 | |
1941 | dsi = devm_kzalloc(dev, size: sizeof(*dsi), GFP_KERNEL); |
1942 | if (!dsi) |
1943 | return -ENOMEM; |
1944 | |
1945 | init_completion(x: &dsi->completed); |
1946 | spin_lock_init(&dsi->transfer_lock); |
1947 | INIT_LIST_HEAD(list: &dsi->transfer_list); |
1948 | |
1949 | dsi->dsi_host.ops = &samsung_dsim_ops; |
1950 | dsi->dsi_host.dev = dev; |
1951 | |
1952 | dsi->dev = dev; |
1953 | dsi->plat_data = of_device_get_match_data(dev); |
1954 | dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type]; |
1955 | |
1956 | dsi->supplies[0].supply = "vddcore" ; |
1957 | dsi->supplies[1].supply = "vddio" ; |
1958 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), |
1959 | consumers: dsi->supplies); |
1960 | if (ret) |
1961 | return dev_err_probe(dev, err: ret, fmt: "failed to get regulators\n" ); |
1962 | |
1963 | dsi->clks = devm_kcalloc(dev, n: dsi->driver_data->num_clks, |
1964 | size: sizeof(*dsi->clks), GFP_KERNEL); |
1965 | if (!dsi->clks) |
1966 | return -ENOMEM; |
1967 | |
1968 | for (i = 0; i < dsi->driver_data->num_clks; i++) { |
1969 | dsi->clks[i] = devm_clk_get(dev, id: clk_names[i]); |
1970 | if (IS_ERR(ptr: dsi->clks[i])) { |
1971 | if (strcmp(clk_names[i], "sclk_mipi" ) == 0) { |
1972 | dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); |
1973 | if (!IS_ERR(ptr: dsi->clks[i])) |
1974 | continue; |
1975 | } |
1976 | |
1977 | dev_info(dev, "failed to get the clock: %s\n" , clk_names[i]); |
1978 | return PTR_ERR(ptr: dsi->clks[i]); |
1979 | } |
1980 | } |
1981 | |
1982 | dsi->reg_base = devm_platform_ioremap_resource(pdev, index: 0); |
1983 | if (IS_ERR(ptr: dsi->reg_base)) |
1984 | return PTR_ERR(ptr: dsi->reg_base); |
1985 | |
1986 | dsi->phy = devm_phy_optional_get(dev, string: "dsim" ); |
1987 | if (IS_ERR(ptr: dsi->phy)) { |
1988 | dev_info(dev, "failed to get dsim phy\n" ); |
1989 | return PTR_ERR(ptr: dsi->phy); |
1990 | } |
1991 | |
1992 | dsi->irq = platform_get_irq(pdev, 0); |
1993 | if (dsi->irq < 0) |
1994 | return dsi->irq; |
1995 | |
1996 | ret = devm_request_threaded_irq(dev, irq: dsi->irq, NULL, |
1997 | thread_fn: samsung_dsim_irq, |
1998 | IRQF_ONESHOT | IRQF_NO_AUTOEN, |
1999 | devname: dev_name(dev), dev_id: dsi); |
2000 | if (ret) { |
2001 | dev_err(dev, "failed to request dsi irq\n" ); |
2002 | return ret; |
2003 | } |
2004 | |
2005 | ret = samsung_dsim_parse_dt(dsi); |
2006 | if (ret) |
2007 | return ret; |
2008 | |
2009 | platform_set_drvdata(pdev, data: dsi); |
2010 | |
2011 | pm_runtime_enable(dev); |
2012 | |
2013 | dsi->bridge.funcs = &samsung_dsim_bridge_funcs; |
2014 | dsi->bridge.of_node = dev->of_node; |
2015 | dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; |
2016 | |
2017 | /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ |
2018 | if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) |
2019 | dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low; |
2020 | else |
2021 | dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high; |
2022 | |
2023 | if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) |
2024 | ret = dsi->plat_data->host_ops->register_host(dsi); |
2025 | |
2026 | if (ret) |
2027 | goto err_disable_runtime; |
2028 | |
2029 | return 0; |
2030 | |
2031 | err_disable_runtime: |
2032 | pm_runtime_disable(dev); |
2033 | |
2034 | return ret; |
2035 | } |
2036 | EXPORT_SYMBOL_GPL(samsung_dsim_probe); |
2037 | |
2038 | void samsung_dsim_remove(struct platform_device *pdev) |
2039 | { |
2040 | struct samsung_dsim *dsi = platform_get_drvdata(pdev); |
2041 | |
2042 | pm_runtime_disable(dev: &pdev->dev); |
2043 | |
2044 | if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host) |
2045 | dsi->plat_data->host_ops->unregister_host(dsi); |
2046 | } |
2047 | EXPORT_SYMBOL_GPL(samsung_dsim_remove); |
2048 | |
2049 | static int __maybe_unused samsung_dsim_suspend(struct device *dev) |
2050 | { |
2051 | struct samsung_dsim *dsi = dev_get_drvdata(dev); |
2052 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
2053 | int ret, i; |
2054 | |
2055 | usleep_range(min: 10000, max: 20000); |
2056 | |
2057 | if (dsi->state & DSIM_STATE_INITIALIZED) { |
2058 | dsi->state &= ~DSIM_STATE_INITIALIZED; |
2059 | |
2060 | samsung_dsim_disable_clock(dsi); |
2061 | |
2062 | samsung_dsim_disable_irq(dsi); |
2063 | } |
2064 | |
2065 | dsi->state &= ~DSIM_STATE_CMD_LPM; |
2066 | |
2067 | phy_power_off(phy: dsi->phy); |
2068 | |
2069 | for (i = driver_data->num_clks - 1; i > -1; i--) |
2070 | clk_disable_unprepare(clk: dsi->clks[i]); |
2071 | |
2072 | ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), consumers: dsi->supplies); |
2073 | if (ret < 0) |
2074 | dev_err(dsi->dev, "cannot disable regulators %d\n" , ret); |
2075 | |
2076 | return 0; |
2077 | } |
2078 | |
2079 | static int __maybe_unused samsung_dsim_resume(struct device *dev) |
2080 | { |
2081 | struct samsung_dsim *dsi = dev_get_drvdata(dev); |
2082 | const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; |
2083 | int ret, i; |
2084 | |
2085 | ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), consumers: dsi->supplies); |
2086 | if (ret < 0) { |
2087 | dev_err(dsi->dev, "cannot enable regulators %d\n" , ret); |
2088 | return ret; |
2089 | } |
2090 | |
2091 | for (i = 0; i < driver_data->num_clks; i++) { |
2092 | ret = clk_prepare_enable(clk: dsi->clks[i]); |
2093 | if (ret < 0) |
2094 | goto err_clk; |
2095 | } |
2096 | |
2097 | ret = phy_power_on(phy: dsi->phy); |
2098 | if (ret < 0) { |
2099 | dev_err(dsi->dev, "cannot enable phy %d\n" , ret); |
2100 | goto err_clk; |
2101 | } |
2102 | |
2103 | return 0; |
2104 | |
2105 | err_clk: |
2106 | while (--i > -1) |
2107 | clk_disable_unprepare(clk: dsi->clks[i]); |
2108 | regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), consumers: dsi->supplies); |
2109 | |
2110 | return ret; |
2111 | } |
2112 | |
2113 | const struct dev_pm_ops samsung_dsim_pm_ops = { |
2114 | SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL) |
2115 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
2116 | pm_runtime_force_resume) |
2117 | }; |
2118 | EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); |
2119 | |
2120 | static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { |
2121 | .hw_type = DSIM_TYPE_IMX8MM, |
2122 | .host_ops = &generic_dsim_host_ops, |
2123 | }; |
2124 | |
2125 | static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = { |
2126 | .hw_type = DSIM_TYPE_IMX8MP, |
2127 | .host_ops = &generic_dsim_host_ops, |
2128 | }; |
2129 | |
2130 | static const struct of_device_id samsung_dsim_of_match[] = { |
2131 | { |
2132 | .compatible = "fsl,imx8mm-mipi-dsim" , |
2133 | .data = &samsung_dsim_imx8mm_pdata, |
2134 | }, |
2135 | { |
2136 | .compatible = "fsl,imx8mp-mipi-dsim" , |
2137 | .data = &samsung_dsim_imx8mp_pdata, |
2138 | }, |
2139 | { /* sentinel. */ } |
2140 | }; |
2141 | MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); |
2142 | |
2143 | static struct platform_driver samsung_dsim_driver = { |
2144 | .probe = samsung_dsim_probe, |
2145 | .remove_new = samsung_dsim_remove, |
2146 | .driver = { |
2147 | .name = "samsung-dsim" , |
2148 | .pm = &samsung_dsim_pm_ops, |
2149 | .of_match_table = samsung_dsim_of_match, |
2150 | }, |
2151 | }; |
2152 | |
2153 | module_platform_driver(samsung_dsim_driver); |
2154 | |
2155 | MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>" ); |
2156 | MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge" ); |
2157 | MODULE_LICENSE("GPL" ); |
2158 | |