1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright © 2022 Intel Corporation |
4 | */ |
5 | |
6 | #include "i915_drv.h" |
7 | #include "i915_reg.h" |
8 | |
9 | #include "vlv_sideband_reg.h" |
10 | |
11 | #include "intel_display_power_map.h" |
12 | #include "intel_display_power_well.h" |
13 | #include "intel_display_types.h" |
14 | |
15 | #define __LIST_INLINE_ELEMS(__elem_type, ...) \ |
16 | ((__elem_type[]) { __VA_ARGS__ }) |
17 | |
18 | #define __LIST(__elems) { \ |
19 | .list = __elems, \ |
20 | .count = ARRAY_SIZE(__elems), \ |
21 | } |
22 | |
23 | #define I915_PW_DOMAINS(...) \ |
24 | (const struct i915_power_domain_list) \ |
25 | __LIST(__LIST_INLINE_ELEMS(const enum intel_display_power_domain, __VA_ARGS__)) |
26 | |
27 | #define I915_DECL_PW_DOMAINS(__name, ...) \ |
28 | static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__) |
29 | |
30 | /* Zero-length list assigns all power domains, a NULL list assigns none. */ |
31 | #define I915_PW_DOMAINS_NONE NULL |
32 | #define I915_PW_DOMAINS_ALL /* zero-length list */ |
33 | |
34 | #define I915_PW_INSTANCES(...) \ |
35 | (const struct i915_power_well_instance_list) \ |
36 | __LIST(__LIST_INLINE_ELEMS(const struct i915_power_well_instance, __VA_ARGS__)) |
37 | |
38 | #define I915_PW(_name, _domain_list, ...) \ |
39 | { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ } |
40 | |
41 | |
42 | struct i915_power_well_desc_list { |
43 | const struct i915_power_well_desc *list; |
44 | u8 count; |
45 | }; |
46 | |
47 | #define I915_PW_DESCRIPTORS(x) __LIST(x) |
48 | |
49 | |
50 | I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL); |
51 | |
52 | static const struct i915_power_well_desc i9xx_power_wells_always_on[] = { |
53 | { |
54 | .instances = &I915_PW_INSTANCES( |
55 | I915_PW("always-on" , &i9xx_pwdoms_always_on), |
56 | ), |
57 | .ops = &i9xx_always_on_power_well_ops, |
58 | .always_on = true, |
59 | }, |
60 | }; |
61 | |
62 | static const struct i915_power_well_desc_list i9xx_power_wells[] = { |
63 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
64 | }; |
65 | |
66 | I915_DECL_PW_DOMAINS(i830_pwdoms_pipes, |
67 | POWER_DOMAIN_PIPE_A, |
68 | POWER_DOMAIN_PIPE_B, |
69 | POWER_DOMAIN_PIPE_PANEL_FITTER_A, |
70 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, |
71 | POWER_DOMAIN_TRANSCODER_A, |
72 | POWER_DOMAIN_TRANSCODER_B, |
73 | POWER_DOMAIN_INIT); |
74 | |
75 | static const struct i915_power_well_desc i830_power_wells_main[] = { |
76 | { |
77 | .instances = &I915_PW_INSTANCES( |
78 | I915_PW("pipes" , &i830_pwdoms_pipes), |
79 | ), |
80 | .ops = &i830_pipes_power_well_ops, |
81 | }, |
82 | }; |
83 | |
84 | static const struct i915_power_well_desc_list i830_power_wells[] = { |
85 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
86 | I915_PW_DESCRIPTORS(i830_power_wells_main), |
87 | }; |
88 | |
89 | I915_DECL_PW_DOMAINS(hsw_pwdoms_display, |
90 | POWER_DOMAIN_PIPE_B, |
91 | POWER_DOMAIN_PIPE_C, |
92 | POWER_DOMAIN_PIPE_PANEL_FITTER_A, |
93 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, |
94 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, |
95 | POWER_DOMAIN_TRANSCODER_A, |
96 | POWER_DOMAIN_TRANSCODER_B, |
97 | POWER_DOMAIN_TRANSCODER_C, |
98 | POWER_DOMAIN_PORT_DDI_LANES_B, |
99 | POWER_DOMAIN_PORT_DDI_LANES_C, |
100 | POWER_DOMAIN_PORT_DDI_LANES_D, |
101 | POWER_DOMAIN_PORT_CRT, /* DDI E */ |
102 | POWER_DOMAIN_VGA, |
103 | POWER_DOMAIN_AUDIO_MMIO, |
104 | POWER_DOMAIN_AUDIO_PLAYBACK, |
105 | POWER_DOMAIN_INIT); |
106 | |
107 | static const struct i915_power_well_desc hsw_power_wells_main[] = { |
108 | { |
109 | .instances = &I915_PW_INSTANCES( |
110 | I915_PW("display" , &hsw_pwdoms_display, |
111 | .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, |
112 | .id = HSW_DISP_PW_GLOBAL), |
113 | ), |
114 | .ops = &hsw_power_well_ops, |
115 | .has_vga = true, |
116 | }, |
117 | }; |
118 | |
119 | static const struct i915_power_well_desc_list hsw_power_wells[] = { |
120 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
121 | I915_PW_DESCRIPTORS(hsw_power_wells_main), |
122 | }; |
123 | |
124 | I915_DECL_PW_DOMAINS(bdw_pwdoms_display, |
125 | POWER_DOMAIN_PIPE_B, |
126 | POWER_DOMAIN_PIPE_C, |
127 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, |
128 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, |
129 | POWER_DOMAIN_TRANSCODER_A, |
130 | POWER_DOMAIN_TRANSCODER_B, |
131 | POWER_DOMAIN_TRANSCODER_C, |
132 | POWER_DOMAIN_PORT_DDI_LANES_B, |
133 | POWER_DOMAIN_PORT_DDI_LANES_C, |
134 | POWER_DOMAIN_PORT_DDI_LANES_D, |
135 | POWER_DOMAIN_PORT_CRT, /* DDI E */ |
136 | POWER_DOMAIN_VGA, |
137 | POWER_DOMAIN_AUDIO_MMIO, |
138 | POWER_DOMAIN_AUDIO_PLAYBACK, |
139 | POWER_DOMAIN_INIT); |
140 | |
141 | static const struct i915_power_well_desc bdw_power_wells_main[] = { |
142 | { |
143 | .instances = &I915_PW_INSTANCES( |
144 | I915_PW("display" , &bdw_pwdoms_display, |
145 | .hsw.idx = HSW_PW_CTL_IDX_GLOBAL, |
146 | .id = HSW_DISP_PW_GLOBAL), |
147 | ), |
148 | .ops = &hsw_power_well_ops, |
149 | .has_vga = true, |
150 | .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), |
151 | }, |
152 | }; |
153 | |
154 | static const struct i915_power_well_desc_list bdw_power_wells[] = { |
155 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
156 | I915_PW_DESCRIPTORS(bdw_power_wells_main), |
157 | }; |
158 | |
159 | I915_DECL_PW_DOMAINS(vlv_pwdoms_display, |
160 | POWER_DOMAIN_DISPLAY_CORE, |
161 | POWER_DOMAIN_PIPE_A, |
162 | POWER_DOMAIN_PIPE_B, |
163 | POWER_DOMAIN_PIPE_PANEL_FITTER_A, |
164 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, |
165 | POWER_DOMAIN_TRANSCODER_A, |
166 | POWER_DOMAIN_TRANSCODER_B, |
167 | POWER_DOMAIN_PORT_DDI_LANES_B, |
168 | POWER_DOMAIN_PORT_DDI_LANES_C, |
169 | POWER_DOMAIN_PORT_DSI, |
170 | POWER_DOMAIN_PORT_CRT, |
171 | POWER_DOMAIN_VGA, |
172 | POWER_DOMAIN_AUDIO_MMIO, |
173 | POWER_DOMAIN_AUDIO_PLAYBACK, |
174 | POWER_DOMAIN_AUX_IO_B, |
175 | POWER_DOMAIN_AUX_IO_C, |
176 | POWER_DOMAIN_AUX_B, |
177 | POWER_DOMAIN_AUX_C, |
178 | POWER_DOMAIN_GMBUS, |
179 | POWER_DOMAIN_INIT); |
180 | |
181 | I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc, |
182 | POWER_DOMAIN_PORT_DDI_LANES_B, |
183 | POWER_DOMAIN_PORT_DDI_LANES_C, |
184 | POWER_DOMAIN_PORT_CRT, |
185 | POWER_DOMAIN_AUX_IO_B, |
186 | POWER_DOMAIN_AUX_IO_C, |
187 | POWER_DOMAIN_AUX_B, |
188 | POWER_DOMAIN_AUX_C, |
189 | POWER_DOMAIN_INIT); |
190 | |
191 | I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes, |
192 | POWER_DOMAIN_PORT_DDI_LANES_B, |
193 | POWER_DOMAIN_PORT_DDI_LANES_C, |
194 | POWER_DOMAIN_AUX_IO_B, |
195 | POWER_DOMAIN_AUX_IO_C, |
196 | POWER_DOMAIN_AUX_B, |
197 | POWER_DOMAIN_AUX_C, |
198 | POWER_DOMAIN_INIT); |
199 | |
200 | static const struct i915_power_well_desc vlv_power_wells_main[] = { |
201 | { |
202 | .instances = &I915_PW_INSTANCES( |
203 | I915_PW("display" , &vlv_pwdoms_display, |
204 | .vlv.idx = PUNIT_PWGT_IDX_DISP2D, |
205 | .id = VLV_DISP_PW_DISP2D), |
206 | ), |
207 | .ops = &vlv_display_power_well_ops, |
208 | }, { |
209 | .instances = &I915_PW_INSTANCES( |
210 | I915_PW("dpio-tx-b-01" , &vlv_pwdoms_dpio_tx_bc_lanes, |
211 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01), |
212 | I915_PW("dpio-tx-b-23" , &vlv_pwdoms_dpio_tx_bc_lanes, |
213 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23), |
214 | I915_PW("dpio-tx-c-01" , &vlv_pwdoms_dpio_tx_bc_lanes, |
215 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01), |
216 | I915_PW("dpio-tx-c-23" , &vlv_pwdoms_dpio_tx_bc_lanes, |
217 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23), |
218 | ), |
219 | .ops = &vlv_dpio_power_well_ops, |
220 | }, { |
221 | .instances = &I915_PW_INSTANCES( |
222 | I915_PW("dpio-common" , &vlv_pwdoms_dpio_cmn_bc, |
223 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, |
224 | .id = VLV_DISP_PW_DPIO_CMN_BC), |
225 | ), |
226 | .ops = &vlv_dpio_cmn_power_well_ops, |
227 | }, |
228 | }; |
229 | |
230 | static const struct i915_power_well_desc_list vlv_power_wells[] = { |
231 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
232 | I915_PW_DESCRIPTORS(vlv_power_wells_main), |
233 | }; |
234 | |
235 | I915_DECL_PW_DOMAINS(chv_pwdoms_display, |
236 | POWER_DOMAIN_DISPLAY_CORE, |
237 | POWER_DOMAIN_PIPE_A, |
238 | POWER_DOMAIN_PIPE_B, |
239 | POWER_DOMAIN_PIPE_C, |
240 | POWER_DOMAIN_PIPE_PANEL_FITTER_A, |
241 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, |
242 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, |
243 | POWER_DOMAIN_TRANSCODER_A, |
244 | POWER_DOMAIN_TRANSCODER_B, |
245 | POWER_DOMAIN_TRANSCODER_C, |
246 | POWER_DOMAIN_PORT_DDI_LANES_B, |
247 | POWER_DOMAIN_PORT_DDI_LANES_C, |
248 | POWER_DOMAIN_PORT_DDI_LANES_D, |
249 | POWER_DOMAIN_PORT_DSI, |
250 | POWER_DOMAIN_VGA, |
251 | POWER_DOMAIN_AUDIO_MMIO, |
252 | POWER_DOMAIN_AUDIO_PLAYBACK, |
253 | POWER_DOMAIN_AUX_IO_B, |
254 | POWER_DOMAIN_AUX_IO_C, |
255 | POWER_DOMAIN_AUX_IO_D, |
256 | POWER_DOMAIN_AUX_B, |
257 | POWER_DOMAIN_AUX_C, |
258 | POWER_DOMAIN_AUX_D, |
259 | POWER_DOMAIN_GMBUS, |
260 | POWER_DOMAIN_INIT); |
261 | |
262 | I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc, |
263 | POWER_DOMAIN_PORT_DDI_LANES_B, |
264 | POWER_DOMAIN_PORT_DDI_LANES_C, |
265 | POWER_DOMAIN_AUX_IO_B, |
266 | POWER_DOMAIN_AUX_IO_C, |
267 | POWER_DOMAIN_AUX_B, |
268 | POWER_DOMAIN_AUX_C, |
269 | POWER_DOMAIN_INIT); |
270 | |
271 | I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d, |
272 | POWER_DOMAIN_PORT_DDI_LANES_D, |
273 | POWER_DOMAIN_AUX_IO_D, |
274 | POWER_DOMAIN_AUX_D, |
275 | POWER_DOMAIN_INIT); |
276 | |
277 | static const struct i915_power_well_desc chv_power_wells_main[] = { |
278 | { |
279 | /* |
280 | * Pipe A power well is the new disp2d well. Pipe B and C |
281 | * power wells don't actually exist. Pipe A power well is |
282 | * required for any pipe to work. |
283 | */ |
284 | .instances = &I915_PW_INSTANCES( |
285 | I915_PW("display" , &chv_pwdoms_display), |
286 | ), |
287 | .ops = &chv_pipe_power_well_ops, |
288 | }, { |
289 | .instances = &I915_PW_INSTANCES( |
290 | I915_PW("dpio-common-bc" , &chv_pwdoms_dpio_cmn_bc, |
291 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC, |
292 | .id = VLV_DISP_PW_DPIO_CMN_BC), |
293 | I915_PW("dpio-common-d" , &chv_pwdoms_dpio_cmn_d, |
294 | .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D, |
295 | .id = CHV_DISP_PW_DPIO_CMN_D), |
296 | ), |
297 | .ops = &chv_dpio_cmn_power_well_ops, |
298 | }, |
299 | }; |
300 | |
301 | static const struct i915_power_well_desc_list chv_power_wells[] = { |
302 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
303 | I915_PW_DESCRIPTORS(chv_power_wells_main), |
304 | }; |
305 | |
306 | #define SKL_PW_2_POWER_DOMAINS \ |
307 | POWER_DOMAIN_PIPE_B, \ |
308 | POWER_DOMAIN_PIPE_C, \ |
309 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
310 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ |
311 | POWER_DOMAIN_TRANSCODER_A, \ |
312 | POWER_DOMAIN_TRANSCODER_B, \ |
313 | POWER_DOMAIN_TRANSCODER_C, \ |
314 | POWER_DOMAIN_PORT_DDI_LANES_B, \ |
315 | POWER_DOMAIN_PORT_DDI_LANES_C, \ |
316 | POWER_DOMAIN_PORT_DDI_LANES_D, \ |
317 | POWER_DOMAIN_PORT_DDI_LANES_E, \ |
318 | POWER_DOMAIN_VGA, \ |
319 | POWER_DOMAIN_AUDIO_MMIO, \ |
320 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
321 | POWER_DOMAIN_AUX_IO_B, \ |
322 | POWER_DOMAIN_AUX_IO_C, \ |
323 | POWER_DOMAIN_AUX_IO_D, \ |
324 | POWER_DOMAIN_AUX_B, \ |
325 | POWER_DOMAIN_AUX_C, \ |
326 | POWER_DOMAIN_AUX_D |
327 | |
328 | I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2, |
329 | SKL_PW_2_POWER_DOMAINS, |
330 | POWER_DOMAIN_INIT); |
331 | |
332 | I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off, |
333 | SKL_PW_2_POWER_DOMAINS, |
334 | POWER_DOMAIN_AUX_A, |
335 | POWER_DOMAIN_GT_IRQ, |
336 | POWER_DOMAIN_DC_OFF, |
337 | POWER_DOMAIN_INIT); |
338 | |
339 | I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e, |
340 | POWER_DOMAIN_PORT_DDI_IO_A, |
341 | POWER_DOMAIN_PORT_DDI_IO_E, |
342 | POWER_DOMAIN_INIT); |
343 | |
344 | I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b, |
345 | POWER_DOMAIN_PORT_DDI_IO_B, |
346 | POWER_DOMAIN_INIT); |
347 | |
348 | I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c, |
349 | POWER_DOMAIN_PORT_DDI_IO_C, |
350 | POWER_DOMAIN_INIT); |
351 | |
352 | I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d, |
353 | POWER_DOMAIN_PORT_DDI_IO_D, |
354 | POWER_DOMAIN_INIT); |
355 | |
356 | static const struct i915_power_well_desc skl_power_wells_pw_1[] = { |
357 | { |
358 | /* Handled by the DMC firmware */ |
359 | .instances = &I915_PW_INSTANCES( |
360 | I915_PW("PW_1" , I915_PW_DOMAINS_NONE, |
361 | .hsw.idx = SKL_PW_CTL_IDX_PW_1, |
362 | .id = SKL_DISP_PW_1), |
363 | ), |
364 | .ops = &hsw_power_well_ops, |
365 | .always_on = true, |
366 | .has_fuses = true, |
367 | }, |
368 | }; |
369 | |
370 | static const struct i915_power_well_desc skl_power_wells_main[] = { |
371 | { |
372 | /* Handled by the DMC firmware */ |
373 | .instances = &I915_PW_INSTANCES( |
374 | I915_PW("MISC_IO" , I915_PW_DOMAINS_NONE, |
375 | .hsw.idx = SKL_PW_CTL_IDX_MISC_IO, |
376 | .id = SKL_DISP_PW_MISC_IO), |
377 | ), |
378 | .ops = &hsw_power_well_ops, |
379 | .always_on = true, |
380 | }, { |
381 | .instances = &I915_PW_INSTANCES( |
382 | I915_PW("DC_off" , &skl_pwdoms_dc_off, |
383 | .id = SKL_DISP_DC_OFF), |
384 | ), |
385 | .ops = &gen9_dc_off_power_well_ops, |
386 | }, { |
387 | .instances = &I915_PW_INSTANCES( |
388 | I915_PW("PW_2" , &skl_pwdoms_pw_2, |
389 | .hsw.idx = SKL_PW_CTL_IDX_PW_2, |
390 | .id = SKL_DISP_PW_2), |
391 | ), |
392 | .ops = &hsw_power_well_ops, |
393 | .has_vga = true, |
394 | .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), |
395 | .has_fuses = true, |
396 | }, { |
397 | .instances = &I915_PW_INSTANCES( |
398 | I915_PW("DDI_IO_A_E" , &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E), |
399 | I915_PW("DDI_IO_B" , &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), |
400 | I915_PW("DDI_IO_C" , &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), |
401 | I915_PW("DDI_IO_D" , &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D), |
402 | ), |
403 | .ops = &hsw_power_well_ops, |
404 | }, |
405 | }; |
406 | |
407 | static const struct i915_power_well_desc_list skl_power_wells[] = { |
408 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
409 | I915_PW_DESCRIPTORS(skl_power_wells_pw_1), |
410 | I915_PW_DESCRIPTORS(skl_power_wells_main), |
411 | }; |
412 | |
413 | #define BXT_PW_2_POWER_DOMAINS \ |
414 | POWER_DOMAIN_PIPE_B, \ |
415 | POWER_DOMAIN_PIPE_C, \ |
416 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
417 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ |
418 | POWER_DOMAIN_TRANSCODER_A, \ |
419 | POWER_DOMAIN_TRANSCODER_B, \ |
420 | POWER_DOMAIN_TRANSCODER_C, \ |
421 | POWER_DOMAIN_PORT_DDI_LANES_B, \ |
422 | POWER_DOMAIN_PORT_DDI_LANES_C, \ |
423 | POWER_DOMAIN_VGA, \ |
424 | POWER_DOMAIN_AUDIO_MMIO, \ |
425 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
426 | POWER_DOMAIN_AUX_IO_B, \ |
427 | POWER_DOMAIN_AUX_IO_C, \ |
428 | POWER_DOMAIN_AUX_B, \ |
429 | POWER_DOMAIN_AUX_C |
430 | |
431 | I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2, |
432 | BXT_PW_2_POWER_DOMAINS, |
433 | POWER_DOMAIN_INIT); |
434 | |
435 | I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off, |
436 | BXT_PW_2_POWER_DOMAINS, |
437 | POWER_DOMAIN_AUX_A, |
438 | POWER_DOMAIN_GMBUS, |
439 | POWER_DOMAIN_GT_IRQ, |
440 | POWER_DOMAIN_DC_OFF, |
441 | POWER_DOMAIN_INIT); |
442 | |
443 | I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a, |
444 | POWER_DOMAIN_PORT_DDI_LANES_A, |
445 | POWER_DOMAIN_AUX_IO_A, |
446 | POWER_DOMAIN_AUX_A, |
447 | POWER_DOMAIN_INIT); |
448 | |
449 | I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc, |
450 | POWER_DOMAIN_PORT_DDI_LANES_B, |
451 | POWER_DOMAIN_PORT_DDI_LANES_C, |
452 | POWER_DOMAIN_AUX_IO_B, |
453 | POWER_DOMAIN_AUX_IO_C, |
454 | POWER_DOMAIN_AUX_B, |
455 | POWER_DOMAIN_AUX_C, |
456 | POWER_DOMAIN_INIT); |
457 | |
458 | static const struct i915_power_well_desc bxt_power_wells_main[] = { |
459 | { |
460 | .instances = &I915_PW_INSTANCES( |
461 | I915_PW("DC_off" , &bxt_pwdoms_dc_off, |
462 | .id = SKL_DISP_DC_OFF), |
463 | ), |
464 | .ops = &gen9_dc_off_power_well_ops, |
465 | }, { |
466 | .instances = &I915_PW_INSTANCES( |
467 | I915_PW("PW_2" , &bxt_pwdoms_pw_2, |
468 | .hsw.idx = SKL_PW_CTL_IDX_PW_2, |
469 | .id = SKL_DISP_PW_2), |
470 | ), |
471 | .ops = &hsw_power_well_ops, |
472 | .has_vga = true, |
473 | .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), |
474 | .has_fuses = true, |
475 | }, { |
476 | .instances = &I915_PW_INSTANCES( |
477 | I915_PW("dpio-common-a" , &bxt_pwdoms_dpio_cmn_a, |
478 | .bxt.phy = DPIO_PHY1, |
479 | .id = BXT_DISP_PW_DPIO_CMN_A), |
480 | I915_PW("dpio-common-bc" , &bxt_pwdoms_dpio_cmn_bc, |
481 | .bxt.phy = DPIO_PHY0, |
482 | .id = VLV_DISP_PW_DPIO_CMN_BC), |
483 | ), |
484 | .ops = &bxt_dpio_cmn_power_well_ops, |
485 | }, |
486 | }; |
487 | |
488 | static const struct i915_power_well_desc_list bxt_power_wells[] = { |
489 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
490 | I915_PW_DESCRIPTORS(skl_power_wells_pw_1), |
491 | I915_PW_DESCRIPTORS(bxt_power_wells_main), |
492 | }; |
493 | |
494 | #define GLK_PW_2_POWER_DOMAINS \ |
495 | POWER_DOMAIN_PIPE_B, \ |
496 | POWER_DOMAIN_PIPE_C, \ |
497 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
498 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ |
499 | POWER_DOMAIN_TRANSCODER_A, \ |
500 | POWER_DOMAIN_TRANSCODER_B, \ |
501 | POWER_DOMAIN_TRANSCODER_C, \ |
502 | POWER_DOMAIN_PORT_DDI_LANES_B, \ |
503 | POWER_DOMAIN_PORT_DDI_LANES_C, \ |
504 | POWER_DOMAIN_VGA, \ |
505 | POWER_DOMAIN_AUDIO_MMIO, \ |
506 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
507 | POWER_DOMAIN_AUX_IO_B, \ |
508 | POWER_DOMAIN_AUX_IO_C, \ |
509 | POWER_DOMAIN_AUX_B, \ |
510 | POWER_DOMAIN_AUX_C |
511 | |
512 | I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2, |
513 | GLK_PW_2_POWER_DOMAINS, |
514 | POWER_DOMAIN_INIT); |
515 | |
516 | I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off, |
517 | GLK_PW_2_POWER_DOMAINS, |
518 | POWER_DOMAIN_AUX_A, |
519 | POWER_DOMAIN_GMBUS, |
520 | POWER_DOMAIN_GT_IRQ, |
521 | POWER_DOMAIN_DC_OFF, |
522 | POWER_DOMAIN_INIT); |
523 | |
524 | I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A); |
525 | I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B); |
526 | I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C); |
527 | |
528 | I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a, |
529 | POWER_DOMAIN_PORT_DDI_LANES_A, |
530 | POWER_DOMAIN_AUX_IO_A, |
531 | POWER_DOMAIN_AUX_A, |
532 | POWER_DOMAIN_INIT); |
533 | |
534 | I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b, |
535 | POWER_DOMAIN_PORT_DDI_LANES_B, |
536 | POWER_DOMAIN_AUX_IO_B, |
537 | POWER_DOMAIN_AUX_B, |
538 | POWER_DOMAIN_INIT); |
539 | |
540 | I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c, |
541 | POWER_DOMAIN_PORT_DDI_LANES_C, |
542 | POWER_DOMAIN_AUX_IO_C, |
543 | POWER_DOMAIN_AUX_C, |
544 | POWER_DOMAIN_INIT); |
545 | |
546 | I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a, |
547 | POWER_DOMAIN_AUX_IO_A, |
548 | POWER_DOMAIN_AUX_A, |
549 | POWER_DOMAIN_INIT); |
550 | |
551 | I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b, |
552 | POWER_DOMAIN_AUX_IO_B, |
553 | POWER_DOMAIN_AUX_B, |
554 | POWER_DOMAIN_INIT); |
555 | |
556 | I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c, |
557 | POWER_DOMAIN_AUX_IO_C, |
558 | POWER_DOMAIN_AUX_C, |
559 | POWER_DOMAIN_INIT); |
560 | |
561 | static const struct i915_power_well_desc glk_power_wells_main[] = { |
562 | { |
563 | .instances = &I915_PW_INSTANCES( |
564 | I915_PW("DC_off" , &glk_pwdoms_dc_off, |
565 | .id = SKL_DISP_DC_OFF), |
566 | ), |
567 | .ops = &gen9_dc_off_power_well_ops, |
568 | }, { |
569 | .instances = &I915_PW_INSTANCES( |
570 | I915_PW("PW_2" , &glk_pwdoms_pw_2, |
571 | .hsw.idx = SKL_PW_CTL_IDX_PW_2, |
572 | .id = SKL_DISP_PW_2), |
573 | ), |
574 | .ops = &hsw_power_well_ops, |
575 | .has_vga = true, |
576 | .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), |
577 | .has_fuses = true, |
578 | }, { |
579 | .instances = &I915_PW_INSTANCES( |
580 | I915_PW("dpio-common-a" , &glk_pwdoms_dpio_cmn_a, |
581 | .bxt.phy = DPIO_PHY1, |
582 | .id = BXT_DISP_PW_DPIO_CMN_A), |
583 | I915_PW("dpio-common-b" , &glk_pwdoms_dpio_cmn_b, |
584 | .bxt.phy = DPIO_PHY0, |
585 | .id = VLV_DISP_PW_DPIO_CMN_BC), |
586 | I915_PW("dpio-common-c" , &glk_pwdoms_dpio_cmn_c, |
587 | .bxt.phy = DPIO_PHY2, |
588 | .id = GLK_DISP_PW_DPIO_CMN_C), |
589 | ), |
590 | .ops = &bxt_dpio_cmn_power_well_ops, |
591 | }, { |
592 | .instances = &I915_PW_INSTANCES( |
593 | I915_PW("AUX_A" , &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A), |
594 | I915_PW("AUX_B" , &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B), |
595 | I915_PW("AUX_C" , &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C), |
596 | I915_PW("DDI_IO_A" , &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A), |
597 | I915_PW("DDI_IO_B" , &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B), |
598 | I915_PW("DDI_IO_C" , &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C), |
599 | ), |
600 | .ops = &hsw_power_well_ops, |
601 | }, |
602 | }; |
603 | |
604 | static const struct i915_power_well_desc_list glk_power_wells[] = { |
605 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
606 | I915_PW_DESCRIPTORS(skl_power_wells_pw_1), |
607 | I915_PW_DESCRIPTORS(glk_power_wells_main), |
608 | }; |
609 | |
610 | /* |
611 | * ICL PW_0/PG_0 domains (HW/DMC control): |
612 | * - PCI |
613 | * - clocks except port PLL |
614 | * - central power except FBC |
615 | * - shared functions except pipe interrupts, pipe MBUS, DBUF registers |
616 | * ICL PW_1/PG_1 domains (HW/DMC control): |
617 | * - DBUF function |
618 | * - PIPE_A and its planes, except VGA |
619 | * - transcoder EDP + PSR |
620 | * - transcoder DSI |
621 | * - DDI_A |
622 | * - FBC |
623 | */ |
624 | #define ICL_PW_4_POWER_DOMAINS \ |
625 | POWER_DOMAIN_PIPE_C, \ |
626 | POWER_DOMAIN_PIPE_PANEL_FITTER_C |
627 | |
628 | I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4, |
629 | ICL_PW_4_POWER_DOMAINS, |
630 | POWER_DOMAIN_INIT); |
631 | /* VDSC/joining */ |
632 | |
633 | #define ICL_PW_3_POWER_DOMAINS \ |
634 | ICL_PW_4_POWER_DOMAINS, \ |
635 | POWER_DOMAIN_PIPE_B, \ |
636 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
637 | POWER_DOMAIN_TRANSCODER_A, \ |
638 | POWER_DOMAIN_TRANSCODER_B, \ |
639 | POWER_DOMAIN_TRANSCODER_C, \ |
640 | POWER_DOMAIN_PORT_DDI_LANES_B, \ |
641 | POWER_DOMAIN_PORT_DDI_LANES_C, \ |
642 | POWER_DOMAIN_PORT_DDI_LANES_D, \ |
643 | POWER_DOMAIN_PORT_DDI_LANES_E, \ |
644 | POWER_DOMAIN_PORT_DDI_LANES_F, \ |
645 | POWER_DOMAIN_VGA, \ |
646 | POWER_DOMAIN_AUDIO_MMIO, \ |
647 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
648 | POWER_DOMAIN_AUX_IO_B, \ |
649 | POWER_DOMAIN_AUX_IO_C, \ |
650 | POWER_DOMAIN_AUX_IO_D, \ |
651 | POWER_DOMAIN_AUX_IO_E, \ |
652 | POWER_DOMAIN_AUX_IO_F, \ |
653 | POWER_DOMAIN_AUX_B, \ |
654 | POWER_DOMAIN_AUX_C, \ |
655 | POWER_DOMAIN_AUX_D, \ |
656 | POWER_DOMAIN_AUX_E, \ |
657 | POWER_DOMAIN_AUX_F, \ |
658 | POWER_DOMAIN_AUX_TBT1, \ |
659 | POWER_DOMAIN_AUX_TBT2, \ |
660 | POWER_DOMAIN_AUX_TBT3, \ |
661 | POWER_DOMAIN_AUX_TBT4 |
662 | |
663 | I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3, |
664 | ICL_PW_3_POWER_DOMAINS, |
665 | POWER_DOMAIN_INIT); |
666 | /* |
667 | * - transcoder WD |
668 | * - KVMR (HW control) |
669 | */ |
670 | |
671 | #define ICL_PW_2_POWER_DOMAINS \ |
672 | ICL_PW_3_POWER_DOMAINS, \ |
673 | POWER_DOMAIN_TRANSCODER_VDSC_PW2 |
674 | |
675 | I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2, |
676 | ICL_PW_2_POWER_DOMAINS, |
677 | POWER_DOMAIN_INIT); |
678 | /* |
679 | * - KVMR (HW control) |
680 | */ |
681 | |
682 | I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off, |
683 | ICL_PW_2_POWER_DOMAINS, |
684 | POWER_DOMAIN_AUX_A, |
685 | POWER_DOMAIN_DC_OFF, |
686 | POWER_DOMAIN_INIT); |
687 | |
688 | I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D); |
689 | I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E); |
690 | I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F); |
691 | |
692 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a, |
693 | POWER_DOMAIN_AUX_IO_A, |
694 | POWER_DOMAIN_AUX_A); |
695 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, |
696 | POWER_DOMAIN_AUX_IO_B, |
697 | POWER_DOMAIN_AUX_B); |
698 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, |
699 | POWER_DOMAIN_AUX_IO_C, |
700 | POWER_DOMAIN_AUX_C); |
701 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, |
702 | POWER_DOMAIN_AUX_IO_D, |
703 | POWER_DOMAIN_AUX_D); |
704 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, |
705 | POWER_DOMAIN_AUX_IO_E, |
706 | POWER_DOMAIN_AUX_E); |
707 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, |
708 | POWER_DOMAIN_AUX_IO_F, |
709 | POWER_DOMAIN_AUX_F); |
710 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); |
711 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); |
712 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); |
713 | I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); |
714 | |
715 | static const struct i915_power_well_desc icl_power_wells_pw_1[] = { |
716 | { |
717 | /* Handled by the DMC firmware */ |
718 | .instances = &I915_PW_INSTANCES( |
719 | I915_PW("PW_1" , I915_PW_DOMAINS_NONE, |
720 | .hsw.idx = ICL_PW_CTL_IDX_PW_1, |
721 | .id = SKL_DISP_PW_1), |
722 | ), |
723 | .ops = &hsw_power_well_ops, |
724 | .always_on = true, |
725 | .has_fuses = true, |
726 | }, |
727 | }; |
728 | |
729 | static const struct i915_power_well_desc icl_power_wells_main[] = { |
730 | { |
731 | .instances = &I915_PW_INSTANCES( |
732 | I915_PW("DC_off" , &icl_pwdoms_dc_off, |
733 | .id = SKL_DISP_DC_OFF), |
734 | ), |
735 | .ops = &gen9_dc_off_power_well_ops, |
736 | }, { |
737 | .instances = &I915_PW_INSTANCES( |
738 | I915_PW("PW_2" , &icl_pwdoms_pw_2, |
739 | .hsw.idx = ICL_PW_CTL_IDX_PW_2, |
740 | .id = SKL_DISP_PW_2), |
741 | ), |
742 | .ops = &hsw_power_well_ops, |
743 | .has_fuses = true, |
744 | }, { |
745 | .instances = &I915_PW_INSTANCES( |
746 | I915_PW("PW_3" , &icl_pwdoms_pw_3, |
747 | .hsw.idx = ICL_PW_CTL_IDX_PW_3, |
748 | .id = ICL_DISP_PW_3), |
749 | ), |
750 | .ops = &hsw_power_well_ops, |
751 | .has_vga = true, |
752 | .irq_pipe_mask = BIT(PIPE_B), |
753 | .has_fuses = true, |
754 | }, { |
755 | .instances = &I915_PW_INSTANCES( |
756 | I915_PW("DDI_IO_A" , &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), |
757 | I915_PW("DDI_IO_B" , &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), |
758 | I915_PW("DDI_IO_C" , &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), |
759 | I915_PW("DDI_IO_D" , &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D), |
760 | I915_PW("DDI_IO_E" , &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E), |
761 | I915_PW("DDI_IO_F" , &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F), |
762 | ), |
763 | .ops = &icl_ddi_power_well_ops, |
764 | }, { |
765 | .instances = &I915_PW_INSTANCES( |
766 | I915_PW("AUX_A" , &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), |
767 | I915_PW("AUX_B" , &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), |
768 | I915_PW("AUX_C" , &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), |
769 | I915_PW("AUX_D" , &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D), |
770 | I915_PW("AUX_E" , &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E), |
771 | I915_PW("AUX_F" , &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F), |
772 | ), |
773 | .ops = &icl_aux_power_well_ops, |
774 | }, { |
775 | .instances = &I915_PW_INSTANCES( |
776 | I915_PW("AUX_TBT1" , &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1), |
777 | I915_PW("AUX_TBT2" , &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2), |
778 | I915_PW("AUX_TBT3" , &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3), |
779 | I915_PW("AUX_TBT4" , &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4), |
780 | ), |
781 | .ops = &icl_aux_power_well_ops, |
782 | .is_tc_tbt = true, |
783 | }, { |
784 | .instances = &I915_PW_INSTANCES( |
785 | I915_PW("PW_4" , &icl_pwdoms_pw_4, |
786 | .hsw.idx = ICL_PW_CTL_IDX_PW_4), |
787 | ), |
788 | .ops = &hsw_power_well_ops, |
789 | .irq_pipe_mask = BIT(PIPE_C), |
790 | .has_fuses = true, |
791 | }, |
792 | }; |
793 | |
794 | static const struct i915_power_well_desc_list icl_power_wells[] = { |
795 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
796 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
797 | I915_PW_DESCRIPTORS(icl_power_wells_main), |
798 | }; |
799 | |
800 | #define TGL_PW_5_POWER_DOMAINS \ |
801 | POWER_DOMAIN_PIPE_D, \ |
802 | POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ |
803 | POWER_DOMAIN_TRANSCODER_D |
804 | |
805 | I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5, |
806 | TGL_PW_5_POWER_DOMAINS, |
807 | POWER_DOMAIN_INIT); |
808 | |
809 | #define TGL_PW_4_POWER_DOMAINS \ |
810 | TGL_PW_5_POWER_DOMAINS, \ |
811 | POWER_DOMAIN_PIPE_C, \ |
812 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ |
813 | POWER_DOMAIN_TRANSCODER_C |
814 | |
815 | I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4, |
816 | TGL_PW_4_POWER_DOMAINS, |
817 | POWER_DOMAIN_INIT); |
818 | |
819 | #define TGL_PW_3_POWER_DOMAINS \ |
820 | TGL_PW_4_POWER_DOMAINS, \ |
821 | POWER_DOMAIN_PIPE_B, \ |
822 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
823 | POWER_DOMAIN_TRANSCODER_B, \ |
824 | POWER_DOMAIN_PORT_DDI_LANES_TC1, \ |
825 | POWER_DOMAIN_PORT_DDI_LANES_TC2, \ |
826 | POWER_DOMAIN_PORT_DDI_LANES_TC3, \ |
827 | POWER_DOMAIN_PORT_DDI_LANES_TC4, \ |
828 | POWER_DOMAIN_PORT_DDI_LANES_TC5, \ |
829 | POWER_DOMAIN_PORT_DDI_LANES_TC6, \ |
830 | POWER_DOMAIN_VGA, \ |
831 | POWER_DOMAIN_AUDIO_MMIO, \ |
832 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
833 | POWER_DOMAIN_AUX_USBC1, \ |
834 | POWER_DOMAIN_AUX_USBC2, \ |
835 | POWER_DOMAIN_AUX_USBC3, \ |
836 | POWER_DOMAIN_AUX_USBC4, \ |
837 | POWER_DOMAIN_AUX_USBC5, \ |
838 | POWER_DOMAIN_AUX_USBC6, \ |
839 | POWER_DOMAIN_AUX_TBT1, \ |
840 | POWER_DOMAIN_AUX_TBT2, \ |
841 | POWER_DOMAIN_AUX_TBT3, \ |
842 | POWER_DOMAIN_AUX_TBT4, \ |
843 | POWER_DOMAIN_AUX_TBT5, \ |
844 | POWER_DOMAIN_AUX_TBT6 |
845 | |
846 | I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3, |
847 | TGL_PW_3_POWER_DOMAINS, |
848 | POWER_DOMAIN_INIT); |
849 | |
850 | I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2, |
851 | TGL_PW_3_POWER_DOMAINS, |
852 | POWER_DOMAIN_TRANSCODER_VDSC_PW2, |
853 | POWER_DOMAIN_INIT); |
854 | |
855 | I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off, |
856 | TGL_PW_3_POWER_DOMAINS, |
857 | POWER_DOMAIN_AUX_A, |
858 | POWER_DOMAIN_AUX_B, |
859 | POWER_DOMAIN_AUX_C, |
860 | POWER_DOMAIN_DC_OFF, |
861 | POWER_DOMAIN_INIT); |
862 | |
863 | I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1); |
864 | I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2); |
865 | I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3); |
866 | I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4); |
867 | I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5); |
868 | I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6); |
869 | |
870 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1); |
871 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2); |
872 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3); |
873 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4); |
874 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5); |
875 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6); |
876 | |
877 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5); |
878 | I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6); |
879 | |
880 | I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off, |
881 | POWER_DOMAIN_AUX_USBC1, |
882 | POWER_DOMAIN_AUX_USBC2, |
883 | POWER_DOMAIN_AUX_USBC3, |
884 | POWER_DOMAIN_AUX_USBC4, |
885 | POWER_DOMAIN_AUX_USBC5, |
886 | POWER_DOMAIN_AUX_USBC6, |
887 | POWER_DOMAIN_AUX_TBT1, |
888 | POWER_DOMAIN_AUX_TBT2, |
889 | POWER_DOMAIN_AUX_TBT3, |
890 | POWER_DOMAIN_AUX_TBT4, |
891 | POWER_DOMAIN_AUX_TBT5, |
892 | POWER_DOMAIN_AUX_TBT6, |
893 | POWER_DOMAIN_TC_COLD_OFF); |
894 | |
895 | static const struct i915_power_well_desc tgl_power_wells_main[] = { |
896 | { |
897 | .instances = &I915_PW_INSTANCES( |
898 | I915_PW("DC_off" , &tgl_pwdoms_dc_off, |
899 | .id = SKL_DISP_DC_OFF), |
900 | ), |
901 | .ops = &gen9_dc_off_power_well_ops, |
902 | }, { |
903 | .instances = &I915_PW_INSTANCES( |
904 | I915_PW("PW_2" , &tgl_pwdoms_pw_2, |
905 | .hsw.idx = ICL_PW_CTL_IDX_PW_2, |
906 | .id = SKL_DISP_PW_2), |
907 | ), |
908 | .ops = &hsw_power_well_ops, |
909 | .has_fuses = true, |
910 | }, { |
911 | .instances = &I915_PW_INSTANCES( |
912 | I915_PW("PW_3" , &tgl_pwdoms_pw_3, |
913 | .hsw.idx = ICL_PW_CTL_IDX_PW_3, |
914 | .id = ICL_DISP_PW_3), |
915 | ), |
916 | .ops = &hsw_power_well_ops, |
917 | .has_vga = true, |
918 | .irq_pipe_mask = BIT(PIPE_B), |
919 | .has_fuses = true, |
920 | }, { |
921 | .instances = &I915_PW_INSTANCES( |
922 | I915_PW("DDI_IO_A" , &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), |
923 | I915_PW("DDI_IO_B" , &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), |
924 | I915_PW("DDI_IO_C" , &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), |
925 | I915_PW("DDI_IO_TC1" , &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), |
926 | I915_PW("DDI_IO_TC2" , &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), |
927 | I915_PW("DDI_IO_TC3" , &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), |
928 | I915_PW("DDI_IO_TC4" , &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), |
929 | I915_PW("DDI_IO_TC5" , &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5), |
930 | I915_PW("DDI_IO_TC6" , &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6), |
931 | ), |
932 | .ops = &icl_ddi_power_well_ops, |
933 | }, { |
934 | .instances = &I915_PW_INSTANCES( |
935 | I915_PW("PW_4" , &tgl_pwdoms_pw_4, |
936 | .hsw.idx = ICL_PW_CTL_IDX_PW_4), |
937 | ), |
938 | .ops = &hsw_power_well_ops, |
939 | .has_fuses = true, |
940 | .irq_pipe_mask = BIT(PIPE_C), |
941 | }, { |
942 | .instances = &I915_PW_INSTANCES( |
943 | I915_PW("PW_5" , &tgl_pwdoms_pw_5, |
944 | .hsw.idx = TGL_PW_CTL_IDX_PW_5), |
945 | ), |
946 | .ops = &hsw_power_well_ops, |
947 | .has_fuses = true, |
948 | .irq_pipe_mask = BIT(PIPE_D), |
949 | }, |
950 | }; |
951 | |
952 | static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = { |
953 | { |
954 | .instances = &I915_PW_INSTANCES( |
955 | I915_PW("TC_cold_off" , &tgl_pwdoms_tc_cold_off, |
956 | .id = TGL_DISP_PW_TC_COLD_OFF), |
957 | ), |
958 | .ops = &tgl_tc_cold_off_ops, |
959 | }, |
960 | }; |
961 | |
962 | static const struct i915_power_well_desc tgl_power_wells_aux[] = { |
963 | { |
964 | .instances = &I915_PW_INSTANCES( |
965 | I915_PW("AUX_A" , &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), |
966 | I915_PW("AUX_B" , &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), |
967 | I915_PW("AUX_C" , &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), |
968 | I915_PW("AUX_USBC1" , &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), |
969 | I915_PW("AUX_USBC2" , &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), |
970 | I915_PW("AUX_USBC3" , &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), |
971 | I915_PW("AUX_USBC4" , &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), |
972 | I915_PW("AUX_USBC5" , &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5), |
973 | I915_PW("AUX_USBC6" , &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6), |
974 | ), |
975 | .ops = &icl_aux_power_well_ops, |
976 | }, { |
977 | .instances = &I915_PW_INSTANCES( |
978 | I915_PW("AUX_TBT1" , &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), |
979 | I915_PW("AUX_TBT2" , &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), |
980 | I915_PW("AUX_TBT3" , &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), |
981 | I915_PW("AUX_TBT4" , &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), |
982 | I915_PW("AUX_TBT5" , &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5), |
983 | I915_PW("AUX_TBT6" , &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6), |
984 | ), |
985 | .ops = &icl_aux_power_well_ops, |
986 | .is_tc_tbt = true, |
987 | }, |
988 | }; |
989 | |
990 | static const struct i915_power_well_desc_list tgl_power_wells[] = { |
991 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
992 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
993 | I915_PW_DESCRIPTORS(tgl_power_wells_main), |
994 | I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off), |
995 | I915_PW_DESCRIPTORS(tgl_power_wells_aux), |
996 | }; |
997 | |
998 | static const struct i915_power_well_desc_list adls_power_wells[] = { |
999 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1000 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1001 | I915_PW_DESCRIPTORS(tgl_power_wells_main), |
1002 | I915_PW_DESCRIPTORS(tgl_power_wells_aux), |
1003 | }; |
1004 | |
1005 | #define RKL_PW_4_POWER_DOMAINS \ |
1006 | POWER_DOMAIN_PIPE_C, \ |
1007 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ |
1008 | POWER_DOMAIN_TRANSCODER_C |
1009 | |
1010 | I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4, |
1011 | RKL_PW_4_POWER_DOMAINS, |
1012 | POWER_DOMAIN_INIT); |
1013 | |
1014 | #define RKL_PW_3_POWER_DOMAINS \ |
1015 | RKL_PW_4_POWER_DOMAINS, \ |
1016 | POWER_DOMAIN_PIPE_B, \ |
1017 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
1018 | POWER_DOMAIN_TRANSCODER_B, \ |
1019 | POWER_DOMAIN_PORT_DDI_LANES_TC1, \ |
1020 | POWER_DOMAIN_PORT_DDI_LANES_TC2, \ |
1021 | POWER_DOMAIN_VGA, \ |
1022 | POWER_DOMAIN_AUDIO_MMIO, \ |
1023 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
1024 | POWER_DOMAIN_AUX_USBC1, \ |
1025 | POWER_DOMAIN_AUX_USBC2 |
1026 | |
1027 | I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3, |
1028 | RKL_PW_3_POWER_DOMAINS, |
1029 | POWER_DOMAIN_INIT); |
1030 | |
1031 | /* |
1032 | * There is no PW_2/PG_2 on RKL. |
1033 | * |
1034 | * RKL PW_1/PG_1 domains (under HW/DMC control): |
1035 | * - DBUF function (note: registers are in PW0) |
1036 | * - PIPE_A and its planes and VDSC/joining, except VGA |
1037 | * - transcoder A |
1038 | * - DDI_A and DDI_B |
1039 | * - FBC |
1040 | * |
1041 | * RKL PW_0/PG_0 domains (under HW/DMC control): |
1042 | * - PCI |
1043 | * - clocks except port PLL |
1044 | * - shared functions: |
1045 | * * interrupts except pipe interrupts |
1046 | * * MBus except PIPE_MBUS_DBOX_CTL |
1047 | * * DBUF registers |
1048 | * - central power except FBC |
1049 | * - top-level GTC (DDI-level GTC is in the well associated with the DDI) |
1050 | */ |
1051 | |
1052 | I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off, |
1053 | RKL_PW_3_POWER_DOMAINS, |
1054 | POWER_DOMAIN_AUX_A, |
1055 | POWER_DOMAIN_AUX_B, |
1056 | POWER_DOMAIN_DC_OFF, |
1057 | POWER_DOMAIN_INIT); |
1058 | |
1059 | static const struct i915_power_well_desc rkl_power_wells_main[] = { |
1060 | { |
1061 | .instances = &I915_PW_INSTANCES( |
1062 | I915_PW("DC_off" , &rkl_pwdoms_dc_off, |
1063 | .id = SKL_DISP_DC_OFF), |
1064 | ), |
1065 | .ops = &gen9_dc_off_power_well_ops, |
1066 | }, { |
1067 | .instances = &I915_PW_INSTANCES( |
1068 | I915_PW("PW_3" , &rkl_pwdoms_pw_3, |
1069 | .hsw.idx = ICL_PW_CTL_IDX_PW_3, |
1070 | .id = ICL_DISP_PW_3), |
1071 | ), |
1072 | .ops = &hsw_power_well_ops, |
1073 | .irq_pipe_mask = BIT(PIPE_B), |
1074 | .has_vga = true, |
1075 | .has_fuses = true, |
1076 | }, { |
1077 | .instances = &I915_PW_INSTANCES( |
1078 | I915_PW("PW_4" , &rkl_pwdoms_pw_4, |
1079 | .hsw.idx = ICL_PW_CTL_IDX_PW_4), |
1080 | ), |
1081 | .ops = &hsw_power_well_ops, |
1082 | .has_fuses = true, |
1083 | .irq_pipe_mask = BIT(PIPE_C), |
1084 | }, |
1085 | }; |
1086 | |
1087 | static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = { |
1088 | { |
1089 | .instances = &I915_PW_INSTANCES( |
1090 | I915_PW("DDI_IO_A" , &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), |
1091 | I915_PW("DDI_IO_B" , &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), |
1092 | I915_PW("DDI_IO_TC1" , &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), |
1093 | I915_PW("DDI_IO_TC2" , &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), |
1094 | ), |
1095 | .ops = &icl_ddi_power_well_ops, |
1096 | }, { |
1097 | .instances = &I915_PW_INSTANCES( |
1098 | I915_PW("AUX_A" , &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), |
1099 | I915_PW("AUX_B" , &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), |
1100 | I915_PW("AUX_USBC1" , &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), |
1101 | I915_PW("AUX_USBC2" , &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), |
1102 | ), |
1103 | .ops = &icl_aux_power_well_ops, |
1104 | }, |
1105 | }; |
1106 | |
1107 | static const struct i915_power_well_desc_list rkl_power_wells[] = { |
1108 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1109 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1110 | I915_PW_DESCRIPTORS(rkl_power_wells_main), |
1111 | I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), |
1112 | }; |
1113 | |
1114 | /* |
1115 | * DG1 onwards Audio MMIO/VERBS lies in PG0 power well. |
1116 | */ |
1117 | #define DG1_PW_3_POWER_DOMAINS \ |
1118 | TGL_PW_4_POWER_DOMAINS, \ |
1119 | POWER_DOMAIN_PIPE_B, \ |
1120 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
1121 | POWER_DOMAIN_TRANSCODER_B, \ |
1122 | POWER_DOMAIN_PORT_DDI_LANES_TC1, \ |
1123 | POWER_DOMAIN_PORT_DDI_LANES_TC2, \ |
1124 | POWER_DOMAIN_VGA, \ |
1125 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
1126 | POWER_DOMAIN_AUX_USBC1, \ |
1127 | POWER_DOMAIN_AUX_USBC2 |
1128 | |
1129 | I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3, |
1130 | DG1_PW_3_POWER_DOMAINS, |
1131 | POWER_DOMAIN_INIT); |
1132 | |
1133 | I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off, |
1134 | DG1_PW_3_POWER_DOMAINS, |
1135 | POWER_DOMAIN_AUDIO_MMIO, |
1136 | POWER_DOMAIN_AUX_A, |
1137 | POWER_DOMAIN_AUX_B, |
1138 | POWER_DOMAIN_DC_OFF, |
1139 | POWER_DOMAIN_INIT); |
1140 | |
1141 | I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2, |
1142 | DG1_PW_3_POWER_DOMAINS, |
1143 | POWER_DOMAIN_TRANSCODER_VDSC_PW2, |
1144 | POWER_DOMAIN_INIT); |
1145 | |
1146 | static const struct i915_power_well_desc dg1_power_wells_main[] = { |
1147 | { |
1148 | .instances = &I915_PW_INSTANCES( |
1149 | I915_PW("DC_off" , &dg1_pwdoms_dc_off, |
1150 | .id = SKL_DISP_DC_OFF), |
1151 | ), |
1152 | .ops = &gen9_dc_off_power_well_ops, |
1153 | }, { |
1154 | .instances = &I915_PW_INSTANCES( |
1155 | I915_PW("PW_2" , &dg1_pwdoms_pw_2, |
1156 | .hsw.idx = ICL_PW_CTL_IDX_PW_2, |
1157 | .id = SKL_DISP_PW_2), |
1158 | ), |
1159 | .ops = &hsw_power_well_ops, |
1160 | .has_fuses = true, |
1161 | }, { |
1162 | .instances = &I915_PW_INSTANCES( |
1163 | I915_PW("PW_3" , &dg1_pwdoms_pw_3, |
1164 | .hsw.idx = ICL_PW_CTL_IDX_PW_3, |
1165 | .id = ICL_DISP_PW_3), |
1166 | ), |
1167 | .ops = &hsw_power_well_ops, |
1168 | .irq_pipe_mask = BIT(PIPE_B), |
1169 | .has_vga = true, |
1170 | .has_fuses = true, |
1171 | }, { |
1172 | .instances = &I915_PW_INSTANCES( |
1173 | I915_PW("PW_4" , &tgl_pwdoms_pw_4, |
1174 | .hsw.idx = ICL_PW_CTL_IDX_PW_4), |
1175 | ), |
1176 | .ops = &hsw_power_well_ops, |
1177 | .has_fuses = true, |
1178 | .irq_pipe_mask = BIT(PIPE_C), |
1179 | }, { |
1180 | .instances = &I915_PW_INSTANCES( |
1181 | I915_PW("PW_5" , &tgl_pwdoms_pw_5, |
1182 | .hsw.idx = TGL_PW_CTL_IDX_PW_5), |
1183 | ), |
1184 | .ops = &hsw_power_well_ops, |
1185 | .has_fuses = true, |
1186 | .irq_pipe_mask = BIT(PIPE_D), |
1187 | }, |
1188 | }; |
1189 | |
1190 | static const struct i915_power_well_desc_list dg1_power_wells[] = { |
1191 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1192 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1193 | I915_PW_DESCRIPTORS(dg1_power_wells_main), |
1194 | I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux), |
1195 | }; |
1196 | |
1197 | /* |
1198 | * XE_LPD Power Domains |
1199 | * |
1200 | * Previous platforms required that PG(n-1) be enabled before PG(n). That |
1201 | * dependency chain turns into a dependency tree on XE_LPD: |
1202 | * |
1203 | * PG0 |
1204 | * | |
1205 | * --PG1-- |
1206 | * / \ |
1207 | * PGA --PG2-- |
1208 | * / | \ |
1209 | * PGB PGC PGD |
1210 | * |
1211 | * Power wells must be enabled from top to bottom and disabled from bottom |
1212 | * to top. This allows pipes to be power gated independently. |
1213 | */ |
1214 | |
1215 | #define XELPD_PW_D_POWER_DOMAINS \ |
1216 | POWER_DOMAIN_PIPE_D, \ |
1217 | POWER_DOMAIN_PIPE_PANEL_FITTER_D, \ |
1218 | POWER_DOMAIN_TRANSCODER_D |
1219 | |
1220 | I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d, |
1221 | XELPD_PW_D_POWER_DOMAINS, |
1222 | POWER_DOMAIN_INIT); |
1223 | |
1224 | #define XELPD_PW_C_POWER_DOMAINS \ |
1225 | POWER_DOMAIN_PIPE_C, \ |
1226 | POWER_DOMAIN_PIPE_PANEL_FITTER_C, \ |
1227 | POWER_DOMAIN_TRANSCODER_C |
1228 | |
1229 | I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c, |
1230 | XELPD_PW_C_POWER_DOMAINS, |
1231 | POWER_DOMAIN_INIT); |
1232 | |
1233 | #define XELPD_PW_B_POWER_DOMAINS \ |
1234 | POWER_DOMAIN_PIPE_B, \ |
1235 | POWER_DOMAIN_PIPE_PANEL_FITTER_B, \ |
1236 | POWER_DOMAIN_TRANSCODER_B |
1237 | |
1238 | I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b, |
1239 | XELPD_PW_B_POWER_DOMAINS, |
1240 | POWER_DOMAIN_INIT); |
1241 | |
1242 | I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, |
1243 | POWER_DOMAIN_PIPE_A, |
1244 | POWER_DOMAIN_PIPE_PANEL_FITTER_A, |
1245 | POWER_DOMAIN_INIT); |
1246 | |
1247 | #define XELPD_DC_OFF_PORT_POWER_DOMAINS \ |
1248 | POWER_DOMAIN_PORT_DDI_LANES_C, \ |
1249 | POWER_DOMAIN_PORT_DDI_LANES_D, \ |
1250 | POWER_DOMAIN_PORT_DDI_LANES_E, \ |
1251 | POWER_DOMAIN_PORT_DDI_LANES_TC1, \ |
1252 | POWER_DOMAIN_PORT_DDI_LANES_TC2, \ |
1253 | POWER_DOMAIN_PORT_DDI_LANES_TC3, \ |
1254 | POWER_DOMAIN_PORT_DDI_LANES_TC4, \ |
1255 | POWER_DOMAIN_VGA, \ |
1256 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
1257 | POWER_DOMAIN_AUX_IO_C, \ |
1258 | POWER_DOMAIN_AUX_IO_D, \ |
1259 | POWER_DOMAIN_AUX_IO_E, \ |
1260 | POWER_DOMAIN_AUX_C, \ |
1261 | POWER_DOMAIN_AUX_D, \ |
1262 | POWER_DOMAIN_AUX_E, \ |
1263 | POWER_DOMAIN_AUX_USBC1, \ |
1264 | POWER_DOMAIN_AUX_USBC2, \ |
1265 | POWER_DOMAIN_AUX_USBC3, \ |
1266 | POWER_DOMAIN_AUX_USBC4, \ |
1267 | POWER_DOMAIN_AUX_TBT1, \ |
1268 | POWER_DOMAIN_AUX_TBT2, \ |
1269 | POWER_DOMAIN_AUX_TBT3, \ |
1270 | POWER_DOMAIN_AUX_TBT4 |
1271 | |
1272 | #define XELPD_PW_2_POWER_DOMAINS \ |
1273 | XELPD_PW_B_POWER_DOMAINS, \ |
1274 | XELPD_PW_C_POWER_DOMAINS, \ |
1275 | XELPD_PW_D_POWER_DOMAINS, \ |
1276 | XELPD_DC_OFF_PORT_POWER_DOMAINS |
1277 | |
1278 | I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, |
1279 | XELPD_PW_2_POWER_DOMAINS, |
1280 | POWER_DOMAIN_INIT); |
1281 | |
1282 | /* |
1283 | * XELPD PW_1/PG_1 domains (under HW/DMC control): |
1284 | * - DBUF function (registers are in PW0) |
1285 | * - Transcoder A |
1286 | * - DDI_A and DDI_B |
1287 | * |
1288 | * XELPD PW_0/PW_1 domains (under HW/DMC control): |
1289 | * - PCI |
1290 | * - Clocks except port PLL |
1291 | * - Shared functions: |
1292 | * * interrupts except pipe interrupts |
1293 | * * MBus except PIPE_MBUS_DBOX_CTL |
1294 | * * DBUF registers |
1295 | * - Central power except FBC |
1296 | * - Top-level GTC (DDI-level GTC is in the well associated with the DDI) |
1297 | */ |
1298 | |
1299 | I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off, |
1300 | XELPD_DC_OFF_PORT_POWER_DOMAINS, |
1301 | XELPD_PW_C_POWER_DOMAINS, |
1302 | XELPD_PW_D_POWER_DOMAINS, |
1303 | POWER_DOMAIN_PORT_DSI, |
1304 | POWER_DOMAIN_AUDIO_MMIO, |
1305 | POWER_DOMAIN_AUX_A, |
1306 | POWER_DOMAIN_AUX_B, |
1307 | POWER_DOMAIN_DC_OFF, |
1308 | POWER_DOMAIN_INIT); |
1309 | |
1310 | static const struct i915_power_well_desc xelpd_power_wells_dc_off[] = { |
1311 | { |
1312 | .instances = &I915_PW_INSTANCES( |
1313 | I915_PW("DC_off" , &xelpd_pwdoms_dc_off, |
1314 | .id = SKL_DISP_DC_OFF), |
1315 | ), |
1316 | .ops = &gen9_dc_off_power_well_ops, |
1317 | } |
1318 | }; |
1319 | |
1320 | static const struct i915_power_well_desc xelpd_power_wells_main[] = { |
1321 | { |
1322 | .instances = &I915_PW_INSTANCES( |
1323 | I915_PW("PW_2" , &xelpd_pwdoms_pw_2, |
1324 | .hsw.idx = ICL_PW_CTL_IDX_PW_2, |
1325 | .id = SKL_DISP_PW_2), |
1326 | ), |
1327 | .ops = &hsw_power_well_ops, |
1328 | .has_vga = true, |
1329 | .has_fuses = true, |
1330 | }, { |
1331 | .instances = &I915_PW_INSTANCES( |
1332 | I915_PW("PW_A" , &xelpd_pwdoms_pw_a, |
1333 | .hsw.idx = XELPD_PW_CTL_IDX_PW_A), |
1334 | ), |
1335 | .ops = &hsw_power_well_ops, |
1336 | .irq_pipe_mask = BIT(PIPE_A), |
1337 | .has_fuses = true, |
1338 | }, { |
1339 | .instances = &I915_PW_INSTANCES( |
1340 | I915_PW("PW_B" , &xelpd_pwdoms_pw_b, |
1341 | .hsw.idx = XELPD_PW_CTL_IDX_PW_B), |
1342 | ), |
1343 | .ops = &hsw_power_well_ops, |
1344 | .irq_pipe_mask = BIT(PIPE_B), |
1345 | .has_fuses = true, |
1346 | }, { |
1347 | .instances = &I915_PW_INSTANCES( |
1348 | I915_PW("PW_C" , &xelpd_pwdoms_pw_c, |
1349 | .hsw.idx = XELPD_PW_CTL_IDX_PW_C), |
1350 | ), |
1351 | .ops = &hsw_power_well_ops, |
1352 | .irq_pipe_mask = BIT(PIPE_C), |
1353 | .has_fuses = true, |
1354 | }, { |
1355 | .instances = &I915_PW_INSTANCES( |
1356 | I915_PW("PW_D" , &xelpd_pwdoms_pw_d, |
1357 | .hsw.idx = XELPD_PW_CTL_IDX_PW_D), |
1358 | ), |
1359 | .ops = &hsw_power_well_ops, |
1360 | .irq_pipe_mask = BIT(PIPE_D), |
1361 | .has_fuses = true, |
1362 | }, { |
1363 | .instances = &I915_PW_INSTANCES( |
1364 | I915_PW("DDI_IO_A" , &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A), |
1365 | I915_PW("DDI_IO_B" , &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B), |
1366 | I915_PW("DDI_IO_C" , &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C), |
1367 | I915_PW("DDI_IO_D" , &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D), |
1368 | I915_PW("DDI_IO_E" , &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E), |
1369 | I915_PW("DDI_IO_TC1" , &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1), |
1370 | I915_PW("DDI_IO_TC2" , &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2), |
1371 | I915_PW("DDI_IO_TC3" , &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3), |
1372 | I915_PW("DDI_IO_TC4" , &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4), |
1373 | ), |
1374 | .ops = &icl_ddi_power_well_ops, |
1375 | }, { |
1376 | .instances = &I915_PW_INSTANCES( |
1377 | I915_PW("AUX_A" , &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A), |
1378 | I915_PW("AUX_B" , &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B), |
1379 | I915_PW("AUX_C" , &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C), |
1380 | I915_PW("AUX_D" , &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D), |
1381 | I915_PW("AUX_E" , &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E), |
1382 | ), |
1383 | .ops = &icl_aux_power_well_ops, |
1384 | .fixed_enable_delay = true, |
1385 | }, { |
1386 | .instances = &I915_PW_INSTANCES( |
1387 | I915_PW("AUX_USBC1" , &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1), |
1388 | I915_PW("AUX_USBC2" , &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2), |
1389 | I915_PW("AUX_USBC3" , &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3), |
1390 | I915_PW("AUX_USBC4" , &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4), |
1391 | ), |
1392 | .ops = &icl_aux_power_well_ops, |
1393 | .fixed_enable_delay = true, |
1394 | /* WA_14017248603: adlp */ |
1395 | .enable_timeout = 500, |
1396 | }, { |
1397 | .instances = &I915_PW_INSTANCES( |
1398 | I915_PW("AUX_TBT1" , &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1), |
1399 | I915_PW("AUX_TBT2" , &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2), |
1400 | I915_PW("AUX_TBT3" , &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3), |
1401 | I915_PW("AUX_TBT4" , &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4), |
1402 | ), |
1403 | .ops = &icl_aux_power_well_ops, |
1404 | .is_tc_tbt = true, |
1405 | }, |
1406 | }; |
1407 | |
1408 | static const struct i915_power_well_desc_list xelpd_power_wells[] = { |
1409 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1410 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1411 | I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), |
1412 | I915_PW_DESCRIPTORS(xelpd_power_wells_main), |
1413 | }; |
1414 | |
1415 | I915_DECL_PW_DOMAINS(xehpd_pwdoms_dc_off, |
1416 | XELPD_PW_2_POWER_DOMAINS, |
1417 | POWER_DOMAIN_PORT_DSI, |
1418 | POWER_DOMAIN_AUDIO_MMIO, |
1419 | POWER_DOMAIN_AUX_A, |
1420 | POWER_DOMAIN_AUX_B, |
1421 | POWER_DOMAIN_DC_OFF, |
1422 | POWER_DOMAIN_INIT); |
1423 | |
1424 | static const struct i915_power_well_desc xehpd_power_wells_dc_off[] = { |
1425 | { |
1426 | .instances = &I915_PW_INSTANCES( |
1427 | I915_PW("DC_off" , &xehpd_pwdoms_dc_off, |
1428 | .id = SKL_DISP_DC_OFF), |
1429 | ), |
1430 | .ops = &gen9_dc_off_power_well_ops, |
1431 | } |
1432 | }; |
1433 | |
1434 | static const struct i915_power_well_desc_list xehpd_power_wells[] = { |
1435 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1436 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1437 | I915_PW_DESCRIPTORS(xehpd_power_wells_dc_off), |
1438 | I915_PW_DESCRIPTORS(xelpd_power_wells_main), |
1439 | }; |
1440 | |
1441 | /* |
1442 | * MTL is based on XELPD power domains with the exception of power gating for: |
1443 | * - DDI_IO (moved to PLL logic) |
1444 | * - AUX and AUX_IO functionality and register access for USBC1-4 (PICA always-on) |
1445 | */ |
1446 | #define XELPDP_PW_2_POWER_DOMAINS \ |
1447 | XELPD_PW_B_POWER_DOMAINS, \ |
1448 | XELPD_PW_C_POWER_DOMAINS, \ |
1449 | XELPD_PW_D_POWER_DOMAINS, \ |
1450 | POWER_DOMAIN_AUDIO_PLAYBACK, \ |
1451 | POWER_DOMAIN_VGA, \ |
1452 | POWER_DOMAIN_PORT_DDI_LANES_TC1, \ |
1453 | POWER_DOMAIN_PORT_DDI_LANES_TC2, \ |
1454 | POWER_DOMAIN_PORT_DDI_LANES_TC3, \ |
1455 | POWER_DOMAIN_PORT_DDI_LANES_TC4 |
1456 | |
1457 | I915_DECL_PW_DOMAINS(xelpdp_pwdoms_pw_2, |
1458 | XELPDP_PW_2_POWER_DOMAINS, |
1459 | POWER_DOMAIN_INIT); |
1460 | |
1461 | I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc1, |
1462 | POWER_DOMAIN_AUX_USBC1, |
1463 | POWER_DOMAIN_AUX_TBT1); |
1464 | |
1465 | I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc2, |
1466 | POWER_DOMAIN_AUX_USBC2, |
1467 | POWER_DOMAIN_AUX_TBT2); |
1468 | |
1469 | I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc3, |
1470 | POWER_DOMAIN_AUX_USBC3, |
1471 | POWER_DOMAIN_AUX_TBT3); |
1472 | |
1473 | I915_DECL_PW_DOMAINS(xelpdp_pwdoms_aux_tc4, |
1474 | POWER_DOMAIN_AUX_USBC4, |
1475 | POWER_DOMAIN_AUX_TBT4); |
1476 | |
1477 | static const struct i915_power_well_desc xelpdp_power_wells_main[] = { |
1478 | { |
1479 | .instances = &I915_PW_INSTANCES( |
1480 | I915_PW("PW_2" , &xelpdp_pwdoms_pw_2, |
1481 | .hsw.idx = ICL_PW_CTL_IDX_PW_2, |
1482 | .id = SKL_DISP_PW_2), |
1483 | ), |
1484 | .ops = &hsw_power_well_ops, |
1485 | .has_vga = true, |
1486 | .has_fuses = true, |
1487 | }, { |
1488 | .instances = &I915_PW_INSTANCES( |
1489 | I915_PW("PW_A" , &xelpd_pwdoms_pw_a, |
1490 | .hsw.idx = XELPD_PW_CTL_IDX_PW_A), |
1491 | ), |
1492 | .ops = &hsw_power_well_ops, |
1493 | .irq_pipe_mask = BIT(PIPE_A), |
1494 | .has_fuses = true, |
1495 | }, { |
1496 | .instances = &I915_PW_INSTANCES( |
1497 | I915_PW("PW_B" , &xelpd_pwdoms_pw_b, |
1498 | .hsw.idx = XELPD_PW_CTL_IDX_PW_B), |
1499 | ), |
1500 | .ops = &hsw_power_well_ops, |
1501 | .irq_pipe_mask = BIT(PIPE_B), |
1502 | .has_fuses = true, |
1503 | }, { |
1504 | .instances = &I915_PW_INSTANCES( |
1505 | I915_PW("PW_C" , &xelpd_pwdoms_pw_c, |
1506 | .hsw.idx = XELPD_PW_CTL_IDX_PW_C), |
1507 | ), |
1508 | .ops = &hsw_power_well_ops, |
1509 | .irq_pipe_mask = BIT(PIPE_C), |
1510 | .has_fuses = true, |
1511 | }, { |
1512 | .instances = &I915_PW_INSTANCES( |
1513 | I915_PW("PW_D" , &xelpd_pwdoms_pw_d, |
1514 | .hsw.idx = XELPD_PW_CTL_IDX_PW_D), |
1515 | ), |
1516 | .ops = &hsw_power_well_ops, |
1517 | .irq_pipe_mask = BIT(PIPE_D), |
1518 | .has_fuses = true, |
1519 | }, { |
1520 | .instances = &I915_PW_INSTANCES( |
1521 | I915_PW("AUX_A" , &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), |
1522 | I915_PW("AUX_B" , &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), |
1523 | I915_PW("AUX_TC1" , &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), |
1524 | I915_PW("AUX_TC2" , &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), |
1525 | I915_PW("AUX_TC3" , &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), |
1526 | I915_PW("AUX_TC4" , &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), |
1527 | ), |
1528 | .ops = &xelpdp_aux_power_well_ops, |
1529 | }, |
1530 | }; |
1531 | |
1532 | static const struct i915_power_well_desc_list xelpdp_power_wells[] = { |
1533 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1534 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1535 | I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off), |
1536 | I915_PW_DESCRIPTORS(xelpdp_power_wells_main), |
1537 | }; |
1538 | |
1539 | I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc, |
1540 | POWER_DOMAIN_PORT_DDI_LANES_TC1, |
1541 | POWER_DOMAIN_PORT_DDI_LANES_TC2, |
1542 | POWER_DOMAIN_PORT_DDI_LANES_TC3, |
1543 | POWER_DOMAIN_PORT_DDI_LANES_TC4, |
1544 | POWER_DOMAIN_AUX_USBC1, |
1545 | POWER_DOMAIN_AUX_USBC2, |
1546 | POWER_DOMAIN_AUX_USBC3, |
1547 | POWER_DOMAIN_AUX_USBC4, |
1548 | POWER_DOMAIN_AUX_TBT1, |
1549 | POWER_DOMAIN_AUX_TBT2, |
1550 | POWER_DOMAIN_AUX_TBT3, |
1551 | POWER_DOMAIN_AUX_TBT4, |
1552 | POWER_DOMAIN_INIT); |
1553 | |
1554 | static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = { |
1555 | { |
1556 | .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC" , |
1557 | &xe2lpd_pwdoms_pica_tc, |
1558 | .id = DISP_PW_ID_NONE), |
1559 | ), |
1560 | .ops = &xe2lpd_pica_power_well_ops, |
1561 | }, |
1562 | }; |
1563 | |
1564 | I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off, |
1565 | POWER_DOMAIN_DC_OFF, |
1566 | XELPD_PW_C_POWER_DOMAINS, |
1567 | XELPD_PW_D_POWER_DOMAINS, |
1568 | POWER_DOMAIN_AUDIO_MMIO, |
1569 | POWER_DOMAIN_INIT); |
1570 | |
1571 | static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = { |
1572 | { |
1573 | .instances = &I915_PW_INSTANCES( |
1574 | I915_PW("DC_off" , &xe2lpd_pwdoms_dc_off, |
1575 | .id = SKL_DISP_DC_OFF), |
1576 | ), |
1577 | .ops = &gen9_dc_off_power_well_ops, |
1578 | }, |
1579 | }; |
1580 | |
1581 | static const struct i915_power_well_desc_list xe2lpd_power_wells[] = { |
1582 | I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), |
1583 | I915_PW_DESCRIPTORS(icl_power_wells_pw_1), |
1584 | I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff), |
1585 | I915_PW_DESCRIPTORS(xelpdp_power_wells_main), |
1586 | I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), |
1587 | }; |
1588 | |
1589 | static void init_power_well_domains(const struct i915_power_well_instance *inst, |
1590 | struct i915_power_well *power_well) |
1591 | { |
1592 | int j; |
1593 | |
1594 | if (!inst->domain_list) |
1595 | return; |
1596 | |
1597 | if (inst->domain_list->count == 0) { |
1598 | bitmap_fill(dst: power_well->domains.bits, nbits: POWER_DOMAIN_NUM); |
1599 | |
1600 | return; |
1601 | } |
1602 | |
1603 | for (j = 0; j < inst->domain_list->count; j++) |
1604 | set_bit(nr: inst->domain_list->list[j], addr: power_well->domains.bits); |
1605 | } |
1606 | |
1607 | #define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \ |
1608 | for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \ |
1609 | for ((_inst) = (_desc)->instances->list; \ |
1610 | (_inst) - (_desc)->instances->list < (_desc)->instances->count; \ |
1611 | (_inst)++) |
1612 | |
1613 | #define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \ |
1614 | for ((_descs) = (_desc_list); \ |
1615 | (_descs) - (_desc_list) < (_desc_count); \ |
1616 | (_descs)++) \ |
1617 | for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \ |
1618 | (_desc), (_inst)) |
1619 | |
1620 | static int |
1621 | __set_power_wells(struct i915_power_domains *power_domains, |
1622 | const struct i915_power_well_desc_list *power_well_descs, |
1623 | int power_well_descs_sz) |
1624 | { |
1625 | struct drm_i915_private *i915 = container_of(power_domains, |
1626 | struct drm_i915_private, |
1627 | display.power.domains); |
1628 | u64 power_well_ids = 0; |
1629 | const struct i915_power_well_desc_list *desc_list; |
1630 | const struct i915_power_well_desc *desc; |
1631 | const struct i915_power_well_instance *inst; |
1632 | int power_well_count = 0; |
1633 | int plt_idx = 0; |
1634 | |
1635 | for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) |
1636 | power_well_count++; |
1637 | |
1638 | power_domains->power_well_count = power_well_count; |
1639 | power_domains->power_wells = |
1640 | kcalloc(n: power_well_count, |
1641 | size: sizeof(*power_domains->power_wells), |
1642 | GFP_KERNEL); |
1643 | if (!power_domains->power_wells) |
1644 | return -ENOMEM; |
1645 | |
1646 | for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) { |
1647 | struct i915_power_well *pw = &power_domains->power_wells[plt_idx]; |
1648 | enum i915_power_well_id id = inst->id; |
1649 | |
1650 | pw->desc = desc; |
1651 | drm_WARN_ON(&i915->drm, |
1652 | overflows_type(inst - desc->instances->list, pw->instance_idx)); |
1653 | pw->instance_idx = inst - desc->instances->list; |
1654 | |
1655 | init_power_well_domains(inst, power_well: pw); |
1656 | |
1657 | plt_idx++; |
1658 | |
1659 | if (id == DISP_PW_ID_NONE) |
1660 | continue; |
1661 | |
1662 | drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8); |
1663 | drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id)); |
1664 | power_well_ids |= BIT_ULL(id); |
1665 | } |
1666 | |
1667 | return 0; |
1668 | } |
1669 | |
1670 | #define set_power_wells(power_domains, __power_well_descs) \ |
1671 | __set_power_wells(power_domains, __power_well_descs, \ |
1672 | ARRAY_SIZE(__power_well_descs)) |
1673 | |
1674 | /** |
1675 | * intel_display_power_map_init - initialize power domain -> power well mappings |
1676 | * @power_domains: power domain state |
1677 | * |
1678 | * Creates all the power wells for the current platform, initializes the |
1679 | * dynamic state for them and initializes the mapping of each power well to |
1680 | * all the power domains the power well belongs to. |
1681 | */ |
1682 | int intel_display_power_map_init(struct i915_power_domains *power_domains) |
1683 | { |
1684 | struct drm_i915_private *i915 = container_of(power_domains, |
1685 | struct drm_i915_private, |
1686 | display.power.domains); |
1687 | /* |
1688 | * The enabling order will be from lower to higher indexed wells, |
1689 | * the disabling order is reversed. |
1690 | */ |
1691 | if (!HAS_DISPLAY(i915)) { |
1692 | power_domains->power_well_count = 0; |
1693 | return 0; |
1694 | } |
1695 | |
1696 | if (DISPLAY_VER(i915) >= 20) |
1697 | return set_power_wells(power_domains, xe2lpd_power_wells); |
1698 | else if (DISPLAY_VER(i915) >= 14) |
1699 | return set_power_wells(power_domains, xelpdp_power_wells); |
1700 | else if (IS_DG2(i915)) |
1701 | return set_power_wells(power_domains, xehpd_power_wells); |
1702 | else if (DISPLAY_VER(i915) >= 13) |
1703 | return set_power_wells(power_domains, xelpd_power_wells); |
1704 | else if (IS_DG1(i915)) |
1705 | return set_power_wells(power_domains, dg1_power_wells); |
1706 | else if (IS_ALDERLAKE_S(i915)) |
1707 | return set_power_wells(power_domains, adls_power_wells); |
1708 | else if (IS_ROCKETLAKE(i915)) |
1709 | return set_power_wells(power_domains, rkl_power_wells); |
1710 | else if (DISPLAY_VER(i915) == 12) |
1711 | return set_power_wells(power_domains, tgl_power_wells); |
1712 | else if (DISPLAY_VER(i915) == 11) |
1713 | return set_power_wells(power_domains, icl_power_wells); |
1714 | else if (IS_GEMINILAKE(i915)) |
1715 | return set_power_wells(power_domains, glk_power_wells); |
1716 | else if (IS_BROXTON(i915)) |
1717 | return set_power_wells(power_domains, bxt_power_wells); |
1718 | else if (DISPLAY_VER(i915) == 9) |
1719 | return set_power_wells(power_domains, skl_power_wells); |
1720 | else if (IS_CHERRYVIEW(i915)) |
1721 | return set_power_wells(power_domains, chv_power_wells); |
1722 | else if (IS_BROADWELL(i915)) |
1723 | return set_power_wells(power_domains, bdw_power_wells); |
1724 | else if (IS_HASWELL(i915)) |
1725 | return set_power_wells(power_domains, hsw_power_wells); |
1726 | else if (IS_VALLEYVIEW(i915)) |
1727 | return set_power_wells(power_domains, vlv_power_wells); |
1728 | else if (IS_I830(i915)) |
1729 | return set_power_wells(power_domains, i830_power_wells); |
1730 | else |
1731 | return set_power_wells(power_domains, i9xx_power_wells); |
1732 | } |
1733 | |
1734 | /** |
1735 | * intel_display_power_map_cleanup - clean up power domain -> power well mappings |
1736 | * @power_domains: power domain state |
1737 | * |
1738 | * Cleans up all the state that was initialized by intel_display_power_map_init(). |
1739 | */ |
1740 | void intel_display_power_map_cleanup(struct i915_power_domains *power_domains) |
1741 | { |
1742 | kfree(objp: power_domains->power_wells); |
1743 | } |
1744 | |