1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright © 2022 Intel Corporation |
4 | */ |
5 | #ifndef __INTEL_DISPLAY_POWER_WELL_H__ |
6 | #define __INTEL_DISPLAY_POWER_WELL_H__ |
7 | |
8 | #include <linux/types.h> |
9 | |
10 | #include "intel_display_power.h" |
11 | #include "intel_dpio_phy.h" |
12 | |
13 | struct drm_i915_private; |
14 | struct i915_power_well_ops; |
15 | struct intel_encoder; |
16 | |
17 | #define for_each_power_well(__dev_priv, __power_well) \ |
18 | for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \ |
19 | (__power_well) - (__dev_priv)->display.power.domains.power_wells < \ |
20 | (__dev_priv)->display.power.domains.power_well_count; \ |
21 | (__power_well)++) |
22 | |
23 | #define for_each_power_well_reverse(__dev_priv, __power_well) \ |
24 | for ((__power_well) = (__dev_priv)->display.power.domains.power_wells + \ |
25 | (__dev_priv)->display.power.domains.power_well_count - 1; \ |
26 | (__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0; \ |
27 | (__power_well)--) |
28 | |
29 | /* |
30 | * i915_power_well_id: |
31 | * |
32 | * IDs used to look up power wells. Power wells accessed directly bypassing |
33 | * the power domains framework must be assigned a unique ID. The rest of power |
34 | * wells must be assigned DISP_PW_ID_NONE. |
35 | */ |
36 | enum i915_power_well_id { |
37 | DISP_PW_ID_NONE = 0, /* must be kept zero */ |
38 | |
39 | VLV_DISP_PW_DISP2D, |
40 | BXT_DISP_PW_DPIO_CMN_A, |
41 | VLV_DISP_PW_DPIO_CMN_BC, |
42 | GLK_DISP_PW_DPIO_CMN_C, |
43 | CHV_DISP_PW_DPIO_CMN_D, |
44 | HSW_DISP_PW_GLOBAL, |
45 | SKL_DISP_PW_MISC_IO, |
46 | SKL_DISP_PW_1, |
47 | SKL_DISP_PW_2, |
48 | ICL_DISP_PW_3, |
49 | SKL_DISP_DC_OFF, |
50 | TGL_DISP_PW_TC_COLD_OFF, |
51 | }; |
52 | |
53 | struct i915_power_well_instance { |
54 | const char *name; |
55 | const struct i915_power_domain_list { |
56 | const enum intel_display_power_domain *list; |
57 | u8 count; |
58 | } *domain_list; |
59 | |
60 | /* unique identifier for this power well */ |
61 | enum i915_power_well_id id; |
62 | /* |
63 | * Arbitraty data associated with this power well. Platform and power |
64 | * well specific. |
65 | */ |
66 | union { |
67 | struct { |
68 | /* |
69 | * request/status flag index in the PUNIT power well |
70 | * control/status registers. |
71 | */ |
72 | u8 idx; |
73 | } vlv; |
74 | struct { |
75 | enum dpio_phy phy; |
76 | } bxt; |
77 | struct { |
78 | /* |
79 | * request/status flag index in the power well |
80 | * constrol/status registers. |
81 | */ |
82 | u8 idx; |
83 | } hsw; |
84 | struct { |
85 | u8 aux_ch; |
86 | } xelpdp; |
87 | }; |
88 | }; |
89 | |
90 | struct i915_power_well_desc { |
91 | const struct i915_power_well_ops *ops; |
92 | const struct i915_power_well_instance_list { |
93 | const struct i915_power_well_instance *list; |
94 | u8 count; |
95 | } *instances; |
96 | |
97 | /* Mask of pipes whose IRQ logic is backed by the pw */ |
98 | u16 irq_pipe_mask:4; |
99 | u16 always_on:1; |
100 | /* |
101 | * Instead of waiting for the status bit to ack enables, |
102 | * just wait a specific amount of time and then consider |
103 | * the well enabled. |
104 | */ |
105 | u16 fixed_enable_delay:1; |
106 | /* The pw is backing the VGA functionality */ |
107 | u16 has_vga:1; |
108 | u16 has_fuses:1; |
109 | /* |
110 | * The pw is for an ICL+ TypeC PHY port in |
111 | * Thunderbolt mode. |
112 | */ |
113 | u16 is_tc_tbt:1; |
114 | /* Enable timeout if greater than the default 1ms */ |
115 | u16 enable_timeout; |
116 | }; |
117 | |
118 | struct i915_power_well { |
119 | const struct i915_power_well_desc *desc; |
120 | struct intel_power_domain_mask domains; |
121 | /* power well enable/disable usage count */ |
122 | int count; |
123 | /* cached hw enabled state */ |
124 | bool hw_enabled; |
125 | /* index into desc->instances->list */ |
126 | u8 instance_idx; |
127 | }; |
128 | |
129 | struct i915_power_well *lookup_power_well(struct drm_i915_private *i915, |
130 | enum i915_power_well_id id); |
131 | |
132 | void intel_power_well_enable(struct drm_i915_private *i915, |
133 | struct i915_power_well *power_well); |
134 | void intel_power_well_disable(struct drm_i915_private *i915, |
135 | struct i915_power_well *power_well); |
136 | void intel_power_well_sync_hw(struct drm_i915_private *i915, |
137 | struct i915_power_well *power_well); |
138 | void intel_power_well_get(struct drm_i915_private *i915, |
139 | struct i915_power_well *power_well); |
140 | void intel_power_well_put(struct drm_i915_private *i915, |
141 | struct i915_power_well *power_well); |
142 | bool intel_power_well_is_enabled(struct drm_i915_private *i915, |
143 | struct i915_power_well *power_well); |
144 | bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well); |
145 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
146 | enum i915_power_well_id power_well_id); |
147 | bool intel_power_well_is_always_on(struct i915_power_well *power_well); |
148 | const char *intel_power_well_name(struct i915_power_well *power_well); |
149 | struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well); |
150 | int intel_power_well_refcount(struct i915_power_well *power_well); |
151 | |
152 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
153 | bool override, unsigned int mask); |
154 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
155 | enum dpio_channel ch, bool override); |
156 | |
157 | void gen9_enable_dc5(struct drm_i915_private *dev_priv); |
158 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
159 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); |
160 | void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state); |
161 | void gen9_disable_dc_states(struct drm_i915_private *dev_priv); |
162 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
163 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); |
164 | |
165 | extern const struct i915_power_well_ops i9xx_always_on_power_well_ops; |
166 | extern const struct i915_power_well_ops chv_pipe_power_well_ops; |
167 | extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops; |
168 | extern const struct i915_power_well_ops i830_pipes_power_well_ops; |
169 | extern const struct i915_power_well_ops hsw_power_well_ops; |
170 | extern const struct i915_power_well_ops gen9_dc_off_power_well_ops; |
171 | extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops; |
172 | extern const struct i915_power_well_ops vlv_display_power_well_ops; |
173 | extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops; |
174 | extern const struct i915_power_well_ops vlv_dpio_power_well_ops; |
175 | extern const struct i915_power_well_ops icl_aux_power_well_ops; |
176 | extern const struct i915_power_well_ops icl_ddi_power_well_ops; |
177 | extern const struct i915_power_well_ops tgl_tc_cold_off_ops; |
178 | extern const struct i915_power_well_ops xelpdp_aux_power_well_ops; |
179 | extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops; |
180 | |
181 | #endif |
182 | |