1 | /* |
2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
21 | * SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Ke Yu |
25 | * Zhiyuan Lv <zhiyuan.lv@intel.com> |
26 | * |
27 | * Contributors: |
28 | * Terrence Xu <terrence.xu@intel.com> |
29 | * Changbin Du <changbin.du@intel.com> |
30 | * Bing Niu <bing.niu@intel.com> |
31 | * Zhi Wang <zhi.a.wang@intel.com> |
32 | * |
33 | */ |
34 | |
35 | #include "i915_drv.h" |
36 | #include "i915_reg.h" |
37 | #include "gvt.h" |
38 | |
39 | #include "display/intel_display.h" |
40 | #include "display/intel_dpio_phy.h" |
41 | |
42 | static int get_edp_pipe(struct intel_vgpu *vgpu) |
43 | { |
44 | u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP); |
45 | int pipe = -1; |
46 | |
47 | switch (data & TRANS_DDI_EDP_INPUT_MASK) { |
48 | case TRANS_DDI_EDP_INPUT_A_ON: |
49 | case TRANS_DDI_EDP_INPUT_A_ONOFF: |
50 | pipe = PIPE_A; |
51 | break; |
52 | case TRANS_DDI_EDP_INPUT_B_ONOFF: |
53 | pipe = PIPE_B; |
54 | break; |
55 | case TRANS_DDI_EDP_INPUT_C_ONOFF: |
56 | pipe = PIPE_C; |
57 | break; |
58 | } |
59 | return pipe; |
60 | } |
61 | |
62 | static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) |
63 | { |
64 | struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
65 | |
66 | if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE)) |
67 | return 0; |
68 | |
69 | if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) |
70 | return 0; |
71 | return 1; |
72 | } |
73 | |
74 | int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) |
75 | { |
76 | struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
77 | |
78 | if (drm_WARN_ON(&dev_priv->drm, |
79 | pipe < PIPE_A || pipe >= I915_MAX_PIPES)) |
80 | return -EINVAL; |
81 | |
82 | if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE) |
83 | return 1; |
84 | |
85 | if (edp_pipe_is_enabled(vgpu) && |
86 | get_edp_pipe(vgpu) == pipe) |
87 | return 1; |
88 | return 0; |
89 | } |
90 | |
91 | static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { |
92 | { |
93 | /* EDID with 1024x768 as its resolution */ |
94 | /*Header*/ |
95 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, |
96 | /* Vendor & Product Identification */ |
97 | 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, |
98 | /* Version & Revision */ |
99 | 0x01, 0x04, |
100 | /* Basic Display Parameters & Features */ |
101 | 0xa5, 0x34, 0x20, 0x78, 0x23, |
102 | /* Color Characteristics */ |
103 | 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, |
104 | /* Established Timings: maximum resolution is 1024x768 */ |
105 | 0x21, 0x08, 0x00, |
106 | /* Standard Timings. All invalid */ |
107 | 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00, |
108 | 0x00, 0x40, 0x00, 0x00, 0x00, 0x01, |
109 | /* 18 Byte Data Blocks 1: invalid */ |
110 | 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0, |
111 | 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, |
112 | /* 18 Byte Data Blocks 2: invalid */ |
113 | 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, |
114 | 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, |
115 | /* 18 Byte Data Blocks 3: invalid */ |
116 | 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, |
117 | 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, |
118 | /* 18 Byte Data Blocks 4: invalid */ |
119 | 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, |
120 | 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, |
121 | /* Extension Block Count */ |
122 | 0x00, |
123 | /* Checksum */ |
124 | 0xef, |
125 | }, |
126 | { |
127 | /* EDID with 1920x1200 as its resolution */ |
128 | /*Header*/ |
129 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, |
130 | /* Vendor & Product Identification */ |
131 | 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17, |
132 | /* Version & Revision */ |
133 | 0x01, 0x04, |
134 | /* Basic Display Parameters & Features */ |
135 | 0xa5, 0x34, 0x20, 0x78, 0x23, |
136 | /* Color Characteristics */ |
137 | 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54, |
138 | /* Established Timings: maximum resolution is 1024x768 */ |
139 | 0x21, 0x08, 0x00, |
140 | /* |
141 | * Standard Timings. |
142 | * below new resolutions can be supported: |
143 | * 1920x1080, 1280x720, 1280x960, 1280x1024, |
144 | * 1440x900, 1600x1200, 1680x1050 |
145 | */ |
146 | 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, |
147 | 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01, |
148 | /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */ |
149 | 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, |
150 | 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a, |
151 | /* 18 Byte Data Blocks 2: invalid */ |
152 | 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a, |
153 | 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, |
154 | /* 18 Byte Data Blocks 3: invalid */ |
155 | 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48, |
156 | 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20, |
157 | /* 18 Byte Data Blocks 4: invalid */ |
158 | 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30, |
159 | 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20, |
160 | /* Extension Block Count */ |
161 | 0x00, |
162 | /* Checksum */ |
163 | 0x45, |
164 | }, |
165 | }; |
166 | |
167 | #define 0xb |
168 | |
169 | /* let the virtual display supports DP1.2 */ |
170 | static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { |
171 | 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
172 | }; |
173 | |
174 | static void emulate_monitor_status_change(struct intel_vgpu *vgpu) |
175 | { |
176 | struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
177 | int pipe; |
178 | |
179 | if (IS_BROXTON(dev_priv)) { |
180 | enum transcoder trans; |
181 | enum port port; |
182 | |
183 | /* Clear PIPE, DDI, PHY, HPD before setting new */ |
184 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= |
185 | ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | |
186 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | |
187 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); |
188 | |
189 | for_each_pipe(dev_priv, pipe) { |
190 | vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= |
191 | ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); |
192 | vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; |
193 | vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; |
194 | vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; |
195 | vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; |
196 | } |
197 | |
198 | for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { |
199 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= |
200 | ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | |
201 | TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); |
202 | } |
203 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= |
204 | ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | |
205 | TRANS_DDI_PORT_MASK); |
206 | |
207 | for (port = PORT_A; port <= PORT_C; port++) { |
208 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &= |
209 | ~BXT_PHY_LANE_ENABLED; |
210 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |= |
211 | (BXT_PHY_CMNLANE_POWERDOWN_ACK | |
212 | BXT_PHY_LANE_POWERDOWN_ACK); |
213 | |
214 | vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &= |
215 | ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | |
216 | PORT_PLL_REF_SEL | PORT_PLL_LOCK | |
217 | PORT_PLL_ENABLE); |
218 | |
219 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= |
220 | ~(DDI_INIT_DISPLAY_DETECTED | |
221 | DDI_BUF_CTL_ENABLE); |
222 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; |
223 | } |
224 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= |
225 | ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); |
226 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= |
227 | ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK); |
228 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= |
229 | ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK); |
230 | /* No hpd_invert set in vgpu vbt, need to clear invert mask */ |
231 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK; |
232 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK; |
233 | |
234 | vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); |
235 | vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= |
236 | ~PHY_POWER_GOOD; |
237 | vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= |
238 | ~PHY_POWER_GOOD; |
239 | vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); |
240 | vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); |
241 | |
242 | vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED; |
243 | vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED; |
244 | |
245 | /* |
246 | * Only 1 PIPE enabled in current vGPU display and PIPE_A is |
247 | * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, |
248 | * TRANSCODER_A can be enabled. PORT_x depends on the input of |
249 | * setup_virtual_dp_monitor. |
250 | */ |
251 | vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; |
252 | vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; |
253 | |
254 | /* |
255 | * Golden M/N are calculated based on: |
256 | * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), |
257 | * DP link clk 1620 MHz and non-constant_n. |
258 | * TODO: calculate DP link symbol clk and stream clk m/n. |
259 | */ |
260 | vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); |
261 | vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; |
262 | vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; |
263 | vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; |
264 | vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; |
265 | |
266 | /* Enable per-DDI/PORT vreg */ |
267 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { |
268 | vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1); |
269 | vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= |
270 | PHY_POWER_GOOD; |
271 | vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= |
272 | BIT(30); |
273 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= |
274 | BXT_PHY_LANE_ENABLED; |
275 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= |
276 | ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | |
277 | BXT_PHY_LANE_POWERDOWN_ACK); |
278 | vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= |
279 | (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | |
280 | PORT_PLL_REF_SEL | PORT_PLL_LOCK | |
281 | PORT_PLL_ENABLE); |
282 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= |
283 | (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); |
284 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= |
285 | ~DDI_BUF_IS_IDLE; |
286 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= |
287 | (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | |
288 | TRANS_DDI_FUNC_ENABLE); |
289 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
290 | PORTA_HOTPLUG_ENABLE; |
291 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
292 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); |
293 | } |
294 | |
295 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { |
296 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; |
297 | vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); |
298 | vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= |
299 | PHY_POWER_GOOD; |
300 | vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= |
301 | BIT(30); |
302 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= |
303 | BXT_PHY_LANE_ENABLED; |
304 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= |
305 | ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | |
306 | BXT_PHY_LANE_POWERDOWN_ACK); |
307 | vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |= |
308 | (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | |
309 | PORT_PLL_REF_SEL | PORT_PLL_LOCK | |
310 | PORT_PLL_ENABLE); |
311 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= |
312 | DDI_BUF_CTL_ENABLE; |
313 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= |
314 | ~DDI_BUF_IS_IDLE; |
315 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= |
316 | (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | |
317 | (PORT_B << TRANS_DDI_PORT_SHIFT) | |
318 | TRANS_DDI_FUNC_ENABLE); |
319 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
320 | PORTB_HOTPLUG_ENABLE; |
321 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
322 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); |
323 | } |
324 | |
325 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { |
326 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; |
327 | vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0); |
328 | vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= |
329 | PHY_POWER_GOOD; |
330 | vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= |
331 | BIT(30); |
332 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= |
333 | BXT_PHY_LANE_ENABLED; |
334 | vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= |
335 | ~(BXT_PHY_CMNLANE_POWERDOWN_ACK | |
336 | BXT_PHY_LANE_POWERDOWN_ACK); |
337 | vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |= |
338 | (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | |
339 | PORT_PLL_REF_SEL | PORT_PLL_LOCK | |
340 | PORT_PLL_ENABLE); |
341 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= |
342 | DDI_BUF_CTL_ENABLE; |
343 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= |
344 | ~DDI_BUF_IS_IDLE; |
345 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= |
346 | (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | |
347 | (PORT_B << TRANS_DDI_PORT_SHIFT) | |
348 | TRANS_DDI_FUNC_ENABLE); |
349 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
350 | PORTC_HOTPLUG_ENABLE; |
351 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
352 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); |
353 | } |
354 | |
355 | return; |
356 | } |
357 | |
358 | vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT | |
359 | SDE_PORTC_HOTPLUG_CPT | |
360 | SDE_PORTD_HOTPLUG_CPT); |
361 | |
362 | if (IS_SKYLAKE(dev_priv) || |
363 | IS_KABYLAKE(dev_priv) || |
364 | IS_COFFEELAKE(dev_priv) || |
365 | IS_COMETLAKE(dev_priv)) { |
366 | vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | |
367 | SDE_PORTE_HOTPLUG_SPT); |
368 | vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= |
369 | SKL_FUSE_DOWNLOAD_STATUS | |
370 | SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | |
371 | SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | |
372 | SKL_FUSE_PG_DIST_STATUS(SKL_PG2); |
373 | /* |
374 | * Only 1 PIPE enabled in current vGPU display and PIPE_A is |
375 | * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, |
376 | * TRANSCODER_A can be enabled. PORT_x depends on the input of |
377 | * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x |
378 | * so we fixed to DPLL0 here. |
379 | * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode |
380 | */ |
381 | vgpu_vreg_t(vgpu, DPLL_CTRL1) = |
382 | DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); |
383 | vgpu_vreg_t(vgpu, DPLL_CTRL1) |= |
384 | DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); |
385 | vgpu_vreg_t(vgpu, LCPLL1_CTL) = |
386 | LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; |
387 | vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); |
388 | /* |
389 | * Golden M/N are calculated based on: |
390 | * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), |
391 | * DP link clk 1620 MHz and non-constant_n. |
392 | * TODO: calculate DP link symbol clk and stream clk m/n. |
393 | */ |
394 | vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); |
395 | vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; |
396 | vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; |
397 | vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; |
398 | vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; |
399 | } |
400 | |
401 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { |
402 | vgpu_vreg_t(vgpu, DPLL_CTRL2) &= |
403 | ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); |
404 | vgpu_vreg_t(vgpu, DPLL_CTRL2) |= |
405 | DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); |
406 | vgpu_vreg_t(vgpu, DPLL_CTRL2) |= |
407 | DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); |
408 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; |
409 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= |
410 | ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | |
411 | TRANS_DDI_PORT_MASK); |
412 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= |
413 | (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | |
414 | (PORT_B << TRANS_DDI_PORT_SHIFT) | |
415 | TRANS_DDI_FUNC_ENABLE); |
416 | if (IS_BROADWELL(dev_priv)) { |
417 | vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= |
418 | ~PORT_CLK_SEL_MASK; |
419 | vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= |
420 | PORT_CLK_SEL_LCPLL_810; |
421 | } |
422 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; |
423 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; |
424 | vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; |
425 | } |
426 | |
427 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { |
428 | vgpu_vreg_t(vgpu, DPLL_CTRL2) &= |
429 | ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); |
430 | vgpu_vreg_t(vgpu, DPLL_CTRL2) |= |
431 | DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); |
432 | vgpu_vreg_t(vgpu, DPLL_CTRL2) |= |
433 | DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); |
434 | vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; |
435 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= |
436 | ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | |
437 | TRANS_DDI_PORT_MASK); |
438 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= |
439 | (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | |
440 | (PORT_C << TRANS_DDI_PORT_SHIFT) | |
441 | TRANS_DDI_FUNC_ENABLE); |
442 | if (IS_BROADWELL(dev_priv)) { |
443 | vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &= |
444 | ~PORT_CLK_SEL_MASK; |
445 | vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= |
446 | PORT_CLK_SEL_LCPLL_810; |
447 | } |
448 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; |
449 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; |
450 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; |
451 | } |
452 | |
453 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { |
454 | vgpu_vreg_t(vgpu, DPLL_CTRL2) &= |
455 | ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); |
456 | vgpu_vreg_t(vgpu, DPLL_CTRL2) |= |
457 | DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); |
458 | vgpu_vreg_t(vgpu, DPLL_CTRL2) |= |
459 | DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); |
460 | vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; |
461 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= |
462 | ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | |
463 | TRANS_DDI_PORT_MASK); |
464 | vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= |
465 | (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | |
466 | (PORT_D << TRANS_DDI_PORT_SHIFT) | |
467 | TRANS_DDI_FUNC_ENABLE); |
468 | if (IS_BROADWELL(dev_priv)) { |
469 | vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &= |
470 | ~PORT_CLK_SEL_MASK; |
471 | vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= |
472 | PORT_CLK_SEL_LCPLL_810; |
473 | } |
474 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; |
475 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; |
476 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; |
477 | } |
478 | |
479 | if ((IS_SKYLAKE(dev_priv) || |
480 | IS_KABYLAKE(dev_priv) || |
481 | IS_COFFEELAKE(dev_priv) || |
482 | IS_COMETLAKE(dev_priv)) && |
483 | intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { |
484 | vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; |
485 | } |
486 | |
487 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { |
488 | if (IS_BROADWELL(dev_priv)) |
489 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
490 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); |
491 | else |
492 | vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; |
493 | |
494 | vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; |
495 | } |
496 | |
497 | /* Clear host CRT status, so guest couldn't detect this host CRT. */ |
498 | if (IS_BROADWELL(dev_priv)) |
499 | vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK; |
500 | |
501 | /* Disable Primary/Sprite/Cursor plane */ |
502 | for_each_pipe(dev_priv, pipe) { |
503 | vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; |
504 | vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; |
505 | vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; |
506 | vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; |
507 | } |
508 | |
509 | vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; |
510 | } |
511 | |
512 | static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) |
513 | { |
514 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); |
515 | |
516 | kfree(objp: port->edid); |
517 | port->edid = NULL; |
518 | |
519 | kfree(objp: port->dpcd); |
520 | port->dpcd = NULL; |
521 | } |
522 | |
523 | static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data) |
524 | { |
525 | struct intel_vgpu_vblank_timer *vblank_timer; |
526 | struct intel_vgpu *vgpu; |
527 | |
528 | vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer); |
529 | vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer); |
530 | |
531 | /* Set vblank emulation request per-vGPU bit */ |
532 | intel_gvt_request_service(gvt: vgpu->gvt, |
533 | service: INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id); |
534 | hrtimer_add_expires_ns(timer: &vblank_timer->timer, ns: vblank_timer->period); |
535 | return HRTIMER_RESTART; |
536 | } |
537 | |
538 | static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, |
539 | int type, unsigned int resolution) |
540 | { |
541 | struct drm_i915_private *i915 = vgpu->gvt->gt->i915; |
542 | struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); |
543 | struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; |
544 | |
545 | if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM)) |
546 | return -EINVAL; |
547 | |
548 | port->edid = kzalloc(size: sizeof(*(port->edid)), GFP_KERNEL); |
549 | if (!port->edid) |
550 | return -ENOMEM; |
551 | |
552 | port->dpcd = kzalloc(size: sizeof(*(port->dpcd)), GFP_KERNEL); |
553 | if (!port->dpcd) { |
554 | kfree(objp: port->edid); |
555 | return -ENOMEM; |
556 | } |
557 | |
558 | memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution], |
559 | EDID_SIZE); |
560 | port->edid->data_valid = true; |
561 | |
562 | memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); |
563 | port->dpcd->data_valid = true; |
564 | port->dpcd->data[DPCD_SINK_COUNT] = 0x1; |
565 | port->type = type; |
566 | port->id = resolution; |
567 | port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC; |
568 | vgpu->display.port_num = port_num; |
569 | |
570 | /* Init hrtimer based on default refresh rate */ |
571 | hrtimer_init(timer: &vblank_timer->timer, CLOCK_MONOTONIC, mode: HRTIMER_MODE_ABS); |
572 | vblank_timer->timer.function = vblank_timer_fn; |
573 | vblank_timer->vrefresh_k = port->vrefresh_k; |
574 | vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); |
575 | |
576 | emulate_monitor_status_change(vgpu); |
577 | |
578 | return 0; |
579 | } |
580 | |
581 | /** |
582 | * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer |
583 | * @vgpu: vGPU operated |
584 | * @turnon: Turn ON/OFF vblank_timer |
585 | * |
586 | * This function is used to turn on/off or update the per-vGPU vblank_timer |
587 | * when TRANSCONF is enabled or disabled. vblank_timer period is also updated |
588 | * if guest changed the refresh rate. |
589 | * |
590 | */ |
591 | void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon) |
592 | { |
593 | struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer; |
594 | struct intel_vgpu_port *port = |
595 | intel_vgpu_port(vgpu, vgpu->display.port_num); |
596 | |
597 | if (turnon) { |
598 | /* |
599 | * Skip the re-enable if already active and vrefresh unchanged. |
600 | * Otherwise, stop timer if already active and restart with new |
601 | * period. |
602 | */ |
603 | if (vblank_timer->vrefresh_k != port->vrefresh_k || |
604 | !hrtimer_active(timer: &vblank_timer->timer)) { |
605 | /* Stop timer before start with new period if active */ |
606 | if (hrtimer_active(timer: &vblank_timer->timer)) |
607 | hrtimer_cancel(timer: &vblank_timer->timer); |
608 | |
609 | /* Make sure new refresh rate updated to timer period */ |
610 | vblank_timer->vrefresh_k = port->vrefresh_k; |
611 | vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); |
612 | hrtimer_start(timer: &vblank_timer->timer, |
613 | ktime_add_ns(ktime_get(), vblank_timer->period), |
614 | mode: HRTIMER_MODE_ABS); |
615 | } |
616 | } else { |
617 | /* Caller request to stop vblank */ |
618 | hrtimer_cancel(timer: &vblank_timer->timer); |
619 | } |
620 | } |
621 | |
622 | static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) |
623 | { |
624 | struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
625 | struct intel_vgpu_irq *irq = &vgpu->irq; |
626 | int vblank_event[] = { |
627 | [PIPE_A] = PIPE_A_VBLANK, |
628 | [PIPE_B] = PIPE_B_VBLANK, |
629 | [PIPE_C] = PIPE_C_VBLANK, |
630 | }; |
631 | int event; |
632 | |
633 | if (pipe < PIPE_A || pipe > PIPE_C) |
634 | return; |
635 | |
636 | for_each_set_bit(event, irq->flip_done_event[pipe], |
637 | INTEL_GVT_EVENT_MAX) { |
638 | clear_bit(nr: event, addr: irq->flip_done_event[pipe]); |
639 | if (!pipe_is_enabled(vgpu, pipe)) |
640 | continue; |
641 | |
642 | intel_vgpu_trigger_virtual_event(vgpu, event); |
643 | } |
644 | |
645 | if (pipe_is_enabled(vgpu, pipe)) { |
646 | vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; |
647 | intel_vgpu_trigger_virtual_event(vgpu, event: vblank_event[pipe]); |
648 | } |
649 | } |
650 | |
651 | void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu) |
652 | { |
653 | int pipe; |
654 | |
655 | mutex_lock(&vgpu->vgpu_lock); |
656 | for_each_pipe(vgpu->gvt->gt->i915, pipe) |
657 | emulate_vblank_on_pipe(vgpu, pipe); |
658 | mutex_unlock(lock: &vgpu->vgpu_lock); |
659 | } |
660 | |
661 | /** |
662 | * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU |
663 | * @vgpu: a vGPU |
664 | * @connected: link state |
665 | * |
666 | * This function is used to trigger hotplug interrupt for vGPU |
667 | * |
668 | */ |
669 | void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) |
670 | { |
671 | struct drm_i915_private *i915 = vgpu->gvt->gt->i915; |
672 | |
673 | /* TODO: add more platforms support */ |
674 | if (IS_SKYLAKE(i915) || |
675 | IS_KABYLAKE(i915) || |
676 | IS_COFFEELAKE(i915) || |
677 | IS_COMETLAKE(i915)) { |
678 | if (connected) { |
679 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= |
680 | SFUSE_STRAP_DDID_DETECTED; |
681 | vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; |
682 | } else { |
683 | vgpu_vreg_t(vgpu, SFUSE_STRAP) &= |
684 | ~SFUSE_STRAP_DDID_DETECTED; |
685 | vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT; |
686 | } |
687 | vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT; |
688 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
689 | PORTD_HOTPLUG_STATUS_MASK; |
690 | intel_vgpu_trigger_virtual_event(vgpu, event: DP_D_HOTPLUG); |
691 | } else if (IS_BROXTON(i915)) { |
692 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { |
693 | if (connected) { |
694 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
695 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); |
696 | } else { |
697 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= |
698 | ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); |
699 | } |
700 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= |
701 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_A); |
702 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= |
703 | ~PORTA_HOTPLUG_STATUS_MASK; |
704 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
705 | PORTA_HOTPLUG_LONG_DETECT; |
706 | intel_vgpu_trigger_virtual_event(vgpu, event: DP_A_HOTPLUG); |
707 | } |
708 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { |
709 | if (connected) { |
710 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
711 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); |
712 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= |
713 | SFUSE_STRAP_DDIB_DETECTED; |
714 | } else { |
715 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= |
716 | ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); |
717 | vgpu_vreg_t(vgpu, SFUSE_STRAP) &= |
718 | ~SFUSE_STRAP_DDIB_DETECTED; |
719 | } |
720 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= |
721 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_B); |
722 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= |
723 | ~PORTB_HOTPLUG_STATUS_MASK; |
724 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
725 | PORTB_HOTPLUG_LONG_DETECT; |
726 | intel_vgpu_trigger_virtual_event(vgpu, event: DP_B_HOTPLUG); |
727 | } |
728 | if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { |
729 | if (connected) { |
730 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= |
731 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); |
732 | vgpu_vreg_t(vgpu, SFUSE_STRAP) |= |
733 | SFUSE_STRAP_DDIC_DETECTED; |
734 | } else { |
735 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= |
736 | ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); |
737 | vgpu_vreg_t(vgpu, SFUSE_STRAP) &= |
738 | ~SFUSE_STRAP_DDIC_DETECTED; |
739 | } |
740 | vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |= |
741 | GEN8_DE_PORT_HOTPLUG(HPD_PORT_C); |
742 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= |
743 | ~PORTC_HOTPLUG_STATUS_MASK; |
744 | vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= |
745 | PORTC_HOTPLUG_LONG_DETECT; |
746 | intel_vgpu_trigger_virtual_event(vgpu, event: DP_C_HOTPLUG); |
747 | } |
748 | } |
749 | } |
750 | |
751 | /** |
752 | * intel_vgpu_clean_display - clean vGPU virtual display emulation |
753 | * @vgpu: a vGPU |
754 | * |
755 | * This function is used to clean vGPU virtual display emulation stuffs |
756 | * |
757 | */ |
758 | void intel_vgpu_clean_display(struct intel_vgpu *vgpu) |
759 | { |
760 | struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
761 | |
762 | if (IS_SKYLAKE(dev_priv) || |
763 | IS_KABYLAKE(dev_priv) || |
764 | IS_COFFEELAKE(dev_priv) || |
765 | IS_COMETLAKE(dev_priv)) |
766 | clean_virtual_dp_monitor(vgpu, port_num: PORT_D); |
767 | else |
768 | clean_virtual_dp_monitor(vgpu, port_num: PORT_B); |
769 | |
770 | vgpu_update_vblank_emulation(vgpu, turnon: false); |
771 | } |
772 | |
773 | /** |
774 | * intel_vgpu_init_display- initialize vGPU virtual display emulation |
775 | * @vgpu: a vGPU |
776 | * @resolution: resolution index for intel_vgpu_edid |
777 | * |
778 | * This function is used to initialize vGPU virtual display emulation stuffs |
779 | * |
780 | * Returns: |
781 | * Zero on success, negative error code if failed. |
782 | * |
783 | */ |
784 | int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) |
785 | { |
786 | struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; |
787 | |
788 | intel_vgpu_init_i2c_edid(vgpu); |
789 | |
790 | if (IS_SKYLAKE(dev_priv) || |
791 | IS_KABYLAKE(dev_priv) || |
792 | IS_COFFEELAKE(dev_priv) || |
793 | IS_COMETLAKE(dev_priv)) |
794 | return setup_virtual_dp_monitor(vgpu, port_num: PORT_D, type: GVT_DP_D, |
795 | resolution); |
796 | else |
797 | return setup_virtual_dp_monitor(vgpu, port_num: PORT_B, type: GVT_DP_B, |
798 | resolution); |
799 | } |
800 | |
801 | /** |
802 | * intel_vgpu_reset_display- reset vGPU virtual display emulation |
803 | * @vgpu: a vGPU |
804 | * |
805 | * This function is used to reset vGPU virtual display emulation stuffs |
806 | * |
807 | */ |
808 | void intel_vgpu_reset_display(struct intel_vgpu *vgpu) |
809 | { |
810 | emulate_monitor_status_change(vgpu); |
811 | } |
812 | |