1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/io.h>
9#include <linux/interrupt.h>
10#include <linux/module.h>
11#include <linux/mod_devicetable.h>
12#include <linux/platform_device.h>
13
14#include "mtk_cec.h"
15#include "mtk_drm_drv.h"
16
17#define TR_CONFIG 0x00
18#define CLEAR_CEC_IRQ BIT(15)
19
20#define CEC_CKGEN 0x04
21#define CEC_32K_PDN BIT(19)
22#define PDN BIT(16)
23
24#define RX_EVENT 0x54
25#define HDMI_PORD BIT(25)
26#define HDMI_HTPLG BIT(24)
27#define HDMI_PORD_INT_EN BIT(9)
28#define HDMI_HTPLG_INT_EN BIT(8)
29
30#define RX_GEN_WD 0x58
31#define HDMI_PORD_INT_32K_STATUS BIT(26)
32#define RX_RISC_INT_32K_STATUS BIT(25)
33#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
34#define HDMI_PORD_INT_32K_CLR BIT(18)
35#define RX_INT_32K_CLR BIT(17)
36#define HDMI_HTPLG_INT_32K_CLR BIT(16)
37#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
38#define RX_RISC_INT_32K_STA_MASK BIT(9)
39#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
40#define HDMI_PORD_INT_32K_EN BIT(2)
41#define RX_INT_32K_EN BIT(1)
42#define HDMI_HTPLG_INT_32K_EN BIT(0)
43
44#define NORMAL_INT_CTRL 0x5C
45#define HDMI_HTPLG_INT_STA BIT(0)
46#define HDMI_PORD_INT_STA BIT(1)
47#define HDMI_HTPLG_INT_CLR BIT(16)
48#define HDMI_PORD_INT_CLR BIT(17)
49#define HDMI_FULL_INT_CLR BIT(20)
50
51struct mtk_cec {
52 void __iomem *regs;
53 struct clk *clk;
54 int irq;
55 bool hpd;
56 void (*hpd_event)(bool hpd, struct device *dev);
57 struct device *hdmi_dev;
58 spinlock_t lock;
59};
60
61static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
62 unsigned int bits)
63{
64 void __iomem *reg = cec->regs + offset;
65 u32 tmp;
66
67 tmp = readl(addr: reg);
68 tmp &= ~bits;
69 writel(val: tmp, addr: reg);
70}
71
72static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
73 unsigned int bits)
74{
75 void __iomem *reg = cec->regs + offset;
76 u32 tmp;
77
78 tmp = readl(addr: reg);
79 tmp |= bits;
80 writel(val: tmp, addr: reg);
81}
82
83static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
84 unsigned int val, unsigned int mask)
85{
86 u32 tmp = readl(addr: cec->regs + offset) & ~mask;
87
88 tmp |= val & mask;
89 writel(val: tmp, addr: cec->regs + offset);
90}
91
92void mtk_cec_set_hpd_event(struct device *dev,
93 void (*hpd_event)(bool hpd, struct device *dev),
94 struct device *hdmi_dev)
95{
96 struct mtk_cec *cec = dev_get_drvdata(dev);
97 unsigned long flags;
98
99 spin_lock_irqsave(&cec->lock, flags);
100 cec->hdmi_dev = hdmi_dev;
101 cec->hpd_event = hpd_event;
102 spin_unlock_irqrestore(lock: &cec->lock, flags);
103}
104EXPORT_SYMBOL_NS_GPL(mtk_cec_set_hpd_event, "DRM_MTK_HDMI_V1");
105
106bool mtk_cec_hpd_high(struct device *dev)
107{
108 struct mtk_cec *cec = dev_get_drvdata(dev);
109 unsigned int status;
110
111 status = readl(addr: cec->regs + RX_EVENT);
112
113 return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
114}
115EXPORT_SYMBOL_NS_GPL(mtk_cec_hpd_high, "DRM_MTK_HDMI_V1");
116
117static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
118{
119 mtk_cec_mask(cec, CEC_CKGEN, val: 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
120 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
121 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
122 mtk_cec_mask(cec, RX_GEN_WD, val: 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
123 HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
124 RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
125}
126
127static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
128{
129 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
130}
131
132static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
133{
134 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
135}
136
137static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
138{
139 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
140 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
141 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
142 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
143 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
144 usleep_range(min: 5, max: 10);
145 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
146 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
147 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
148 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
149 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
150}
151
152static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
153{
154 void (*hpd_event)(bool hpd, struct device *dev);
155 struct device *hdmi_dev;
156 unsigned long flags;
157
158 spin_lock_irqsave(&cec->lock, flags);
159 hpd_event = cec->hpd_event;
160 hdmi_dev = cec->hdmi_dev;
161 spin_unlock_irqrestore(lock: &cec->lock, flags);
162
163 if (hpd_event)
164 hpd_event(hpd, hdmi_dev);
165}
166
167static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
168{
169 struct device *dev = arg;
170 struct mtk_cec *cec = dev_get_drvdata(dev);
171 bool hpd;
172
173 mtk_cec_clear_htplg_irq(cec);
174 hpd = mtk_cec_hpd_high(dev);
175
176 if (cec->hpd != hpd) {
177 dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
178 cec->hpd, hpd);
179 cec->hpd = hpd;
180 mtk_cec_hpd_event(cec, hpd);
181 }
182 return IRQ_HANDLED;
183}
184
185static int mtk_cec_probe(struct platform_device *pdev)
186{
187 struct device *dev = &pdev->dev;
188 struct mtk_cec *cec;
189 int ret;
190
191 cec = devm_kzalloc(dev, size: sizeof(*cec), GFP_KERNEL);
192 if (!cec)
193 return -ENOMEM;
194
195 platform_set_drvdata(pdev, data: cec);
196 spin_lock_init(&cec->lock);
197
198 cec->regs = devm_platform_ioremap_resource(pdev, index: 0);
199 if (IS_ERR(ptr: cec->regs))
200 return dev_err_probe(dev, err: PTR_ERR(ptr: cec->regs),
201 fmt: "Failed to ioremap cec\n");
202
203 cec->clk = devm_clk_get(dev, NULL);
204 if (IS_ERR(ptr: cec->clk))
205 return dev_err_probe(dev, err: PTR_ERR(ptr: cec->clk),
206 fmt: "Failed to get cec clock\n");
207
208 cec->irq = platform_get_irq(pdev, 0);
209 if (cec->irq < 0)
210 return cec->irq;
211
212 ret = devm_request_threaded_irq(dev, irq: cec->irq, NULL,
213 thread_fn: mtk_cec_htplg_isr_thread,
214 IRQF_SHARED | IRQF_TRIGGER_LOW |
215 IRQF_ONESHOT, devname: "hdmi hpd", dev_id: dev);
216 if (ret)
217 return dev_err_probe(dev, err: ret, fmt: "Failed to register cec irq\n");
218
219 ret = clk_prepare_enable(clk: cec->clk);
220 if (ret)
221 return dev_err_probe(dev, err: ret, fmt: "Failed to enable cec clock\n");
222
223 mtk_cec_htplg_irq_init(cec);
224 mtk_cec_htplg_irq_enable(cec);
225
226 return 0;
227}
228
229static void mtk_cec_remove(struct platform_device *pdev)
230{
231 struct mtk_cec *cec = platform_get_drvdata(pdev);
232
233 mtk_cec_htplg_irq_disable(cec);
234 clk_disable_unprepare(clk: cec->clk);
235}
236
237static const struct of_device_id mtk_cec_of_ids[] = {
238 { .compatible = "mediatek,mt8173-cec", },
239 {}
240};
241MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
242
243struct platform_driver mtk_cec_driver = {
244 .probe = mtk_cec_probe,
245 .remove = mtk_cec_remove,
246 .driver = {
247 .name = "mediatek-cec",
248 .of_match_table = mtk_cec_of_ids,
249 },
250};
251module_platform_driver(mtk_cec_driver);
252
253MODULE_DESCRIPTION("MediaTek HDMI CEC Driver");
254MODULE_LICENSE("GPL");
255

source code of linux/drivers/gpu/drm/mediatek/mtk_cec.c