1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2014 MediaTek Inc. |
4 | * Author: Jie Qiu <jie.qiu@mediatek.com> |
5 | */ |
6 | #include <linux/clk.h> |
7 | #include <linux/delay.h> |
8 | #include <linux/io.h> |
9 | #include <linux/interrupt.h> |
10 | #include <linux/module.h> |
11 | #include <linux/mod_devicetable.h> |
12 | #include <linux/platform_device.h> |
13 | |
14 | #include "mtk_cec.h" |
15 | #include "mtk_hdmi.h" |
16 | #include "mtk_drm_drv.h" |
17 | |
18 | #define TR_CONFIG 0x00 |
19 | #define CLEAR_CEC_IRQ BIT(15) |
20 | |
21 | #define CEC_CKGEN 0x04 |
22 | #define CEC_32K_PDN BIT(19) |
23 | #define PDN BIT(16) |
24 | |
25 | #define RX_EVENT 0x54 |
26 | #define HDMI_PORD BIT(25) |
27 | #define HDMI_HTPLG BIT(24) |
28 | #define HDMI_PORD_INT_EN BIT(9) |
29 | #define HDMI_HTPLG_INT_EN BIT(8) |
30 | |
31 | #define RX_GEN_WD 0x58 |
32 | #define HDMI_PORD_INT_32K_STATUS BIT(26) |
33 | #define RX_RISC_INT_32K_STATUS BIT(25) |
34 | #define HDMI_HTPLG_INT_32K_STATUS BIT(24) |
35 | #define HDMI_PORD_INT_32K_CLR BIT(18) |
36 | #define RX_INT_32K_CLR BIT(17) |
37 | #define HDMI_HTPLG_INT_32K_CLR BIT(16) |
38 | #define HDMI_PORD_INT_32K_STA_MASK BIT(10) |
39 | #define RX_RISC_INT_32K_STA_MASK BIT(9) |
40 | #define HDMI_HTPLG_INT_32K_STA_MASK BIT(8) |
41 | #define HDMI_PORD_INT_32K_EN BIT(2) |
42 | #define RX_INT_32K_EN BIT(1) |
43 | #define HDMI_HTPLG_INT_32K_EN BIT(0) |
44 | |
45 | #define NORMAL_INT_CTRL 0x5C |
46 | #define HDMI_HTPLG_INT_STA BIT(0) |
47 | #define HDMI_PORD_INT_STA BIT(1) |
48 | #define HDMI_HTPLG_INT_CLR BIT(16) |
49 | #define HDMI_PORD_INT_CLR BIT(17) |
50 | #define HDMI_FULL_INT_CLR BIT(20) |
51 | |
52 | struct mtk_cec { |
53 | void __iomem *regs; |
54 | struct clk *clk; |
55 | int irq; |
56 | bool hpd; |
57 | void (*hpd_event)(bool hpd, struct device *dev); |
58 | struct device *hdmi_dev; |
59 | spinlock_t lock; |
60 | }; |
61 | |
62 | static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset, |
63 | unsigned int bits) |
64 | { |
65 | void __iomem *reg = cec->regs + offset; |
66 | u32 tmp; |
67 | |
68 | tmp = readl(addr: reg); |
69 | tmp &= ~bits; |
70 | writel(val: tmp, addr: reg); |
71 | } |
72 | |
73 | static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset, |
74 | unsigned int bits) |
75 | { |
76 | void __iomem *reg = cec->regs + offset; |
77 | u32 tmp; |
78 | |
79 | tmp = readl(addr: reg); |
80 | tmp |= bits; |
81 | writel(val: tmp, addr: reg); |
82 | } |
83 | |
84 | static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset, |
85 | unsigned int val, unsigned int mask) |
86 | { |
87 | u32 tmp = readl(addr: cec->regs + offset) & ~mask; |
88 | |
89 | tmp |= val & mask; |
90 | writel(val: tmp, addr: cec->regs + offset); |
91 | } |
92 | |
93 | void mtk_cec_set_hpd_event(struct device *dev, |
94 | void (*hpd_event)(bool hpd, struct device *dev), |
95 | struct device *hdmi_dev) |
96 | { |
97 | struct mtk_cec *cec = dev_get_drvdata(dev); |
98 | unsigned long flags; |
99 | |
100 | spin_lock_irqsave(&cec->lock, flags); |
101 | cec->hdmi_dev = hdmi_dev; |
102 | cec->hpd_event = hpd_event; |
103 | spin_unlock_irqrestore(lock: &cec->lock, flags); |
104 | } |
105 | |
106 | bool mtk_cec_hpd_high(struct device *dev) |
107 | { |
108 | struct mtk_cec *cec = dev_get_drvdata(dev); |
109 | unsigned int status; |
110 | |
111 | status = readl(addr: cec->regs + RX_EVENT); |
112 | |
113 | return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG); |
114 | } |
115 | |
116 | static void mtk_cec_htplg_irq_init(struct mtk_cec *cec) |
117 | { |
118 | mtk_cec_mask(cec, CEC_CKGEN, val: 0 | CEC_32K_PDN, PDN | CEC_32K_PDN); |
119 | mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR | |
120 | RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR); |
121 | mtk_cec_mask(cec, RX_GEN_WD, val: 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR | |
122 | HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN | |
123 | RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN); |
124 | } |
125 | |
126 | static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec) |
127 | { |
128 | mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN); |
129 | } |
130 | |
131 | static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec) |
132 | { |
133 | mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN); |
134 | } |
135 | |
136 | static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec) |
137 | { |
138 | mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ); |
139 | mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR | |
140 | HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR); |
141 | mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR | |
142 | RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR); |
143 | usleep_range(min: 5, max: 10); |
144 | mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR | |
145 | HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR); |
146 | mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ); |
147 | mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR | |
148 | RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR); |
149 | } |
150 | |
151 | static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd) |
152 | { |
153 | void (*hpd_event)(bool hpd, struct device *dev); |
154 | struct device *hdmi_dev; |
155 | unsigned long flags; |
156 | |
157 | spin_lock_irqsave(&cec->lock, flags); |
158 | hpd_event = cec->hpd_event; |
159 | hdmi_dev = cec->hdmi_dev; |
160 | spin_unlock_irqrestore(lock: &cec->lock, flags); |
161 | |
162 | if (hpd_event) |
163 | hpd_event(hpd, hdmi_dev); |
164 | } |
165 | |
166 | static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg) |
167 | { |
168 | struct device *dev = arg; |
169 | struct mtk_cec *cec = dev_get_drvdata(dev); |
170 | bool hpd; |
171 | |
172 | mtk_cec_clear_htplg_irq(cec); |
173 | hpd = mtk_cec_hpd_high(dev); |
174 | |
175 | if (cec->hpd != hpd) { |
176 | dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n" , |
177 | cec->hpd, hpd); |
178 | cec->hpd = hpd; |
179 | mtk_cec_hpd_event(cec, hpd); |
180 | } |
181 | return IRQ_HANDLED; |
182 | } |
183 | |
184 | static int mtk_cec_probe(struct platform_device *pdev) |
185 | { |
186 | struct device *dev = &pdev->dev; |
187 | struct mtk_cec *cec; |
188 | int ret; |
189 | |
190 | cec = devm_kzalloc(dev, size: sizeof(*cec), GFP_KERNEL); |
191 | if (!cec) |
192 | return -ENOMEM; |
193 | |
194 | platform_set_drvdata(pdev, data: cec); |
195 | spin_lock_init(&cec->lock); |
196 | |
197 | cec->regs = devm_platform_ioremap_resource(pdev, index: 0); |
198 | if (IS_ERR(ptr: cec->regs)) { |
199 | ret = PTR_ERR(ptr: cec->regs); |
200 | dev_err(dev, "Failed to ioremap cec: %d\n" , ret); |
201 | return ret; |
202 | } |
203 | |
204 | cec->clk = devm_clk_get(dev, NULL); |
205 | if (IS_ERR(ptr: cec->clk)) { |
206 | ret = PTR_ERR(ptr: cec->clk); |
207 | dev_err(dev, "Failed to get cec clock: %d\n" , ret); |
208 | return ret; |
209 | } |
210 | |
211 | cec->irq = platform_get_irq(pdev, 0); |
212 | if (cec->irq < 0) |
213 | return cec->irq; |
214 | |
215 | ret = devm_request_threaded_irq(dev, irq: cec->irq, NULL, |
216 | thread_fn: mtk_cec_htplg_isr_thread, |
217 | IRQF_SHARED | IRQF_TRIGGER_LOW | |
218 | IRQF_ONESHOT, devname: "hdmi hpd" , dev_id: dev); |
219 | if (ret) { |
220 | dev_err(dev, "Failed to register cec irq: %d\n" , ret); |
221 | return ret; |
222 | } |
223 | |
224 | ret = clk_prepare_enable(clk: cec->clk); |
225 | if (ret) { |
226 | dev_err(dev, "Failed to enable cec clock: %d\n" , ret); |
227 | return ret; |
228 | } |
229 | |
230 | mtk_cec_htplg_irq_init(cec); |
231 | mtk_cec_htplg_irq_enable(cec); |
232 | |
233 | return 0; |
234 | } |
235 | |
236 | static void mtk_cec_remove(struct platform_device *pdev) |
237 | { |
238 | struct mtk_cec *cec = platform_get_drvdata(pdev); |
239 | |
240 | mtk_cec_htplg_irq_disable(cec); |
241 | clk_disable_unprepare(clk: cec->clk); |
242 | } |
243 | |
244 | static const struct of_device_id mtk_cec_of_ids[] = { |
245 | { .compatible = "mediatek,mt8173-cec" , }, |
246 | {} |
247 | }; |
248 | MODULE_DEVICE_TABLE(of, mtk_cec_of_ids); |
249 | |
250 | struct platform_driver mtk_cec_driver = { |
251 | .probe = mtk_cec_probe, |
252 | .remove_new = mtk_cec_remove, |
253 | .driver = { |
254 | .name = "mediatek-cec" , |
255 | .of_match_table = mtk_cec_of_ids, |
256 | }, |
257 | }; |
258 | |