1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright © 2018 Broadcom |
4 | * |
5 | * Authors: |
6 | * Eric Anholt <eric@anholt.net> |
7 | * Boris Brezillon <boris.brezillon@bootlin.com> |
8 | */ |
9 | |
10 | #include <linux/clk.h> |
11 | #include <linux/component.h> |
12 | #include <linux/mod_devicetable.h> |
13 | #include <linux/platform_device.h> |
14 | #include <linux/pm_runtime.h> |
15 | |
16 | #include <drm/drm_atomic.h> |
17 | #include <drm/drm_atomic_helper.h> |
18 | #include <drm/drm_drv.h> |
19 | #include <drm/drm_edid.h> |
20 | #include <drm/drm_fb_dma_helper.h> |
21 | #include <drm/drm_fourcc.h> |
22 | #include <drm/drm_framebuffer.h> |
23 | #include <drm/drm_panel.h> |
24 | #include <drm/drm_probe_helper.h> |
25 | #include <drm/drm_vblank.h> |
26 | #include <drm/drm_writeback.h> |
27 | |
28 | #include "vc4_drv.h" |
29 | #include "vc4_regs.h" |
30 | |
31 | /* Base address of the output. Raster formats must be 4-byte aligned, |
32 | * T and LT must be 16-byte aligned or maybe utile-aligned (docs are |
33 | * inconsistent, but probably utile). |
34 | */ |
35 | #define TXP_DST_PTR 0x00 |
36 | |
37 | /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's |
38 | * the width in tiles. |
39 | */ |
40 | #define TXP_DST_PITCH 0x04 |
41 | /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide, |
42 | * shifted up. |
43 | */ |
44 | # define TXP_T_TILE_WIDTH_SHIFT 7 |
45 | /* For LT-tiled images, DST_PITCH should be the number of utiles wide, |
46 | * shifted up. |
47 | */ |
48 | # define TXP_LT_TILE_WIDTH_SHIFT 4 |
49 | |
50 | /* Pre-rotation width/height of the image. Must match HVS config. |
51 | * |
52 | * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit |
53 | * and width/height must be tile or utile-aligned as appropriate. If |
54 | * transposing (rotating), width is limited to 1920. |
55 | * |
56 | * Height is limited to various numbers between 4088 and 4095. I'd |
57 | * just use 4088 to be safe. |
58 | */ |
59 | #define TXP_DIM 0x08 |
60 | # define TXP_HEIGHT_SHIFT 16 |
61 | # define TXP_HEIGHT_MASK GENMASK(31, 16) |
62 | # define TXP_WIDTH_SHIFT 0 |
63 | # define TXP_WIDTH_MASK GENMASK(15, 0) |
64 | |
65 | #define TXP_DST_CTRL 0x0c |
66 | /* These bits are set to 0x54 */ |
67 | #define TXP_PILOT_SHIFT 24 |
68 | #define TXP_PILOT_MASK GENMASK(31, 24) |
69 | /* Bits 22-23 are set to 0x01 */ |
70 | #define TXP_VERSION_SHIFT 22 |
71 | #define TXP_VERSION_MASK GENMASK(23, 22) |
72 | |
73 | /* Powers down the internal memory. */ |
74 | # define TXP_POWERDOWN BIT(21) |
75 | |
76 | /* Enables storing the alpha component in 8888/4444, instead of |
77 | * filling with ~ALPHA_INVERT. |
78 | */ |
79 | # define TXP_ALPHA_ENABLE BIT(20) |
80 | |
81 | /* 4 bits, each enables stores for a channel in each set of 4 bytes. |
82 | * Set to 0xf for normal operation. |
83 | */ |
84 | # define TXP_BYTE_ENABLE_SHIFT 16 |
85 | # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16) |
86 | |
87 | /* Debug: Generate VSTART again at EOF. */ |
88 | # define TXP_VSTART_AT_EOF BIT(15) |
89 | |
90 | /* Debug: Terminate the current frame immediately. Stops AXI |
91 | * writes. |
92 | */ |
93 | # define TXP_ABORT BIT(14) |
94 | |
95 | # define TXP_DITHER BIT(13) |
96 | |
97 | /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for |
98 | * !TXP_ALPHA_ENABLE. |
99 | */ |
100 | # define TXP_ALPHA_INVERT BIT(12) |
101 | |
102 | /* Note: I've listed the channels here in high bit (in byte 3/2/1) to |
103 | * low bit (in byte 0) order. |
104 | */ |
105 | # define TXP_FORMAT_SHIFT 8 |
106 | # define TXP_FORMAT_MASK GENMASK(11, 8) |
107 | # define TXP_FORMAT_ABGR4444 0 |
108 | # define TXP_FORMAT_ARGB4444 1 |
109 | # define TXP_FORMAT_BGRA4444 2 |
110 | # define TXP_FORMAT_RGBA4444 3 |
111 | # define TXP_FORMAT_BGR565 6 |
112 | # define TXP_FORMAT_RGB565 7 |
113 | /* 888s are non-rotated, raster-only */ |
114 | # define TXP_FORMAT_BGR888 8 |
115 | # define TXP_FORMAT_RGB888 9 |
116 | # define TXP_FORMAT_ABGR8888 12 |
117 | # define TXP_FORMAT_ARGB8888 13 |
118 | # define TXP_FORMAT_BGRA8888 14 |
119 | # define TXP_FORMAT_RGBA8888 15 |
120 | |
121 | /* If TFORMAT is set, generates LT instead of T format. */ |
122 | # define TXP_LINEAR_UTILE BIT(7) |
123 | |
124 | /* Rotate output by 90 degrees. */ |
125 | # define TXP_TRANSPOSE BIT(6) |
126 | |
127 | /* Generate a tiled format for V3D. */ |
128 | # define TXP_TFORMAT BIT(5) |
129 | |
130 | /* Generates some undefined test mode output. */ |
131 | # define TXP_TEST_MODE BIT(4) |
132 | |
133 | /* Request odd field from HVS. */ |
134 | # define TXP_FIELD BIT(3) |
135 | |
136 | /* Raise interrupt when idle. */ |
137 | # define TXP_EI BIT(2) |
138 | |
139 | /* Set when generating a frame, clears when idle. */ |
140 | # define TXP_BUSY BIT(1) |
141 | |
142 | /* Starts a frame. Self-clearing. */ |
143 | # define TXP_GO BIT(0) |
144 | |
145 | /* Number of lines received and committed to memory. */ |
146 | #define TXP_PROGRESS 0x10 |
147 | |
148 | #define TXP_READ(offset) \ |
149 | ({ \ |
150 | kunit_fail_current_test("Accessing a register in a unit test!\n"); \ |
151 | readl(txp->regs + (offset)); \ |
152 | }) |
153 | |
154 | #define TXP_WRITE(offset, val) \ |
155 | do { \ |
156 | kunit_fail_current_test("Accessing a register in a unit test!\n"); \ |
157 | writel(val, txp->regs + (offset)); \ |
158 | } while (0) |
159 | |
160 | struct vc4_txp { |
161 | struct vc4_crtc base; |
162 | |
163 | struct platform_device *pdev; |
164 | |
165 | struct vc4_encoder encoder; |
166 | struct drm_writeback_connector connector; |
167 | |
168 | void __iomem *regs; |
169 | }; |
170 | |
171 | #define encoder_to_vc4_txp(_encoder) \ |
172 | container_of_const(_encoder, struct vc4_txp, encoder.base) |
173 | |
174 | #define connector_to_vc4_txp(_connector) \ |
175 | container_of_const(_connector, struct vc4_txp, connector.base) |
176 | |
177 | static const struct debugfs_reg32 txp_regs[] = { |
178 | VC4_REG32(TXP_DST_PTR), |
179 | VC4_REG32(TXP_DST_PITCH), |
180 | VC4_REG32(TXP_DIM), |
181 | VC4_REG32(TXP_DST_CTRL), |
182 | VC4_REG32(TXP_PROGRESS), |
183 | }; |
184 | |
185 | static int vc4_txp_connector_get_modes(struct drm_connector *connector) |
186 | { |
187 | struct drm_device *dev = connector->dev; |
188 | |
189 | return drm_add_modes_noedid(connector, hdisplay: dev->mode_config.max_width, |
190 | vdisplay: dev->mode_config.max_height); |
191 | } |
192 | |
193 | static enum drm_mode_status |
194 | vc4_txp_connector_mode_valid(struct drm_connector *connector, |
195 | struct drm_display_mode *mode) |
196 | { |
197 | struct drm_device *dev = connector->dev; |
198 | struct drm_mode_config *mode_config = &dev->mode_config; |
199 | int w = mode->hdisplay, h = mode->vdisplay; |
200 | |
201 | if (w < mode_config->min_width || w > mode_config->max_width) |
202 | return MODE_BAD_HVALUE; |
203 | |
204 | if (h < mode_config->min_height || h > mode_config->max_height) |
205 | return MODE_BAD_VVALUE; |
206 | |
207 | return MODE_OK; |
208 | } |
209 | |
210 | static const u32 drm_fmts[] = { |
211 | DRM_FORMAT_RGB888, |
212 | DRM_FORMAT_BGR888, |
213 | DRM_FORMAT_XRGB8888, |
214 | DRM_FORMAT_XBGR8888, |
215 | DRM_FORMAT_ARGB8888, |
216 | DRM_FORMAT_ABGR8888, |
217 | DRM_FORMAT_RGBX8888, |
218 | DRM_FORMAT_BGRX8888, |
219 | DRM_FORMAT_RGBA8888, |
220 | DRM_FORMAT_BGRA8888, |
221 | }; |
222 | |
223 | static const u32 txp_fmts[] = { |
224 | TXP_FORMAT_RGB888, |
225 | TXP_FORMAT_BGR888, |
226 | TXP_FORMAT_ARGB8888, |
227 | TXP_FORMAT_ABGR8888, |
228 | TXP_FORMAT_ARGB8888, |
229 | TXP_FORMAT_ABGR8888, |
230 | TXP_FORMAT_RGBA8888, |
231 | TXP_FORMAT_BGRA8888, |
232 | TXP_FORMAT_RGBA8888, |
233 | TXP_FORMAT_BGRA8888, |
234 | }; |
235 | |
236 | static void vc4_txp_armed(struct drm_crtc_state *state) |
237 | { |
238 | struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); |
239 | |
240 | vc4_state->txp_armed = true; |
241 | } |
242 | |
243 | static int vc4_txp_connector_atomic_check(struct drm_connector *conn, |
244 | struct drm_atomic_state *state) |
245 | { |
246 | struct drm_connector_state *conn_state; |
247 | struct drm_crtc_state *crtc_state; |
248 | struct drm_framebuffer *fb; |
249 | int i; |
250 | |
251 | conn_state = drm_atomic_get_new_connector_state(state, connector: conn); |
252 | if (!conn_state->writeback_job) |
253 | return 0; |
254 | |
255 | crtc_state = drm_atomic_get_new_crtc_state(state, crtc: conn_state->crtc); |
256 | |
257 | fb = conn_state->writeback_job->fb; |
258 | if (fb->width != crtc_state->mode.hdisplay || |
259 | fb->height != crtc_state->mode.vdisplay) { |
260 | DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n" , |
261 | fb->width, fb->height); |
262 | return -EINVAL; |
263 | } |
264 | |
265 | for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { |
266 | if (fb->format->format == drm_fmts[i]) |
267 | break; |
268 | } |
269 | |
270 | if (i == ARRAY_SIZE(drm_fmts)) |
271 | return -EINVAL; |
272 | |
273 | /* Pitch must be aligned on 16 bytes. */ |
274 | if (fb->pitches[0] & GENMASK(3, 0)) |
275 | return -EINVAL; |
276 | |
277 | vc4_txp_armed(state: crtc_state); |
278 | |
279 | return 0; |
280 | } |
281 | |
282 | static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, |
283 | struct drm_atomic_state *state) |
284 | { |
285 | struct drm_device *drm = conn->dev; |
286 | struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, |
287 | connector: conn); |
288 | struct vc4_txp *txp = connector_to_vc4_txp(conn); |
289 | struct drm_gem_dma_object *gem; |
290 | struct drm_display_mode *mode; |
291 | struct drm_framebuffer *fb; |
292 | u32 ctrl; |
293 | int idx; |
294 | int i; |
295 | |
296 | if (WARN_ON(!conn_state->writeback_job)) |
297 | return; |
298 | |
299 | mode = &conn_state->crtc->state->adjusted_mode; |
300 | fb = conn_state->writeback_job->fb; |
301 | |
302 | for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { |
303 | if (fb->format->format == drm_fmts[i]) |
304 | break; |
305 | } |
306 | |
307 | if (WARN_ON(i == ARRAY_SIZE(drm_fmts))) |
308 | return; |
309 | |
310 | ctrl = TXP_GO | TXP_EI | |
311 | VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | |
312 | VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); |
313 | |
314 | if (fb->format->has_alpha) |
315 | ctrl |= TXP_ALPHA_ENABLE; |
316 | else |
317 | /* |
318 | * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the |
319 | * hardware will force the output padding to be 0xff. |
320 | */ |
321 | ctrl |= TXP_ALPHA_INVERT; |
322 | |
323 | if (!drm_dev_enter(dev: drm, idx: &idx)) |
324 | return; |
325 | |
326 | gem = drm_fb_dma_get_gem_obj(fb, plane: 0); |
327 | TXP_WRITE(TXP_DST_PTR, gem->dma_addr + fb->offsets[0]); |
328 | TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]); |
329 | TXP_WRITE(TXP_DIM, |
330 | VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | |
331 | VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); |
332 | |
333 | TXP_WRITE(TXP_DST_CTRL, ctrl); |
334 | |
335 | drm_writeback_queue_job(wb_connector: &txp->connector, conn_state); |
336 | |
337 | drm_dev_exit(idx); |
338 | } |
339 | |
340 | static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = { |
341 | .get_modes = vc4_txp_connector_get_modes, |
342 | .mode_valid = vc4_txp_connector_mode_valid, |
343 | .atomic_check = vc4_txp_connector_atomic_check, |
344 | .atomic_commit = vc4_txp_connector_atomic_commit, |
345 | }; |
346 | |
347 | static enum drm_connector_status |
348 | vc4_txp_connector_detect(struct drm_connector *connector, bool force) |
349 | { |
350 | return connector_status_connected; |
351 | } |
352 | |
353 | static const struct drm_connector_funcs vc4_txp_connector_funcs = { |
354 | .detect = vc4_txp_connector_detect, |
355 | .fill_modes = drm_helper_probe_single_connector_modes, |
356 | .destroy = drm_connector_cleanup, |
357 | .reset = drm_atomic_helper_connector_reset, |
358 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
359 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
360 | }; |
361 | |
362 | static void vc4_txp_encoder_disable(struct drm_encoder *encoder) |
363 | { |
364 | struct drm_device *drm = encoder->dev; |
365 | struct vc4_txp *txp = encoder_to_vc4_txp(encoder); |
366 | int idx; |
367 | |
368 | if (!drm_dev_enter(dev: drm, idx: &idx)) |
369 | return; |
370 | |
371 | if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) { |
372 | unsigned long timeout = jiffies + msecs_to_jiffies(m: 1000); |
373 | |
374 | TXP_WRITE(TXP_DST_CTRL, TXP_ABORT); |
375 | |
376 | while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY && |
377 | time_before(jiffies, timeout)) |
378 | ; |
379 | |
380 | WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY); |
381 | } |
382 | |
383 | TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN); |
384 | |
385 | drm_dev_exit(idx); |
386 | } |
387 | |
388 | static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = { |
389 | .disable = vc4_txp_encoder_disable, |
390 | }; |
391 | |
392 | static int vc4_txp_enable_vblank(struct drm_crtc *crtc) |
393 | { |
394 | return 0; |
395 | } |
396 | |
397 | static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {} |
398 | |
399 | static const struct drm_crtc_funcs vc4_txp_crtc_funcs = { |
400 | .set_config = drm_atomic_helper_set_config, |
401 | .page_flip = vc4_page_flip, |
402 | .reset = vc4_crtc_reset, |
403 | .atomic_duplicate_state = vc4_crtc_duplicate_state, |
404 | .atomic_destroy_state = vc4_crtc_destroy_state, |
405 | .enable_vblank = vc4_txp_enable_vblank, |
406 | .disable_vblank = vc4_txp_disable_vblank, |
407 | .late_register = vc4_crtc_late_register, |
408 | }; |
409 | |
410 | static int vc4_txp_atomic_check(struct drm_crtc *crtc, |
411 | struct drm_atomic_state *state) |
412 | { |
413 | struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, |
414 | crtc); |
415 | int ret; |
416 | |
417 | ret = vc4_hvs_atomic_check(crtc, state); |
418 | if (ret) |
419 | return ret; |
420 | |
421 | crtc_state->no_vblank = true; |
422 | |
423 | return 0; |
424 | } |
425 | |
426 | static void vc4_txp_atomic_enable(struct drm_crtc *crtc, |
427 | struct drm_atomic_state *state) |
428 | { |
429 | drm_crtc_vblank_on(crtc); |
430 | vc4_hvs_atomic_enable(crtc, state); |
431 | } |
432 | |
433 | static void vc4_txp_atomic_disable(struct drm_crtc *crtc, |
434 | struct drm_atomic_state *state) |
435 | { |
436 | struct drm_device *dev = crtc->dev; |
437 | |
438 | /* Disable vblank irq handling before crtc is disabled. */ |
439 | drm_crtc_vblank_off(crtc); |
440 | |
441 | vc4_hvs_atomic_disable(crtc, state); |
442 | |
443 | /* |
444 | * Make sure we issue a vblank event after disabling the CRTC if |
445 | * someone was waiting it. |
446 | */ |
447 | if (crtc->state->event) { |
448 | unsigned long flags; |
449 | |
450 | spin_lock_irqsave(&dev->event_lock, flags); |
451 | drm_crtc_send_vblank_event(crtc, e: crtc->state->event); |
452 | crtc->state->event = NULL; |
453 | spin_unlock_irqrestore(lock: &dev->event_lock, flags); |
454 | } |
455 | } |
456 | |
457 | static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = { |
458 | .atomic_check = vc4_txp_atomic_check, |
459 | .atomic_begin = vc4_hvs_atomic_begin, |
460 | .atomic_flush = vc4_hvs_atomic_flush, |
461 | .atomic_enable = vc4_txp_atomic_enable, |
462 | .atomic_disable = vc4_txp_atomic_disable, |
463 | }; |
464 | |
465 | static irqreturn_t vc4_txp_interrupt(int irq, void *data) |
466 | { |
467 | struct vc4_txp *txp = data; |
468 | struct vc4_crtc *vc4_crtc = &txp->base; |
469 | |
470 | /* |
471 | * We don't need to protect the register access using |
472 | * drm_dev_enter() there because the interrupt handler lifetime |
473 | * is tied to the device itself, and not to the DRM device. |
474 | * |
475 | * So when the device will be gone, one of the first thing we |
476 | * will be doing will be to unregister the interrupt handler, |
477 | * and then unregister the DRM device. drm_dev_enter() would |
478 | * thus always succeed if we are here. |
479 | */ |
480 | TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI); |
481 | vc4_crtc_handle_vblank(crtc: vc4_crtc); |
482 | drm_writeback_signal_completion(wb_connector: &txp->connector, status: 0); |
483 | |
484 | return IRQ_HANDLED; |
485 | } |
486 | |
487 | const struct vc4_crtc_data vc4_txp_crtc_data = { |
488 | .name = "txp" , |
489 | .debugfs_name = "txp_regs" , |
490 | .hvs_available_channels = BIT(2), |
491 | .hvs_output = 2, |
492 | }; |
493 | |
494 | static int vc4_txp_bind(struct device *dev, struct device *master, void *data) |
495 | { |
496 | struct platform_device *pdev = to_platform_device(dev); |
497 | struct drm_device *drm = dev_get_drvdata(dev: master); |
498 | struct vc4_encoder *vc4_encoder; |
499 | struct drm_encoder *encoder; |
500 | struct vc4_crtc *vc4_crtc; |
501 | struct vc4_txp *txp; |
502 | int ret, irq; |
503 | |
504 | irq = platform_get_irq(pdev, 0); |
505 | if (irq < 0) |
506 | return irq; |
507 | |
508 | txp = drmm_kzalloc(dev: drm, size: sizeof(*txp), GFP_KERNEL); |
509 | if (!txp) |
510 | return -ENOMEM; |
511 | |
512 | txp->pdev = pdev; |
513 | txp->regs = vc4_ioremap_regs(dev: pdev, index: 0); |
514 | if (IS_ERR(ptr: txp->regs)) |
515 | return PTR_ERR(ptr: txp->regs); |
516 | |
517 | vc4_crtc = &txp->base; |
518 | vc4_crtc->regset.base = txp->regs; |
519 | vc4_crtc->regset.regs = txp_regs; |
520 | vc4_crtc->regset.nregs = ARRAY_SIZE(txp_regs); |
521 | |
522 | ret = vc4_crtc_init(drm, pdev, vc4_crtc, data: &vc4_txp_crtc_data, |
523 | crtc_funcs: &vc4_txp_crtc_funcs, crtc_helper_funcs: &vc4_txp_crtc_helper_funcs, feeds_txp: true); |
524 | if (ret) |
525 | return ret; |
526 | |
527 | vc4_encoder = &txp->encoder; |
528 | txp->encoder.type = VC4_ENCODER_TYPE_TXP; |
529 | |
530 | encoder = &vc4_encoder->base; |
531 | encoder->possible_crtcs = drm_crtc_mask(crtc: &vc4_crtc->base); |
532 | |
533 | drm_encoder_helper_add(encoder, funcs: &vc4_txp_encoder_helper_funcs); |
534 | |
535 | ret = drmm_encoder_init(dev: drm, encoder, NULL, DRM_MODE_ENCODER_VIRTUAL, NULL); |
536 | if (ret) |
537 | return ret; |
538 | |
539 | drm_connector_helper_add(connector: &txp->connector.base, |
540 | funcs: &vc4_txp_connector_helper_funcs); |
541 | ret = drm_writeback_connector_init_with_encoder(dev: drm, wb_connector: &txp->connector, |
542 | enc: encoder, |
543 | con_funcs: &vc4_txp_connector_funcs, |
544 | formats: drm_fmts, ARRAY_SIZE(drm_fmts)); |
545 | if (ret) |
546 | return ret; |
547 | |
548 | ret = devm_request_irq(dev, irq, handler: vc4_txp_interrupt, irqflags: 0, |
549 | devname: dev_name(dev), dev_id: txp); |
550 | if (ret) |
551 | return ret; |
552 | |
553 | dev_set_drvdata(dev, data: txp); |
554 | |
555 | return 0; |
556 | } |
557 | |
558 | static void vc4_txp_unbind(struct device *dev, struct device *master, |
559 | void *data) |
560 | { |
561 | struct vc4_txp *txp = dev_get_drvdata(dev); |
562 | |
563 | drm_connector_cleanup(connector: &txp->connector.base); |
564 | } |
565 | |
566 | static const struct component_ops vc4_txp_ops = { |
567 | .bind = vc4_txp_bind, |
568 | .unbind = vc4_txp_unbind, |
569 | }; |
570 | |
571 | static int vc4_txp_probe(struct platform_device *pdev) |
572 | { |
573 | return component_add(&pdev->dev, &vc4_txp_ops); |
574 | } |
575 | |
576 | static void vc4_txp_remove(struct platform_device *pdev) |
577 | { |
578 | component_del(&pdev->dev, &vc4_txp_ops); |
579 | } |
580 | |
581 | static const struct of_device_id vc4_txp_dt_match[] = { |
582 | { .compatible = "brcm,bcm2835-txp" }, |
583 | { /* sentinel */ }, |
584 | }; |
585 | |
586 | struct platform_driver vc4_txp_driver = { |
587 | .probe = vc4_txp_probe, |
588 | .remove_new = vc4_txp_remove, |
589 | .driver = { |
590 | .name = "vc4_txp" , |
591 | .of_match_table = vc4_txp_dt_match, |
592 | }, |
593 | }; |
594 | |