1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * drivers/i2c/busses/i2c-mt7621.c |
4 | * |
5 | * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com> |
6 | * Copyright (C) 2016 Michael Lee <igvtee@gmail.com> |
7 | * Copyright (C) 2018 Jan Breuer <jan.breuer@jaybee.cz> |
8 | * |
9 | * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus. |
10 | * (C) 2014 Sittisak <sittisaks@hotmail.com> |
11 | */ |
12 | |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/i2c.h> |
16 | #include <linux/io.h> |
17 | #include <linux/iopoll.h> |
18 | #include <linux/module.h> |
19 | #include <linux/of.h> |
20 | #include <linux/platform_device.h> |
21 | #include <linux/reset.h> |
22 | |
23 | #define REG_SM0CFG2_REG 0x28 |
24 | #define REG_SM0CTL0_REG 0x40 |
25 | #define REG_SM0CTL1_REG 0x44 |
26 | #define REG_SM0D0_REG 0x50 |
27 | #define REG_SM0D1_REG 0x54 |
28 | #define REG_PINTEN_REG 0x5c |
29 | #define REG_PINTST_REG 0x60 |
30 | #define REG_PINTCL_REG 0x64 |
31 | |
32 | /* REG_SM0CFG2_REG */ |
33 | #define SM0CFG2_IS_AUTOMODE BIT(0) |
34 | |
35 | /* REG_SM0CTL0_REG */ |
36 | #define SM0CTL0_ODRAIN BIT(31) |
37 | #define SM0CTL0_CLK_DIV_MASK (0x7ff << 16) |
38 | #define SM0CTL0_CLK_DIV_MAX 0x7ff |
39 | #define SM0CTL0_CS_STATUS BIT(4) |
40 | #define SM0CTL0_SCL_STATE BIT(3) |
41 | #define SM0CTL0_SDA_STATE BIT(2) |
42 | #define SM0CTL0_EN BIT(1) |
43 | #define SM0CTL0_SCL_STRETCH BIT(0) |
44 | |
45 | /* REG_SM0CTL1_REG */ |
46 | #define SM0CTL1_ACK_MASK (0xff << 16) |
47 | #define SM0CTL1_PGLEN_MASK (0x7 << 8) |
48 | #define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK) |
49 | #define SM0CTL1_READ (5 << 4) |
50 | #define SM0CTL1_READ_LAST (4 << 4) |
51 | #define SM0CTL1_STOP (3 << 4) |
52 | #define SM0CTL1_WRITE (2 << 4) |
53 | #define SM0CTL1_START (1 << 4) |
54 | #define SM0CTL1_MODE_MASK (0x7 << 4) |
55 | #define SM0CTL1_TRI BIT(0) |
56 | |
57 | /* timeout waiting for I2C devices to respond */ |
58 | #define TIMEOUT_MS 1000 |
59 | |
60 | struct mtk_i2c { |
61 | void __iomem *base; |
62 | struct device *dev; |
63 | struct i2c_adapter adap; |
64 | u32 bus_freq; |
65 | u32 clk_div; |
66 | u32 flags; |
67 | struct clk *clk; |
68 | }; |
69 | |
70 | static int mtk_i2c_wait_idle(struct mtk_i2c *i2c) |
71 | { |
72 | int ret; |
73 | u32 val; |
74 | |
75 | ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG, |
76 | val, !(val & SM0CTL1_TRI), |
77 | 10, TIMEOUT_MS * 1000); |
78 | if (ret) |
79 | dev_dbg(i2c->dev, "idle err(%d)\n" , ret); |
80 | |
81 | return ret; |
82 | } |
83 | |
84 | static void mtk_i2c_reset(struct mtk_i2c *i2c) |
85 | { |
86 | int ret; |
87 | |
88 | ret = device_reset(dev: i2c->adap.dev.parent); |
89 | if (ret) |
90 | dev_err(i2c->dev, "I2C reset failed!\n" ); |
91 | |
92 | /* |
93 | * Don't set SM0CTL0_ODRAIN as its bit meaning is inverted. To |
94 | * configure open-drain mode, this bit needs to be cleared. |
95 | */ |
96 | iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN | |
97 | SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG); |
98 | iowrite32(0, i2c->base + REG_SM0CFG2_REG); |
99 | } |
100 | |
101 | static void mtk_i2c_dump_reg(struct mtk_i2c *i2c) |
102 | { |
103 | dev_dbg(i2c->dev, |
104 | "SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n" , |
105 | ioread32(i2c->base + REG_SM0CFG2_REG), |
106 | ioread32(i2c->base + REG_SM0CTL0_REG), |
107 | ioread32(i2c->base + REG_SM0CTL1_REG), |
108 | ioread32(i2c->base + REG_SM0D0_REG), |
109 | ioread32(i2c->base + REG_SM0D1_REG)); |
110 | } |
111 | |
112 | static int mtk_i2c_check_ack(struct mtk_i2c *i2c, u32 expected) |
113 | { |
114 | u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG); |
115 | u32 ack_expected = (expected << 16) & SM0CTL1_ACK_MASK; |
116 | |
117 | return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO; |
118 | } |
119 | |
120 | static int mtk_i2c_master_start(struct mtk_i2c *i2c) |
121 | { |
122 | iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG); |
123 | return mtk_i2c_wait_idle(i2c); |
124 | } |
125 | |
126 | static int mtk_i2c_master_stop(struct mtk_i2c *i2c) |
127 | { |
128 | iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG); |
129 | return mtk_i2c_wait_idle(i2c); |
130 | } |
131 | |
132 | static int mtk_i2c_master_cmd(struct mtk_i2c *i2c, u32 cmd, int page_len) |
133 | { |
134 | iowrite32(cmd | SM0CTL1_TRI | SM0CTL1_PGLEN(page_len), |
135 | i2c->base + REG_SM0CTL1_REG); |
136 | return mtk_i2c_wait_idle(i2c); |
137 | } |
138 | |
139 | static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, |
140 | int num) |
141 | { |
142 | struct mtk_i2c *i2c; |
143 | struct i2c_msg *pmsg; |
144 | u16 addr; |
145 | int i, j, ret, len, page_len; |
146 | u32 cmd; |
147 | u32 data[2]; |
148 | |
149 | i2c = i2c_get_adapdata(adap); |
150 | |
151 | for (i = 0; i < num; i++) { |
152 | pmsg = &msgs[i]; |
153 | |
154 | /* wait hardware idle */ |
155 | ret = mtk_i2c_wait_idle(i2c); |
156 | if (ret) |
157 | goto err_timeout; |
158 | |
159 | /* start sequence */ |
160 | ret = mtk_i2c_master_start(i2c); |
161 | if (ret) |
162 | goto err_timeout; |
163 | |
164 | /* write address */ |
165 | if (pmsg->flags & I2C_M_TEN) { |
166 | /* 10 bits address */ |
167 | addr = 0xf0 | ((pmsg->addr >> 7) & 0x06); |
168 | addr |= (pmsg->addr & 0xff) << 8; |
169 | if (pmsg->flags & I2C_M_RD) |
170 | addr |= 1; |
171 | iowrite32(addr, i2c->base + REG_SM0D0_REG); |
172 | ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, page_len: 2); |
173 | if (ret) |
174 | goto err_timeout; |
175 | } else { |
176 | /* 7 bits address */ |
177 | addr = i2c_8bit_addr_from_msg(msg: pmsg); |
178 | iowrite32(addr, i2c->base + REG_SM0D0_REG); |
179 | ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, page_len: 1); |
180 | if (ret) |
181 | goto err_timeout; |
182 | } |
183 | |
184 | /* check address ACK */ |
185 | if (!(pmsg->flags & I2C_M_IGNORE_NAK)) { |
186 | ret = mtk_i2c_check_ack(i2c, BIT(0)); |
187 | if (ret) |
188 | goto err_ack; |
189 | } |
190 | |
191 | /* transfer data */ |
192 | for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) { |
193 | page_len = (len >= 8) ? 8 : len; |
194 | |
195 | if (pmsg->flags & I2C_M_RD) { |
196 | cmd = (len > 8) ? |
197 | SM0CTL1_READ : SM0CTL1_READ_LAST; |
198 | } else { |
199 | memcpy(data, &pmsg->buf[j], page_len); |
200 | iowrite32(data[0], i2c->base + REG_SM0D0_REG); |
201 | iowrite32(data[1], i2c->base + REG_SM0D1_REG); |
202 | cmd = SM0CTL1_WRITE; |
203 | } |
204 | |
205 | ret = mtk_i2c_master_cmd(i2c, cmd, page_len); |
206 | if (ret) |
207 | goto err_timeout; |
208 | |
209 | if (pmsg->flags & I2C_M_RD) { |
210 | data[0] = ioread32(i2c->base + REG_SM0D0_REG); |
211 | data[1] = ioread32(i2c->base + REG_SM0D1_REG); |
212 | memcpy(&pmsg->buf[j], data, page_len); |
213 | } else { |
214 | if (!(pmsg->flags & I2C_M_IGNORE_NAK)) { |
215 | ret = mtk_i2c_check_ack(i2c, |
216 | expected: (1 << page_len) |
217 | - 1); |
218 | if (ret) |
219 | goto err_ack; |
220 | } |
221 | } |
222 | } |
223 | } |
224 | |
225 | ret = mtk_i2c_master_stop(i2c); |
226 | if (ret) |
227 | goto err_timeout; |
228 | |
229 | /* the return value is number of executed messages */ |
230 | return i; |
231 | |
232 | err_ack: |
233 | ret = mtk_i2c_master_stop(i2c); |
234 | if (ret) |
235 | goto err_timeout; |
236 | return -ENXIO; |
237 | |
238 | err_timeout: |
239 | mtk_i2c_dump_reg(i2c); |
240 | mtk_i2c_reset(i2c); |
241 | return ret; |
242 | } |
243 | |
244 | static u32 mtk_i2c_func(struct i2c_adapter *a) |
245 | { |
246 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; |
247 | } |
248 | |
249 | static const struct i2c_algorithm mtk_i2c_algo = { |
250 | .master_xfer = mtk_i2c_master_xfer, |
251 | .functionality = mtk_i2c_func, |
252 | }; |
253 | |
254 | static const struct of_device_id i2c_mtk_dt_ids[] = { |
255 | { .compatible = "mediatek,mt7621-i2c" }, |
256 | { /* sentinel */ } |
257 | }; |
258 | |
259 | MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids); |
260 | |
261 | static void mtk_i2c_init(struct mtk_i2c *i2c) |
262 | { |
263 | i2c->clk_div = clk_get_rate(clk: i2c->clk) / i2c->bus_freq - 1; |
264 | if (i2c->clk_div < 99) |
265 | i2c->clk_div = 99; |
266 | if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX) |
267 | i2c->clk_div = SM0CTL0_CLK_DIV_MAX; |
268 | |
269 | mtk_i2c_reset(i2c); |
270 | } |
271 | |
272 | static int mtk_i2c_probe(struct platform_device *pdev) |
273 | { |
274 | struct mtk_i2c *i2c; |
275 | struct i2c_adapter *adap; |
276 | int ret; |
277 | |
278 | i2c = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct mtk_i2c), GFP_KERNEL); |
279 | if (!i2c) |
280 | return -ENOMEM; |
281 | |
282 | i2c->base = devm_platform_get_and_ioremap_resource(pdev, index: 0, NULL); |
283 | if (IS_ERR(ptr: i2c->base)) |
284 | return PTR_ERR(ptr: i2c->base); |
285 | |
286 | i2c->clk = devm_clk_get_enabled(dev: &pdev->dev, NULL); |
287 | if (IS_ERR(ptr: i2c->clk)) { |
288 | dev_err(&pdev->dev, "Failed to enable clock\n" ); |
289 | return PTR_ERR(ptr: i2c->clk); |
290 | } |
291 | |
292 | i2c->dev = &pdev->dev; |
293 | |
294 | if (of_property_read_u32(np: pdev->dev.of_node, propname: "clock-frequency" , |
295 | out_value: &i2c->bus_freq)) |
296 | i2c->bus_freq = I2C_MAX_STANDARD_MODE_FREQ; |
297 | |
298 | if (i2c->bus_freq == 0) { |
299 | dev_warn(i2c->dev, "clock-frequency 0 not supported\n" ); |
300 | return -EINVAL; |
301 | } |
302 | |
303 | adap = &i2c->adap; |
304 | adap->owner = THIS_MODULE; |
305 | adap->algo = &mtk_i2c_algo; |
306 | adap->retries = 3; |
307 | adap->dev.parent = &pdev->dev; |
308 | i2c_set_adapdata(adap, data: i2c); |
309 | adap->dev.of_node = pdev->dev.of_node; |
310 | strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); |
311 | |
312 | platform_set_drvdata(pdev, data: i2c); |
313 | |
314 | mtk_i2c_init(i2c); |
315 | |
316 | ret = i2c_add_adapter(adap); |
317 | if (ret < 0) |
318 | return ret; |
319 | |
320 | dev_info(&pdev->dev, "clock %u kHz\n" , i2c->bus_freq / 1000); |
321 | |
322 | return 0; |
323 | } |
324 | |
325 | static void mtk_i2c_remove(struct platform_device *pdev) |
326 | { |
327 | struct mtk_i2c *i2c = platform_get_drvdata(pdev); |
328 | |
329 | i2c_del_adapter(adap: &i2c->adap); |
330 | } |
331 | |
332 | static struct platform_driver mtk_i2c_driver = { |
333 | .probe = mtk_i2c_probe, |
334 | .remove_new = mtk_i2c_remove, |
335 | .driver = { |
336 | .name = "i2c-mt7621" , |
337 | .of_match_table = i2c_mtk_dt_ids, |
338 | }, |
339 | }; |
340 | |
341 | module_platform_driver(mtk_i2c_driver); |
342 | |
343 | MODULE_AUTHOR("Steven Liu" ); |
344 | MODULE_DESCRIPTION("MT7621 I2C host driver" ); |
345 | MODULE_LICENSE("GPL v2" ); |
346 | MODULE_ALIAS("platform:MT7621-I2C" ); |
347 | |