1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
5 *
6 * Copyright 2012-2020 Analog Devices Inc.
7 */
8
9#include <linux/adi-axi-common.h>
10#include <linux/bitfield.h>
11#include <linux/cleanup.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23
24#include <linux/iio/backend.h>
25#include <linux/iio/buffer-dmaengine.h>
26#include <linux/iio/buffer.h>
27#include <linux/iio/iio.h>
28
29#include "ad7606_bus_iface.h"
30/*
31 * Register definitions:
32 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
33 */
34
35/* ADC controls */
36
37#define ADI_AXI_REG_RSTN 0x0040
38#define ADI_AXI_REG_RSTN_CE_N BIT(2)
39#define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
40#define ADI_AXI_REG_RSTN_RSTN BIT(0)
41
42#define ADI_AXI_ADC_REG_CONFIG 0x000c
43#define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7)
44
45#define ADI_AXI_ADC_REG_CTRL 0x0044
46#define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8)
47#define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3)
48#define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1)
49
50#define ADI_AXI_ADC_REG_CNTRL_3 0x004c
51#define AXI_AD485X_CNTRL_3_OS_EN_MSK BIT(2)
52#define AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK GENMASK(1, 0)
53#define AXI_AD485X_PACKET_FORMAT_20BIT 0x0
54#define AXI_AD485X_PACKET_FORMAT_24BIT 0x1
55#define AXI_AD485X_PACKET_FORMAT_32BIT 0x2
56#define AXI_AD408X_CNTRL_3_FILTER_EN_MSK BIT(0)
57
58#define ADI_AXI_ADC_REG_SYNC_STATUS 0x0068
59#define ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK BIT(0)
60
61#define ADI_AXI_ADC_REG_DRP_STATUS 0x0074
62#define ADI_AXI_ADC_DRP_LOCKED BIT(17)
63
64/* ADC Channel controls */
65
66#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
67#define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
68#define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
69#define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
70#define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
71#define ADI_AXI_REG_CHAN_CTRL_FMT_MASK GENMASK(6, 4)
72#define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
73#define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
74#define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
75#define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
76#define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
77
78#define ADI_AXI_ADC_REG_CHAN_STATUS(c) (0x0404 + (c) * 0x40)
79#define ADI_AXI_ADC_CHAN_STAT_PN_MASK GENMASK(2, 1)
80/* out of sync */
81#define ADI_AXI_ADC_CHAN_STAT_PN_OOS BIT(1)
82/* spurious out of sync */
83#define ADI_AXI_ADC_CHAN_STAT_PN_ERR BIT(2)
84
85#define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40)
86#define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16)
87
88#define ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(c) (0x0424 + (c) * 0x40)
89#define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0)
90
91/* IO Delays */
92#define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4)
93#define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0)
94
95#define ADI_AXI_REG_CONFIG_WR 0x0080
96#define ADI_AXI_REG_CONFIG_RD 0x0084
97#define ADI_AXI_REG_CONFIG_CTRL 0x008c
98#define ADI_AXI_REG_CONFIG_CTRL_READ 0x03
99#define ADI_AXI_REG_CONFIG_CTRL_WRITE 0x01
100
101#define ADI_AXI_ADC_MAX_IO_NUM_LANES 15
102
103#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
104 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
105 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
106 ADI_AXI_REG_CHAN_CTRL_ENABLE)
107
108#define ADI_AXI_REG_READ_BIT 0x8000
109#define ADI_AXI_REG_ADDRESS_MASK 0xff00
110#define ADI_AXI_REG_VALUE_MASK 0x00ff
111
112struct axi_adc_info {
113 unsigned int version;
114 const struct iio_backend_info *backend_info;
115 bool has_child_nodes;
116 const void *pdata;
117 unsigned int pdata_sz;
118};
119
120struct adi_axi_adc_state {
121 const struct axi_adc_info *info;
122 struct regmap *regmap;
123 struct device *dev;
124 /* lock to protect multiple accesses to the device registers */
125 struct mutex lock;
126};
127
128static int axi_adc_enable(struct iio_backend *back)
129{
130 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
131 unsigned int __val;
132 int ret;
133
134 guard(mutex)(T: &st->lock);
135 ret = regmap_set_bits(map: st->regmap, ADI_AXI_REG_RSTN,
136 ADI_AXI_REG_RSTN_MMCM_RSTN);
137 if (ret)
138 return ret;
139
140 /*
141 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
142 * designs really use it but if they don't we still get the lock bit
143 * set. So let's do it all the time so the code is generic.
144 */
145 ret = regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_DRP_STATUS,
146 __val, __val & ADI_AXI_ADC_DRP_LOCKED,
147 100, 1000);
148 if (ret)
149 return ret;
150
151 return regmap_set_bits(map: st->regmap, ADI_AXI_REG_RSTN,
152 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
153}
154
155static void axi_adc_disable(struct iio_backend *back)
156{
157 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
158
159 guard(mutex)(T: &st->lock);
160 regmap_write(map: st->regmap, ADI_AXI_REG_RSTN, val: 0);
161}
162
163static int axi_adc_data_format_set(struct iio_backend *back, unsigned int chan,
164 const struct iio_backend_data_fmt *data)
165{
166 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
167 u32 val;
168
169 if (!data->enable)
170 return regmap_clear_bits(map: st->regmap,
171 ADI_AXI_REG_CHAN_CTRL(chan),
172 ADI_AXI_REG_CHAN_CTRL_FMT_EN);
173
174 val = FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_EN, true);
175 if (data->sign_extend)
176 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT, true);
177 if (data->type == IIO_BACKEND_OFFSET_BINARY)
178 val |= FIELD_PREP(ADI_AXI_REG_CHAN_CTRL_FMT_TYPE, true);
179
180 return regmap_update_bits(map: st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
181 ADI_AXI_REG_CHAN_CTRL_FMT_MASK, val);
182}
183
184static int axi_adc_data_sample_trigger(struct iio_backend *back,
185 enum iio_backend_sample_trigger trigger)
186{
187 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
188
189 switch (trigger) {
190 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING:
191 return regmap_clear_bits(map: st->regmap, ADI_AXI_ADC_REG_CTRL,
192 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK);
193 case IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING:
194 return regmap_set_bits(map: st->regmap, ADI_AXI_ADC_REG_CTRL,
195 ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK);
196 default:
197 return -EINVAL;
198 }
199}
200
201static int axi_adc_iodelays_set(struct iio_backend *back, unsigned int lane,
202 unsigned int tap)
203{
204 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
205 int ret;
206 u32 val;
207
208 if (tap > FIELD_MAX(AXI_ADC_DELAY_CTRL_MASK))
209 return -EINVAL;
210 if (lane > ADI_AXI_ADC_MAX_IO_NUM_LANES)
211 return -EINVAL;
212
213 guard(mutex)(T: &st->lock);
214 ret = regmap_write(map: st->regmap, ADI_AXI_ADC_REG_DELAY(lane), val: tap);
215 if (ret)
216 return ret;
217 /*
218 * If readback is ~0, that means there are issues with the
219 * delay_clk.
220 */
221 ret = regmap_read(map: st->regmap, ADI_AXI_ADC_REG_DELAY(lane), val: &val);
222 if (ret)
223 return ret;
224 if (val == U32_MAX)
225 return -EIO;
226
227 return 0;
228}
229
230static int axi_adc_test_pattern_set(struct iio_backend *back,
231 unsigned int chan,
232 enum iio_backend_test_pattern pattern)
233{
234 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
235
236 switch (pattern) {
237 case IIO_BACKEND_NO_TEST_PATTERN:
238 /* nothing to do */
239 return 0;
240 case IIO_BACKEND_ADI_PRBS_9A:
241 return regmap_update_bits(map: st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan),
242 ADI_AXI_ADC_CHAN_PN_SEL_MASK,
243 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 0));
244 case IIO_BACKEND_ADI_PRBS_23A:
245 return regmap_update_bits(map: st->regmap, ADI_AXI_ADC_REG_CHAN_CTRL_3(chan),
246 ADI_AXI_ADC_CHAN_PN_SEL_MASK,
247 FIELD_PREP(ADI_AXI_ADC_CHAN_PN_SEL_MASK, 1));
248 default:
249 return -EINVAL;
250 }
251}
252
253static int axi_adc_oversampling_ratio_set(struct iio_backend *back,
254 unsigned int chan,
255 unsigned int rate)
256{
257 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
258
259 return regmap_update_bits(map: st->regmap,
260 ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(chan),
261 ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK,
262 FIELD_PREP(ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK,
263 rate));
264}
265
266static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan,
267 unsigned int *status)
268{
269 int ret;
270
271 guard(mutex)(T: &st->lock);
272 /* reset test bits by setting them */
273 ret = regmap_write(map: st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan),
274 ADI_AXI_ADC_CHAN_STAT_PN_MASK);
275 if (ret)
276 return ret;
277
278 /* let's give enough time to validate or erroring the incoming pattern */
279 fsleep(usecs: 1000);
280
281 return regmap_read(map: st->regmap, ADI_AXI_ADC_REG_CHAN_STATUS(chan),
282 val: status);
283}
284
285static int axi_adc_chan_status(struct iio_backend *back, unsigned int chan,
286 bool *error)
287{
288 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
289 u32 val;
290 int ret;
291
292 ret = axi_adc_read_chan_status(st, chan, status: &val);
293 if (ret)
294 return ret;
295
296 if (ADI_AXI_ADC_CHAN_STAT_PN_MASK & val)
297 *error = true;
298 else
299 *error = false;
300
301 return 0;
302}
303
304static int axi_adc_debugfs_print_chan_status(struct iio_backend *back,
305 unsigned int chan, char *buf,
306 size_t len)
307{
308 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
309 u32 val;
310 int ret;
311
312 ret = axi_adc_read_chan_status(st, chan, status: &val);
313 if (ret)
314 return ret;
315
316 /*
317 * PN_ERR is cleared in case out of sync is set. Hence, no point in
318 * checking both bits.
319 */
320 if (val & ADI_AXI_ADC_CHAN_STAT_PN_OOS)
321 return scnprintf(buf, size: len, fmt: "CH%u: Out of Sync.\n", chan);
322 if (val & ADI_AXI_ADC_CHAN_STAT_PN_ERR)
323 return scnprintf(buf, size: len, fmt: "CH%u: Spurious Out of Sync.\n", chan);
324
325 return scnprintf(buf, size: len, fmt: "CH%u: OK.\n", chan);
326}
327
328static int axi_adc_chan_enable(struct iio_backend *back, unsigned int chan)
329{
330 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
331
332 return regmap_set_bits(map: st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
333 ADI_AXI_REG_CHAN_CTRL_ENABLE);
334}
335
336static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan)
337{
338 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
339
340 return regmap_clear_bits(map: st->regmap, ADI_AXI_REG_CHAN_CTRL(chan),
341 ADI_AXI_REG_CHAN_CTRL_ENABLE);
342}
343
344static int axi_adc_interface_type_get(struct iio_backend *back,
345 enum iio_backend_interface_type *type)
346{
347 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
348 unsigned int val;
349 int ret;
350
351 ret = regmap_read(map: st->regmap, ADI_AXI_ADC_REG_CONFIG, val: &val);
352 if (ret)
353 return ret;
354
355 if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N)
356 *type = IIO_BACKEND_INTERFACE_SERIAL_CMOS;
357 else
358 *type = IIO_BACKEND_INTERFACE_SERIAL_LVDS;
359
360 return 0;
361}
362
363static int axi_adc_ad485x_data_size_set(struct iio_backend *back,
364 unsigned int size)
365{
366 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
367 unsigned int val;
368
369 switch (size) {
370 /*
371 * There are two different variants of the AXI AXI_AD485X IP block, a
372 * 16-bit and a 20-bit variant.
373 * The 0x0 value (AXI_AD485X_PACKET_FORMAT_20BIT) is corresponding also
374 * to the 16-bit variant of the IP block.
375 */
376 case 16:
377 case 20:
378 val = AXI_AD485X_PACKET_FORMAT_20BIT;
379 break;
380 case 24:
381 val = AXI_AD485X_PACKET_FORMAT_24BIT;
382 break;
383 /*
384 * The 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT) corresponds only to the
385 * 20-bit variant of the IP block. Setting this value properly is
386 * ensured by the upper layers of the drivers calling the axi-adc
387 * functions.
388 * Also, for 16-bit IP block, the 0x2 (AXI_AD485X_PACKET_FORMAT_32BIT)
389 * value is handled as maximum size available which is 24-bit for this
390 * configuration.
391 */
392 case 32:
393 val = AXI_AD485X_PACKET_FORMAT_32BIT;
394 break;
395 default:
396 return -EINVAL;
397 }
398
399 return regmap_update_bits(map: st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
400 AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK,
401 FIELD_PREP(AXI_AD485X_CNTRL_3_PACKET_FORMAT_MSK, val));
402}
403
404static int axi_adc_ad485x_oversampling_ratio_set(struct iio_backend *back,
405 unsigned int chan,
406 unsigned int ratio)
407{
408 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
409
410 /* The current state of the function enables or disables the
411 * oversampling in REG_CNTRL_3 register. A ratio equal to 1 implies no
412 * oversampling, while a value greater than 1 implies oversampling being
413 * enabled.
414 */
415 switch (ratio) {
416 case 0:
417 return -EINVAL;
418 case 1:
419 return regmap_clear_bits(map: st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
420 AXI_AD485X_CNTRL_3_OS_EN_MSK);
421 default:
422 return regmap_set_bits(map: st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
423 AXI_AD485X_CNTRL_3_OS_EN_MSK);
424 }
425}
426
427static int axi_adc_ad408x_filter_type_set(struct iio_backend *back,
428 enum iio_backend_filter_type type)
429{
430 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
431
432 if (type)
433 return regmap_set_bits(map: st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
434 AXI_AD408X_CNTRL_3_FILTER_EN_MSK);
435
436 return regmap_clear_bits(map: st->regmap, ADI_AXI_ADC_REG_CNTRL_3,
437 AXI_AD408X_CNTRL_3_FILTER_EN_MSK);
438}
439
440static int axi_adc_ad408x_interface_data_align(struct iio_backend *back,
441 u32 timeout_us)
442{
443 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
444 u32 val;
445 int ret;
446
447 ret = regmap_set_bits(map: st->regmap, ADI_AXI_ADC_REG_CTRL,
448 ADI_AXI_ADC_CTRL_SYNC_MSK);
449 if (ret)
450 return ret;
451
452 return regmap_read_poll_timeout(st->regmap, ADI_AXI_ADC_REG_SYNC_STATUS,
453 val,
454 FIELD_GET(ADI_AXI_ADC_SYNC_STATUS_ADC_SYNC_MSK, val),
455 1, timeout_us);
456}
457
458static int axi_adc_num_lanes_set(struct iio_backend *back,
459 unsigned int num_lanes)
460{
461 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
462
463 if (!num_lanes)
464 return -EINVAL;
465
466 return regmap_update_bits(map: st->regmap, ADI_AXI_ADC_REG_CTRL,
467 ADI_AXI_ADC_CTRL_NUM_LANES_MSK,
468 FIELD_PREP(ADI_AXI_ADC_CTRL_NUM_LANES_MSK, num_lanes));
469}
470
471static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back,
472 struct iio_dev *indio_dev)
473{
474 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
475 const char *dma_name;
476
477 if (device_property_read_string(dev: st->dev, propname: "dma-names", val: &dma_name))
478 dma_name = "rx";
479
480 return iio_dmaengine_buffer_setup(st->dev, indio_dev, dma_name);
481}
482
483static int axi_adc_raw_write(struct iio_backend *back, u32 val)
484{
485 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
486
487 regmap_write(map: st->regmap, ADI_AXI_REG_CONFIG_WR, val);
488 regmap_write(map: st->regmap, ADI_AXI_REG_CONFIG_CTRL,
489 ADI_AXI_REG_CONFIG_CTRL_WRITE);
490 fsleep(usecs: 100);
491 regmap_write(map: st->regmap, ADI_AXI_REG_CONFIG_CTRL, val: 0x00);
492 fsleep(usecs: 100);
493
494 return 0;
495}
496
497static int axi_adc_raw_read(struct iio_backend *back, u32 *val)
498{
499 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
500
501 regmap_write(map: st->regmap, ADI_AXI_REG_CONFIG_CTRL,
502 ADI_AXI_REG_CONFIG_CTRL_READ);
503 fsleep(usecs: 100);
504 regmap_read(map: st->regmap, ADI_AXI_REG_CONFIG_RD, val);
505 regmap_write(map: st->regmap, ADI_AXI_REG_CONFIG_CTRL, val: 0x00);
506 fsleep(usecs: 100);
507
508 return 0;
509}
510
511static int ad7606_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val)
512{
513 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
514 u32 addr, reg_val;
515
516 guard(mutex)(T: &st->lock);
517
518 /*
519 * The address is written on the highest weight byte, and the MSB set
520 * at 1 indicates a read operation.
521 */
522 addr = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) | ADI_AXI_REG_READ_BIT;
523 axi_adc_raw_write(back, val: addr);
524 axi_adc_raw_read(back, val: &reg_val);
525
526 *val = FIELD_GET(ADI_AXI_REG_VALUE_MASK, reg_val);
527
528 /* Write 0x0 on the bus to get back to ADC mode */
529 axi_adc_raw_write(back, val: 0);
530
531 return 0;
532}
533
534static int ad7606_bus_reg_write(struct iio_backend *back, u32 reg, u32 val)
535{
536 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
537 u32 buf;
538
539 guard(mutex)(T: &st->lock);
540
541 /* Write any register to switch to register mode */
542 axi_adc_raw_write(back, val: 0xaf00);
543
544 buf = FIELD_PREP(ADI_AXI_REG_ADDRESS_MASK, reg) |
545 FIELD_PREP(ADI_AXI_REG_VALUE_MASK, val);
546 axi_adc_raw_write(back, val: buf);
547
548 /* Write 0x0 on the bus to get back to ADC mode */
549 axi_adc_raw_write(back, val: 0);
550
551 return 0;
552}
553
554static void axi_adc_free_buffer(struct iio_backend *back,
555 struct iio_buffer *buffer)
556{
557 iio_dmaengine_buffer_teardown(buffer);
558}
559
560static int axi_adc_reg_access(struct iio_backend *back, unsigned int reg,
561 unsigned int writeval, unsigned int *readval)
562{
563 struct adi_axi_adc_state *st = iio_backend_get_priv(conv: back);
564
565 if (readval)
566 return regmap_read(map: st->regmap, reg, val: readval);
567
568 return regmap_write(map: st->regmap, reg, val: writeval);
569}
570
571static const struct regmap_config axi_adc_regmap_config = {
572 .val_bits = 32,
573 .reg_bits = 32,
574 .reg_stride = 4,
575};
576
577static void axi_adc_child_remove(void *data)
578{
579 platform_device_unregister(data);
580}
581
582static int axi_adc_create_platform_device(struct adi_axi_adc_state *st,
583 struct fwnode_handle *child)
584{
585 struct platform_device_info pi = {
586 .parent = st->dev,
587 .name = fwnode_get_name(fwnode: child),
588 .id = PLATFORM_DEVID_AUTO,
589 .fwnode = child,
590 .data = st->info->pdata,
591 .size_data = st->info->pdata_sz,
592 };
593 struct platform_device *pdev;
594 int ret;
595
596 pdev = platform_device_register_full(pdevinfo: &pi);
597 if (IS_ERR(ptr: pdev))
598 return PTR_ERR(ptr: pdev);
599
600 ret = devm_add_action_or_reset(st->dev, axi_adc_child_remove, pdev);
601 if (ret)
602 return ret;
603
604 return 0;
605}
606
607static const struct iio_backend_ops adi_axi_adc_ops = {
608 .enable = axi_adc_enable,
609 .disable = axi_adc_disable,
610 .data_format_set = axi_adc_data_format_set,
611 .chan_enable = axi_adc_chan_enable,
612 .chan_disable = axi_adc_chan_disable,
613 .request_buffer = axi_adc_request_buffer,
614 .free_buffer = axi_adc_free_buffer,
615 .data_sample_trigger = axi_adc_data_sample_trigger,
616 .iodelay_set = axi_adc_iodelays_set,
617 .test_pattern_set = axi_adc_test_pattern_set,
618 .chan_status = axi_adc_chan_status,
619 .interface_type_get = axi_adc_interface_type_get,
620 .oversampling_ratio_set = axi_adc_oversampling_ratio_set,
621 .num_lanes_set = axi_adc_num_lanes_set,
622 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
623 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
624};
625
626static const struct iio_backend_info adi_axi_adc_generic = {
627 .name = "axi-adc",
628 .ops = &adi_axi_adc_ops,
629};
630
631static const struct iio_backend_ops adi_ad485x_ops = {
632 .enable = axi_adc_enable,
633 .disable = axi_adc_disable,
634 .data_format_set = axi_adc_data_format_set,
635 .chan_enable = axi_adc_chan_enable,
636 .chan_disable = axi_adc_chan_disable,
637 .request_buffer = axi_adc_request_buffer,
638 .free_buffer = axi_adc_free_buffer,
639 .data_sample_trigger = axi_adc_data_sample_trigger,
640 .iodelay_set = axi_adc_iodelays_set,
641 .chan_status = axi_adc_chan_status,
642 .interface_type_get = axi_adc_interface_type_get,
643 .data_size_set = axi_adc_ad485x_data_size_set,
644 .oversampling_ratio_set = axi_adc_ad485x_oversampling_ratio_set,
645 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
646 .debugfs_print_chan_status =
647 iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
648};
649
650static const struct iio_backend_info axi_ad485x = {
651 .name = "axi-ad485x",
652 .ops = &adi_ad485x_ops,
653};
654
655static const struct iio_backend_ops adi_ad408x_ops = {
656 .enable = axi_adc_enable,
657 .disable = axi_adc_disable,
658 .chan_enable = axi_adc_chan_enable,
659 .chan_disable = axi_adc_chan_disable,
660 .request_buffer = axi_adc_request_buffer,
661 .free_buffer = axi_adc_free_buffer,
662 .data_sample_trigger = axi_adc_data_sample_trigger,
663 .filter_type_set = axi_adc_ad408x_filter_type_set,
664 .interface_data_align = axi_adc_ad408x_interface_data_align,
665 .num_lanes_set = axi_adc_num_lanes_set,
666 .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
667 .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
668};
669
670static const struct iio_backend_info axi_ad408x = {
671 .name = "axi-ad408x",
672 .ops = &adi_ad408x_ops,
673};
674
675static int adi_axi_adc_probe(struct platform_device *pdev)
676{
677 struct adi_axi_adc_state *st;
678 void __iomem *base;
679 unsigned int ver;
680 struct clk *clk;
681 int ret;
682
683 st = devm_kzalloc(dev: &pdev->dev, size: sizeof(*st), GFP_KERNEL);
684 if (!st)
685 return -ENOMEM;
686
687 base = devm_platform_ioremap_resource(pdev, index: 0);
688 if (IS_ERR(ptr: base))
689 return PTR_ERR(ptr: base);
690
691 st->dev = &pdev->dev;
692 st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
693 &axi_adc_regmap_config);
694 if (IS_ERR(ptr: st->regmap))
695 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: st->regmap),
696 fmt: "failed to init register map\n");
697
698 st->info = device_get_match_data(dev: &pdev->dev);
699 if (!st->info)
700 return -ENODEV;
701
702 clk = devm_clk_get_enabled(dev: &pdev->dev, NULL);
703 if (IS_ERR(ptr: clk))
704 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: clk),
705 fmt: "failed to get clock\n");
706
707 /*
708 * Force disable the core. Up to the frontend to enable us. And we can
709 * still read/write registers...
710 */
711 ret = regmap_write(map: st->regmap, ADI_AXI_REG_RSTN, val: 0);
712 if (ret)
713 return ret;
714
715 ret = regmap_read(map: st->regmap, ADI_AXI_REG_VERSION, val: &ver);
716 if (ret)
717 return ret;
718
719 if (ADI_AXI_PCORE_VER_MAJOR(ver) !=
720 ADI_AXI_PCORE_VER_MAJOR(st->info->version)) {
721 dev_err(&pdev->dev,
722 "Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
723 ADI_AXI_PCORE_VER_MAJOR(st->info->version),
724 ADI_AXI_PCORE_VER_MINOR(st->info->version),
725 ADI_AXI_PCORE_VER_PATCH(st->info->version),
726 ADI_AXI_PCORE_VER_MAJOR(ver),
727 ADI_AXI_PCORE_VER_MINOR(ver),
728 ADI_AXI_PCORE_VER_PATCH(ver));
729 return -ENODEV;
730 }
731
732 ret = devm_iio_backend_register(dev: &pdev->dev, info: st->info->backend_info, priv: st);
733 if (ret)
734 return dev_err_probe(dev: &pdev->dev, err: ret,
735 fmt: "failed to register iio backend\n");
736
737 device_for_each_child_node_scoped(&pdev->dev, child) {
738 int val;
739
740 if (!st->info->has_child_nodes)
741 return dev_err_probe(dev: &pdev->dev, err: -EINVAL,
742 fmt: "invalid fdt axi-dac compatible.");
743
744 /* Processing only reg 0 node */
745 ret = fwnode_property_read_u32(fwnode: child, propname: "reg", val: &val);
746 if (ret)
747 return dev_err_probe(dev: &pdev->dev, err: ret,
748 fmt: "invalid reg property.");
749 if (val != 0)
750 return dev_err_probe(dev: &pdev->dev, err: -EINVAL,
751 fmt: "invalid node address.");
752
753 ret = axi_adc_create_platform_device(st, child);
754 if (ret)
755 return dev_err_probe(dev: &pdev->dev, err: -EINVAL,
756 fmt: "cannot create device.");
757 }
758
759 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
760 ADI_AXI_PCORE_VER_MAJOR(ver),
761 ADI_AXI_PCORE_VER_MINOR(ver),
762 ADI_AXI_PCORE_VER_PATCH(ver));
763
764 return 0;
765}
766
767static const struct axi_adc_info adc_generic = {
768 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
769 .backend_info = &adi_axi_adc_generic,
770};
771
772static const struct axi_adc_info adi_axi_ad485x = {
773 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
774 .backend_info = &axi_ad485x,
775};
776
777static const struct ad7606_platform_data ad7606_pdata = {
778 .bus_reg_read = ad7606_bus_reg_read,
779 .bus_reg_write = ad7606_bus_reg_write,
780};
781
782static const struct axi_adc_info adc_ad7606 = {
783 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
784 .backend_info = &adi_axi_adc_generic,
785 .pdata = &ad7606_pdata,
786 .pdata_sz = sizeof(ad7606_pdata),
787 .has_child_nodes = true,
788};
789
790static const struct axi_adc_info adi_axi_ad408x = {
791 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
792 .backend_info = &axi_ad408x,
793};
794
795/* Match table for of_platform binding */
796static const struct of_device_id adi_axi_adc_of_match[] = {
797 { .compatible = "adi,axi-adc-10.0.a", .data = &adc_generic },
798 { .compatible = "adi,axi-ad408x", .data = &adi_axi_ad408x },
799 { .compatible = "adi,axi-ad485x", .data = &adi_axi_ad485x },
800 { .compatible = "adi,axi-ad7606x", .data = &adc_ad7606 },
801 { }
802};
803MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
804
805static struct platform_driver adi_axi_adc_driver = {
806 .driver = {
807 .name = KBUILD_MODNAME,
808 .of_match_table = adi_axi_adc_of_match,
809 },
810 .probe = adi_axi_adc_probe,
811};
812module_platform_driver(adi_axi_adc_driver);
813
814MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
815MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
816MODULE_LICENSE("GPL v2");
817MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
818MODULE_IMPORT_NS("IIO_BACKEND");
819

source code of linux/drivers/iio/adc/adi-axi-adc.c