1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com> |
4 | * Loongson HyperTransport Interrupt Vector support |
5 | */ |
6 | |
7 | #define pr_fmt(fmt) "htvec: " fmt |
8 | |
9 | #include <linux/interrupt.h> |
10 | #include <linux/irq.h> |
11 | #include <linux/irqchip.h> |
12 | #include <linux/irqdomain.h> |
13 | #include <linux/irqchip/chained_irq.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/of_address.h> |
17 | #include <linux/of_irq.h> |
18 | #include <linux/syscore_ops.h> |
19 | |
20 | /* Registers */ |
21 | #define HTVEC_EN_OFF 0x20 |
22 | #define HTVEC_MAX_PARENT_IRQ 8 |
23 | #define VEC_COUNT_PER_REG 32 |
24 | #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) |
25 | #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) |
26 | |
27 | struct htvec { |
28 | int num_parents; |
29 | void __iomem *base; |
30 | struct irq_domain *htvec_domain; |
31 | raw_spinlock_t htvec_lock; |
32 | u32 saved_vec_en[HTVEC_MAX_PARENT_IRQ]; |
33 | }; |
34 | |
35 | static struct htvec *htvec_priv; |
36 | |
37 | static void htvec_irq_dispatch(struct irq_desc *desc) |
38 | { |
39 | int i; |
40 | u32 pending; |
41 | bool handled = false; |
42 | struct irq_chip *chip = irq_desc_get_chip(desc); |
43 | struct htvec *priv = irq_desc_get_handler_data(desc); |
44 | |
45 | chained_irq_enter(chip, desc); |
46 | |
47 | for (i = 0; i < priv->num_parents; i++) { |
48 | pending = readl(addr: priv->base + 4 * i); |
49 | while (pending) { |
50 | int bit = __ffs(pending); |
51 | |
52 | generic_handle_domain_irq(domain: priv->htvec_domain, |
53 | hwirq: bit + VEC_COUNT_PER_REG * i); |
54 | pending &= ~BIT(bit); |
55 | handled = true; |
56 | } |
57 | } |
58 | |
59 | if (!handled) |
60 | spurious_interrupt(); |
61 | |
62 | chained_irq_exit(chip, desc); |
63 | } |
64 | |
65 | static void htvec_ack_irq(struct irq_data *d) |
66 | { |
67 | struct htvec *priv = irq_data_get_irq_chip_data(d); |
68 | |
69 | writel(BIT(VEC_REG_BIT(d->hwirq)), |
70 | addr: priv->base + VEC_REG_IDX(d->hwirq) * 4); |
71 | } |
72 | |
73 | static void htvec_mask_irq(struct irq_data *d) |
74 | { |
75 | u32 reg; |
76 | void __iomem *addr; |
77 | struct htvec *priv = irq_data_get_irq_chip_data(d); |
78 | |
79 | raw_spin_lock(&priv->htvec_lock); |
80 | addr = priv->base + HTVEC_EN_OFF; |
81 | addr += VEC_REG_IDX(d->hwirq) * 4; |
82 | reg = readl(addr); |
83 | reg &= ~BIT(VEC_REG_BIT(d->hwirq)); |
84 | writel(val: reg, addr); |
85 | raw_spin_unlock(&priv->htvec_lock); |
86 | } |
87 | |
88 | static void htvec_unmask_irq(struct irq_data *d) |
89 | { |
90 | u32 reg; |
91 | void __iomem *addr; |
92 | struct htvec *priv = irq_data_get_irq_chip_data(d); |
93 | |
94 | raw_spin_lock(&priv->htvec_lock); |
95 | addr = priv->base + HTVEC_EN_OFF; |
96 | addr += VEC_REG_IDX(d->hwirq) * 4; |
97 | reg = readl(addr); |
98 | reg |= BIT(VEC_REG_BIT(d->hwirq)); |
99 | writel(val: reg, addr); |
100 | raw_spin_unlock(&priv->htvec_lock); |
101 | } |
102 | |
103 | static struct irq_chip htvec_irq_chip = { |
104 | .name = "LOONGSON_HTVEC" , |
105 | .irq_mask = htvec_mask_irq, |
106 | .irq_unmask = htvec_unmask_irq, |
107 | .irq_ack = htvec_ack_irq, |
108 | }; |
109 | |
110 | static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq, |
111 | unsigned int nr_irqs, void *arg) |
112 | { |
113 | int ret; |
114 | unsigned long hwirq; |
115 | unsigned int type, i; |
116 | struct htvec *priv = domain->host_data; |
117 | |
118 | ret = irq_domain_translate_onecell(d: domain, fwspec: arg, out_hwirq: &hwirq, out_type: &type); |
119 | if (ret) |
120 | return ret; |
121 | |
122 | for (i = 0; i < nr_irqs; i++) { |
123 | irq_domain_set_info(domain, virq: virq + i, hwirq: hwirq + i, chip: &htvec_irq_chip, |
124 | chip_data: priv, handler: handle_edge_irq, NULL, NULL); |
125 | } |
126 | |
127 | return 0; |
128 | } |
129 | |
130 | static void htvec_domain_free(struct irq_domain *domain, unsigned int virq, |
131 | unsigned int nr_irqs) |
132 | { |
133 | int i; |
134 | |
135 | for (i = 0; i < nr_irqs; i++) { |
136 | struct irq_data *d = irq_domain_get_irq_data(domain, virq: virq + i); |
137 | |
138 | irq_set_handler(irq: virq + i, NULL); |
139 | irq_domain_reset_irq_data(irq_data: d); |
140 | } |
141 | } |
142 | |
143 | static const struct irq_domain_ops htvec_domain_ops = { |
144 | .translate = irq_domain_translate_onecell, |
145 | .alloc = htvec_domain_alloc, |
146 | .free = htvec_domain_free, |
147 | }; |
148 | |
149 | static void htvec_reset(struct htvec *priv) |
150 | { |
151 | u32 idx; |
152 | |
153 | /* Clear IRQ cause registers, mask all interrupts */ |
154 | for (idx = 0; idx < priv->num_parents; idx++) { |
155 | writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx); |
156 | writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx); |
157 | } |
158 | } |
159 | |
160 | static int htvec_suspend(void) |
161 | { |
162 | int i; |
163 | |
164 | for (i = 0; i < htvec_priv->num_parents; i++) |
165 | htvec_priv->saved_vec_en[i] = readl(addr: htvec_priv->base + HTVEC_EN_OFF + 4 * i); |
166 | |
167 | return 0; |
168 | } |
169 | |
170 | static void htvec_resume(void) |
171 | { |
172 | int i; |
173 | |
174 | for (i = 0; i < htvec_priv->num_parents; i++) |
175 | writel(val: htvec_priv->saved_vec_en[i], addr: htvec_priv->base + HTVEC_EN_OFF + 4 * i); |
176 | } |
177 | |
178 | static struct syscore_ops htvec_syscore_ops = { |
179 | .suspend = htvec_suspend, |
180 | .resume = htvec_resume, |
181 | }; |
182 | |
183 | static int htvec_init(phys_addr_t addr, unsigned long size, |
184 | int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) |
185 | { |
186 | int i; |
187 | struct htvec *priv; |
188 | |
189 | priv = kzalloc(size: sizeof(*priv), GFP_KERNEL); |
190 | if (!priv) |
191 | return -ENOMEM; |
192 | |
193 | priv->num_parents = num_parents; |
194 | priv->base = ioremap(offset: addr, size); |
195 | raw_spin_lock_init(&priv->htvec_lock); |
196 | |
197 | /* Setup IRQ domain */ |
198 | priv->htvec_domain = irq_domain_create_linear(fwnode: domain_handle, |
199 | size: (VEC_COUNT_PER_REG * priv->num_parents), |
200 | ops: &htvec_domain_ops, host_data: priv); |
201 | if (!priv->htvec_domain) { |
202 | pr_err("loongson-htvec: cannot add IRQ domain\n" ); |
203 | goto iounmap_base; |
204 | } |
205 | |
206 | htvec_reset(priv); |
207 | |
208 | for (i = 0; i < priv->num_parents; i++) { |
209 | irq_set_chained_handler_and_data(irq: parent_irq[i], |
210 | handle: htvec_irq_dispatch, data: priv); |
211 | } |
212 | |
213 | htvec_priv = priv; |
214 | |
215 | register_syscore_ops(ops: &htvec_syscore_ops); |
216 | |
217 | return 0; |
218 | |
219 | iounmap_base: |
220 | iounmap(addr: priv->base); |
221 | kfree(objp: priv); |
222 | |
223 | return -EINVAL; |
224 | } |
225 | |
226 | #ifdef CONFIG_OF |
227 | |
228 | static int htvec_of_init(struct device_node *node, |
229 | struct device_node *parent) |
230 | { |
231 | int i, err; |
232 | int parent_irq[8]; |
233 | int num_parents = 0; |
234 | struct resource res; |
235 | |
236 | if (of_address_to_resource(dev: node, index: 0, r: &res)) |
237 | return -EINVAL; |
238 | |
239 | /* Interrupt may come from any of the 8 interrupt lines */ |
240 | for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) { |
241 | parent_irq[i] = irq_of_parse_and_map(node, index: i); |
242 | if (parent_irq[i] <= 0) |
243 | break; |
244 | |
245 | num_parents++; |
246 | } |
247 | |
248 | err = htvec_init(addr: res.start, size: resource_size(res: &res), |
249 | num_parents, parent_irq, domain_handle: of_node_to_fwnode(node)); |
250 | if (err < 0) |
251 | return err; |
252 | |
253 | return 0; |
254 | } |
255 | |
256 | IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0" , htvec_of_init); |
257 | |
258 | #endif |
259 | |
260 | #ifdef CONFIG_ACPI |
261 | static int __init pch_pic_parse_madt(union acpi_subtable_headers *, |
262 | const unsigned long end) |
263 | { |
264 | struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header; |
265 | |
266 | return pch_pic_acpi_init(htvec_priv->htvec_domain, pchpic_entry); |
267 | } |
268 | |
269 | static int __init pch_msi_parse_madt(union acpi_subtable_headers *, |
270 | const unsigned long end) |
271 | { |
272 | struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header; |
273 | |
274 | return pch_msi_acpi_init(htvec_priv->htvec_domain, pchmsi_entry); |
275 | } |
276 | |
277 | static int __init acpi_cascade_irqdomain_init(void) |
278 | { |
279 | int r; |
280 | |
281 | r = acpi_table_parse_madt(id: ACPI_MADT_TYPE_BIO_PIC, handler: pch_pic_parse_madt, max_entries: 0); |
282 | if (r < 0) |
283 | return r; |
284 | |
285 | r = acpi_table_parse_madt(id: ACPI_MADT_TYPE_MSI_PIC, handler: pch_msi_parse_madt, max_entries: 0); |
286 | if (r < 0) |
287 | return r; |
288 | |
289 | return 0; |
290 | } |
291 | |
292 | int __init htvec_acpi_init(struct irq_domain *parent, |
293 | struct acpi_madt_ht_pic *acpi_htvec) |
294 | { |
295 | int i, ret; |
296 | int num_parents, parent_irq[8]; |
297 | struct fwnode_handle *domain_handle; |
298 | |
299 | if (!acpi_htvec) |
300 | return -EINVAL; |
301 | |
302 | num_parents = HTVEC_MAX_PARENT_IRQ; |
303 | |
304 | domain_handle = irq_domain_alloc_fwnode(pa: &acpi_htvec->address); |
305 | if (!domain_handle) { |
306 | pr_err("Unable to allocate domain handle\n" ); |
307 | return -ENOMEM; |
308 | } |
309 | |
310 | /* Interrupt may come from any of the 8 interrupt lines */ |
311 | for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) |
312 | parent_irq[i] = irq_create_mapping(host: parent, hwirq: acpi_htvec->cascade[i]); |
313 | |
314 | ret = htvec_init(addr: acpi_htvec->address, size: acpi_htvec->size, |
315 | num_parents, parent_irq, domain_handle); |
316 | |
317 | if (ret == 0) |
318 | ret = acpi_cascade_irqdomain_init(); |
319 | else |
320 | irq_domain_free_fwnode(fwnode: domain_handle); |
321 | |
322 | return ret; |
323 | } |
324 | |
325 | #endif |
326 | |