1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Copyright 2020-2021 NXP
4	*/
5
6	#include <linux/init.h>
7	#include <linux/interconnect.h>
8	#include <linux/ioctl.h>
9	#include <linux/list.h>
10	#include <linux/kernel.h>
11	#include <linux/module.h>
12	#include <linux/platform_device.h>
13	#include <linux/delay.h>
14	#include <linux/rational.h>
15	#include <linux/time64.h>
16	#include <media/videobuf2-v4l2.h>
17	#include <media/videobuf2-dma-contig.h>
18	#include <linux/videodev2.h>
19	#include "vpu.h"
20	#include "vpu_rpc.h"
21	#include "vpu_defs.h"
22	#include "vpu_helpers.h"
23	#include "vpu_v4l2.h"
24	#include "vpu_cmds.h"
25	#include "vpu_imx8q.h"
26	#include "vpu_malone.h"
27
28	#define CMD_SIZE 25600
29	#define MSG_SIZE 25600
30	#define CODEC_SIZE 0x1000
31	#define JPEG_SIZE 0x1000
32	#define SEQ_SIZE 0x1000
33	#define GOP_SIZE 0x1000
34	#define PIC_SIZE 0x1000
35	#define QMETER_SIZE 0x1000
36	#define DBGLOG_SIZE 0x10000
37	#define DEBUG_SIZE 0x80000
38	#define ENG_SIZE 0x1000
39	#define MALONE_SKIPPED_FRAME_ID 0x555
40
41	#define MALONE_ALIGN_MBI 0x800
42	#define MALONE_DCP_CHUNK_BIT 16
43	#define MALONE_DCP_SIZE_MAX 0x3000000
44	#define MALONE_DCP_SIZE_MIN 0x100000
45	#define MALONE_DCP_FIXED_MB_ALLOC 250
46
47	#define CONFIG_SET(val, cfg, pos, mask) \
48	(*(cfg) |= (((val) << (pos)) & (mask)))
49	//x means source data , y means destination data
50	#define STREAM_CONFIG_FORMAT_SET(x, y) CONFIG_SET(x, y, 0, 0x0000000F)
51	#define STREAM_CONFIG_STRBUFIDX_SET(x, y) CONFIG_SET(x, y, 8, 0x00000300)
52	#define STREAM_CONFIG_NOSEQ_SET(x, y) CONFIG_SET(x, y, 10, 0x00000400)
53	#define STREAM_CONFIG_DEBLOCK_SET(x, y) CONFIG_SET(x, y, 11, 0x00000800)
54	#define STREAM_CONFIG_DERING_SET(x, y) CONFIG_SET(x, y, 12, 0x00001000)
55	#define STREAM_CONFIG_IBWAIT_SET(x, y) CONFIG_SET(x, y, 13, 0x00002000)
56	#define STREAM_CONFIG_FBC_SET(x, y) CONFIG_SET(x, y, 14, 0x00004000)
57	#define STREAM_CONFIG_PLAY_MODE_SET(x, y) CONFIG_SET(x, y, 16, 0x00030000)
58	#define STREAM_CONFIG_ENABLE_DCP_SET(x, y) CONFIG_SET(x, y, 20, 0x00100000)
59	#define STREAM_CONFIG_NUM_STR_BUF_SET(x, y) CONFIG_SET(x, y, 21, 0x00600000)
60	#define STREAM_CONFIG_MALONE_USAGE_SET(x, y) CONFIG_SET(x, y, 23, 0x01800000)
61	#define STREAM_CONFIG_MULTI_VID_SET(x, y) CONFIG_SET(x, y, 25, 0x02000000)
62	#define STREAM_CONFIG_OBFUSC_EN_SET(x, y) CONFIG_SET(x, y, 26, 0x04000000)
63	#define STREAM_CONFIG_RC4_EN_SET(x, y) CONFIG_SET(x, y, 27, 0x08000000)
64	#define STREAM_CONFIG_MCX_SET(x, y) CONFIG_SET(x, y, 28, 0x10000000)
65	#define STREAM_CONFIG_PES_SET(x, y) CONFIG_SET(x, y, 29, 0x20000000)
66	#define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000)
67	#define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000)
68
69	#define MALONE_DEC_FMT_RV_MASK BIT(21)
70
71	enum vpu_malone_stream_input_mode {
72	INVALID_MODE = 0,
73	FRAME_LVL,
74	NON_FRAME_LVL
75	};
76
77	enum vpu_malone_format {
78	MALONE_FMT_NULL = 0x0,
79	MALONE_FMT_AVC = 0x1,
80	MALONE_FMT_MP2 = 0x2,
81	MALONE_FMT_VC1 = 0x3,
82	MALONE_FMT_AVS = 0x4,
83	MALONE_FMT_ASP = 0x5,
84	MALONE_FMT_JPG = 0x6,
85	MALONE_FMT_RV = 0x7,
86	MALONE_FMT_VP6 = 0x8,
87	MALONE_FMT_SPK = 0x9,
88	MALONE_FMT_VP8 = 0xA,
89	MALONE_FMT_HEVC = 0xB,
90	MALONE_FMT_LAST = MALONE_FMT_HEVC
91	};
92
93	enum {
94	VID_API_CMD_NULL = 0x00,
95	VID_API_CMD_PARSE_NEXT_SEQ = 0x01,
96	VID_API_CMD_PARSE_NEXT_I = 0x02,
97	VID_API_CMD_PARSE_NEXT_IP = 0x03,
98	VID_API_CMD_PARSE_NEXT_ANY = 0x04,
99	VID_API_CMD_DEC_PIC = 0x05,
100	VID_API_CMD_UPDATE_ES_WR_PTR = 0x06,
101	VID_API_CMD_UPDATE_ES_RD_PTR = 0x07,
102	VID_API_CMD_UPDATE_UDATA = 0x08,
103	VID_API_CMD_GET_FSINFO = 0x09,
104	VID_API_CMD_SKIP_PIC = 0x0a,
105	VID_API_CMD_DEC_CHUNK = 0x0b,
106	VID_API_CMD_START = 0x10,
107	VID_API_CMD_STOP = 0x11,
108	VID_API_CMD_ABORT = 0x12,
109	VID_API_CMD_RST_BUF = 0x13,
110	VID_API_CMD_FS_RELEASE = 0x15,
111	VID_API_CMD_MEM_REGION_ATTACH = 0x16,
112	VID_API_CMD_MEM_REGION_DETACH = 0x17,
113	VID_API_CMD_MVC_VIEW_SELECT = 0x18,
114	VID_API_CMD_FS_ALLOC = 0x19,
115	VID_API_CMD_DBG_GET_STATUS = 0x1C,
116	VID_API_CMD_DBG_START_LOG = 0x1D,
117	VID_API_CMD_DBG_STOP_LOG = 0x1E,
118	VID_API_CMD_DBG_DUMP_LOG = 0x1F,
119	VID_API_CMD_YUV_READY = 0x20,
120	VID_API_CMD_TS = 0x21,
121
122	VID_API_CMD_FIRM_RESET = 0x40,
123
124	VID_API_CMD_SNAPSHOT = 0xAA,
125	VID_API_CMD_ROLL_SNAPSHOT = 0xAB,
126	VID_API_CMD_LOCK_SCHEDULER = 0xAC,
127	VID_API_CMD_UNLOCK_SCHEDULER = 0xAD,
128	VID_API_CMD_CQ_FIFO_DUMP = 0xAE,
129	VID_API_CMD_DBG_FIFO_DUMP = 0xAF,
130	VID_API_CMD_SVC_ILP = 0xBB,
131	VID_API_CMD_FW_STATUS = 0xF0,
132	VID_API_CMD_INVALID = 0xFF
133	};
134
135	enum {
136	VID_API_EVENT_NULL = 0x00,
137	VID_API_EVENT_RESET_DONE = 0x01,
138	VID_API_EVENT_SEQ_HDR_FOUND = 0x02,
139	VID_API_EVENT_PIC_HDR_FOUND = 0x03,
140	VID_API_EVENT_PIC_DECODED = 0x04,
141	VID_API_EVENT_FIFO_LOW = 0x05,
142	VID_API_EVENT_FIFO_HIGH = 0x06,
143	VID_API_EVENT_FIFO_EMPTY = 0x07,
144	VID_API_EVENT_FIFO_FULL = 0x08,
145	VID_API_EVENT_BS_ERROR = 0x09,
146	VID_API_EVENT_UDATA_FIFO_UPTD = 0x0A,
147	VID_API_EVENT_RES_CHANGE = 0x0B,
148	VID_API_EVENT_FIFO_OVF = 0x0C,
149	VID_API_EVENT_CHUNK_DECODED = 0x0D,
150	VID_API_EVENT_REQ_FRAME_BUFF = 0x10,
151	VID_API_EVENT_FRAME_BUFF_RDY = 0x11,
152	VID_API_EVENT_REL_FRAME_BUFF = 0x12,
153	VID_API_EVENT_STR_BUF_RST = 0x13,
154	VID_API_EVENT_RET_PING = 0x14,
155	VID_API_EVENT_QMETER = 0x15,
156	VID_API_EVENT_STR_FMT_CHANGE = 0x16,
157	VID_API_EVENT_FIRMWARE_XCPT = 0x17,
158	VID_API_EVENT_START_DONE = 0x18,
159	VID_API_EVENT_STOPPED = 0x19,
160	VID_API_EVENT_ABORT_DONE = 0x1A,
161	VID_API_EVENT_FINISHED = 0x1B,
162	VID_API_EVENT_DBG_STAT_UPDATE = 0x1C,
163	VID_API_EVENT_DBG_LOG_STARTED = 0x1D,
164	VID_API_EVENT_DBG_LOG_STOPPED = 0x1E,
165	VID_API_EVENT_DBG_LOG_UPDATED = 0x1F,
166	VID_API_EVENT_DBG_MSG_DEC = 0x20,
167	VID_API_EVENT_DEC_SC_ERR = 0x21,
168	VID_API_EVENT_CQ_FIFO_DUMP = 0x22,
169	VID_API_EVENT_DBG_FIFO_DUMP = 0x23,
170	VID_API_EVENT_DEC_CHECK_RES = 0x24,
171	VID_API_EVENT_DEC_CFG_INFO = 0x25,
172	VID_API_EVENT_UNSUPPORTED_STREAM = 0x26,
173	VID_API_EVENT_PIC_SKIPPED = 0x27,
174	VID_API_EVENT_STR_SUSPENDED = 0x30,
175	VID_API_EVENT_SNAPSHOT_DONE = 0x40,
176	VID_API_EVENT_FW_STATUS = 0xF0,
177	VID_API_EVENT_INVALID = 0xFF
178	};
179
180	struct vpu_malone_buffer_desc {
181	struct vpu_rpc_buffer_desc buffer;
182	u32 low;
183	u32 high;
184	};
185
186	struct vpu_malone_str_buffer {
187	u32 wptr;
188	u32 rptr;
189	u32 start;
190	u32 end;
191	u32 lwm;
192	};
193
194	struct vpu_malone_picth_info {
195	u32 frame_pitch;
196	};
197
198	struct vpu_malone_table_desc {
199	u32 array_base;
200	u32 size;
201	};
202
203	struct vpu_malone_dbglog_desc {
204	u32 addr;
205	u32 size;
206	u32 level;
207	u32 reserved;
208	};
209
210	struct vpu_malone_frame_buffer {
211	u32 addr;
212	u32 size;
213	};
214
215	struct vpu_malone_udata {
216	u32 base;
217	u32 total_size;
218	u32 slot_size;
219	};
220
221	struct vpu_malone_buffer_info {
222	u32 stream_input_mode;
223	u32 stream_pic_input_count;
224	u32 stream_pic_parsed_count;
225	u32 stream_buffer_threshold;
226	u32 stream_pic_end_flag;
227	};
228
229	struct vpu_malone_encrypt_info {
230	u32 rec4key[8];
231	u32 obfusc;
232	};
233
234	struct malone_iface {
235	u32 exec_base_addr;
236	u32 exec_area_size;
237	struct vpu_malone_buffer_desc cmd_buffer_desc;
238	struct vpu_malone_buffer_desc msg_buffer_desc;
239	u32 cmd_int_enable[VID_API_NUM_STREAMS];
240	struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
241	u32 stream_config[VID_API_NUM_STREAMS];
242	struct vpu_malone_table_desc codec_param_tab_desc;
243	struct vpu_malone_table_desc jpeg_param_tab_desc;
244	u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
245	struct vpu_malone_table_desc seq_info_tab_desc;
246	struct vpu_malone_table_desc pic_info_tab_desc;
247	struct vpu_malone_table_desc gop_info_tab_desc;
248	struct vpu_malone_table_desc qmeter_info_tab_desc;
249	u32 stream_error[VID_API_NUM_STREAMS];
250	u32 fw_version;
251	u32 fw_offset;
252	u32 max_streams;
253	struct vpu_malone_dbglog_desc dbglog_desc;
254	struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
255	struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
256	struct vpu_malone_buffer_desc debug_buffer_desc;
257	struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
258	u32 encrypt_info[VID_API_NUM_STREAMS];
259	struct vpu_rpc_system_config system_cfg;
260	u32 api_version;
261	struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
262	};
263
264	struct malone_jpg_params {
265	u32 rotation_angle;
266	u32 horiz_scale_factor;
267	u32 vert_scale_factor;
268	u32 rotation_mode;
269	u32 rgb_mode;
270	u32 chunk_mode; /* 0 ~ 1 */
271	u32 last_chunk; /* 0 ~ 1 */
272	u32 chunk_rows; /* 0 ~ 255 */
273	u32 num_bytes;
274	u32 jpg_crop_x;
275	u32 jpg_crop_y;
276	u32 jpg_crop_width;
277	u32 jpg_crop_height;
278	u32 jpg_mjpeg_mode;
279	u32 jpg_mjpeg_interlaced;
280	};
281
282	struct malone_codec_params {
283	u32 disp_imm;
284	u32 fourcc;
285	u32 codec_version;
286	u32 frame_rate;
287	u32 dbglog_enable;
288	u32 bsdma_lwm;
289	u32 bbd_coring;
290	u32 bbd_s_thr_row;
291	u32 bbd_p_thr_row;
292	u32 bbd_s_thr_logo_row;
293	u32 bbd_p_thr_logo_row;
294	u32 bbd_s_thr_col;
295	u32 bbd_p_thr_col;
296	u32 bbd_chr_thr_row;
297	u32 bbd_chr_thr_col;
298	u32 bbd_uv_mid_level;
299	u32 bbd_excl_win_mb_left;
300	u32 bbd_excl_win_mb_right;
301	};
302
303	struct malone_padding_scode {
304	u32 scode_type;
305	u32 pixelformat;
306	u32 data[2];
307	};
308
309	struct malone_fmt_mapping {
310	u32 pixelformat;
311	enum vpu_malone_format malone_format;
312	u32 is_disabled;
313	};
314
315	struct malone_scode_t {
316	struct vpu_inst *inst;
317	struct vb2_buffer *vb;
318	u32 wptr;
319	u32 need_data;
320	};
321
322	struct malone_scode_handler {
323	u32 pixelformat;
324	int (*insert_scode_seq)(struct malone_scode_t *scode);
325	int (*insert_scode_pic)(struct malone_scode_t *scode);
326	};
327
328	struct vpu_dec_ctrl {
329	struct malone_codec_params *codec_param;
330	struct malone_jpg_params *jpg;
331	void *seq_mem;
332	void *pic_mem;
333	void *gop_mem;
334	void *qmeter_mem;
335	void *dbglog_mem;
336	struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS];
337	u32 buf_addr[VID_API_NUM_STREAMS];
338	};
339
340	u32 vpu_malone_get_data_size(void)
341	{
342	return sizeof(struct vpu_dec_ctrl);
343	}
344
345	void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
346	struct vpu_buffer *rpc, dma_addr_t boot_addr)
347	{
348	struct malone_iface *iface;
349	struct vpu_dec_ctrl *hc;
350	unsigned long base_phy_addr;
351	unsigned long phy_addr;
352	unsigned long offset;
353	unsigned int i;
354
355	if (rpc->phys < boot_addr)
356	return;
357
358	iface = rpc->virt;
359	base_phy_addr = rpc->phys - boot_addr;
360	hc = shared->priv;
361
362	shared->iface = iface;
363	shared->boot_addr = boot_addr;
364
365	iface->exec_base_addr = base_phy_addr;
366	iface->exec_area_size = rpc->length;
367
368	offset = sizeof(struct malone_iface);
369	phy_addr = base_phy_addr + offset;
370
371	shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
372	shared->cmd_mem_vir = rpc->virt + offset;
373	iface->cmd_buffer_desc.buffer.start =
374	iface->cmd_buffer_desc.buffer.rptr =
375	iface->cmd_buffer_desc.buffer.wptr = phy_addr;
376	iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
377	offset += CMD_SIZE;
378	phy_addr = base_phy_addr + offset;
379
380	shared->msg_desc = &iface->msg_buffer_desc.buffer;
381	shared->msg_mem_vir = rpc->virt + offset;
382	iface->msg_buffer_desc.buffer.start =
383	iface->msg_buffer_desc.buffer.wptr =
384	iface->msg_buffer_desc.buffer.rptr = phy_addr;
385	iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
386	offset += MSG_SIZE;
387	phy_addr = base_phy_addr + offset;
388
389	iface->codec_param_tab_desc.array_base = phy_addr;
390	hc->codec_param = rpc->virt + offset;
391	offset += CODEC_SIZE;
392	phy_addr = base_phy_addr + offset;
393
394	iface->jpeg_param_tab_desc.array_base = phy_addr;
395	hc->jpg = rpc->virt + offset;
396	offset += JPEG_SIZE;
397	phy_addr = base_phy_addr + offset;
398
399	iface->seq_info_tab_desc.array_base = phy_addr;
400	hc->seq_mem = rpc->virt + offset;
401	offset += SEQ_SIZE;
402	phy_addr = base_phy_addr + offset;
403
404	iface->pic_info_tab_desc.array_base = phy_addr;
405	hc->pic_mem = rpc->virt + offset;
406	offset += PIC_SIZE;
407	phy_addr = base_phy_addr + offset;
408
409	iface->gop_info_tab_desc.array_base = phy_addr;
410	hc->gop_mem = rpc->virt + offset;
411	offset += GOP_SIZE;
412	phy_addr = base_phy_addr + offset;
413
414	iface->qmeter_info_tab_desc.array_base = phy_addr;
415	hc->qmeter_mem = rpc->virt + offset;
416	offset += QMETER_SIZE;
417	phy_addr = base_phy_addr + offset;
418
419	iface->dbglog_desc.addr = phy_addr;
420	iface->dbglog_desc.size = DBGLOG_SIZE;
421	hc->dbglog_mem = rpc->virt + offset;
422	offset += DBGLOG_SIZE;
423	phy_addr = base_phy_addr + offset;
424
425	for (i = 0; i < VID_API_NUM_STREAMS; i++) {
426	iface->eng_access_buff_desc[i].buffer.start =
427	iface->eng_access_buff_desc[i].buffer.wptr =
428	iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
429	iface->eng_access_buff_desc[i].buffer.end =
430	iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
431	offset += ENG_SIZE;
432	phy_addr = base_phy_addr + offset;
433	}
434
435	for (i = 0; i < VID_API_NUM_STREAMS; i++) {
436	iface->encrypt_info[i] = phy_addr;
437	offset += sizeof(struct vpu_malone_encrypt_info);
438	phy_addr = base_phy_addr + offset;
439	}
440
441	rpc->bytesused = offset;
442	}
443
444	void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
445	struct vpu_buffer *log)
446	{
447	struct malone_iface *iface = shared->iface;
448
449	iface->debug_buffer_desc.buffer.start =
450	iface->debug_buffer_desc.buffer.wptr =
451	iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
452	iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
453	}
454
455	static u32 get_str_buffer_offset(u32 instance)
456	{
457	return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
458	}
459
460	void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
461	u32 regs_base, void __iomem *regs, u32 core_id)
462	{
463	struct malone_iface *iface = shared->iface;
464	struct vpu_rpc_system_config *config = &iface->system_cfg;
465	struct vpu_dec_ctrl *hc = shared->priv;
466	int i;
467
468	vpu_imx8q_set_system_cfg_common(config, regs: regs_base, core_id);
469	for (i = 0; i < VID_API_NUM_STREAMS; i++) {
470	u32 offset = get_str_buffer_offset(instance: i);
471
472	hc->buf_addr[i] = regs_base + offset;
473	hc->str_buf[i] = regs + offset;
474	}
475	}
476
477	u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
478	{
479	struct malone_iface *iface = shared->iface;
480
481	vpu_malone_enable_format(V4L2_PIX_FMT_RV30, enable: iface->fw_version & MALONE_DEC_FMT_RV_MASK);
482	vpu_malone_enable_format(V4L2_PIX_FMT_RV40, enable: iface->fw_version & MALONE_DEC_FMT_RV_MASK);
483
484	return iface->fw_version;
485	}
486
487	int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
488	{
489	return 0xc00000;
490	}
491
492	int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
493	u32 instance,
494	struct vpu_buffer *buf)
495	{
496	struct malone_iface *iface = shared->iface;
497	struct vpu_dec_ctrl *hc = shared->priv;
498	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
499
500	writel(val: buf->phys, addr: &str_buf->start);
501	writel(val: buf->phys, addr: &str_buf->rptr);
502	writel(val: buf->phys, addr: &str_buf->wptr);
503	writel(val: buf->phys + buf->length, addr: &str_buf->end);
504	writel(val: 0x1, addr: &str_buf->lwm);
505
506	iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
507
508	return 0;
509	}
510
511	int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
512	u32 instance,
513	struct vpu_rpc_buffer_desc *desc)
514	{
515	struct vpu_dec_ctrl *hc = shared->priv;
516	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
517
518	if (desc) {
519	desc->wptr = readl(addr: &str_buf->wptr);
520	desc->rptr = readl(addr: &str_buf->rptr);
521	desc->start = readl(addr: &str_buf->start);
522	desc->end = readl(addr: &str_buf->end);
523	}
524
525	return 0;
526	}
527
528	static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr)
529	{
530	/*update wptr after data is written*/
531	mb();
532	writel(val: wptr, addr: &str_buf->wptr);
533	}
534
535	static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr)
536	{
537	/*update rptr after data is read*/
538	mb();
539	writel(val: rptr, addr: &str_buf->rptr);
540	}
541
542	int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
543	u32 instance, u32 ptr, bool write)
544	{
545	struct vpu_dec_ctrl *hc = shared->priv;
546	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
547
548	if (write)
549	vpu_malone_update_wptr(str_buf, wptr: ptr);
550	else
551	vpu_malone_update_rptr(str_buf, rptr: ptr);
552
553	return 0;
554	}
555
556	static struct malone_fmt_mapping fmt_mappings[] = {
557	{V4L2_PIX_FMT_H264, MALONE_FMT_AVC},
558	{V4L2_PIX_FMT_H264_MVC, MALONE_FMT_AVC},
559	{V4L2_PIX_FMT_HEVC, MALONE_FMT_HEVC},
560	{V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
561	{V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
562	{V4L2_PIX_FMT_MPEG2, MALONE_FMT_MP2},
563	{V4L2_PIX_FMT_MPEG4, MALONE_FMT_ASP},
564	{V4L2_PIX_FMT_XVID, MALONE_FMT_ASP},
565	{V4L2_PIX_FMT_H263, MALONE_FMT_ASP},
566	{V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG},
567	{V4L2_PIX_FMT_VP8, MALONE_FMT_VP8},
568	{V4L2_PIX_FMT_SPK, MALONE_FMT_SPK},
569	{V4L2_PIX_FMT_RV30, MALONE_FMT_RV},
570	{V4L2_PIX_FMT_RV40, MALONE_FMT_RV},
571	};
572
573	void vpu_malone_enable_format(u32 pixelformat, int enable)
574	{
575	u32 i;
576
577	for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
578	if (pixelformat == fmt_mappings[i].pixelformat) {
579	fmt_mappings[i].is_disabled = enable ? 0 : 1;
580	return;
581	}
582	}
583	}
584
585	static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
586	{
587	u32 i;
588
589	for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
590	if (fmt_mappings[i].is_disabled)
591	continue;
592	if (pixelformat == fmt_mappings[i].pixelformat)
593	return fmt_mappings[i].malone_format;
594	}
595
596	return MALONE_FMT_NULL;
597	}
598
599	bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt)
600	{
601	if (!vpu_imx8q_check_fmt(type, pixelfmt))
602	return false;
603
604	if (pixelfmt == V4L2_PIX_FMT_NV12_8L128 || pixelfmt == V4L2_PIX_FMT_NV12_10BE_8L128 ||
605	pixelfmt == V4L2_PIX_FMT_NV12M_8L128 || pixelfmt == V4L2_PIX_FMT_NV12M_10BE_8L128)
606	return true;
607	if (vpu_malone_format_remap(pixelformat: pixelfmt) == MALONE_FMT_NULL)
608	return false;
609
610	return true;
611	}
612
613	static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
614	u32 instance,
615	enum vpu_malone_format malone_format)
616	{
617	struct malone_iface *iface = shared->iface;
618	u32 *curr_str_cfg = &iface->stream_config[instance];
619
620	*curr_str_cfg = 0;
621	STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
622	STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
623	STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
624	STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
625	STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
626	STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
627	STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
628	STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
629	STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
630	STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
631	STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
632	STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
633	STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
634	STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
635	STREAM_CONFIG_PES_SET(0, curr_str_cfg);
636	STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
637	}
638
639	static int vpu_malone_set_params(struct vpu_shared_addr *shared,
640	u32 instance,
641	struct vpu_decode_params *params)
642	{
643	struct malone_iface *iface = shared->iface;
644	struct vpu_dec_ctrl *hc = shared->priv;
645	enum vpu_malone_format malone_format;
646
647	malone_format = vpu_malone_format_remap(pixelformat: params->codec_format);
648	if (WARN_ON(malone_format == MALONE_FMT_NULL))
649	return -EINVAL;
650	iface->udata_buffer[instance].base = params->udata.base;
651	iface->udata_buffer[instance].slot_size = params->udata.size;
652
653	vpu_malone_set_stream_cfg(shared, instance, malone_format);
654
655	if (malone_format == MALONE_FMT_JPG) {
656	//1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B
657	hc->jpg[instance].jpg_mjpeg_mode = 1;
658	//0: JPGD_MJPEG_PROGRESSIVE
659	hc->jpg[instance].jpg_mjpeg_interlaced = 0;
660	}
661
662	hc->codec_param[instance].disp_imm = params->display_delay_enable ? 1 : 0;
663	if (malone_format != MALONE_FMT_AVC)
664	hc->codec_param[instance].disp_imm = 0;
665	hc->codec_param[instance].dbglog_enable = 0;
666	iface->dbglog_desc.level = 0;
667
668	if (params->b_non_frame)
669	iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
670	else
671	iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
672	iface->stream_buff_info[instance].stream_buffer_threshold = 0;
673	iface->stream_buff_info[instance].stream_pic_input_count = 0;
674
675	return 0;
676	}
677
678	static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance)
679	{
680	struct malone_iface *iface = shared->iface;
681
682	if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
683	return true;
684
685	return false;
686	}
687
688	static int vpu_malone_update_params(struct vpu_shared_addr *shared,
689	u32 instance,
690	struct vpu_decode_params *params)
691	{
692	struct malone_iface *iface = shared->iface;
693
694	if (params->end_flag)
695	iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
696	params->end_flag = 0;
697
698	return 0;
699	}
700
701	int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
702	u32 instance,
703	struct vpu_decode_params *params,
704	u32 update)
705	{
706	if (!params)
707	return -EINVAL;
708
709	if (!update)
710	return vpu_malone_set_params(shared, instance, params);
711	else
712	return vpu_malone_update_params(shared, instance, params);
713	}
714
715	static struct vpu_pair malone_cmds[] = {
716	{VPU_CMD_ID_NOOP, VID_API_CMD_NULL},
717	{VPU_CMD_ID_START, VID_API_CMD_START},
718	{VPU_CMD_ID_STOP, VID_API_CMD_STOP},
719	{VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
720	{VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
721	{VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
722	{VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
723	{VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
724	{VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
725	{VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
726	{VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
727	};
728
729	static struct vpu_pair malone_msgs[] = {
730	{VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
731	{VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
732	{VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
733	{VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
734	{VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
735	{VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
736	{VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
737	{VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
738	{VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
739	{VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
740	{VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
741	{VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
742	{VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
743	{VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
744	{VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
745	{VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
746	{VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
747	{VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED},
748	{VPU_MSG_ID_DBG_MSG, VID_API_EVENT_DBG_MSG_DEC},
749	};
750
751	static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
752	struct vpu_fs_info *fs)
753	{
754	const u32 fs_type[] = {
755	[MEM_RES_FRAME] = 0,
756	[MEM_RES_MBI] = 1,
757	[MEM_RES_DCP] = 2,
758	};
759
760	pkt->hdr.num = 7;
761	pkt->data[0] = fs->id | (fs->tag << 24);
762	pkt->data[1] = fs->luma_addr;
763	if (fs->type == MEM_RES_FRAME) {
764	/*
765	* if luma_addr equal to chroma_addr,
766	* means luma(plane[0]) and chromau(plane[1]) used the
767	* same fd -- usage of NXP codec2. Need to manually
768	* offset chroma addr.
769	*/
770	if (fs->luma_addr == fs->chroma_addr)
771	fs->chroma_addr = fs->luma_addr + fs->luma_size;
772	pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
773	pkt->data[3] = fs->chroma_addr;
774	pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
775	pkt->data[5] = fs->bytesperline;
776	} else {
777	pkt->data[2] = fs->luma_size;
778	pkt->data[3] = 0;
779	pkt->data[4] = 0;
780	pkt->data[5] = 0;
781	}
782	pkt->data[6] = fs_type[fs->type];
783	}
784
785	static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
786	struct vpu_fs_info *fs)
787	{
788	pkt->hdr.num = 1;
789	pkt->data[0] = fs->id | (fs->tag << 24);
790	}
791
792	static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
793	struct vpu_ts_info *info)
794	{
795	struct timespec64 ts = ns_to_timespec64(nsec: info->timestamp);
796
797	pkt->hdr.num = 3;
798
799	pkt->data[0] = ts.tv_sec;
800	pkt->data[1] = ts.tv_nsec;
801	pkt->data[2] = info->size;
802	}
803
804	int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
805	{
806	int ret;
807
808	ret = vpu_find_dst_by_src(pairs: malone_cmds, ARRAY_SIZE(malone_cmds), src: id);
809	if (ret < 0)
810	return ret;
811
812	pkt->hdr.id = ret;
813	pkt->hdr.num = 0;
814	pkt->hdr.index = index;
815
816	switch (id) {
817	case VPU_CMD_ID_FS_ALLOC:
818	vpu_malone_pack_fs_alloc(pkt, fs: data);
819	break;
820	case VPU_CMD_ID_FS_RELEASE:
821	vpu_malone_pack_fs_release(pkt, fs: data);
822	break;
823	case VPU_CMD_ID_TIMESTAMP:
824	vpu_malone_pack_timestamp(pkt, info: data);
825	break;
826	}
827
828	pkt->hdr.index = index;
829	return 0;
830	}
831
832	int vpu_malone_convert_msg_id(u32 id)
833	{
834	return vpu_find_src_by_dst(pairs: malone_msgs, ARRAY_SIZE(malone_msgs), dst: id);
835	}
836
837	static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info)
838	{
839	u32 interlaced = info->progressive ? 0 : 1;
840
841	info->bytesperline[0] = 0;
842	info->sizeimage[0] = vpu_helper_get_plane_size(fmt: info->pixfmt,
843	width: info->decoded_width,
844	height: info->decoded_height,
845	plane_no: 0,
846	stride: info->stride,
847	interlaced,
848	pbl: &info->bytesperline[0]);
849	info->bytesperline[1] = 0;
850	info->sizeimage[1] = vpu_helper_get_plane_size(fmt: info->pixfmt,
851	width: info->decoded_width,
852	height: info->decoded_height,
853	plane_no: 1,
854	stride: info->stride,
855	interlaced,
856	pbl: &info->bytesperline[1]);
857	}
858
859	static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
860	{
861	u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
862
863	vpu_malone_fill_planes(info);
864
865	info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
866	info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
867
868	info->dcp_size = MALONE_DCP_SIZE_MAX;
869	if (chunks) {
870	u32 mb_num;
871	u32 mb_w;
872	u32 mb_h;
873
874	mb_w = DIV_ROUND_UP(info->decoded_width, 16);
875	mb_h = DIV_ROUND_UP(info->decoded_height, 16);
876	mb_num = mb_w * mb_h;
877	info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
878	info->dcp_size = clamp_t(u32, info->dcp_size,
879	MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
880	}
881	}
882
883	static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
884	struct vpu_dec_codec_info *info)
885	{
886	info->num_ref_frms = pkt->data[0];
887	info->num_dpb_frms = pkt->data[1];
888	info->num_dfe_area = pkt->data[2];
889	info->progressive = pkt->data[3];
890	info->width = pkt->data[5];
891	info->height = pkt->data[4];
892	info->decoded_width = pkt->data[12];
893	info->decoded_height = pkt->data[11];
894	info->frame_rate.numerator = 1000;
895	info->frame_rate.denominator = pkt->data[8];
896	info->dsp_asp_ratio = pkt->data[9];
897	info->level_idc = pkt->data[10];
898	info->bit_depth_luma = pkt->data[13];
899	info->bit_depth_chroma = pkt->data[14];
900	info->chroma_fmt = pkt->data[15];
901	info->color_primaries = vpu_color_cvrt_primaries_i2v(primaries: pkt->data[16]);
902	info->transfer_chars = vpu_color_cvrt_transfers_i2v(transfers: pkt->data[17]);
903	info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(matrix: pkt->data[18]);
904	info->full_range = vpu_color_cvrt_full_range_i2v(full_range: pkt->data[19]);
905	info->vui_present = pkt->data[20];
906	info->mvc_num_views = pkt->data[21];
907	info->offset_x = pkt->data[23];
908	info->offset_y = pkt->data[25];
909	info->tag = pkt->data[27];
910	if (info->bit_depth_luma > 8)
911	info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128;
912	else
913	info->pixfmt = V4L2_PIX_FMT_NV12M_8L128;
914	if (info->frame_rate.numerator && info->frame_rate.denominator) {
915	unsigned long n, d;
916
917	rational_best_approximation(given_numerator: info->frame_rate.numerator,
918	given_denominator: info->frame_rate.denominator,
919	max_numerator: info->frame_rate.numerator,
920	max_denominator: info->frame_rate.denominator,
921	best_numerator: &n, best_denominator: &d);
922	info->frame_rate.numerator = n;
923	info->frame_rate.denominator = d;
924	}
925	vpu_malone_init_seq_hdr(info);
926	}
927
928	static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
929	struct vpu_dec_pic_info *info)
930	{
931	info->id = pkt->data[7];
932	info->luma = pkt->data[0];
933	info->start = pkt->data[10];
934	info->end = pkt->data[12];
935	info->pic_size = pkt->data[11];
936	info->stride = pkt->data[5];
937	info->consumed_count = pkt->data[13];
938	if (info->id == MALONE_SKIPPED_FRAME_ID)
939	info->skipped = 1;
940	else
941	info->skipped = 0;
942	}
943
944	static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
945	struct vpu_fs_info *info)
946	{
947	info->type = pkt->data[1];
948	}
949
950	static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
951	struct vpu_fs_info *info)
952	{
953	info->id = pkt->data[0];
954	info->type = pkt->data[1];
955	info->not_displayed = pkt->data[2];
956	}
957
958	static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
959	struct vpu_dec_pic_info *info)
960	{
961	struct timespec64 ts = { pkt->data[9], pkt->data[10] };
962
963	info->id = pkt->data[0];
964	info->luma = pkt->data[1];
965	info->stride = pkt->data[3];
966	if (info->id == MALONE_SKIPPED_FRAME_ID)
967	info->skipped = 1;
968	else
969	info->skipped = 0;
970
971	info->timestamp = timespec64_to_ns(ts: &ts);
972	}
973
974	int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
975	{
976	if (!pkt || !data)
977	return -EINVAL;
978
979	switch (pkt->hdr.id) {
980	case VID_API_EVENT_SEQ_HDR_FOUND:
981	vpu_malone_unpack_seq_hdr(pkt, info: data);
982	break;
983	case VID_API_EVENT_PIC_DECODED:
984	vpu_malone_unpack_pic_info(pkt, info: data);
985	break;
986	case VID_API_EVENT_REQ_FRAME_BUFF:
987	vpu_malone_unpack_req_frame(pkt, info: data);
988	break;
989	case VID_API_EVENT_REL_FRAME_BUFF:
990	vpu_malone_unpack_rel_frame(pkt, info: data);
991	break;
992	case VID_API_EVENT_FRAME_BUFF_RDY:
993	vpu_malone_unpack_buff_rdy(pkt, info: data);
994	break;
995	}
996
997	return 0;
998	}
999
1000	static const struct malone_padding_scode padding_scodes[] = {
1001	{SCODE_PADDING_EOS, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
1002	{SCODE_PADDING_EOS, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
1003	{SCODE_PADDING_EOS, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
1004	{SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
1005	{SCODE_PADDING_EOS, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
1006	{SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG2, {0xCC010000, 0x0}},
1007	{SCODE_PADDING_EOS, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
1008	{SCODE_PADDING_EOS, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
1009	{SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
1010	{SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
1011	{SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}},
1012	{SCODE_PADDING_EOS, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}},
1013	{SCODE_PADDING_EOS, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}},
1014	{SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}},
1015	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}},
1016	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}},
1017	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_HEVC, {0x4A010000, 0x20}},
1018	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
1019	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
1020	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG2, {0xb7010000, 0x0}},
1021	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_MPEG4, {0xb1010000, 0x0}},
1022	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_XVID, {0xb1010000, 0x0}},
1023	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}},
1024	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}},
1025	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}},
1026	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}},
1027	{SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}},
1028	{SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}},
1029	{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}},
1030	{SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}},
1031	};
1032
1033	static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
1034
1035	static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
1036	{
1037	const struct malone_padding_scode *s;
1038	int i;
1039
1040	for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
1041	s = &padding_scodes[i];
1042
1043	if (s->scode_type == type && s->pixelformat == fmt)
1044	return s;
1045	}
1046
1047	if (type != SCODE_PADDING_BUFFLUSH)
1048	return &padding_scode_dft;
1049
1050	return NULL;
1051	}
1052
1053	static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
1054	struct vpu_malone_str_buffer __iomem *str_buf,
1055	u32 pixelformat, u32 scode_type)
1056	{
1057	u32 wptr;
1058	int size;
1059	int total_size = 0;
1060	const struct malone_padding_scode *ps;
1061	const u32 padding_size = 4096;
1062	int ret;
1063
1064	ps = get_padding_scode(type: scode_type, fmt: pixelformat);
1065	if (!ps)
1066	return -EINVAL;
1067
1068	wptr = readl(addr: &str_buf->wptr);
1069	if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length)
1070	return -EINVAL;
1071	if (wptr == stream_buffer->phys + stream_buffer->length)
1072	wptr = stream_buffer->phys;
1073	size = ALIGN(wptr, 4) - wptr;
1074	if (size)
1075	vpu_helper_memset_stream_buffer(stream_buffer, wptr: &wptr, val: 0, size);
1076	total_size += size;
1077
1078	size = sizeof(ps->data);
1079	ret = vpu_helper_copy_to_stream_buffer(stream_buffer, wptr: &wptr, size, src: (void *)ps->data);
1080	if (ret < 0)
1081	return -EINVAL;
1082	total_size += size;
1083
1084	size = padding_size - sizeof(ps->data);
1085	vpu_helper_memset_stream_buffer(stream_buffer, wptr: &wptr, val: 0, size);
1086	total_size += size;
1087
1088	vpu_malone_update_wptr(str_buf, wptr);
1089	return total_size;
1090	}
1091
1092	int vpu_malone_add_scode(struct vpu_shared_addr *shared,
1093	u32 instance,
1094	struct vpu_buffer *stream_buffer,
1095	u32 pixelformat,
1096	u32 scode_type)
1097	{
1098	struct vpu_dec_ctrl *hc = shared->priv;
1099	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
1100	int ret = -EINVAL;
1101
1102	switch (scode_type) {
1103	case SCODE_PADDING_EOS:
1104	case SCODE_PADDING_ABORT:
1105	case SCODE_PADDING_BUFFLUSH:
1106	ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type);
1107	break;
1108	default:
1109	break;
1110	}
1111
1112	return ret;
1113	}
1114
1115	#define MALONE_PAYLOAD_HEADER_SIZE 16
1116	#define MALONE_CODEC_VERSION_ID 0x1
1117	#define MALONE_CODEC_ID_VC1_SIMPLE 0x10
1118	#define MALONE_CODEC_ID_VC1_MAIN 0x11
1119	#define MALONE_CODEC_ID_ARV8 0x28
1120	#define MALONE_CODEC_ID_ARV9 0x29
1121	#define MALONE_CODEC_ID_VP6 0x36
1122	#define MALONE_CODEC_ID_VP8 0x36
1123	#define MALONE_CODEC_ID_DIVX3 0x38
1124	#define MALONE_CODEC_ID_SPK 0x39
1125
1126	#define MALONE_VP8_IVF_SEQ_HEADER_LEN 32
1127	#define MALONE_VP8_IVF_FRAME_HEADER_LEN 8
1128
1129	#define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85
1130	#define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5
1131	#define MALONE_VC1_RCV_NUM_FRAMES 0xFF
1132	#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4
1133	#define MALONE_VC1_RCV_SEQ_HEADER_LEN 20
1134	#define MALONE_VC1_RCV_PIC_HEADER_LEN 4
1135	#define MALONE_VC1_NAL_HEADER_LEN 4
1136	#define MALONE_VC1_CONTAIN_NAL(data) (((data) & 0x00FFFFFF) == 0x00010000)
1137
1138	static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
1139	u32 buffer_size, u32 width, u32 height)
1140	{
1141	unsigned int payload_size;
1142	/* payload_size = buffer_size + itself_size(16) - start_code(4) */
1143	payload_size = buffer_size + 12;
1144
1145	dst[0] = 0x00;
1146	dst[1] = 0x00;
1147	dst[2] = 0x01;
1148	dst[3] = scd_type;
1149
1150	/* length */
1151	dst[4] = ((payload_size >> 16) & 0xff);
1152	dst[5] = ((payload_size >> 8) & 0xff);
1153	dst[6] = 0x4e;
1154	dst[7] = ((payload_size >> 0) & 0xff);
1155
1156	/* Codec ID and Version */
1157	dst[8] = codec_id;
1158	dst[9] = MALONE_CODEC_VERSION_ID;
1159
1160	/* width */
1161	dst[10] = ((width >> 8) & 0xff);
1162	dst[11] = ((width >> 0) & 0xff);
1163	dst[12] = 0x58;
1164
1165	/* height */
1166	dst[13] = ((height >> 8) & 0xff);
1167	dst[14] = ((height >> 0) & 0xff);
1168	dst[15] = 0x50;
1169	}
1170
1171	static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
1172	{
1173	/* 0-3byte signature "DKIF" */
1174	dst[0] = 0x44;
1175	dst[1] = 0x4b;
1176	dst[2] = 0x49;
1177	dst[3] = 0x46;
1178	/* 4-5byte version: should be 0*/
1179	dst[4] = 0x00;
1180	dst[5] = 0x00;
1181	/* 6-7 length of Header */
1182	dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
1183	dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
1184	/* 8-11 VP8 fourcc */
1185	dst[8] = 0x56;
1186	dst[9] = 0x50;
1187	dst[10] = 0x38;
1188	dst[11] = 0x30;
1189	/* 12-13 width in pixels */
1190	dst[12] = width;
1191	dst[13] = width >> 8;
1192	/* 14-15 height in pixels */
1193	dst[14] = height;
1194	dst[15] = height >> 8;
1195	/* 16-19 frame rate */
1196	dst[16] = 0xe8;
1197	dst[17] = 0x03;
1198	dst[18] = 0x00;
1199	dst[19] = 0x00;
1200	/* 20-23 time scale */
1201	dst[20] = 0x01;
1202	dst[21] = 0x00;
1203	dst[22] = 0x00;
1204	dst[23] = 0x00;
1205	/* 24-27 number frames */
1206	dst[24] = 0xdf;
1207	dst[25] = 0xf9;
1208	dst[26] = 0x09;
1209	dst[27] = 0x00;
1210	/* 28-31 reserved */
1211	}
1212
1213	static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
1214	{
1215	/*
1216	* firmware just parse 64-bit timestamp(8 bytes).
1217	* As not transfer timestamp to firmware, use default value(ZERO).
1218	* No need to do anything here
1219	*/
1220	}
1221
1222	static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
1223	{
1224	u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
1225	u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
1226
1227	/* 0-2 Number of frames, used default value 0xFF */
1228	dst[0] = frames;
1229	dst[1] = frames >> 8;
1230	dst[2] = frames >> 16;
1231
1232	/* 3 RCV version, used V1 */
1233	dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
1234
1235	/* 4-7 extension data size */
1236	dst[4] = ext_data_size;
1237	dst[5] = ext_data_size >> 8;
1238	dst[6] = ext_data_size >> 16;
1239	dst[7] = ext_data_size >> 24;
1240	/* 8-11 extension data */
1241	dst[8] = src[0];
1242	dst[9] = src[1];
1243	dst[10] = src[2];
1244	dst[11] = src[3];
1245
1246	/* height */
1247	dst[12] = height;
1248	dst[13] = (height >> 8) & 0xff;
1249	dst[14] = (height >> 16) & 0xff;
1250	dst[15] = (height >> 24) & 0xff;
1251	/* width */
1252	dst[16] = width;
1253	dst[17] = (width >> 8) & 0xff;
1254	dst[18] = (width >> 16) & 0xff;
1255	dst[19] = (width >> 24) & 0xff;
1256	}
1257
1258	static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
1259	{
1260	dst[0] = buffer_size;
1261	dst[1] = buffer_size >> 8;
1262	dst[2] = buffer_size >> 16;
1263	dst[3] = buffer_size >> 24;
1264	}
1265
1266	static void create_vc1_nal_pichdr(u8 *dst)
1267	{
1268	/* need insert nal header: special ID */
1269	dst[0] = 0x0;
1270	dst[1] = 0x0;
1271	dst[2] = 0x01;
1272	dst[3] = 0x0D;
1273	}
1274
1275	static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1276	{
1277	u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1278	int ret;
1279
1280	set_payload_hdr(dst: hdr,
1281	scd_type: SCODE_SEQUENCE,
1282	codec_id,
1283	buffer_size: ext_size,
1284	width: scode->inst->out_format.width,
1285	height: scode->inst->out_format.height);
1286	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1287	wptr: &scode->wptr,
1288	size: sizeof(hdr),
1289	src: hdr);
1290	if (ret < 0)
1291	return ret;
1292	return sizeof(hdr);
1293	}
1294
1295	static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1296	{
1297	u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1298	int ret;
1299
1300	set_payload_hdr(dst: hdr,
1301	scd_type: SCODE_PICTURE,
1302	codec_id,
1303	buffer_size: ext_size + vb2_get_plane_payload(vb: scode->vb, plane_no: 0),
1304	width: scode->inst->out_format.width,
1305	height: scode->inst->out_format.height);
1306	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1307	wptr: &scode->wptr,
1308	size: sizeof(hdr),
1309	src: hdr);
1310	if (ret < 0)
1311	return ret;
1312	return sizeof(hdr);
1313	}
1314
1315	static int vpu_malone_insert_scode_vc1_g_seq(struct malone_scode_t *scode)
1316	{
1317	if (!scode->inst->total_input_count)
1318	return 0;
1319	if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb)))
1320	scode->need_data = 0;
1321	return 0;
1322	}
1323
1324	static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
1325	{
1326	struct vb2_v4l2_buffer *vbuf;
1327	u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
1328	u32 *data = NULL;
1329	int ret;
1330
1331	vbuf = to_vb2_v4l2_buffer(scode->vb);
1332	data = vb2_plane_vaddr(vb: scode->vb, plane_no: 0);
1333
1334	if (scode->inst->total_input_count == 0 || vpu_vb_is_codecconfig(vbuf))
1335	return 0;
1336	if (MALONE_VC1_CONTAIN_NAL(*data))
1337	return 0;
1338
1339	create_vc1_nal_pichdr(dst: nal_hdr);
1340	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1341	wptr: &scode->wptr,
1342	size: sizeof(nal_hdr),
1343	src: nal_hdr);
1344	if (ret < 0)
1345	return ret;
1346	return sizeof(nal_hdr);
1347	}
1348
1349	static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
1350	{
1351	int ret;
1352	int size = 0;
1353	u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
1354
1355	if (vpu_vb_is_codecconfig(to_vb2_v4l2_buffer(scode->vb)))
1356	scode->need_data = 0;
1357	if (scode->inst->total_input_count)
1358	return 0;
1359	scode->need_data = 0;
1360
1361	ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, ext_size: sizeof(rcv_seqhdr));
1362	if (ret < 0)
1363	return ret;
1364	size = ret;
1365
1366	set_vc1_rcv_seqhdr(dst: rcv_seqhdr,
1367	src: vb2_plane_vaddr(vb: scode->vb, plane_no: 0),
1368	width: scode->inst->out_format.width,
1369	height: scode->inst->out_format.height);
1370	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1371	wptr: &scode->wptr,
1372	size: sizeof(rcv_seqhdr),
1373	src: rcv_seqhdr);
1374
1375	if (ret < 0)
1376	return ret;
1377	size += sizeof(rcv_seqhdr);
1378	return size;
1379	}
1380
1381	static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
1382	{
1383	int ret;
1384	int size = 0;
1385	u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
1386
1387	ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
1388	ext_size: sizeof(rcv_pichdr));
1389	if (ret < 0)
1390	return ret;
1391	size = ret;
1392
1393	set_vc1_rcv_pichdr(dst: rcv_pichdr, buffer_size: vb2_get_plane_payload(vb: scode->vb, plane_no: 0));
1394	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1395	wptr: &scode->wptr,
1396	size: sizeof(rcv_pichdr),
1397	src: rcv_pichdr);
1398	if (ret < 0)
1399	return ret;
1400	size += sizeof(rcv_pichdr);
1401	return size;
1402	}
1403
1404	static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
1405	{
1406	int ret;
1407	int size = 0;
1408	u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
1409
1410	ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, ext_size: sizeof(ivf_hdr));
1411	if (ret < 0)
1412	return ret;
1413	size = ret;
1414
1415	set_vp8_ivf_seqhdr(dst: ivf_hdr,
1416	width: scode->inst->out_format.width,
1417	height: scode->inst->out_format.height);
1418	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1419	wptr: &scode->wptr,
1420	size: sizeof(ivf_hdr),
1421	src: ivf_hdr);
1422	if (ret < 0)
1423	return ret;
1424	size += sizeof(ivf_hdr);
1425
1426	return size;
1427	}
1428
1429	static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
1430	{
1431	int ret;
1432	int size = 0;
1433	u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
1434
1435	ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, ext_size: sizeof(ivf_hdr));
1436	if (ret < 0)
1437	return ret;
1438	size = ret;
1439
1440	set_vp8_ivf_pichdr(dst: ivf_hdr, frame_size: vb2_get_plane_payload(vb: scode->vb, plane_no: 0));
1441	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &scode->inst->stream_buffer,
1442	wptr: &scode->wptr,
1443	size: sizeof(ivf_hdr),
1444	src: ivf_hdr);
1445	if (ret < 0)
1446	return ret;
1447	size += sizeof(ivf_hdr);
1448
1449	return size;
1450	}
1451
1452	static int vpu_malone_insert_scode_spk_seq(struct malone_scode_t *scode)
1453	{
1454	return vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_SPK, ext_size: 0);
1455	}
1456
1457	static int vpu_malone_insert_scode_spk_pic(struct malone_scode_t *scode)
1458	{
1459	return vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_SPK, ext_size: 0);
1460	}
1461
1462	static const struct malone_scode_handler scode_handlers[] = {
1463	{
1464	/* fix me, need to swap return operation after gstreamer swap */
1465	.pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
1466	.insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
1467	.insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
1468	},
1469	{
1470	.pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
1471	.insert_scode_seq = vpu_malone_insert_scode_vc1_g_seq,
1472	.insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
1473	},
1474	{
1475	.pixelformat = V4L2_PIX_FMT_VP8,
1476	.insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
1477	.insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
1478	},
1479	{
1480	.pixelformat = V4L2_PIX_FMT_SPK,
1481	.insert_scode_seq = vpu_malone_insert_scode_spk_seq,
1482	.insert_scode_pic = vpu_malone_insert_scode_spk_pic,
1483	},
1484	};
1485
1486	static const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
1487	{
1488	int i;
1489
1490	for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
1491	if (scode_handlers[i].pixelformat == pixelformat)
1492	return &scode_handlers[i];
1493	}
1494
1495	return NULL;
1496	}
1497
1498	static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
1499	{
1500	const struct malone_scode_handler *handler;
1501	int ret = 0;
1502
1503	if (!scode || !scode->inst || !scode->vb)
1504	return 0;
1505
1506	scode->need_data = 1;
1507	handler = get_scode_handler(pixelformat: scode->inst->out_format.pixfmt);
1508	if (!handler)
1509	return 0;
1510
1511	switch (type) {
1512	case SCODE_SEQUENCE:
1513	if (handler->insert_scode_seq)
1514	ret = handler->insert_scode_seq(scode);
1515	break;
1516	case SCODE_PICTURE:
1517	if (handler->insert_scode_pic)
1518	ret = handler->insert_scode_pic(scode);
1519	break;
1520	default:
1521	break;
1522	}
1523
1524	return ret;
1525	}
1526
1527	static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf,
1528	struct vpu_inst *inst, struct vb2_buffer *vb,
1529	u32 disp_imm)
1530	{
1531	struct malone_scode_t scode;
1532	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1533	u32 wptr = readl(addr: &str_buf->wptr);
1534	int size = 0;
1535	int ret = 0;
1536
1537	/*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/
1538	scode.inst = inst;
1539	scode.vb = vb;
1540	scode.wptr = wptr;
1541	scode.need_data = 1;
1542	if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
1543	ret = vpu_malone_insert_scode(scode: &scode, type: SCODE_SEQUENCE);
1544
1545	if (ret < 0)
1546	return -ENOMEM;
1547	size += ret;
1548	wptr = scode.wptr;
1549	if (!scode.need_data) {
1550	vpu_malone_update_wptr(str_buf, wptr);
1551	return size;
1552	}
1553
1554	ret = vpu_malone_insert_scode(scode: &scode, type: SCODE_PICTURE);
1555	if (ret < 0)
1556	return -ENOMEM;
1557	size += ret;
1558	wptr = scode.wptr;
1559
1560	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &inst->stream_buffer,
1561	wptr: &wptr,
1562	size: vb2_get_plane_payload(vb, plane_no: 0),
1563	src: vb2_plane_vaddr(vb, plane_no: 0));
1564	if (ret < 0)
1565	return -ENOMEM;
1566	size += vb2_get_plane_payload(vb, plane_no: 0);
1567
1568	vpu_malone_update_wptr(str_buf, wptr);
1569
1570	if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) {
1571	ret = vpu_malone_add_scode(shared: inst->core->iface,
1572	instance: inst->id,
1573	stream_buffer: &inst->stream_buffer,
1574	pixelformat: inst->out_format.pixfmt,
1575	scode_type: SCODE_PADDING_BUFFLUSH);
1576	if (ret < 0)
1577	return ret;
1578	size += ret;
1579	}
1580
1581	return size;
1582	}
1583
1584	static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf,
1585	struct vpu_inst *inst, struct vb2_buffer *vb)
1586	{
1587	u32 wptr = readl(addr: &str_buf->wptr);
1588	int ret = 0;
1589
1590	ret = vpu_helper_copy_to_stream_buffer(stream_buffer: &inst->stream_buffer,
1591	wptr: &wptr,
1592	size: vb2_get_plane_payload(vb, plane_no: 0),
1593	src: vb2_plane_vaddr(vb, plane_no: 0));
1594	if (ret < 0)
1595	return -ENOMEM;
1596
1597	vpu_malone_update_wptr(str_buf, wptr);
1598
1599	return ret;
1600	}
1601
1602	static int vpu_malone_input_ts(struct vpu_inst *inst, s64 timestamp, u32 size)
1603	{
1604	struct vpu_ts_info info;
1605
1606	memset(&info, 0, sizeof(info));
1607	info.timestamp = timestamp;
1608	info.size = size;
1609
1610	return vpu_session_fill_timestamp(inst, info: &info);
1611	}
1612
1613	int vpu_malone_input_frame(struct vpu_shared_addr *shared,
1614	struct vpu_inst *inst, struct vb2_buffer *vb)
1615	{
1616	struct vpu_dec_ctrl *hc = shared->priv;
1617	struct vb2_v4l2_buffer *vbuf;
1618	struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
1619	u32 disp_imm = hc->codec_param[inst->id].disp_imm;
1620	u32 size;
1621	int ret;
1622
1623	if (vpu_malone_is_non_frame_mode(shared, instance: inst->id))
1624	ret = vpu_malone_input_stream_data(str_buf, inst, vb);
1625	else
1626	ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
1627	if (ret < 0)
1628	return ret;
1629	size = ret;
1630
1631	/*
1632	* if buffer only contain codec data, and the timestamp is invalid,
1633	* don't put the invalid timestamp to resync
1634	* merge the data to next frame
1635	*/
1636	vbuf = to_vb2_v4l2_buffer(vb);
1637	if (vpu_vb_is_codecconfig(vbuf)) {
1638	inst->extra_size += size;
1639	return 0;
1640	}
1641	if (inst->extra_size) {
1642	size += inst->extra_size;
1643	inst->extra_size = 0;
1644	}
1645
1646	ret = vpu_malone_input_ts(inst, timestamp: vb->timestamp, size);
1647	if (ret)
1648	return ret;
1649
1650	return 0;
1651	}
1652
1653	static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
1654	{
1655	struct malone_iface *iface = shared->iface;
1656	struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1657	u32 size = desc->end - desc->start;
1658	u32 rptr = desc->rptr;
1659	u32 wptr = desc->wptr;
1660	u32 used;
1661
1662	if (!size)
1663	return true;
1664
1665	used = (wptr + size - rptr) % size;
1666	if (used < (size / 2))
1667	return true;
1668
1669	return false;
1670	}
1671
1672	bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
1673	{
1674	u32 cnt = 0;
1675
1676	while (!vpu_malone_check_ready(shared, instance)) {
1677	if (cnt > 30)
1678	return false;
1679	mdelay(1);
1680	cnt++;
1681	}
1682	return true;
1683	}
1684
1685	int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
1686	{
1687	if (!vpu_malone_is_ready(shared, instance))
1688	return -EINVAL;
1689
1690	return 0;
1691	}
1692
1693	int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
1694	{
1695	struct malone_iface *iface = shared->iface;
1696	struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1697
1698	desc->wptr++;
1699	if (desc->wptr == desc->end)
1700	desc->wptr = desc->start;
1701
1702	return 0;
1703	}
1704
1705	int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
1706	{
1707	struct malone_iface *iface = shared->iface;
1708	struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1709
1710	desc->wptr = desc->rptr;
1711	if (desc->wptr == desc->end)
1712	desc->wptr = desc->start;
1713
1714	return 0;
1715	}
1716
1717	u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
1718	{
1719	struct malone_iface *iface = shared->iface;
1720
1721	return iface->max_streams;
1722	}
1723