1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	*
4	* Copyright (C) 2005 Mike Isely <isely@pobox.com>
5	*/
6
7	#include <linux/errno.h>
8	#include <linux/string.h>
9	#include <linux/slab.h>
10	#include <linux/module.h>
11	#include <linux/firmware.h>
12	#include <linux/videodev2.h>
13	#include <media/v4l2-common.h>
14	#include <media/tuner.h>
15	#include "pvrusb2.h"
16	#include "pvrusb2-std.h"
17	#include "pvrusb2-util.h"
18	#include "pvrusb2-hdw.h"
19	#include "pvrusb2-i2c-core.h"
20	#include "pvrusb2-eeprom.h"
21	#include "pvrusb2-hdw-internal.h"
22	#include "pvrusb2-encoder.h"
23	#include "pvrusb2-debug.h"
24	#include "pvrusb2-fx2-cmd.h"
25	#include "pvrusb2-wm8775.h"
26	#include "pvrusb2-video-v4l.h"
27	#include "pvrusb2-cx2584x-v4l.h"
28	#include "pvrusb2-cs53l32a.h"
29	#include "pvrusb2-audio.h"
30
31	#define TV_MIN_FREQ 55250000L
32	#define TV_MAX_FREQ 850000000L
33
34	/* This defines a minimum interval that the decoder must remain quiet
35	before we are allowed to start it running. */
36	#define TIME_MSEC_DECODER_WAIT 50
37
38	/* This defines a minimum interval that the decoder must be allowed to run
39	before we can safely begin using its streaming output. */
40	#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
41
42	/* This defines a minimum interval that the encoder must remain quiet
43	before we are allowed to configure it. */
44	#define TIME_MSEC_ENCODER_WAIT 50
45
46	/* This defines the minimum interval that the encoder must successfully run
47	before we consider that the encoder has run at least once since its
48	firmware has been loaded. This measurement is in important for cases
49	where we can't do something until we know that the encoder has been run
50	at least once. */
51	#define TIME_MSEC_ENCODER_OK 250
52
53	static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
54	static DEFINE_MUTEX(pvr2_unit_mtx);
55
56	static int ctlchg;
57	static int procreload;
58	static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
59	static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
60	static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
61	static int init_pause_msec;
62
63	module_param(ctlchg, int, S_IRUGO|S_IWUSR);
64	MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
65	module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
66	MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
67	module_param(procreload, int, S_IRUGO|S_IWUSR);
68	MODULE_PARM_DESC(procreload,
69	"Attempt init failure recovery with firmware reload");
70	module_param_array(tuner, int, NULL, 0444);
71	MODULE_PARM_DESC(tuner,"specify installed tuner type");
72	module_param_array(video_std, int, NULL, 0444);
73	MODULE_PARM_DESC(video_std,"specify initial video standard");
74	module_param_array(tolerance, int, NULL, 0444);
75	MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
76
77	/* US Broadcast channel 3 (61.25 MHz), to help with testing */
78	static int default_tv_freq = 61250000L;
79	/* 104.3 MHz, a usable FM station for my area */
80	static int default_radio_freq = 104300000L;
81
82	module_param_named(tv_freq, default_tv_freq, int, 0444);
83	MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
84	module_param_named(radio_freq, default_radio_freq, int, 0444);
85	MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
86
87	#define PVR2_CTL_WRITE_ENDPOINT 0x01
88	#define PVR2_CTL_READ_ENDPOINT 0x81
89
90	#define PVR2_GPIO_IN 0x9008
91	#define PVR2_GPIO_OUT 0x900c
92	#define PVR2_GPIO_DIR 0x9020
93
94	#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
95
96	#define PVR2_FIRMWARE_ENDPOINT 0x02
97
98	/* size of a firmware chunk */
99	#define FIRMWARE_CHUNK_SIZE 0x2000
100
101	typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
102	struct v4l2_subdev *);
103
104	static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
105	[PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
106	[PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
107	[PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
108	[PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
109	[PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
110	};
111
112	static const char *module_names[] = {
113	[PVR2_CLIENT_ID_MSP3400] = "msp3400",
114	[PVR2_CLIENT_ID_CX25840] = "cx25840",
115	[PVR2_CLIENT_ID_SAA7115] = "saa7115",
116	[PVR2_CLIENT_ID_TUNER] = "tuner",
117	[PVR2_CLIENT_ID_DEMOD] = "tuner",
118	[PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
119	[PVR2_CLIENT_ID_WM8775] = "wm8775",
120	};
121
122
123	static const unsigned char *module_i2c_addresses[] = {
124	[PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
125	[PVR2_CLIENT_ID_DEMOD] = "\x43",
126	[PVR2_CLIENT_ID_MSP3400] = "\x40",
127	[PVR2_CLIENT_ID_SAA7115] = "\x21",
128	[PVR2_CLIENT_ID_WM8775] = "\x1b",
129	[PVR2_CLIENT_ID_CX25840] = "\x44",
130	[PVR2_CLIENT_ID_CS53L32A] = "\x11",
131	};
132
133
134	static const char *ir_scheme_names[] = {
135	[PVR2_IR_SCHEME_NONE] = "none",
136	[PVR2_IR_SCHEME_29XXX] = "29xxx",
137	[PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
138	[PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
139	[PVR2_IR_SCHEME_ZILOG] = "Zilog",
140	};
141
142
143	/* Define the list of additional controls we'll dynamically construct based
144	on query of the cx2341x module. */
145	struct pvr2_mpeg_ids {
146	const char *strid;
147	int id;
148	};
149	static const struct pvr2_mpeg_ids mpeg_ids[] = {
150	{
151	.strid = "audio_layer",
152	.id = V4L2_CID_MPEG_AUDIO_ENCODING,
153	},{
154	.strid = "audio_bitrate",
155	.id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
156	},{
157	/* Already using audio_mode elsewhere :-( */
158	.strid = "mpeg_audio_mode",
159	.id = V4L2_CID_MPEG_AUDIO_MODE,
160	},{
161	.strid = "mpeg_audio_mode_extension",
162	.id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
163	},{
164	.strid = "audio_emphasis",
165	.id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
166	},{
167	.strid = "audio_crc",
168	.id = V4L2_CID_MPEG_AUDIO_CRC,
169	},{
170	.strid = "video_aspect",
171	.id = V4L2_CID_MPEG_VIDEO_ASPECT,
172	},{
173	.strid = "video_b_frames",
174	.id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
175	},{
176	.strid = "video_gop_size",
177	.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
178	},{
179	.strid = "video_gop_closure",
180	.id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
181	},{
182	.strid = "video_bitrate_mode",
183	.id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
184	},{
185	.strid = "video_bitrate",
186	.id = V4L2_CID_MPEG_VIDEO_BITRATE,
187	},{
188	.strid = "video_bitrate_peak",
189	.id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
190	},{
191	.strid = "video_temporal_decimation",
192	.id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
193	},{
194	.strid = "stream_type",
195	.id = V4L2_CID_MPEG_STREAM_TYPE,
196	},{
197	.strid = "video_spatial_filter_mode",
198	.id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
199	},{
200	.strid = "video_spatial_filter",
201	.id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
202	},{
203	.strid = "video_luma_spatial_filter_type",
204	.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
205	},{
206	.strid = "video_chroma_spatial_filter_type",
207	.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
208	},{
209	.strid = "video_temporal_filter_mode",
210	.id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
211	},{
212	.strid = "video_temporal_filter",
213	.id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
214	},{
215	.strid = "video_median_filter_type",
216	.id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
217	},{
218	.strid = "video_luma_median_filter_top",
219	.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
220	},{
221	.strid = "video_luma_median_filter_bottom",
222	.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
223	},{
224	.strid = "video_chroma_median_filter_top",
225	.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
226	},{
227	.strid = "video_chroma_median_filter_bottom",
228	.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
229	}
230	};
231	#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
232
233
234	static const char *control_values_srate[] = {
235	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
236	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
237	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
238	};
239
240
241
242	static const char *control_values_input[] = {
243	[PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
244	[PVR2_CVAL_INPUT_DTV] = "dtv",
245	[PVR2_CVAL_INPUT_RADIO] = "radio",
246	[PVR2_CVAL_INPUT_SVIDEO] = "s-video",
247	[PVR2_CVAL_INPUT_COMPOSITE] = "composite",
248	};
249
250
251	static const char *control_values_audiomode[] = {
252	[V4L2_TUNER_MODE_MONO] = "Mono",
253	[V4L2_TUNER_MODE_STEREO] = "Stereo",
254	[V4L2_TUNER_MODE_LANG1] = "Lang1",
255	[V4L2_TUNER_MODE_LANG2] = "Lang2",
256	[V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
257	};
258
259
260	static const char *control_values_hsm[] = {
261	[PVR2_CVAL_HSM_FAIL] = "Fail",
262	[PVR2_CVAL_HSM_HIGH] = "High",
263	[PVR2_CVAL_HSM_FULL] = "Full",
264	};
265
266
267	static const char *pvr2_state_names[] = {
268	[PVR2_STATE_NONE] = "none",
269	[PVR2_STATE_DEAD] = "dead",
270	[PVR2_STATE_COLD] = "cold",
271	[PVR2_STATE_WARM] = "warm",
272	[PVR2_STATE_ERROR] = "error",
273	[PVR2_STATE_READY] = "ready",
274	[PVR2_STATE_RUN] = "run",
275	};
276
277
278	struct pvr2_fx2cmd_descdef {
279	unsigned char id;
280	unsigned char *desc;
281	};
282
283	static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
284	{FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
285	{FX2CMD_MEM_READ_DWORD, "read encoder dword"},
286	{FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
287	{FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
288	{FX2CMD_REG_WRITE, "write encoder register"},
289	{FX2CMD_REG_READ, "read encoder register"},
290	{FX2CMD_MEMSEL, "encoder memsel"},
291	{FX2CMD_I2C_WRITE, "i2c write"},
292	{FX2CMD_I2C_READ, "i2c read"},
293	{FX2CMD_GET_USB_SPEED, "get USB speed"},
294	{FX2CMD_STREAMING_ON, "stream on"},
295	{FX2CMD_STREAMING_OFF, "stream off"},
296	{FX2CMD_FWPOST1, "fwpost1"},
297	{FX2CMD_POWER_OFF, "power off"},
298	{FX2CMD_POWER_ON, "power on"},
299	{FX2CMD_DEEP_RESET, "deep reset"},
300	{FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
301	{FX2CMD_GET_IR_CODE, "get IR code"},
302	{FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
303	{FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
304	{FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
305	{FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
306	{FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
307	{FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
308	{FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
309	{FX2CMD_HCW_DEMOD_RESET_PIN, "hcw demod reset pin"},
310	{FX2CMD_HCW_MAKO_SLEEP_PIN, "hcw mako sleep pin"},
311	};
312
313
314	static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
315	static void pvr2_hdw_state_sched(struct pvr2_hdw *);
316	static int pvr2_hdw_state_eval(struct pvr2_hdw *);
317	static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
318	static void pvr2_hdw_worker_poll(struct work_struct *work);
319	static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
320	static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
321	static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
322	static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
323	static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
324	static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
325	static void pvr2_hdw_quiescent_timeout(struct timer_list *);
326	static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *);
327	static void pvr2_hdw_encoder_wait_timeout(struct timer_list *);
328	static void pvr2_hdw_encoder_run_timeout(struct timer_list *);
329	static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
330	static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
331	unsigned int timeout,int probe_fl,
332	void *write_data,unsigned int write_len,
333	void *read_data,unsigned int read_len);
334	static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
335	static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
336
337	static void trace_stbit(const char *name,int val)
338	{
339	pvr2_trace(PVR2_TRACE_STBITS,
340	"State bit %s <-- %s",
341	name,(val ? "true" : "false"));
342	}
343
344	static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
345	{
346	struct pvr2_hdw *hdw = cptr->hdw;
347	if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
348	*vp = hdw->freqTable[hdw->freqProgSlot-1];
349	} else {
350	*vp = 0;
351	}
352	return 0;
353	}
354
355	static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
356	{
357	struct pvr2_hdw *hdw = cptr->hdw;
358	unsigned int slotId = hdw->freqProgSlot;
359	if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
360	hdw->freqTable[slotId-1] = v;
361	/* Handle side effects correctly - if we're tuned to this
362	slot, then forgot the slot id relation since the stored
363	frequency has been changed. */
364	if (hdw->freqSelector) {
365	if (hdw->freqSlotRadio == slotId) {
366	hdw->freqSlotRadio = 0;
367	}
368	} else {
369	if (hdw->freqSlotTelevision == slotId) {
370	hdw->freqSlotTelevision = 0;
371	}
372	}
373	}
374	return 0;
375	}
376
377	static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
378	{
379	*vp = cptr->hdw->freqProgSlot;
380	return 0;
381	}
382
383	static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
384	{
385	struct pvr2_hdw *hdw = cptr->hdw;
386	if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
387	hdw->freqProgSlot = v;
388	}
389	return 0;
390	}
391
392	static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
393	{
394	struct pvr2_hdw *hdw = cptr->hdw;
395	*vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
396	return 0;
397	}
398
399	static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
400	{
401	unsigned freq = 0;
402	struct pvr2_hdw *hdw = cptr->hdw;
403	if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
404	if (slotId > 0) {
405	freq = hdw->freqTable[slotId-1];
406	if (!freq) return 0;
407	pvr2_hdw_set_cur_freq(hdw,freq);
408	}
409	if (hdw->freqSelector) {
410	hdw->freqSlotRadio = slotId;
411	} else {
412	hdw->freqSlotTelevision = slotId;
413	}
414	return 0;
415	}
416
417	static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
418	{
419	*vp = pvr2_hdw_get_cur_freq(cptr->hdw);
420	return 0;
421	}
422
423	static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
424	{
425	return cptr->hdw->freqDirty != 0;
426	}
427
428	static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
429	{
430	cptr->hdw->freqDirty = 0;
431	}
432
433	static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
434	{
435	pvr2_hdw_set_cur_freq(cptr->hdw,v);
436	return 0;
437	}
438
439	static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
440	{
441	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
442	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
443	if (stat != 0) {
444	return stat;
445	}
446	*left = cap->bounds.left;
447	return 0;
448	}
449
450	static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
451	{
452	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
453	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
454	if (stat != 0) {
455	return stat;
456	}
457	*left = cap->bounds.left;
458	if (cap->bounds.width > cptr->hdw->cropw_val) {
459	*left += cap->bounds.width - cptr->hdw->cropw_val;
460	}
461	return 0;
462	}
463
464	static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
465	{
466	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
467	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
468	if (stat != 0) {
469	return stat;
470	}
471	*top = cap->bounds.top;
472	return 0;
473	}
474
475	static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
476	{
477	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
478	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
479	if (stat != 0) {
480	return stat;
481	}
482	*top = cap->bounds.top;
483	if (cap->bounds.height > cptr->hdw->croph_val) {
484	*top += cap->bounds.height - cptr->hdw->croph_val;
485	}
486	return 0;
487	}
488
489	static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
490	{
491	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
492	int stat, bleftend, cleft;
493
494	stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
495	if (stat != 0) {
496	return stat;
497	}
498	bleftend = cap->bounds.left+cap->bounds.width;
499	cleft = cptr->hdw->cropl_val;
500
501	*width = cleft < bleftend ? bleftend-cleft : 0;
502	return 0;
503	}
504
505	static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
506	{
507	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
508	int stat, btopend, ctop;
509
510	stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
511	if (stat != 0) {
512	return stat;
513	}
514	btopend = cap->bounds.top+cap->bounds.height;
515	ctop = cptr->hdw->cropt_val;
516
517	*height = ctop < btopend ? btopend-ctop : 0;
518	return 0;
519	}
520
521	static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
522	{
523	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
524	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
525	if (stat != 0) {
526	return stat;
527	}
528	*val = cap->bounds.left;
529	return 0;
530	}
531
532	static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
533	{
534	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
535	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
536	if (stat != 0) {
537	return stat;
538	}
539	*val = cap->bounds.top;
540	return 0;
541	}
542
543	static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
544	{
545	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
546	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
547	if (stat != 0) {
548	return stat;
549	}
550	*val = cap->bounds.width;
551	return 0;
552	}
553
554	static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
555	{
556	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
557	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
558	if (stat != 0) {
559	return stat;
560	}
561	*val = cap->bounds.height;
562	return 0;
563	}
564
565	static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
566	{
567	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
568	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
569	if (stat != 0) {
570	return stat;
571	}
572	*val = cap->defrect.left;
573	return 0;
574	}
575
576	static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
577	{
578	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
579	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
580	if (stat != 0) {
581	return stat;
582	}
583	*val = cap->defrect.top;
584	return 0;
585	}
586
587	static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
588	{
589	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
590	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
591	if (stat != 0) {
592	return stat;
593	}
594	*val = cap->defrect.width;
595	return 0;
596	}
597
598	static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
599	{
600	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
601	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
602	if (stat != 0) {
603	return stat;
604	}
605	*val = cap->defrect.height;
606	return 0;
607	}
608
609	static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
610	{
611	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
612	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
613	if (stat != 0) {
614	return stat;
615	}
616	*val = cap->pixelaspect.numerator;
617	return 0;
618	}
619
620	static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
621	{
622	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
623	int stat = pvr2_hdw_check_cropcap(hdw: cptr->hdw);
624	if (stat != 0) {
625	return stat;
626	}
627	*val = cap->pixelaspect.denominator;
628	return 0;
629	}
630
631	static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
632	{
633	/* Actual maximum depends on the video standard in effect. */
634	if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
635	*vp = 480;
636	} else {
637	*vp = 576;
638	}
639	return 0;
640	}
641
642	static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
643	{
644	/* Actual minimum depends on device digitizer type. */
645	if (cptr->hdw->hdw_desc->flag_has_cx25840) {
646	*vp = 75;
647	} else {
648	*vp = 17;
649	}
650	return 0;
651	}
652
653	static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
654	{
655	*vp = cptr->hdw->input_val;
656	return 0;
657	}
658
659	static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
660	{
661	if (v < 0 || v > PVR2_CVAL_INPUT_MAX)
662	return 0;
663	return ((1UL << v) & cptr->hdw->input_allowed_mask) != 0;
664	}
665
666	static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
667	{
668	return pvr2_hdw_set_input(hdw: cptr->hdw,v);
669	}
670
671	static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
672	{
673	return cptr->hdw->input_dirty != 0;
674	}
675
676	static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
677	{
678	cptr->hdw->input_dirty = 0;
679	}
680
681
682	static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
683	{
684	unsigned long fv;
685	struct pvr2_hdw *hdw = cptr->hdw;
686	if (hdw->tuner_signal_stale) {
687	pvr2_hdw_status_poll(hdw);
688	}
689	fv = hdw->tuner_signal_info.rangehigh;
690	if (!fv) {
691	/* Safety fallback */
692	*vp = TV_MAX_FREQ;
693	return 0;
694	}
695	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
696	fv = (fv * 125) / 2;
697	} else {
698	fv = fv * 62500;
699	}
700	*vp = fv;
701	return 0;
702	}
703
704	static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
705	{
706	unsigned long fv;
707	struct pvr2_hdw *hdw = cptr->hdw;
708	if (hdw->tuner_signal_stale) {
709	pvr2_hdw_status_poll(hdw);
710	}
711	fv = hdw->tuner_signal_info.rangelow;
712	if (!fv) {
713	/* Safety fallback */
714	*vp = TV_MIN_FREQ;
715	return 0;
716	}
717	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
718	fv = (fv * 125) / 2;
719	} else {
720	fv = fv * 62500;
721	}
722	*vp = fv;
723	return 0;
724	}
725
726	static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
727	{
728	return cptr->hdw->enc_stale != 0;
729	}
730
731	static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
732	{
733	cptr->hdw->enc_stale = 0;
734	cptr->hdw->enc_unsafe_stale = 0;
735	}
736
737	static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
738	{
739	int ret;
740	struct v4l2_ext_controls cs;
741	struct v4l2_ext_control c1;
742	memset(&cs,0,sizeof(cs));
743	memset(&c1,0,sizeof(c1));
744	cs.controls = &c1;
745	cs.count = 1;
746	c1.id = cptr->info->v4l_id;
747	ret = cx2341x_ext_ctrls(params: &cptr->hdw->enc_ctl_state, busy: 0, ctrls: &cs,
748	VIDIOC_G_EXT_CTRLS);
749	if (ret) return ret;
750	*vp = c1.value;
751	return 0;
752	}
753
754	static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
755	{
756	int ret;
757	struct pvr2_hdw *hdw = cptr->hdw;
758	struct v4l2_ext_controls cs;
759	struct v4l2_ext_control c1;
760	memset(&cs,0,sizeof(cs));
761	memset(&c1,0,sizeof(c1));
762	cs.controls = &c1;
763	cs.count = 1;
764	c1.id = cptr->info->v4l_id;
765	c1.value = v;
766	ret = cx2341x_ext_ctrls(params: &hdw->enc_ctl_state,
767	busy: hdw->state_encoder_run, ctrls: &cs,
768	VIDIOC_S_EXT_CTRLS);
769	if (ret == -EBUSY) {
770	/* Oops. cx2341x is telling us it's not safe to change
771	this control while we're capturing. Make a note of this
772	fact so that the pipeline will be stopped the next time
773	controls are committed. Then go on ahead and store this
774	change anyway. */
775	ret = cx2341x_ext_ctrls(params: &hdw->enc_ctl_state,
776	busy: 0, ctrls: &cs,
777	VIDIOC_S_EXT_CTRLS);
778	if (!ret) hdw->enc_unsafe_stale = !0;
779	}
780	if (ret) return ret;
781	hdw->enc_stale = !0;
782	return 0;
783	}
784
785	static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
786	{
787	struct v4l2_queryctrl qctrl = {};
788	struct pvr2_ctl_info *info;
789	qctrl.id = cptr->info->v4l_id;
790	cx2341x_ctrl_query(params: &cptr->hdw->enc_ctl_state,qctrl: &qctrl);
791	/* Strip out the const so we can adjust a function pointer. It's
792	OK to do this here because we know this is a dynamically created
793	control, so the underlying storage for the info pointer is (a)
794	private to us, and (b) not in read-only storage. Either we do
795	this or we significantly complicate the underlying control
796	implementation. */
797	info = (struct pvr2_ctl_info *)(cptr->info);
798	if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
799	if (info->set_value) {
800	info->set_value = NULL;
801	}
802	} else {
803	if (!(info->set_value)) {
804	info->set_value = ctrl_cx2341x_set;
805	}
806	}
807	return qctrl.flags;
808	}
809
810	static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
811	{
812	*vp = cptr->hdw->state_pipeline_req;
813	return 0;
814	}
815
816	static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
817	{
818	*vp = cptr->hdw->master_state;
819	return 0;
820	}
821
822	static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
823	{
824	int result = pvr2_hdw_is_hsm(cptr->hdw);
825	*vp = PVR2_CVAL_HSM_FULL;
826	if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
827	if (result) *vp = PVR2_CVAL_HSM_HIGH;
828	return 0;
829	}
830
831	static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
832	{
833	*vp = pvr2_hdw_get_detected_std(hdw: cptr->hdw);
834	return 0;
835	}
836
837	static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
838	{
839	*vp = cptr->hdw->std_mask_avail;
840	return 0;
841	}
842
843	static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
844	{
845	struct pvr2_hdw *hdw = cptr->hdw;
846	v4l2_std_id ns;
847	ns = hdw->std_mask_avail;
848	ns = (ns & ~m) | (v & m);
849	if (ns == hdw->std_mask_avail) return 0;
850	hdw->std_mask_avail = ns;
851	hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
852	return 0;
853	}
854
855	static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
856	char *bufPtr,unsigned int bufSize,
857	unsigned int *len)
858	{
859	*len = pvr2_std_id_to_str(bufPtr,bufSize,id: msk & val);
860	return 0;
861	}
862
863	static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
864	const char *bufPtr,unsigned int bufSize,
865	int *mskp,int *valp)
866	{
867	v4l2_std_id id;
868	if (!pvr2_std_str_to_id(idPtr: &id, bufPtr, bufSize))
869	return -EINVAL;
870	if (mskp) *mskp = id;
871	if (valp) *valp = id;
872	return 0;
873	}
874
875	static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
876	{
877	*vp = cptr->hdw->std_mask_cur;
878	return 0;
879	}
880
881	static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
882	{
883	struct pvr2_hdw *hdw = cptr->hdw;
884	v4l2_std_id ns;
885	ns = hdw->std_mask_cur;
886	ns = (ns & ~m) | (v & m);
887	if (ns == hdw->std_mask_cur) return 0;
888	hdw->std_mask_cur = ns;
889	hdw->std_dirty = !0;
890	return 0;
891	}
892
893	static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
894	{
895	return cptr->hdw->std_dirty != 0;
896	}
897
898	static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
899	{
900	cptr->hdw->std_dirty = 0;
901	}
902
903	static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
904	{
905	struct pvr2_hdw *hdw = cptr->hdw;
906	pvr2_hdw_status_poll(hdw);
907	*vp = hdw->tuner_signal_info.signal;
908	return 0;
909	}
910
911	static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
912	{
913	int val = 0;
914	unsigned int subchan;
915	struct pvr2_hdw *hdw = cptr->hdw;
916	pvr2_hdw_status_poll(hdw);
917	subchan = hdw->tuner_signal_info.rxsubchans;
918	if (subchan & V4L2_TUNER_SUB_MONO) {
919	val |= (1 << V4L2_TUNER_MODE_MONO);
920	}
921	if (subchan & V4L2_TUNER_SUB_STEREO) {
922	val |= (1 << V4L2_TUNER_MODE_STEREO);
923	}
924	if (subchan & V4L2_TUNER_SUB_LANG1) {
925	val |= (1 << V4L2_TUNER_MODE_LANG1);
926	}
927	if (subchan & V4L2_TUNER_SUB_LANG2) {
928	val |= (1 << V4L2_TUNER_MODE_LANG2);
929	}
930	*vp = val;
931	return 0;
932	}
933
934
935	#define DEFINT(vmin,vmax) \
936	.type = pvr2_ctl_int, \
937	.def.type_int.min_value = vmin, \
938	.def.type_int.max_value = vmax
939
940	#define DEFENUM(tab) \
941	.type = pvr2_ctl_enum, \
942	.def.type_enum.count = ARRAY_SIZE(tab), \
943	.def.type_enum.value_names = tab
944
945	#define DEFBOOL \
946	.type = pvr2_ctl_bool
947
948	#define DEFMASK(msk,tab) \
949	.type = pvr2_ctl_bitmask, \
950	.def.type_bitmask.valid_bits = msk, \
951	.def.type_bitmask.bit_names = tab
952
953	#define DEFREF(vname) \
954	.set_value = ctrl_set_##vname, \
955	.get_value = ctrl_get_##vname, \
956	.is_dirty = ctrl_isdirty_##vname, \
957	.clear_dirty = ctrl_cleardirty_##vname
958
959
960	#define VCREATE_FUNCS(vname) \
961	static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
962	{*vp = cptr->hdw->vname##_val; return 0;} \
963	static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
964	{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
965	static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
966	{return cptr->hdw->vname##_dirty != 0;} \
967	static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
968	{cptr->hdw->vname##_dirty = 0;}
969
970	VCREATE_FUNCS(brightness)
971	VCREATE_FUNCS(contrast)
972	VCREATE_FUNCS(saturation)
973	VCREATE_FUNCS(hue)
974	VCREATE_FUNCS(volume)
975	VCREATE_FUNCS(balance)
976	VCREATE_FUNCS(bass)
977	VCREATE_FUNCS(treble)
978	VCREATE_FUNCS(mute)
979	VCREATE_FUNCS(cropl)
980	VCREATE_FUNCS(cropt)
981	VCREATE_FUNCS(cropw)
982	VCREATE_FUNCS(croph)
983	VCREATE_FUNCS(audiomode)
984	VCREATE_FUNCS(res_hor)
985	VCREATE_FUNCS(res_ver)
986	VCREATE_FUNCS(srate)
987
988	/* Table definition of all controls which can be manipulated */
989	static const struct pvr2_ctl_info control_defs[] = {
990	{
991	.v4l_id = V4L2_CID_BRIGHTNESS,
992	.desc = "Brightness",
993	.name = "brightness",
994	.default_value = 128,
995	DEFREF(brightness),
996	DEFINT(0,255),
997	},{
998	.v4l_id = V4L2_CID_CONTRAST,
999	.desc = "Contrast",
1000	.name = "contrast",
1001	.default_value = 68,
1002	DEFREF(contrast),
1003	DEFINT(0,127),
1004	},{
1005	.v4l_id = V4L2_CID_SATURATION,
1006	.desc = "Saturation",
1007	.name = "saturation",
1008	.default_value = 64,
1009	DEFREF(saturation),
1010	DEFINT(0,127),
1011	},{
1012	.v4l_id = V4L2_CID_HUE,
1013	.desc = "Hue",
1014	.name = "hue",
1015	.default_value = 0,
1016	DEFREF(hue),
1017	DEFINT(-128,127),
1018	},{
1019	.v4l_id = V4L2_CID_AUDIO_VOLUME,
1020	.desc = "Volume",
1021	.name = "volume",
1022	.default_value = 62000,
1023	DEFREF(volume),
1024	DEFINT(0,65535),
1025	},{
1026	.v4l_id = V4L2_CID_AUDIO_BALANCE,
1027	.desc = "Balance",
1028	.name = "balance",
1029	.default_value = 0,
1030	DEFREF(balance),
1031	DEFINT(-32768,32767),
1032	},{
1033	.v4l_id = V4L2_CID_AUDIO_BASS,
1034	.desc = "Bass",
1035	.name = "bass",
1036	.default_value = 0,
1037	DEFREF(bass),
1038	DEFINT(-32768,32767),
1039	},{
1040	.v4l_id = V4L2_CID_AUDIO_TREBLE,
1041	.desc = "Treble",
1042	.name = "treble",
1043	.default_value = 0,
1044	DEFREF(treble),
1045	DEFINT(-32768,32767),
1046	},{
1047	.v4l_id = V4L2_CID_AUDIO_MUTE,
1048	.desc = "Mute",
1049	.name = "mute",
1050	.default_value = 0,
1051	DEFREF(mute),
1052	DEFBOOL,
1053	}, {
1054	.desc = "Capture crop left margin",
1055	.name = "crop_left",
1056	.internal_id = PVR2_CID_CROPL,
1057	.default_value = 0,
1058	DEFREF(cropl),
1059	DEFINT(-129, 340),
1060	.get_min_value = ctrl_cropl_min_get,
1061	.get_max_value = ctrl_cropl_max_get,
1062	.get_def_value = ctrl_get_cropcapdl,
1063	}, {
1064	.desc = "Capture crop top margin",
1065	.name = "crop_top",
1066	.internal_id = PVR2_CID_CROPT,
1067	.default_value = 0,
1068	DEFREF(cropt),
1069	DEFINT(-35, 544),
1070	.get_min_value = ctrl_cropt_min_get,
1071	.get_max_value = ctrl_cropt_max_get,
1072	.get_def_value = ctrl_get_cropcapdt,
1073	}, {
1074	.desc = "Capture crop width",
1075	.name = "crop_width",
1076	.internal_id = PVR2_CID_CROPW,
1077	.default_value = 720,
1078	DEFREF(cropw),
1079	DEFINT(0, 864),
1080	.get_max_value = ctrl_cropw_max_get,
1081	.get_def_value = ctrl_get_cropcapdw,
1082	}, {
1083	.desc = "Capture crop height",
1084	.name = "crop_height",
1085	.internal_id = PVR2_CID_CROPH,
1086	.default_value = 480,
1087	DEFREF(croph),
1088	DEFINT(0, 576),
1089	.get_max_value = ctrl_croph_max_get,
1090	.get_def_value = ctrl_get_cropcapdh,
1091	}, {
1092	.desc = "Capture capability pixel aspect numerator",
1093	.name = "cropcap_pixel_numerator",
1094	.internal_id = PVR2_CID_CROPCAPPAN,
1095	.get_value = ctrl_get_cropcappan,
1096	}, {
1097	.desc = "Capture capability pixel aspect denominator",
1098	.name = "cropcap_pixel_denominator",
1099	.internal_id = PVR2_CID_CROPCAPPAD,
1100	.get_value = ctrl_get_cropcappad,
1101	}, {
1102	.desc = "Capture capability bounds top",
1103	.name = "cropcap_bounds_top",
1104	.internal_id = PVR2_CID_CROPCAPBT,
1105	.get_value = ctrl_get_cropcapbt,
1106	}, {
1107	.desc = "Capture capability bounds left",
1108	.name = "cropcap_bounds_left",
1109	.internal_id = PVR2_CID_CROPCAPBL,
1110	.get_value = ctrl_get_cropcapbl,
1111	}, {
1112	.desc = "Capture capability bounds width",
1113	.name = "cropcap_bounds_width",
1114	.internal_id = PVR2_CID_CROPCAPBW,
1115	.get_value = ctrl_get_cropcapbw,
1116	}, {
1117	.desc = "Capture capability bounds height",
1118	.name = "cropcap_bounds_height",
1119	.internal_id = PVR2_CID_CROPCAPBH,
1120	.get_value = ctrl_get_cropcapbh,
1121	},{
1122	.desc = "Video Source",
1123	.name = "input",
1124	.internal_id = PVR2_CID_INPUT,
1125	.default_value = PVR2_CVAL_INPUT_TV,
1126	.check_value = ctrl_check_input,
1127	DEFREF(input),
1128	DEFENUM(control_values_input),
1129	},{
1130	.desc = "Audio Mode",
1131	.name = "audio_mode",
1132	.internal_id = PVR2_CID_AUDIOMODE,
1133	.default_value = V4L2_TUNER_MODE_STEREO,
1134	DEFREF(audiomode),
1135	DEFENUM(control_values_audiomode),
1136	},{
1137	.desc = "Horizontal capture resolution",
1138	.name = "resolution_hor",
1139	.internal_id = PVR2_CID_HRES,
1140	.default_value = 720,
1141	DEFREF(res_hor),
1142	DEFINT(19,720),
1143	},{
1144	.desc = "Vertical capture resolution",
1145	.name = "resolution_ver",
1146	.internal_id = PVR2_CID_VRES,
1147	.default_value = 480,
1148	DEFREF(res_ver),
1149	DEFINT(17,576),
1150	/* Hook in check for video standard and adjust maximum
1151	depending on the standard. */
1152	.get_max_value = ctrl_vres_max_get,
1153	.get_min_value = ctrl_vres_min_get,
1154	},{
1155	.v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1156	.default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1157	.desc = "Audio Sampling Frequency",
1158	.name = "srate",
1159	DEFREF(srate),
1160	DEFENUM(control_values_srate),
1161	},{
1162	.desc = "Tuner Frequency (Hz)",
1163	.name = "frequency",
1164	.internal_id = PVR2_CID_FREQUENCY,
1165	.default_value = 0,
1166	.set_value = ctrl_freq_set,
1167	.get_value = ctrl_freq_get,
1168	.is_dirty = ctrl_freq_is_dirty,
1169	.clear_dirty = ctrl_freq_clear_dirty,
1170	DEFINT(0,0),
1171	/* Hook in check for input value (tv/radio) and adjust
1172	max/min values accordingly */
1173	.get_max_value = ctrl_freq_max_get,
1174	.get_min_value = ctrl_freq_min_get,
1175	},{
1176	.desc = "Channel",
1177	.name = "channel",
1178	.set_value = ctrl_channel_set,
1179	.get_value = ctrl_channel_get,
1180	DEFINT(0,FREQTABLE_SIZE),
1181	},{
1182	.desc = "Channel Program Frequency",
1183	.name = "freq_table_value",
1184	.set_value = ctrl_channelfreq_set,
1185	.get_value = ctrl_channelfreq_get,
1186	DEFINT(0,0),
1187	/* Hook in check for input value (tv/radio) and adjust
1188	max/min values accordingly */
1189	.get_max_value = ctrl_freq_max_get,
1190	.get_min_value = ctrl_freq_min_get,
1191	},{
1192	.desc = "Channel Program ID",
1193	.name = "freq_table_channel",
1194	.set_value = ctrl_channelprog_set,
1195	.get_value = ctrl_channelprog_get,
1196	DEFINT(0,FREQTABLE_SIZE),
1197	},{
1198	.desc = "Streaming Enabled",
1199	.name = "streaming_enabled",
1200	.get_value = ctrl_streamingenabled_get,
1201	DEFBOOL,
1202	},{
1203	.desc = "USB Speed",
1204	.name = "usb_speed",
1205	.get_value = ctrl_hsm_get,
1206	DEFENUM(control_values_hsm),
1207	},{
1208	.desc = "Master State",
1209	.name = "master_state",
1210	.get_value = ctrl_masterstate_get,
1211	DEFENUM(pvr2_state_names),
1212	},{
1213	.desc = "Signal Present",
1214	.name = "signal_present",
1215	.get_value = ctrl_signal_get,
1216	DEFINT(0,65535),
1217	},{
1218	.desc = "Audio Modes Present",
1219	.name = "audio_modes_present",
1220	.get_value = ctrl_audio_modes_present_get,
1221	/* For this type we "borrow" the V4L2_TUNER_MODE enum from
1222	v4l. Nothing outside of this module cares about this,
1223	but I reuse it in order to also reuse the
1224	control_values_audiomode string table. */
1225	DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1226	(1 << V4L2_TUNER_MODE_STEREO)|
1227	(1 << V4L2_TUNER_MODE_LANG1)|
1228	(1 << V4L2_TUNER_MODE_LANG2)),
1229	control_values_audiomode),
1230	},{
1231	.desc = "Video Standards Available Mask",
1232	.name = "video_standard_mask_available",
1233	.internal_id = PVR2_CID_STDAVAIL,
1234	.skip_init = !0,
1235	.get_value = ctrl_stdavail_get,
1236	.set_value = ctrl_stdavail_set,
1237	.val_to_sym = ctrl_std_val_to_sym,
1238	.sym_to_val = ctrl_std_sym_to_val,
1239	.type = pvr2_ctl_bitmask,
1240	},{
1241	.desc = "Video Standards In Use Mask",
1242	.name = "video_standard_mask_active",
1243	.internal_id = PVR2_CID_STDCUR,
1244	.skip_init = !0,
1245	.get_value = ctrl_stdcur_get,
1246	.set_value = ctrl_stdcur_set,
1247	.is_dirty = ctrl_stdcur_is_dirty,
1248	.clear_dirty = ctrl_stdcur_clear_dirty,
1249	.val_to_sym = ctrl_std_val_to_sym,
1250	.sym_to_val = ctrl_std_sym_to_val,
1251	.type = pvr2_ctl_bitmask,
1252	},{
1253	.desc = "Video Standards Detected Mask",
1254	.name = "video_standard_mask_detected",
1255	.internal_id = PVR2_CID_STDDETECT,
1256	.skip_init = !0,
1257	.get_value = ctrl_stddetect_get,
1258	.val_to_sym = ctrl_std_val_to_sym,
1259	.sym_to_val = ctrl_std_sym_to_val,
1260	.type = pvr2_ctl_bitmask,
1261	}
1262	};
1263
1264	#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1265
1266
1267	const char *pvr2_config_get_name(enum pvr2_config cfg)
1268	{
1269	switch (cfg) {
1270	case pvr2_config_empty: return "empty";
1271	case pvr2_config_mpeg: return "mpeg";
1272	case pvr2_config_vbi: return "vbi";
1273	case pvr2_config_pcm: return "pcm";
1274	case pvr2_config_rawvideo: return "raw video";
1275	}
1276	return "<unknown>";
1277	}
1278
1279
1280	struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1281	{
1282	return hdw->usb_dev;
1283	}
1284
1285
1286	unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1287	{
1288	return hdw->serial_number;
1289	}
1290
1291
1292	const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1293	{
1294	return hdw->bus_info;
1295	}
1296
1297
1298	const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1299	{
1300	return hdw->identifier;
1301	}
1302
1303
1304	unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1305	{
1306	return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1307	}
1308
1309	/* Set the currently tuned frequency and account for all possible
1310	driver-core side effects of this action. */
1311	static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1312	{
1313	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1314	if (hdw->freqSelector) {
1315	/* Swing over to radio frequency selection */
1316	hdw->freqSelector = 0;
1317	hdw->freqDirty = !0;
1318	}
1319	if (hdw->freqValRadio != val) {
1320	hdw->freqValRadio = val;
1321	hdw->freqSlotRadio = 0;
1322	hdw->freqDirty = !0;
1323	}
1324	} else {
1325	if (!(hdw->freqSelector)) {
1326	/* Swing over to television frequency selection */
1327	hdw->freqSelector = 1;
1328	hdw->freqDirty = !0;
1329	}
1330	if (hdw->freqValTelevision != val) {
1331	hdw->freqValTelevision = val;
1332	hdw->freqSlotTelevision = 0;
1333	hdw->freqDirty = !0;
1334	}
1335	}
1336	}
1337
1338	int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1339	{
1340	return hdw->unit_number;
1341	}
1342
1343
1344	/* Attempt to locate one of the given set of files. Messages are logged
1345	appropriate to what has been found. The return value will be 0 or
1346	greater on success (it will be the index of the file name found) and
1347	fw_entry will be filled in. Otherwise a negative error is returned on
1348	failure. If the return value is -ENOENT then no viable firmware file
1349	could be located. */
1350	static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1351	const struct firmware **fw_entry,
1352	const char *fwtypename,
1353	unsigned int fwcount,
1354	const char *fwnames[])
1355	{
1356	unsigned int idx;
1357	int ret = -EINVAL;
1358	for (idx = 0; idx < fwcount; idx++) {
1359	ret = request_firmware(fw: fw_entry,
1360	name: fwnames[idx],
1361	device: &hdw->usb_dev->dev);
1362	if (!ret) {
1363	trace_firmware("Located %s firmware: %s; uploading...",
1364	fwtypename,
1365	fwnames[idx]);
1366	return idx;
1367	}
1368	if (ret == -ENOENT) continue;
1369	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1370	"request_firmware fatal error with code=%d",ret);
1371	return ret;
1372	}
1373	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374	"***WARNING*** Device %s firmware seems to be missing.",
1375	fwtypename);
1376	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1377	"Did you install the pvrusb2 firmware files in their proper location?");
1378	if (fwcount == 1) {
1379	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1380	"request_firmware unable to locate %s file %s",
1381	fwtypename,fwnames[0]);
1382	} else {
1383	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1384	"request_firmware unable to locate one of the following %s files:",
1385	fwtypename);
1386	for (idx = 0; idx < fwcount; idx++) {
1387	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1388	"request_firmware: Failed to find %s",
1389	fwnames[idx]);
1390	}
1391	}
1392	return ret;
1393	}
1394
1395
1396	/*
1397	* pvr2_upload_firmware1().
1398	*
1399	* Send the 8051 firmware to the device. After the upload, arrange for
1400	* device to re-enumerate.
1401	*
1402	* NOTE : the pointer to the firmware data given by request_firmware()
1403	* is not suitable for an usb transaction.
1404	*
1405	*/
1406	static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1407	{
1408	const struct firmware *fw_entry = NULL;
1409	void *fw_ptr;
1410	unsigned int pipe;
1411	unsigned int fwsize;
1412	int ret;
1413	u16 address;
1414
1415	if (!hdw->hdw_desc->fx2_firmware.cnt) {
1416	hdw->fw1_state = FW1_STATE_OK;
1417	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418	"Connected device type defines no firmware to upload; ignoring firmware");
1419	return -ENOTTY;
1420	}
1421
1422	hdw->fw1_state = FW1_STATE_FAILED; // default result
1423
1424	trace_firmware("pvr2_upload_firmware1");
1425
1426	ret = pvr2_locate_firmware(hdw,fw_entry: &fw_entry,fwtypename: "fx2 controller",
1427	fwcount: hdw->hdw_desc->fx2_firmware.cnt,
1428	fwnames: hdw->hdw_desc->fx2_firmware.lst);
1429	if (ret < 0) {
1430	if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1431	return ret;
1432	}
1433
1434	usb_clear_halt(dev: hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1435
1436	pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1437	fwsize = fw_entry->size;
1438
1439	if ((fwsize != 0x2000) &&
1440	(!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1441	if (hdw->hdw_desc->flag_fx2_16kb) {
1442	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1443	"Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
1444	fwsize);
1445	} else {
1446	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1447	"Wrong fx2 firmware size (expected 8192, got %u)",
1448	fwsize);
1449	}
1450	release_firmware(fw: fw_entry);
1451	return -ENOMEM;
1452	}
1453
1454	fw_ptr = kmalloc(size: 0x800, GFP_KERNEL);
1455	if (fw_ptr == NULL){
1456	release_firmware(fw: fw_entry);
1457	return -ENOMEM;
1458	}
1459
1460	/* We have to hold the CPU during firmware upload. */
1461	pvr2_hdw_cpureset_assert(hdw,1);
1462
1463	/* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1464	chunk. */
1465
1466	ret = 0;
1467	for (address = 0; address < fwsize; address += 0x800) {
1468	memcpy(fw_ptr, fw_entry->data + address, 0x800);
1469	ret += usb_control_msg(dev: hdw->usb_dev, pipe, request: 0xa0, requesttype: 0x40, value: address,
1470	index: 0, data: fw_ptr, size: 0x800, timeout: 1000);
1471	}
1472
1473	trace_firmware("Upload done, releasing device's CPU");
1474
1475	/* Now release the CPU. It will disconnect and reconnect later. */
1476	pvr2_hdw_cpureset_assert(hdw,0);
1477
1478	kfree(objp: fw_ptr);
1479	release_firmware(fw: fw_entry);
1480
1481	trace_firmware("Upload done (%d bytes sent)",ret);
1482
1483	/* We should have written fwsize bytes */
1484	if (ret == fwsize) {
1485	hdw->fw1_state = FW1_STATE_RELOAD;
1486	return 0;
1487	}
1488
1489	return -EIO;
1490	}
1491
1492
1493	/*
1494	* pvr2_upload_firmware2()
1495	*
1496	* This uploads encoder firmware on endpoint 2.
1497	*
1498	*/
1499
1500	int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1501	{
1502	const struct firmware *fw_entry = NULL;
1503	void *fw_ptr;
1504	unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1505	int actual_length;
1506	int ret = 0;
1507	int fwidx;
1508	static const char *fw_files[] = {
1509	CX2341X_FIRM_ENC_FILENAME,
1510	};
1511
1512	if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1513	return 0;
1514	}
1515
1516	trace_firmware("pvr2_upload_firmware2");
1517
1518	ret = pvr2_locate_firmware(hdw,fw_entry: &fw_entry,fwtypename: "encoder",
1519	ARRAY_SIZE(fw_files), fwnames: fw_files);
1520	if (ret < 0) return ret;
1521	fwidx = ret;
1522	ret = 0;
1523	/* Since we're about to completely reinitialize the encoder,
1524	invalidate our cached copy of its configuration state. Next
1525	time we configure the encoder, then we'll fully configure it. */
1526	hdw->enc_cur_valid = 0;
1527
1528	/* Encoder is about to be reset so note that as far as we're
1529	concerned now, the encoder has never been run. */
1530	del_timer_sync(timer: &hdw->encoder_run_timer);
1531	if (hdw->state_encoder_runok) {
1532	hdw->state_encoder_runok = 0;
1533	trace_stbit(name: "state_encoder_runok",val: hdw->state_encoder_runok);
1534	}
1535
1536	/* First prepare firmware loading */
1537	ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1538	ret |= pvr2_hdw_gpio_chg_dir(hdw,msk: 0xffffffff,val: 0x00000088); /*gpio dir*/
1539	ret |= pvr2_hdw_gpio_chg_out(hdw,msk: 0xffffffff,val: 0x00000008); /*gpio output state*/
1540	ret |= pvr2_hdw_cmd_deep_reset(hdw);
1541	ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1542	ret |= pvr2_hdw_gpio_chg_dir(hdw,msk: 0xffffffff,val: 0x00000408); /*gpio dir*/
1543	ret |= pvr2_hdw_gpio_chg_out(hdw,msk: 0xffffffff,val: 0x00000008); /*gpio output state*/
1544	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1545	ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1546	ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1547	ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1548	ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1549	ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1550	ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1551	ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1552	ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1553	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1554	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1555
1556	if (ret) {
1557	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1558	"firmware2 upload prep failed, ret=%d",ret);
1559	release_firmware(fw: fw_entry);
1560	goto done;
1561	}
1562
1563	/* Now send firmware */
1564
1565	fw_len = fw_entry->size;
1566
1567	if (fw_len % sizeof(u32)) {
1568	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1569	"size of %s firmware must be a multiple of %zu bytes",
1570	fw_files[fwidx],sizeof(u32));
1571	release_firmware(fw: fw_entry);
1572	ret = -EINVAL;
1573	goto done;
1574	}
1575
1576	fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577	if (fw_ptr == NULL){
1578	release_firmware(fw: fw_entry);
1579	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580	"failed to allocate memory for firmware2 upload");
1581	ret = -ENOMEM;
1582	goto done;
1583	}
1584
1585	pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1586
1587	fw_done = 0;
1588	for (fw_done = 0; fw_done < fw_len;) {
1589	bcnt = fw_len - fw_done;
1590	if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591	memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592	/* Usbsnoop log shows that we must swap bytes... */
1593	/* Some background info: The data being swapped here is a
1594	firmware image destined for the mpeg encoder chip that
1595	lives at the other end of a USB endpoint. The encoder
1596	chip always talks in 32 bit chunks and its storage is
1597	organized into 32 bit words. However from the file
1598	system to the encoder chip everything is purely a byte
1599	stream. The firmware file's contents are always 32 bit
1600	swapped from what the encoder expects. Thus the need
1601	always exists to swap the bytes regardless of the endian
1602	type of the host processor and therefore swab32() makes
1603	the most sense. */
1604	for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605	((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1606
1607	ret |= usb_bulk_msg(usb_dev: hdw->usb_dev, pipe, data: fw_ptr,len: bcnt,
1608	actual_length: &actual_length, timeout: 1000);
1609	ret |= (actual_length != bcnt);
1610	if (ret) break;
1611	fw_done += bcnt;
1612	}
1613
1614	trace_firmware("upload of %s : %i / %i ",
1615	fw_files[fwidx],fw_done,fw_len);
1616
1617	kfree(objp: fw_ptr);
1618	release_firmware(fw: fw_entry);
1619
1620	if (ret) {
1621	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622	"firmware2 upload transfer failure");
1623	goto done;
1624	}
1625
1626	/* Finish upload */
1627
1628	ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1631
1632	if (ret) {
1633	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634	"firmware2 upload post-proc failure");
1635	}
1636
1637	done:
1638	if (hdw->hdw_desc->signal_routing_scheme ==
1639	PVR2_ROUTING_SCHEME_GOTVIEW) {
1640	/* Ensure that GPIO 11 is set to output for GOTVIEW
1641	hardware. */
1642	pvr2_hdw_gpio_chg_dir(hdw,msk: (1 << 11),val: ~0);
1643	}
1644	return ret;
1645	}
1646
1647
1648	static const char *pvr2_get_state_name(unsigned int st)
1649	{
1650	if (st < ARRAY_SIZE(pvr2_state_names)) {
1651	return pvr2_state_names[st];
1652	}
1653	return "???";
1654	}
1655
1656	static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1657	{
1658	/* Even though we really only care about the video decoder chip at
1659	this point, we'll broadcast stream on/off to all sub-devices
1660	anyway, just in case somebody else wants to hear the
1661	command... */
1662	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1663	(enablefl ? "on" : "off"));
1664	v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1665	v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1666	if (hdw->decoder_client_id) {
1667	/* We get here if the encoder has been noticed. Otherwise
1668	we'll issue a warning to the user (which should
1669	normally never happen). */
1670	return 0;
1671	}
1672	if (!hdw->flag_decoder_missed) {
1673	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1674	"***WARNING*** No decoder present");
1675	hdw->flag_decoder_missed = !0;
1676	trace_stbit(name: "flag_decoder_missed",
1677	val: hdw->flag_decoder_missed);
1678	}
1679	return -EIO;
1680	}
1681
1682
1683	int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1684	{
1685	return hdw->master_state;
1686	}
1687
1688
1689	static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1690	{
1691	if (!hdw->flag_tripped) return 0;
1692	hdw->flag_tripped = 0;
1693	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694	"Clearing driver error status");
1695	return !0;
1696	}
1697
1698
1699	int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1700	{
1701	int fl;
1702	LOCK_TAKE(hdw->big_lock); do {
1703	fl = pvr2_hdw_untrip_unlocked(hdw);
1704	} while (0); LOCK_GIVE(hdw->big_lock);
1705	if (fl) pvr2_hdw_state_sched(hdw);
1706	return 0;
1707	}
1708
1709
1710
1711
1712	int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1713	{
1714	return hdw->state_pipeline_req != 0;
1715	}
1716
1717
1718	int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1719	{
1720	int ret,st;
1721	LOCK_TAKE(hdw->big_lock);
1722	pvr2_hdw_untrip_unlocked(hdw);
1723	if (!enable_flag != !hdw->state_pipeline_req) {
1724	hdw->state_pipeline_req = enable_flag != 0;
1725	pvr2_trace(PVR2_TRACE_START_STOP,
1726	"/*--TRACE_STREAM--*/ %s",
1727	enable_flag ? "enable" : "disable");
1728	}
1729	pvr2_hdw_state_sched(hdw);
1730	LOCK_GIVE(hdw->big_lock);
1731	if ((ret = pvr2_hdw_wait(hdw,state: 0)) < 0) return ret;
1732	if (enable_flag) {
1733	while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1734	if (st != PVR2_STATE_READY) return -EIO;
1735	if ((ret = pvr2_hdw_wait(hdw,state: st)) < 0) return ret;
1736	}
1737	}
1738	return 0;
1739	}
1740
1741
1742	int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1743	{
1744	int fl;
1745	LOCK_TAKE(hdw->big_lock);
1746	if ((fl = (hdw->desired_stream_type != config)) != 0) {
1747	hdw->desired_stream_type = config;
1748	hdw->state_pipeline_config = 0;
1749	trace_stbit(name: "state_pipeline_config",
1750	val: hdw->state_pipeline_config);
1751	pvr2_hdw_state_sched(hdw);
1752	}
1753	LOCK_GIVE(hdw->big_lock);
1754	if (fl) return 0;
1755	return pvr2_hdw_wait(hdw,state: 0);
1756	}
1757
1758
1759	static int get_default_tuner_type(struct pvr2_hdw *hdw)
1760	{
1761	int unit_number = hdw->unit_number;
1762	int tp = -1;
1763	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1764	tp = tuner[unit_number];
1765	}
1766	if (tp < 0) return -EINVAL;
1767	hdw->tuner_type = tp;
1768	hdw->tuner_updated = !0;
1769	return 0;
1770	}
1771
1772
1773	static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1774	{
1775	int unit_number = hdw->unit_number;
1776	int tp = 0;
1777	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1778	tp = video_std[unit_number];
1779	if (tp) return tp;
1780	}
1781	return 0;
1782	}
1783
1784
1785	static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1786	{
1787	int unit_number = hdw->unit_number;
1788	int tp = 0;
1789	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1790	tp = tolerance[unit_number];
1791	}
1792	return tp;
1793	}
1794
1795
1796	static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1797	{
1798	/* Try a harmless request to fetch the eeprom's address over
1799	endpoint 1. See what happens. Only the full FX2 image can
1800	respond to this. If this probe fails then likely the FX2
1801	firmware needs be loaded. */
1802	int result;
1803	LOCK_TAKE(hdw->ctl_lock); do {
1804	hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1805	result = pvr2_send_request_ex(hdw,HZ*1,probe_fl: !0,
1806	write_data: hdw->cmd_buffer,write_len: 1,
1807	read_data: hdw->cmd_buffer,read_len: 1);
1808	if (result < 0) break;
1809	} while(0); LOCK_GIVE(hdw->ctl_lock);
1810	if (result) {
1811	pvr2_trace(PVR2_TRACE_INIT,
1812	"Probe of device endpoint 1 result status %d",
1813	result);
1814	} else {
1815	pvr2_trace(PVR2_TRACE_INIT,
1816	"Probe of device endpoint 1 succeeded");
1817	}
1818	return result == 0;
1819	}
1820
1821	struct pvr2_std_hack {
1822	v4l2_std_id pat; /* Pattern to match */
1823	v4l2_std_id msk; /* Which bits we care about */
1824	v4l2_std_id std; /* What additional standards or default to set */
1825	};
1826
1827	/* This data structure labels specific combinations of standards from
1828	tveeprom that we'll try to recognize. If we recognize one, then assume
1829	a specified default standard to use. This is here because tveeprom only
1830	tells us about available standards not the intended default standard (if
1831	any) for the device in question. We guess the default based on what has
1832	been reported as available. Note that this is only for guessing a
1833	default - which can always be overridden explicitly - and if the user
1834	has otherwise named a default then that default will always be used in
1835	place of this table. */
1836	static const struct pvr2_std_hack std_eeprom_maps[] = {
1837	{ /* PAL(B/G) */
1838	.pat = V4L2_STD_B|V4L2_STD_GH,
1839	.std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1840	},
1841	{ /* NTSC(M) */
1842	.pat = V4L2_STD_MN,
1843	.std = V4L2_STD_NTSC_M,
1844	},
1845	{ /* PAL(I) */
1846	.pat = V4L2_STD_PAL_I,
1847	.std = V4L2_STD_PAL_I,
1848	},
1849	{ /* SECAM(L/L') */
1850	.pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1851	.std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1852	},
1853	{ /* PAL(D/D1/K) */
1854	.pat = V4L2_STD_DK,
1855	.std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1856	},
1857	};
1858
1859	static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1860	{
1861	char buf[40];
1862	unsigned int bcnt;
1863	v4l2_std_id std1,std2,std3;
1864
1865	std1 = get_default_standard(hdw);
1866	std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1867
1868	bcnt = pvr2_std_id_to_str(bufPtr: buf,bufSize: sizeof(buf),id: hdw->std_mask_eeprom);
1869	pvr2_trace(PVR2_TRACE_STD,
1870	"Supported video standard(s) reported available in hardware: %.*s",
1871	bcnt,buf);
1872
1873	hdw->std_mask_avail = hdw->std_mask_eeprom;
1874
1875	std2 = (std1|std3) & ~hdw->std_mask_avail;
1876	if (std2) {
1877	bcnt = pvr2_std_id_to_str(bufPtr: buf,bufSize: sizeof(buf),id: std2);
1878	pvr2_trace(PVR2_TRACE_STD,
1879	"Expanding supported video standards to include: %.*s",
1880	bcnt,buf);
1881	hdw->std_mask_avail |= std2;
1882	}
1883
1884	hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1885
1886	if (std1) {
1887	bcnt = pvr2_std_id_to_str(bufPtr: buf,bufSize: sizeof(buf),id: std1);
1888	pvr2_trace(PVR2_TRACE_STD,
1889	"Initial video standard forced to %.*s",
1890	bcnt,buf);
1891	hdw->std_mask_cur = std1;
1892	hdw->std_dirty = !0;
1893	return;
1894	}
1895	if (std3) {
1896	bcnt = pvr2_std_id_to_str(bufPtr: buf,bufSize: sizeof(buf),id: std3);
1897	pvr2_trace(PVR2_TRACE_STD,
1898	"Initial video standard (determined by device type): %.*s",
1899	bcnt, buf);
1900	hdw->std_mask_cur = std3;
1901	hdw->std_dirty = !0;
1902	return;
1903	}
1904
1905	{
1906	unsigned int idx;
1907	for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1908	if (std_eeprom_maps[idx].msk ?
1909	((std_eeprom_maps[idx].pat ^
1910	hdw->std_mask_eeprom) &
1911	std_eeprom_maps[idx].msk) :
1912	(std_eeprom_maps[idx].pat !=
1913	hdw->std_mask_eeprom)) continue;
1914	bcnt = pvr2_std_id_to_str(bufPtr: buf,bufSize: sizeof(buf),
1915	id: std_eeprom_maps[idx].std);
1916	pvr2_trace(PVR2_TRACE_STD,
1917	"Initial video standard guessed as %.*s",
1918	bcnt,buf);
1919	hdw->std_mask_cur = std_eeprom_maps[idx].std;
1920	hdw->std_dirty = !0;
1921	return;
1922	}
1923	}
1924
1925	}
1926
1927
1928	static unsigned int pvr2_copy_i2c_addr_list(
1929	unsigned short *dst, const unsigned char *src,
1930	unsigned int dst_max)
1931	{
1932	unsigned int cnt = 0;
1933	if (!src) return 0;
1934	while (src[cnt] && (cnt + 1) < dst_max) {
1935	dst[cnt] = src[cnt];
1936	cnt++;
1937	}
1938	dst[cnt] = I2C_CLIENT_END;
1939	return cnt;
1940	}
1941
1942
1943	static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1944	{
1945	/*
1946	Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1947	for cx25840 causes that module to correctly set up its video
1948	scaling. This is really a problem in the cx25840 module itself,
1949	but we work around it here. The problem has not been seen in
1950	ivtv because there VBI is supported and set up. We don't do VBI
1951	here (at least not yet) and thus we never attempted to even set
1952	it up.
1953	*/
1954	struct v4l2_format fmt;
1955	if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1956	/* We're not using a cx25840 so don't enable the hack */
1957	return;
1958	}
1959
1960	pvr2_trace(PVR2_TRACE_INIT,
1961	"Module ID %u: Executing cx25840 VBI hack",
1962	hdw->decoder_client_id);
1963	memset(&fmt, 0, sizeof(fmt));
1964	fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1965	fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1966	fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1967	v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1968	vbi, s_sliced_fmt, &fmt.fmt.sliced);
1969	}
1970
1971
1972	static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1973	const struct pvr2_device_client_desc *cd)
1974	{
1975	const char *fname;
1976	unsigned char mid;
1977	struct v4l2_subdev *sd;
1978	unsigned int i2ccnt;
1979	const unsigned char *p;
1980	/* Arbitrary count - max # i2c addresses we will probe */
1981	unsigned short i2caddr[25];
1982
1983	mid = cd->module_id;
1984	fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1985	if (!fname) {
1986	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1987	"Module ID %u for device %s has no name? The driver might have a configuration problem.",
1988	mid,
1989	hdw->hdw_desc->description);
1990	return -EINVAL;
1991	}
1992	pvr2_trace(PVR2_TRACE_INIT,
1993	"Module ID %u (%s) for device %s being loaded...",
1994	mid, fname,
1995	hdw->hdw_desc->description);
1996
1997	i2ccnt = pvr2_copy_i2c_addr_list(dst: i2caddr, src: cd->i2c_address_list,
1998	ARRAY_SIZE(i2caddr));
1999	if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2000	module_i2c_addresses[mid] : NULL) != NULL)) {
2001	/* Second chance: Try default i2c address list */
2002	i2ccnt = pvr2_copy_i2c_addr_list(dst: i2caddr, src: p,
2003	ARRAY_SIZE(i2caddr));
2004	if (i2ccnt) {
2005	pvr2_trace(PVR2_TRACE_INIT,
2006	"Module ID %u: Using default i2c address list",
2007	mid);
2008	}
2009	}
2010
2011	if (!i2ccnt) {
2012	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2013	"Module ID %u (%s) for device %s: No i2c addresses. The driver might have a configuration problem.",
2014	mid, fname, hdw->hdw_desc->description);
2015	return -EINVAL;
2016	}
2017
2018	if (i2ccnt == 1) {
2019	pvr2_trace(PVR2_TRACE_INIT,
2020	"Module ID %u: Setting up with specified i2c address 0x%x",
2021	mid, i2caddr[0]);
2022	sd = v4l2_i2c_new_subdev(v4l2_dev: &hdw->v4l2_dev, adapter: &hdw->i2c_adap,
2023	client_type: fname, addr: i2caddr[0], NULL);
2024	} else {
2025	pvr2_trace(PVR2_TRACE_INIT,
2026	"Module ID %u: Setting up with address probe list",
2027	mid);
2028	sd = v4l2_i2c_new_subdev(v4l2_dev: &hdw->v4l2_dev, adapter: &hdw->i2c_adap,
2029	client_type: fname, addr: 0, probe_addrs: i2caddr);
2030	}
2031
2032	if (!sd) {
2033	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2034	"Module ID %u (%s) for device %s failed to load. Possible missing sub-device kernel module or initialization failure within module.",
2035	mid, fname, hdw->hdw_desc->description);
2036	return -EIO;
2037	}
2038
2039	/* Tag this sub-device instance with the module ID we know about.
2040	In other places we'll use that tag to determine if the instance
2041	requires special handling. */
2042	sd->grp_id = mid;
2043
2044	pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2045
2046
2047	/* client-specific setup... */
2048	switch (mid) {
2049	case PVR2_CLIENT_ID_CX25840:
2050	case PVR2_CLIENT_ID_SAA7115:
2051	hdw->decoder_client_id = mid;
2052	break;
2053	default: break;
2054	}
2055
2056	return 0;
2057	}
2058
2059
2060	static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2061	{
2062	unsigned int idx;
2063	const struct pvr2_string_table *cm;
2064	const struct pvr2_device_client_table *ct;
2065	int okFl = !0;
2066
2067	cm = &hdw->hdw_desc->client_modules;
2068	for (idx = 0; idx < cm->cnt; idx++) {
2069	request_module(cm->lst[idx]);
2070	}
2071
2072	ct = &hdw->hdw_desc->client_table;
2073	for (idx = 0; idx < ct->cnt; idx++) {
2074	if (pvr2_hdw_load_subdev(hdw, cd: &ct->lst[idx]) < 0) okFl = 0;
2075	}
2076	if (!okFl) {
2077	hdw->flag_modulefail = !0;
2078	pvr2_hdw_render_useless(hdw);
2079	}
2080	}
2081
2082
2083	static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2084	{
2085	int ret;
2086	unsigned int idx;
2087	struct pvr2_ctrl *cptr;
2088	int reloadFl = 0;
2089	if (hdw->hdw_desc->fx2_firmware.cnt) {
2090	if (!reloadFl) {
2091	reloadFl =
2092	(hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2093	== 0);
2094	if (reloadFl) {
2095	pvr2_trace(PVR2_TRACE_INIT,
2096	"USB endpoint config looks strange; possibly firmware needs to be loaded");
2097	}
2098	}
2099	if (!reloadFl) {
2100	reloadFl = !pvr2_hdw_check_firmware(hdw);
2101	if (reloadFl) {
2102	pvr2_trace(PVR2_TRACE_INIT,
2103	"Check for FX2 firmware failed; possibly firmware needs to be loaded");
2104	}
2105	}
2106	if (reloadFl) {
2107	if (pvr2_upload_firmware1(hdw) != 0) {
2108	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2109	"Failure uploading firmware1");
2110	}
2111	return;
2112	}
2113	}
2114	hdw->fw1_state = FW1_STATE_OK;
2115
2116	if (!pvr2_hdw_dev_ok(hdw)) return;
2117
2118	hdw->force_dirty = !0;
2119
2120	if (!hdw->hdw_desc->flag_no_powerup) {
2121	pvr2_hdw_cmd_powerup(hdw);
2122	if (!pvr2_hdw_dev_ok(hdw)) return;
2123	}
2124
2125	/* Take the IR chip out of reset, if appropriate */
2126	if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2127	pvr2_issue_simple_cmd(hdw,
2128	FX2CMD_HCW_ZILOG_RESET |
2129	(1 << 8) |
2130	((0) << 16));
2131	}
2132
2133	/* This step MUST happen after the earlier powerup step */
2134	pvr2_i2c_core_init(hdw);
2135	if (!pvr2_hdw_dev_ok(hdw)) return;
2136
2137	/* Reset demod only on Hauppauge 160xxx platform */
2138	if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
2139	(le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
2140	le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
2141	pr_info("%s(): resetting 160xxx demod\n", __func__);
2142	/* TODO: not sure this is proper place to reset once only */
2143	pvr2_issue_simple_cmd(hdw,
2144	FX2CMD_HCW_DEMOD_RESET_PIN |
2145	(1 << 8) |
2146	((0) << 16));
2147	usleep_range(min: 10000, max: 10500);
2148	pvr2_issue_simple_cmd(hdw,
2149	FX2CMD_HCW_DEMOD_RESET_PIN |
2150	(1 << 8) |
2151	((1) << 16));
2152	usleep_range(min: 10000, max: 10500);
2153	}
2154
2155	pvr2_hdw_load_modules(hdw);
2156	if (!pvr2_hdw_dev_ok(hdw)) return;
2157
2158	v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2159
2160	for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2161	cptr = hdw->controls + idx;
2162	if (cptr->info->skip_init) continue;
2163	if (!cptr->info->set_value) continue;
2164	cptr->info->set_value(cptr,~0,cptr->info->default_value);
2165	}
2166
2167	pvr2_hdw_cx25840_vbi_hack(hdw);
2168
2169	/* Set up special default values for the television and radio
2170	frequencies here. It's not really important what these defaults
2171	are, but I set them to something usable in the Chicago area just
2172	to make driver testing a little easier. */
2173
2174	hdw->freqValTelevision = default_tv_freq;
2175	hdw->freqValRadio = default_radio_freq;
2176
2177	// Do not use pvr2_reset_ctl_endpoints() here. It is not
2178	// thread-safe against the normal pvr2_send_request() mechanism.
2179	// (We should make it thread safe).
2180
2181	if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2182	ret = pvr2_hdw_get_eeprom_addr(hdw);
2183	if (!pvr2_hdw_dev_ok(hdw)) return;
2184	if (ret < 0) {
2185	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2186	"Unable to determine location of eeprom, skipping");
2187	} else {
2188	hdw->eeprom_addr = ret;
2189	pvr2_eeprom_analyze(hdw);
2190	if (!pvr2_hdw_dev_ok(hdw)) return;
2191	}
2192	} else {
2193	hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2194	hdw->tuner_updated = !0;
2195	hdw->std_mask_eeprom = V4L2_STD_ALL;
2196	}
2197
2198	if (hdw->serial_number) {
2199	idx = scnprintf(buf: hdw->identifier, size: sizeof(hdw->identifier) - 1,
2200	fmt: "sn-%lu", hdw->serial_number);
2201	} else if (hdw->unit_number >= 0) {
2202	idx = scnprintf(buf: hdw->identifier, size: sizeof(hdw->identifier) - 1,
2203	fmt: "unit-%c",
2204	hdw->unit_number + 'a');
2205	} else {
2206	idx = scnprintf(buf: hdw->identifier, size: sizeof(hdw->identifier) - 1,
2207	fmt: "unit-??");
2208	}
2209	hdw->identifier[idx] = 0;
2210
2211	pvr2_hdw_setup_std(hdw);
2212
2213	if (!get_default_tuner_type(hdw)) {
2214	pvr2_trace(PVR2_TRACE_INIT,
2215	"pvr2_hdw_setup: Tuner type overridden to %d",
2216	hdw->tuner_type);
2217	}
2218
2219
2220	if (!pvr2_hdw_dev_ok(hdw)) return;
2221
2222	if (hdw->hdw_desc->signal_routing_scheme ==
2223	PVR2_ROUTING_SCHEME_GOTVIEW) {
2224	/* Ensure that GPIO 11 is set to output for GOTVIEW
2225	hardware. */
2226	pvr2_hdw_gpio_chg_dir(hdw,msk: (1 << 11),val: ~0);
2227	}
2228
2229	pvr2_hdw_commit_setup(hdw);
2230
2231	hdw->vid_stream = pvr2_stream_create();
2232	if (!pvr2_hdw_dev_ok(hdw)) return;
2233	pvr2_trace(PVR2_TRACE_INIT,
2234	"pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2235	if (hdw->vid_stream) {
2236	idx = get_default_error_tolerance(hdw);
2237	if (idx) {
2238	pvr2_trace(PVR2_TRACE_INIT,
2239	"pvr2_hdw_setup: video stream %p setting tolerance %u",
2240	hdw->vid_stream,idx);
2241	}
2242	pvr2_stream_setup(hdw->vid_stream,dev: hdw->usb_dev,
2243	PVR2_VID_ENDPOINT,tolerance: idx);
2244	}
2245
2246	if (!pvr2_hdw_dev_ok(hdw)) return;
2247
2248	hdw->flag_init_ok = !0;
2249
2250	pvr2_hdw_state_sched(hdw);
2251	}
2252
2253
2254	/* Set up the structure and attempt to put the device into a usable state.
2255	This can be a time-consuming operation, which is why it is not done
2256	internally as part of the create() step. */
2257	static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2258	{
2259	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2260	do {
2261	pvr2_hdw_setup_low(hdw);
2262	pvr2_trace(PVR2_TRACE_INIT,
2263	"pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2264	hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2265	if (pvr2_hdw_dev_ok(hdw)) {
2266	if (hdw->flag_init_ok) {
2267	pvr2_trace(
2268	PVR2_TRACE_INFO,
2269	"Device initialization completed successfully.");
2270	break;
2271	}
2272	if (hdw->fw1_state == FW1_STATE_RELOAD) {
2273	pvr2_trace(
2274	PVR2_TRACE_INFO,
2275	"Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
2276	break;
2277	}
2278	pvr2_trace(
2279	PVR2_TRACE_ERROR_LEGS,
2280	"Device initialization was not successful.");
2281	if (hdw->fw1_state == FW1_STATE_MISSING) {
2282	pvr2_trace(
2283	PVR2_TRACE_ERROR_LEGS,
2284	"Giving up since device microcontroller firmware appears to be missing.");
2285	break;
2286	}
2287	}
2288	if (hdw->flag_modulefail) {
2289	pvr2_trace(
2290	PVR2_TRACE_ERROR_LEGS,
2291	"***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
2292	pvr2_trace(
2293	PVR2_TRACE_ERROR_LEGS,
2294	"You need to resolve the failing condition before this driver can function. There should be some earlier messages giving more information about the problem.");
2295	break;
2296	}
2297	if (procreload) {
2298	pvr2_trace(
2299	PVR2_TRACE_ERROR_LEGS,
2300	"Attempting pvrusb2 recovery by reloading primary firmware.");
2301	pvr2_trace(
2302	PVR2_TRACE_ERROR_LEGS,
2303	"If this works, device should disconnect and reconnect in a sane state.");
2304	hdw->fw1_state = FW1_STATE_UNKNOWN;
2305	pvr2_upload_firmware1(hdw);
2306	} else {
2307	pvr2_trace(
2308	PVR2_TRACE_ERROR_LEGS,
2309	"***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
2310	pvr2_trace(
2311	PVR2_TRACE_ERROR_LEGS,
2312	"You might need to power cycle the pvrusb2 device in order to recover.");
2313	}
2314	} while (0);
2315	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2316	}
2317
2318
2319	/* Perform second stage initialization. Set callback pointer first so that
2320	we can avoid a possible initialization race (if the kernel thread runs
2321	before the callback has been set). */
2322	int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2323	void (*callback_func)(void *),
2324	void *callback_data)
2325	{
2326	LOCK_TAKE(hdw->big_lock); do {
2327	if (hdw->flag_disconnected) {
2328	/* Handle a race here: If we're already
2329	disconnected by this point, then give up. If we
2330	get past this then we'll remain connected for
2331	the duration of initialization since the entire
2332	initialization sequence is now protected by the
2333	big_lock. */
2334	break;
2335	}
2336	hdw->state_data = callback_data;
2337	hdw->state_func = callback_func;
2338	pvr2_hdw_setup(hdw);
2339	} while (0); LOCK_GIVE(hdw->big_lock);
2340	return hdw->flag_init_ok;
2341	}
2342
2343
2344	/* Create, set up, and return a structure for interacting with the
2345	underlying hardware. */
2346	struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2347	const struct usb_device_id *devid)
2348	{
2349	unsigned int idx,cnt1,cnt2,m;
2350	struct pvr2_hdw *hdw = NULL;
2351	int valid_std_mask;
2352	struct pvr2_ctrl *cptr;
2353	struct usb_device *usb_dev;
2354	const struct pvr2_device_desc *hdw_desc;
2355	__u8 ifnum;
2356	struct v4l2_queryctrl qctrl;
2357	struct pvr2_ctl_info *ciptr;
2358
2359	usb_dev = interface_to_usbdev(intf);
2360
2361	hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2362
2363	if (hdw_desc == NULL) {
2364	pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
2365	pvr2_trace(PVR2_TRACE_INIT,
2366	"If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver");
2367	goto fail;
2368	}
2369
2370	hdw = kzalloc(size: sizeof(*hdw),GFP_KERNEL);
2371	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2372	hdw,hdw_desc->description);
2373	pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2374	hdw_desc->description);
2375	if (hdw_desc->flag_is_experimental) {
2376	pvr2_trace(PVR2_TRACE_INFO, "**********");
2377	pvr2_trace(PVR2_TRACE_INFO,
2378	"***WARNING*** Support for this device (%s) is experimental.",
2379	hdw_desc->description);
2380	pvr2_trace(PVR2_TRACE_INFO,
2381	"Important functionality might not be entirely working.");
2382	pvr2_trace(PVR2_TRACE_INFO,
2383	"Please consider contacting the driver author to help with further stabilization of the driver.");
2384	pvr2_trace(PVR2_TRACE_INFO, "**********");
2385	}
2386	if (!hdw) goto fail;
2387
2388	timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
2389
2390	timer_setup(&hdw->decoder_stabilization_timer,
2391	pvr2_hdw_decoder_stabilization_timeout, 0);
2392
2393	timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2394	0);
2395
2396	timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
2397
2398	hdw->master_state = PVR2_STATE_DEAD;
2399
2400	init_waitqueue_head(&hdw->state_wait_data);
2401
2402	hdw->tuner_signal_stale = !0;
2403	cx2341x_fill_defaults(p: &hdw->enc_ctl_state);
2404
2405	/* Calculate which inputs are OK */
2406	m = 0;
2407	if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2408	if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2409	m |= 1 << PVR2_CVAL_INPUT_DTV;
2410	}
2411	if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2412	if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2413	if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2414	hdw->input_avail_mask = m;
2415	hdw->input_allowed_mask = hdw->input_avail_mask;
2416
2417	/* If not a hybrid device, pathway_state never changes. So
2418	initialize it here to what it should forever be. */
2419	if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2420	hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2421	} else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2422	hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2423	}
2424
2425	hdw->control_cnt = CTRLDEF_COUNT;
2426	hdw->control_cnt += MPEGDEF_COUNT;
2427	hdw->controls = kcalloc(n: hdw->control_cnt, size: sizeof(struct pvr2_ctrl),
2428	GFP_KERNEL);
2429	if (!hdw->controls) goto fail;
2430	hdw->hdw_desc = hdw_desc;
2431	hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2432	for (idx = 0; idx < hdw->control_cnt; idx++) {
2433	cptr = hdw->controls + idx;
2434	cptr->hdw = hdw;
2435	}
2436	for (idx = 0; idx < 32; idx++) {
2437	hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2438	}
2439	for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2440	cptr = hdw->controls + idx;
2441	cptr->info = control_defs+idx;
2442	}
2443
2444	/* Ensure that default input choice is a valid one. */
2445	m = hdw->input_avail_mask;
2446	if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2447	if (!((1UL << idx) & m)) continue;
2448	hdw->input_val = idx;
2449	break;
2450	}
2451
2452	/* Define and configure additional controls from cx2341x module. */
2453	hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2454	size: sizeof(*(hdw->mpeg_ctrl_info)),
2455	GFP_KERNEL);
2456	if (!hdw->mpeg_ctrl_info) goto fail;
2457	for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2458	cptr = hdw->controls + idx + CTRLDEF_COUNT;
2459	ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2460	ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2461	ciptr->name = mpeg_ids[idx].strid;
2462	ciptr->v4l_id = mpeg_ids[idx].id;
2463	ciptr->skip_init = !0;
2464	ciptr->get_value = ctrl_cx2341x_get;
2465	ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2466	ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2467	if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2468	qctrl.id = ciptr->v4l_id;
2469	cx2341x_ctrl_query(params: &hdw->enc_ctl_state,qctrl: &qctrl);
2470	if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2471	ciptr->set_value = ctrl_cx2341x_set;
2472	}
2473	strscpy(hdw->mpeg_ctrl_info[idx].desc, qctrl.name,
2474	sizeof(hdw->mpeg_ctrl_info[idx].desc));
2475	ciptr->default_value = qctrl.default_value;
2476	switch (qctrl.type) {
2477	default:
2478	case V4L2_CTRL_TYPE_INTEGER:
2479	ciptr->type = pvr2_ctl_int;
2480	ciptr->def.type_int.min_value = qctrl.minimum;
2481	ciptr->def.type_int.max_value = qctrl.maximum;
2482	break;
2483	case V4L2_CTRL_TYPE_BOOLEAN:
2484	ciptr->type = pvr2_ctl_bool;
2485	break;
2486	case V4L2_CTRL_TYPE_MENU:
2487	ciptr->type = pvr2_ctl_enum;
2488	ciptr->def.type_enum.value_names =
2489	cx2341x_ctrl_get_menu(p: &hdw->enc_ctl_state,
2490	id: ciptr->v4l_id);
2491	for (cnt1 = 0;
2492	ciptr->def.type_enum.value_names[cnt1] != NULL;
2493	cnt1++) { }
2494	ciptr->def.type_enum.count = cnt1;
2495	break;
2496	}
2497	cptr->info = ciptr;
2498	}
2499
2500	// Initialize control data regarding video standard masks
2501	valid_std_mask = pvr2_std_get_usable();
2502	for (idx = 0; idx < 32; idx++) {
2503	if (!(valid_std_mask & (1UL << idx))) continue;
2504	cnt1 = pvr2_std_id_to_str(
2505	bufPtr: hdw->std_mask_names[idx],
2506	bufSize: sizeof(hdw->std_mask_names[idx])-1,
2507	id: 1UL << idx);
2508	hdw->std_mask_names[idx][cnt1] = 0;
2509	}
2510	cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2511	if (cptr) {
2512	memcpy(&hdw->std_info_avail,cptr->info,
2513	sizeof(hdw->std_info_avail));
2514	cptr->info = &hdw->std_info_avail;
2515	hdw->std_info_avail.def.type_bitmask.bit_names =
2516	hdw->std_mask_ptrs;
2517	hdw->std_info_avail.def.type_bitmask.valid_bits =
2518	valid_std_mask;
2519	}
2520	cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2521	if (cptr) {
2522	memcpy(&hdw->std_info_cur,cptr->info,
2523	sizeof(hdw->std_info_cur));
2524	cptr->info = &hdw->std_info_cur;
2525	hdw->std_info_cur.def.type_bitmask.bit_names =
2526	hdw->std_mask_ptrs;
2527	hdw->std_info_cur.def.type_bitmask.valid_bits =
2528	valid_std_mask;
2529	}
2530	cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2531	if (cptr) {
2532	memcpy(&hdw->std_info_detect,cptr->info,
2533	sizeof(hdw->std_info_detect));
2534	cptr->info = &hdw->std_info_detect;
2535	hdw->std_info_detect.def.type_bitmask.bit_names =
2536	hdw->std_mask_ptrs;
2537	hdw->std_info_detect.def.type_bitmask.valid_bits =
2538	valid_std_mask;
2539	}
2540
2541	hdw->cropcap_stale = !0;
2542	hdw->eeprom_addr = -1;
2543	hdw->unit_number = -1;
2544	hdw->v4l_minor_number_video = -1;
2545	hdw->v4l_minor_number_vbi = -1;
2546	hdw->v4l_minor_number_radio = -1;
2547	hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2548	if (!hdw->ctl_write_buffer) goto fail;
2549	hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2550	if (!hdw->ctl_read_buffer) goto fail;
2551	hdw->ctl_write_urb = usb_alloc_urb(iso_packets: 0,GFP_KERNEL);
2552	if (!hdw->ctl_write_urb) goto fail;
2553	hdw->ctl_read_urb = usb_alloc_urb(iso_packets: 0,GFP_KERNEL);
2554	if (!hdw->ctl_read_urb) goto fail;
2555
2556	if (v4l2_device_register(dev: &intf->dev, v4l2_dev: &hdw->v4l2_dev) != 0) {
2557	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2558	"Error registering with v4l core, giving up");
2559	goto fail;
2560	}
2561	mutex_lock(&pvr2_unit_mtx);
2562	do {
2563	for (idx = 0; idx < PVR_NUM; idx++) {
2564	if (unit_pointers[idx]) continue;
2565	hdw->unit_number = idx;
2566	unit_pointers[idx] = hdw;
2567	break;
2568	}
2569	} while (0);
2570	mutex_unlock(lock: &pvr2_unit_mtx);
2571
2572	INIT_WORK(&hdw->workpoll, pvr2_hdw_worker_poll);
2573
2574	if (hdw->unit_number == -1)
2575	goto fail;
2576
2577	cnt1 = 0;
2578	cnt2 = scnprintf(buf: hdw->name+cnt1,size: sizeof(hdw->name)-cnt1,fmt: "pvrusb2");
2579	cnt1 += cnt2;
2580	if (hdw->unit_number >= 0) {
2581	cnt2 = scnprintf(buf: hdw->name+cnt1,size: sizeof(hdw->name)-cnt1,fmt: "_%c",
2582	('a' + hdw->unit_number));
2583	cnt1 += cnt2;
2584	}
2585	if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2586	hdw->name[cnt1] = 0;
2587
2588	pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2589	hdw->unit_number,hdw->name);
2590
2591	hdw->tuner_type = -1;
2592	hdw->flag_ok = !0;
2593
2594	hdw->usb_intf = intf;
2595	hdw->usb_dev = usb_dev;
2596
2597	usb_make_path(dev: hdw->usb_dev, buf: hdw->bus_info, size: sizeof(hdw->bus_info));
2598
2599	ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2600	usb_set_interface(dev: hdw->usb_dev,ifnum,alternate: 0);
2601
2602	mutex_init(&hdw->ctl_lock_mutex);
2603	mutex_init(&hdw->big_lock_mutex);
2604
2605	return hdw;
2606	fail:
2607	if (hdw) {
2608	timer_shutdown_sync(timer: &hdw->quiescent_timer);
2609	timer_shutdown_sync(timer: &hdw->decoder_stabilization_timer);
2610	timer_shutdown_sync(timer: &hdw->encoder_run_timer);
2611	timer_shutdown_sync(timer: &hdw->encoder_wait_timer);
2612	flush_work(work: &hdw->workpoll);
2613	v4l2_device_unregister(v4l2_dev: &hdw->v4l2_dev);
2614	usb_free_urb(urb: hdw->ctl_read_urb);
2615	usb_free_urb(urb: hdw->ctl_write_urb);
2616	kfree(objp: hdw->ctl_read_buffer);
2617	kfree(objp: hdw->ctl_write_buffer);
2618	kfree(objp: hdw->controls);
2619	kfree(objp: hdw->mpeg_ctrl_info);
2620	kfree(objp: hdw);
2621	}
2622	return NULL;
2623	}
2624
2625
2626	/* Remove _all_ associations between this driver and the underlying USB
2627	layer. */
2628	static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2629	{
2630	if (hdw->flag_disconnected) return;
2631	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2632	if (hdw->ctl_read_urb) {
2633	usb_kill_urb(urb: hdw->ctl_read_urb);
2634	usb_free_urb(urb: hdw->ctl_read_urb);
2635	hdw->ctl_read_urb = NULL;
2636	}
2637	if (hdw->ctl_write_urb) {
2638	usb_kill_urb(urb: hdw->ctl_write_urb);
2639	usb_free_urb(urb: hdw->ctl_write_urb);
2640	hdw->ctl_write_urb = NULL;
2641	}
2642	if (hdw->ctl_read_buffer) {
2643	kfree(objp: hdw->ctl_read_buffer);
2644	hdw->ctl_read_buffer = NULL;
2645	}
2646	if (hdw->ctl_write_buffer) {
2647	kfree(objp: hdw->ctl_write_buffer);
2648	hdw->ctl_write_buffer = NULL;
2649	}
2650	hdw->flag_disconnected = !0;
2651	/* If we don't do this, then there will be a dangling struct device
2652	reference to our disappearing device persisting inside the V4L
2653	core... */
2654	v4l2_device_disconnect(v4l2_dev: &hdw->v4l2_dev);
2655	hdw->usb_dev = NULL;
2656	hdw->usb_intf = NULL;
2657	pvr2_hdw_render_useless(hdw);
2658	}
2659
2660	void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2661	{
2662	vdev->v4l2_dev = &hdw->v4l2_dev;
2663	}
2664
2665	/* Destroy hardware interaction structure */
2666	void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2667	{
2668	if (!hdw) return;
2669	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2670	flush_work(work: &hdw->workpoll);
2671	timer_shutdown_sync(timer: &hdw->quiescent_timer);
2672	timer_shutdown_sync(timer: &hdw->decoder_stabilization_timer);
2673	timer_shutdown_sync(timer: &hdw->encoder_run_timer);
2674	timer_shutdown_sync(timer: &hdw->encoder_wait_timer);
2675	if (hdw->fw_buffer) {
2676	kfree(objp: hdw->fw_buffer);
2677	hdw->fw_buffer = NULL;
2678	}
2679	if (hdw->vid_stream) {
2680	pvr2_stream_destroy(hdw->vid_stream);
2681	hdw->vid_stream = NULL;
2682	}
2683	v4l2_device_unregister(v4l2_dev: &hdw->v4l2_dev);
2684	pvr2_hdw_disconnect(hdw);
2685	mutex_lock(&pvr2_unit_mtx);
2686	do {
2687	if ((hdw->unit_number >= 0) &&
2688	(hdw->unit_number < PVR_NUM) &&
2689	(unit_pointers[hdw->unit_number] == hdw)) {
2690	unit_pointers[hdw->unit_number] = NULL;
2691	}
2692	} while (0);
2693	mutex_unlock(lock: &pvr2_unit_mtx);
2694	kfree(objp: hdw->controls);
2695	kfree(objp: hdw->mpeg_ctrl_info);
2696	kfree(objp: hdw);
2697	}
2698
2699
2700	int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2701	{
2702	return (hdw && hdw->flag_ok);
2703	}
2704
2705
2706	/* Called when hardware has been unplugged */
2707	void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2708	{
2709	pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2710	LOCK_TAKE(hdw->big_lock);
2711	pvr2_i2c_core_done(hdw);
2712	LOCK_TAKE(hdw->ctl_lock);
2713	pvr2_hdw_remove_usb_stuff(hdw);
2714	LOCK_GIVE(hdw->ctl_lock);
2715	LOCK_GIVE(hdw->big_lock);
2716	}
2717
2718
2719	/* Get the number of defined controls */
2720	unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2721	{
2722	return hdw->control_cnt;
2723	}
2724
2725
2726	/* Retrieve a control handle given its index (0..count-1) */
2727	struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2728	unsigned int idx)
2729	{
2730	if (idx >= hdw->control_cnt) return NULL;
2731	return hdw->controls + idx;
2732	}
2733
2734
2735	/* Retrieve a control handle given its index (0..count-1) */
2736	struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2737	unsigned int ctl_id)
2738	{
2739	struct pvr2_ctrl *cptr;
2740	unsigned int idx;
2741	int i;
2742
2743	/* This could be made a lot more efficient, but for now... */
2744	for (idx = 0; idx < hdw->control_cnt; idx++) {
2745	cptr = hdw->controls + idx;
2746	i = cptr->info->internal_id;
2747	if (i && (i == ctl_id)) return cptr;
2748	}
2749	return NULL;
2750	}
2751
2752
2753	/* Given a V4L ID, retrieve the control structure associated with it. */
2754	struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2755	{
2756	struct pvr2_ctrl *cptr;
2757	unsigned int idx;
2758	int i;
2759
2760	/* This could be made a lot more efficient, but for now... */
2761	for (idx = 0; idx < hdw->control_cnt; idx++) {
2762	cptr = hdw->controls + idx;
2763	i = cptr->info->v4l_id;
2764	if (i && (i == ctl_id)) return cptr;
2765	}
2766	return NULL;
2767	}
2768
2769
2770	/* Given a V4L ID for its immediate predecessor, retrieve the control
2771	structure associated with it. */
2772	struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2773	unsigned int ctl_id)
2774	{
2775	struct pvr2_ctrl *cptr,*cp2;
2776	unsigned int idx;
2777	int i;
2778
2779	/* This could be made a lot more efficient, but for now... */
2780	cp2 = NULL;
2781	for (idx = 0; idx < hdw->control_cnt; idx++) {
2782	cptr = hdw->controls + idx;
2783	i = cptr->info->v4l_id;
2784	if (!i) continue;
2785	if (i <= ctl_id) continue;
2786	if (cp2 && (cp2->info->v4l_id < i)) continue;
2787	cp2 = cptr;
2788	}
2789	return cp2;
2790	return NULL;
2791	}
2792
2793
2794	static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2795	{
2796	switch (tp) {
2797	case pvr2_ctl_int: return "integer";
2798	case pvr2_ctl_enum: return "enum";
2799	case pvr2_ctl_bool: return "boolean";
2800	case pvr2_ctl_bitmask: return "bitmask";
2801	}
2802	return "";
2803	}
2804
2805
2806	static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2807	const char *name, int val)
2808	{
2809	struct v4l2_control ctrl;
2810	struct v4l2_subdev *sd;
2811
2812	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2813	memset(&ctrl, 0, sizeof(ctrl));
2814	ctrl.id = id;
2815	ctrl.value = val;
2816
2817	v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2818	v4l2_s_ctrl(NULL, hdl: sd->ctrl_handler, ctrl: &ctrl);
2819	}
2820
2821	#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2822	if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2823	pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2824	}
2825
2826	static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2827	{
2828	v4l2_std_id std;
2829	std = (v4l2_std_id)hdw->std_mask_avail;
2830	v4l2_device_call_all(&hdw->v4l2_dev, 0,
2831	video, querystd, &std);
2832	return std;
2833	}
2834
2835	/* Execute whatever commands are required to update the state of all the
2836	sub-devices so that they match our current control values. */
2837	static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2838	{
2839	struct v4l2_subdev *sd;
2840	unsigned int id;
2841	pvr2_subdev_update_func fp;
2842
2843	pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2844
2845	if (hdw->tuner_updated || hdw->force_dirty) {
2846	struct tuner_setup setup;
2847	pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2848	hdw->tuner_type);
2849	if (((int)(hdw->tuner_type)) >= 0) {
2850	memset(&setup, 0, sizeof(setup));
2851	setup.addr = ADDR_UNSET;
2852	setup.type = hdw->tuner_type;
2853	setup.mode_mask = T_RADIO | T_ANALOG_TV;
2854	v4l2_device_call_all(&hdw->v4l2_dev, 0,
2855	tuner, s_type_addr, &setup);
2856	}
2857	}
2858
2859	if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2860	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2861	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2862	v4l2_device_call_all(&hdw->v4l2_dev, 0,
2863	tuner, s_radio);
2864	} else {
2865	v4l2_std_id vs;
2866	vs = hdw->std_mask_cur;
2867	v4l2_device_call_all(&hdw->v4l2_dev, 0,
2868	video, s_std, vs);
2869	pvr2_hdw_cx25840_vbi_hack(hdw);
2870	}
2871	hdw->tuner_signal_stale = !0;
2872	hdw->cropcap_stale = !0;
2873	}
2874
2875	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2876	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2877	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2878	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2879	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2880	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2881	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2882	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2883	PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2884
2885	if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2886	struct v4l2_tuner vt;
2887	memset(&vt, 0, sizeof(vt));
2888	vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2889	V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2890	vt.audmode = hdw->audiomode_val;
2891	v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2892	}
2893
2894	if (hdw->freqDirty || hdw->force_dirty) {
2895	unsigned long fv;
2896	struct v4l2_frequency freq;
2897	fv = pvr2_hdw_get_cur_freq(hdw);
2898	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2899	if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2900	memset(&freq, 0, sizeof(freq));
2901	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2902	/* ((fv * 1000) / 62500) */
2903	freq.frequency = (fv * 2) / 125;
2904	} else {
2905	freq.frequency = fv / 62500;
2906	}
2907	/* tuner-core currently doesn't seem to care about this, but
2908	let's set it anyway for completeness. */
2909	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2910	freq.type = V4L2_TUNER_RADIO;
2911	} else {
2912	freq.type = V4L2_TUNER_ANALOG_TV;
2913	}
2914	freq.tuner = 0;
2915	v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2916	s_frequency, &freq);
2917	}
2918
2919	if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2920	struct v4l2_subdev_format format = {
2921	.which = V4L2_SUBDEV_FORMAT_ACTIVE,
2922	};
2923
2924	format.format.width = hdw->res_hor_val;
2925	format.format.height = hdw->res_ver_val;
2926	format.format.code = MEDIA_BUS_FMT_FIXED;
2927	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2928	format.format.width, format.format.height);
2929	v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2930	NULL, &format);
2931	}
2932
2933	if (hdw->srate_dirty || hdw->force_dirty) {
2934	u32 val;
2935	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2936	hdw->srate_val);
2937	switch (hdw->srate_val) {
2938	default:
2939	case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2940	val = 48000;
2941	break;
2942	case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2943	val = 44100;
2944	break;
2945	case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2946	val = 32000;
2947	break;
2948	}
2949	v4l2_device_call_all(&hdw->v4l2_dev, 0,
2950	audio, s_clock_freq, val);
2951	}
2952
2953	/* Unable to set crop parameters; there is apparently no equivalent
2954	for VIDIOC_S_CROP */
2955
2956	v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2957	id = sd->grp_id;
2958	if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2959	fp = pvr2_module_update_functions[id];
2960	if (!fp) continue;
2961	(*fp)(hdw, sd);
2962	}
2963
2964	if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2965	pvr2_hdw_status_poll(hdw);
2966	}
2967	}
2968
2969
2970	/* Figure out if we need to commit control changes. If so, mark internal
2971	state flags to indicate this fact and return true. Otherwise do nothing
2972	else and return false. */
2973	static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2974	{
2975	unsigned int idx;
2976	struct pvr2_ctrl *cptr;
2977	int value;
2978	int commit_flag = hdw->force_dirty;
2979	char buf[100];
2980	unsigned int bcnt,ccnt;
2981
2982	for (idx = 0; idx < hdw->control_cnt; idx++) {
2983	cptr = hdw->controls + idx;
2984	if (!cptr->info->is_dirty) continue;
2985	if (!cptr->info->is_dirty(cptr)) continue;
2986	commit_flag = !0;
2987
2988	if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2989	bcnt = scnprintf(buf,size: sizeof(buf),fmt: "\"%s\" <-- ",
2990	cptr->info->name);
2991	value = 0;
2992	cptr->info->get_value(cptr,&value);
2993	pvr2_ctrl_value_to_sym_internal(cptr,mask: ~0,val: value,
2994	buf: buf+bcnt,
2995	maxlen: sizeof(buf)-bcnt,len: &ccnt);
2996	bcnt += ccnt;
2997	bcnt += scnprintf(buf: buf+bcnt,size: sizeof(buf)-bcnt,fmt: " <%s>",
2998	get_ctrl_typename(tp: cptr->info->type));
2999	pvr2_trace(PVR2_TRACE_CTL,
3000	"/*--TRACE_COMMIT--*/ %.*s",
3001	bcnt,buf);
3002	}
3003
3004	if (!commit_flag) {
3005	/* Nothing has changed */
3006	return 0;
3007	}
3008
3009	hdw->state_pipeline_config = 0;
3010	trace_stbit(name: "state_pipeline_config",val: hdw->state_pipeline_config);
3011	pvr2_hdw_state_sched(hdw);
3012
3013	return !0;
3014	}
3015
3016
3017	/* Perform all operations needed to commit all control changes. This must
3018	be performed in synchronization with the pipeline state and is thus
3019	expected to be called as part of the driver's worker thread. Return
3020	true if commit successful, otherwise return false to indicate that
3021	commit isn't possible at this time. */
3022	static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3023	{
3024	unsigned int idx;
3025	struct pvr2_ctrl *cptr;
3026	int disruptive_change;
3027
3028	if (hdw->input_dirty && hdw->state_pathway_ok &&
3029	(((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3030	PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3031	hdw->pathway_state)) {
3032	/* Change of mode being asked for... */
3033	hdw->state_pathway_ok = 0;
3034	trace_stbit(name: "state_pathway_ok", val: hdw->state_pathway_ok);
3035	}
3036	if (!hdw->state_pathway_ok) {
3037	/* Can't commit anything until pathway is ok. */
3038	return 0;
3039	}
3040
3041	/* Handle some required side effects when the video standard is
3042	changed.... */
3043	if (hdw->std_dirty) {
3044	int nvres;
3045	int gop_size;
3046	if (hdw->std_mask_cur & V4L2_STD_525_60) {
3047	nvres = 480;
3048	gop_size = 15;
3049	} else {
3050	nvres = 576;
3051	gop_size = 12;
3052	}
3053	/* Rewrite the vertical resolution to be appropriate to the
3054	video standard that has been selected. */
3055	if (nvres != hdw->res_ver_val) {
3056	hdw->res_ver_val = nvres;
3057	hdw->res_ver_dirty = !0;
3058	}
3059	/* Rewrite the GOP size to be appropriate to the video
3060	standard that has been selected. */
3061	if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3062	struct v4l2_ext_controls cs;
3063	struct v4l2_ext_control c1;
3064	memset(&cs, 0, sizeof(cs));
3065	memset(&c1, 0, sizeof(c1));
3066	cs.controls = &c1;
3067	cs.count = 1;
3068	c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3069	c1.value = gop_size;
3070	cx2341x_ext_ctrls(params: &hdw->enc_ctl_state, busy: 0, ctrls: &cs,
3071	VIDIOC_S_EXT_CTRLS);
3072	}
3073	}
3074
3075	/* The broadcast decoder can only scale down, so if
3076	* res_*_dirty && crop window < output format ==> enlarge crop.
3077	*
3078	* The mpeg encoder receives fields of res_hor_val dots and
3079	* res_ver_val halflines. Limits: hor<=720, ver<=576.
3080	*/
3081	if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3082	hdw->cropw_val = hdw->res_hor_val;
3083	hdw->cropw_dirty = !0;
3084	} else if (hdw->cropw_dirty) {
3085	hdw->res_hor_dirty = !0; /* must rescale */
3086	hdw->res_hor_val = min(720, hdw->cropw_val);
3087	}
3088	if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3089	hdw->croph_val = hdw->res_ver_val;
3090	hdw->croph_dirty = !0;
3091	} else if (hdw->croph_dirty) {
3092	int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3093	hdw->res_ver_dirty = !0;
3094	hdw->res_ver_val = min(nvres, hdw->croph_val);
3095	}
3096
3097	/* If any of the below has changed, then we can't do the update
3098	while the pipeline is running. Pipeline must be paused first
3099	and decoder -> encoder connection be made quiescent before we
3100	can proceed. */
3101	disruptive_change =
3102	(hdw->std_dirty ||
3103	hdw->enc_unsafe_stale ||
3104	hdw->srate_dirty ||
3105	hdw->res_ver_dirty ||
3106	hdw->res_hor_dirty ||
3107	hdw->cropw_dirty ||
3108	hdw->croph_dirty ||
3109	hdw->input_dirty ||
3110	(hdw->active_stream_type != hdw->desired_stream_type));
3111	if (disruptive_change && !hdw->state_pipeline_idle) {
3112	/* Pipeline is not idle; we can't proceed. Arrange to
3113	cause pipeline to stop so that we can try this again
3114	later.... */
3115	hdw->state_pipeline_pause = !0;
3116	return 0;
3117	}
3118
3119	if (hdw->srate_dirty) {
3120	/* Write new sample rate into control structure since
3121	* the master copy is stale. We must track srate
3122	* separate from the mpeg control structure because
3123	* other logic also uses this value. */
3124	struct v4l2_ext_controls cs;
3125	struct v4l2_ext_control c1;
3126	memset(&cs,0,sizeof(cs));
3127	memset(&c1,0,sizeof(c1));
3128	cs.controls = &c1;
3129	cs.count = 1;
3130	c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3131	c1.value = hdw->srate_val;
3132	cx2341x_ext_ctrls(params: &hdw->enc_ctl_state, busy: 0, ctrls: &cs,VIDIOC_S_EXT_CTRLS);
3133	}
3134
3135	if (hdw->active_stream_type != hdw->desired_stream_type) {
3136	/* Handle any side effects of stream config here */
3137	hdw->active_stream_type = hdw->desired_stream_type;
3138	}
3139
3140	if (hdw->hdw_desc->signal_routing_scheme ==
3141	PVR2_ROUTING_SCHEME_GOTVIEW) {
3142	u32 b;
3143	/* Handle GOTVIEW audio switching */
3144	pvr2_hdw_gpio_get_out(hdw,&b);
3145	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3146	/* Set GPIO 11 */
3147	pvr2_hdw_gpio_chg_out(hdw,msk: (1 << 11),val: ~0);
3148	} else {
3149	/* Clear GPIO 11 */
3150	pvr2_hdw_gpio_chg_out(hdw,msk: (1 << 11),val: 0);
3151	}
3152	}
3153
3154	/* Check and update state for all sub-devices. */
3155	pvr2_subdev_update(hdw);
3156
3157	hdw->tuner_updated = 0;
3158	hdw->force_dirty = 0;
3159	for (idx = 0; idx < hdw->control_cnt; idx++) {
3160	cptr = hdw->controls + idx;
3161	if (!cptr->info->clear_dirty) continue;
3162	cptr->info->clear_dirty(cptr);
3163	}
3164
3165	if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3166	hdw->state_encoder_run) {
3167	/* If encoder isn't running or it can't be touched, then
3168	this will get worked out later when we start the
3169	encoder. */
3170	if (pvr2_encoder_adjust(hdw) < 0) return !0;
3171	}
3172
3173	hdw->state_pipeline_config = !0;
3174	/* Hardware state may have changed in a way to cause the cropping
3175	capabilities to have changed. So mark it stale, which will
3176	cause a later re-fetch. */
3177	trace_stbit(name: "state_pipeline_config",val: hdw->state_pipeline_config);
3178	return !0;
3179	}
3180
3181
3182	int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3183	{
3184	int fl;
3185	LOCK_TAKE(hdw->big_lock);
3186	fl = pvr2_hdw_commit_setup(hdw);
3187	LOCK_GIVE(hdw->big_lock);
3188	if (!fl) return 0;
3189	return pvr2_hdw_wait(hdw,state: 0);
3190	}
3191
3192
3193	static void pvr2_hdw_worker_poll(struct work_struct *work)
3194	{
3195	int fl = 0;
3196	struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3197	LOCK_TAKE(hdw->big_lock); do {
3198	fl = pvr2_hdw_state_eval(hdw);
3199	} while (0); LOCK_GIVE(hdw->big_lock);
3200	if (fl && hdw->state_func) {
3201	hdw->state_func(hdw->state_data);
3202	}
3203	}
3204
3205
3206	static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3207	{
3208	return wait_event_interruptible(
3209	hdw->state_wait_data,
3210	(hdw->state_stale == 0) &&
3211	(!state || (hdw->master_state != state)));
3212	}
3213
3214
3215	/* Return name for this driver instance */
3216	const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3217	{
3218	return hdw->name;
3219	}
3220
3221
3222	const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3223	{
3224	return hdw->hdw_desc->description;
3225	}
3226
3227
3228	const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3229	{
3230	return hdw->hdw_desc->shortname;
3231	}
3232
3233
3234	int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3235	{
3236	int result;
3237	LOCK_TAKE(hdw->ctl_lock); do {
3238	hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3239	result = pvr2_send_request(hdw,
3240	write_ptr: hdw->cmd_buffer,write_len: 1,
3241	read_ptr: hdw->cmd_buffer,read_len: 1);
3242	if (result < 0) break;
3243	result = (hdw->cmd_buffer[0] != 0);
3244	} while(0); LOCK_GIVE(hdw->ctl_lock);
3245	return result;
3246	}
3247
3248
3249	/* Execute poll of tuner status */
3250	void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3251	{
3252	LOCK_TAKE(hdw->big_lock); do {
3253	pvr2_hdw_status_poll(hdw);
3254	} while (0); LOCK_GIVE(hdw->big_lock);
3255	}
3256
3257
3258	static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3259	{
3260	if (!hdw->cropcap_stale) {
3261	return 0;
3262	}
3263	pvr2_hdw_status_poll(hdw);
3264	if (hdw->cropcap_stale) {
3265	return -EIO;
3266	}
3267	return 0;
3268	}
3269
3270
3271	/* Return information about cropping capabilities */
3272	int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3273	{
3274	int stat = 0;
3275	LOCK_TAKE(hdw->big_lock);
3276	stat = pvr2_hdw_check_cropcap(hdw);
3277	if (!stat) {
3278	memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3279	}
3280	LOCK_GIVE(hdw->big_lock);
3281	return stat;
3282	}
3283
3284
3285	/* Return information about the tuner */
3286	int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3287	{
3288	LOCK_TAKE(hdw->big_lock);
3289	do {
3290	if (hdw->tuner_signal_stale) {
3291	pvr2_hdw_status_poll(hdw);
3292	}
3293	memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3294	} while (0);
3295	LOCK_GIVE(hdw->big_lock);
3296	return 0;
3297	}
3298
3299
3300	/* Get handle to video output stream */
3301	struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3302	{
3303	return hp->vid_stream;
3304	}
3305
3306
3307	void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3308	{
3309	int nr = pvr2_hdw_get_unit_number(hdw);
3310	LOCK_TAKE(hdw->big_lock);
3311	do {
3312	pr_info("pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
3313	v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3314	pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3315	cx2341x_log_status(p: &hdw->enc_ctl_state, prefix: "pvrusb2");
3316	pvr2_hdw_state_log_state(hdw);
3317	pr_info("pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
3318	} while (0);
3319	LOCK_GIVE(hdw->big_lock);
3320	}
3321
3322
3323	/* Grab EEPROM contents, needed for direct method. */
3324	#define EEPROM_SIZE 8192
3325	#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3326	static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3327	{
3328	struct i2c_msg msg[2];
3329	u8 *eeprom;
3330	u8 iadd[2];
3331	u8 addr;
3332	u16 eepromSize;
3333	unsigned int offs;
3334	int ret;
3335	int mode16 = 0;
3336	unsigned pcnt,tcnt;
3337	eeprom = kzalloc(EEPROM_SIZE, GFP_KERNEL);
3338	if (!eeprom) {
3339	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3340	"Failed to allocate memory required to read eeprom");
3341	return NULL;
3342	}
3343
3344	trace_eeprom("Value for eeprom addr from controller was 0x%x",
3345	hdw->eeprom_addr);
3346	addr = hdw->eeprom_addr;
3347	/* Seems that if the high bit is set, then the *real* eeprom
3348	address is shifted right now bit position (noticed this in
3349	newer PVR USB2 hardware) */
3350	if (addr & 0x80) addr >>= 1;
3351
3352	/* FX2 documentation states that a 16bit-addressed eeprom is
3353	expected if the I2C address is an odd number (yeah, this is
3354	strange but it's what they do) */
3355	mode16 = (addr & 1);
3356	eepromSize = (mode16 ? EEPROM_SIZE : 256);
3357	trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
3358	eepromSize, addr,
3359	mode16 ? 16 : 8);
3360
3361	msg[0].addr = addr;
3362	msg[0].flags = 0;
3363	msg[0].len = mode16 ? 2 : 1;
3364	msg[0].buf = iadd;
3365	msg[1].addr = addr;
3366	msg[1].flags = I2C_M_RD;
3367
3368	/* We have to do the actual eeprom data fetch ourselves, because
3369	(1) we're only fetching part of the eeprom, and (2) if we were
3370	getting the whole thing our I2C driver can't grab it in one
3371	pass - which is what tveeprom is otherwise going to attempt */
3372	for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3373	pcnt = 16;
3374	if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3375	offs = tcnt + (eepromSize - EEPROM_SIZE);
3376	if (mode16) {
3377	iadd[0] = offs >> 8;
3378	iadd[1] = offs;
3379	} else {
3380	iadd[0] = offs;
3381	}
3382	msg[1].len = pcnt;
3383	msg[1].buf = eeprom+tcnt;
3384	if ((ret = i2c_transfer(adap: &hdw->i2c_adap,
3385	msgs: msg,ARRAY_SIZE(msg))) != 2) {
3386	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3387	"eeprom fetch set offs err=%d",ret);
3388	kfree(objp: eeprom);
3389	return NULL;
3390	}
3391	}
3392	return eeprom;
3393	}
3394
3395
3396	void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3397	int mode,
3398	int enable_flag)
3399	{
3400	int ret;
3401	u16 address;
3402	unsigned int pipe;
3403	LOCK_TAKE(hdw->big_lock);
3404	do {
3405	if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3406
3407	if (!enable_flag) {
3408	pvr2_trace(PVR2_TRACE_FIRMWARE,
3409	"Cleaning up after CPU firmware fetch");
3410	kfree(objp: hdw->fw_buffer);
3411	hdw->fw_buffer = NULL;
3412	hdw->fw_size = 0;
3413	if (hdw->fw_cpu_flag) {
3414	/* Now release the CPU. It will disconnect
3415	and reconnect later. */
3416	pvr2_hdw_cpureset_assert(hdw,0);
3417	}
3418	break;
3419	}
3420
3421	hdw->fw_cpu_flag = (mode != 2);
3422	if (hdw->fw_cpu_flag) {
3423	hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3424	pvr2_trace(PVR2_TRACE_FIRMWARE,
3425	"Preparing to suck out CPU firmware (size=%u)",
3426	hdw->fw_size);
3427	hdw->fw_buffer = kzalloc(size: hdw->fw_size,GFP_KERNEL);
3428	if (!hdw->fw_buffer) {
3429	hdw->fw_size = 0;
3430	break;
3431	}
3432
3433	/* We have to hold the CPU during firmware upload. */
3434	pvr2_hdw_cpureset_assert(hdw,1);
3435
3436	/* download the firmware from address 0000-1fff in 2048
3437	(=0x800) bytes chunk. */
3438
3439	pvr2_trace(PVR2_TRACE_FIRMWARE,
3440	"Grabbing CPU firmware");
3441	pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3442	for(address = 0; address < hdw->fw_size;
3443	address += 0x800) {
3444	ret = usb_control_msg(dev: hdw->usb_dev,pipe,
3445	request: 0xa0,requesttype: 0xc0,
3446	value: address,index: 0,
3447	data: hdw->fw_buffer+address,
3448	size: 0x800,timeout: 1000);
3449	if (ret < 0) break;
3450	}
3451
3452	pvr2_trace(PVR2_TRACE_FIRMWARE,
3453	"Done grabbing CPU firmware");
3454	} else {
3455	pvr2_trace(PVR2_TRACE_FIRMWARE,
3456	"Sucking down EEPROM contents");
3457	hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3458	if (!hdw->fw_buffer) {
3459	pvr2_trace(PVR2_TRACE_FIRMWARE,
3460	"EEPROM content suck failed.");
3461	break;
3462	}
3463	hdw->fw_size = EEPROM_SIZE;
3464	pvr2_trace(PVR2_TRACE_FIRMWARE,
3465	"Done sucking down EEPROM contents");
3466	}
3467	} while (0);
3468	LOCK_GIVE(hdw->big_lock);
3469	}
3470
3471
3472	/* Return true if we're in a mode for retrieval CPU firmware */
3473	int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3474	{
3475	return hdw->fw_buffer != NULL;
3476	}
3477
3478
3479	int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3480	char *buf,unsigned int cnt)
3481	{
3482	int ret = -EINVAL;
3483	LOCK_TAKE(hdw->big_lock);
3484	do {
3485	if (!buf) break;
3486	if (!cnt) break;
3487
3488	if (!hdw->fw_buffer) {
3489	ret = -EIO;
3490	break;
3491	}
3492
3493	if (offs >= hdw->fw_size) {
3494	pvr2_trace(PVR2_TRACE_FIRMWARE,
3495	"Read firmware data offs=%d EOF",
3496	offs);
3497	ret = 0;
3498	break;
3499	}
3500
3501	if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3502
3503	memcpy(buf,hdw->fw_buffer+offs,cnt);
3504
3505	pvr2_trace(PVR2_TRACE_FIRMWARE,
3506	"Read firmware data offs=%d cnt=%d",
3507	offs,cnt);
3508	ret = cnt;
3509	} while (0);
3510	LOCK_GIVE(hdw->big_lock);
3511
3512	return ret;
3513	}
3514
3515
3516	int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3517	enum pvr2_v4l_type index)
3518	{
3519	switch (index) {
3520	case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3521	case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3522	case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3523	default: return -1;
3524	}
3525	}
3526
3527
3528	/* Store a v4l minor device number */
3529	void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3530	enum pvr2_v4l_type index,int v)
3531	{
3532	switch (index) {
3533	case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3534	case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3535	case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3536	default: break;
3537	}
3538	}
3539
3540
3541	static void pvr2_ctl_write_complete(struct urb *urb)
3542	{
3543	struct pvr2_hdw *hdw = urb->context;
3544	hdw->ctl_write_pend_flag = 0;
3545	if (hdw->ctl_read_pend_flag) return;
3546	complete(&hdw->ctl_done);
3547	}
3548
3549
3550	static void pvr2_ctl_read_complete(struct urb *urb)
3551	{
3552	struct pvr2_hdw *hdw = urb->context;
3553	hdw->ctl_read_pend_flag = 0;
3554	if (hdw->ctl_write_pend_flag) return;
3555	complete(&hdw->ctl_done);
3556	}
3557
3558	struct hdw_timer {
3559	struct timer_list timer;
3560	struct pvr2_hdw *hdw;
3561	};
3562
3563	static void pvr2_ctl_timeout(struct timer_list *t)
3564	{
3565	struct hdw_timer *timer = from_timer(timer, t, timer);
3566	struct pvr2_hdw *hdw = timer->hdw;
3567
3568	if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3569	hdw->ctl_timeout_flag = !0;
3570	if (hdw->ctl_write_pend_flag)
3571	usb_unlink_urb(urb: hdw->ctl_write_urb);
3572	if (hdw->ctl_read_pend_flag)
3573	usb_unlink_urb(urb: hdw->ctl_read_urb);
3574	}
3575	}
3576
3577
3578	/* Issue a command and get a response from the device. This extended
3579	version includes a probe flag (which if set means that device errors
3580	should not be logged or treated as fatal) and a timeout in jiffies.
3581	This can be used to non-lethally probe the health of endpoint 1. */
3582	static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3583	unsigned int timeout,int probe_fl,
3584	void *write_data,unsigned int write_len,
3585	void *read_data,unsigned int read_len)
3586	{
3587	unsigned int idx;
3588	int status = 0;
3589	struct hdw_timer timer = {
3590	.hdw = hdw,
3591	};
3592
3593	if (!hdw->ctl_lock_held) {
3594	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3595	"Attempted to execute control transfer without lock!!");
3596	return -EDEADLK;
3597	}
3598	if (!hdw->flag_ok && !probe_fl) {
3599	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3600	"Attempted to execute control transfer when device not ok");
3601	return -EIO;
3602	}
3603	if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3604	if (!probe_fl) {
3605	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3606	"Attempted to execute control transfer when USB is disconnected");
3607	}
3608	return -ENOTTY;
3609	}
3610
3611	/* Ensure that we have sane parameters */
3612	if (!write_data) write_len = 0;
3613	if (!read_data) read_len = 0;
3614	if (write_len > PVR2_CTL_BUFFSIZE) {
3615	pvr2_trace(
3616	PVR2_TRACE_ERROR_LEGS,
3617	"Attempted to execute %d byte control-write transfer (limit=%d)",
3618	write_len,PVR2_CTL_BUFFSIZE);
3619	return -EINVAL;
3620	}
3621	if (read_len > PVR2_CTL_BUFFSIZE) {
3622	pvr2_trace(
3623	PVR2_TRACE_ERROR_LEGS,
3624	"Attempted to execute %d byte control-read transfer (limit=%d)",
3625	write_len,PVR2_CTL_BUFFSIZE);
3626	return -EINVAL;
3627	}
3628	if ((!write_len) && (!read_len)) {
3629	pvr2_trace(
3630	PVR2_TRACE_ERROR_LEGS,
3631	"Attempted to execute null control transfer?");
3632	return -EINVAL;
3633	}
3634
3635
3636	hdw->cmd_debug_state = 1;
3637	if (write_len && write_data)
3638	hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3639	else
3640	hdw->cmd_debug_code = 0;
3641	hdw->cmd_debug_write_len = write_len;
3642	hdw->cmd_debug_read_len = read_len;
3643
3644	/* Initialize common stuff */
3645	init_completion(x: &hdw->ctl_done);
3646	hdw->ctl_timeout_flag = 0;
3647	hdw->ctl_write_pend_flag = 0;
3648	hdw->ctl_read_pend_flag = 0;
3649	timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0);
3650	timer.timer.expires = jiffies + timeout;
3651
3652	if (write_len && write_data) {
3653	hdw->cmd_debug_state = 2;
3654	/* Transfer write data to internal buffer */
3655	for (idx = 0; idx < write_len; idx++) {
3656	hdw->ctl_write_buffer[idx] =
3657	((unsigned char *)write_data)[idx];
3658	}
3659	/* Initiate a write request */
3660	usb_fill_bulk_urb(urb: hdw->ctl_write_urb,
3661	dev: hdw->usb_dev,
3662	usb_sndbulkpipe(hdw->usb_dev,
3663	PVR2_CTL_WRITE_ENDPOINT),
3664	transfer_buffer: hdw->ctl_write_buffer,
3665	buffer_length: write_len,
3666	complete_fn: pvr2_ctl_write_complete,
3667	context: hdw);
3668	hdw->ctl_write_urb->actual_length = 0;
3669	hdw->ctl_write_pend_flag = !0;
3670	if (usb_urb_ep_type_check(urb: hdw->ctl_write_urb)) {
3671	pvr2_trace(
3672	PVR2_TRACE_ERROR_LEGS,
3673	"Invalid write control endpoint");
3674	return -EINVAL;
3675	}
3676	status = usb_submit_urb(urb: hdw->ctl_write_urb,GFP_KERNEL);
3677	if (status < 0) {
3678	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3679	"Failed to submit write-control URB status=%d",
3680	status);
3681	hdw->ctl_write_pend_flag = 0;
3682	goto done;
3683	}
3684	}
3685
3686	if (read_len) {
3687	hdw->cmd_debug_state = 3;
3688	memset(hdw->ctl_read_buffer,0x43,read_len);
3689	/* Initiate a read request */
3690	usb_fill_bulk_urb(urb: hdw->ctl_read_urb,
3691	dev: hdw->usb_dev,
3692	usb_rcvbulkpipe(hdw->usb_dev,
3693	PVR2_CTL_READ_ENDPOINT),
3694	transfer_buffer: hdw->ctl_read_buffer,
3695	buffer_length: read_len,
3696	complete_fn: pvr2_ctl_read_complete,
3697	context: hdw);
3698	hdw->ctl_read_urb->actual_length = 0;
3699	hdw->ctl_read_pend_flag = !0;
3700	if (usb_urb_ep_type_check(urb: hdw->ctl_read_urb)) {
3701	pvr2_trace(
3702	PVR2_TRACE_ERROR_LEGS,
3703	"Invalid read control endpoint");
3704	return -EINVAL;
3705	}
3706	status = usb_submit_urb(urb: hdw->ctl_read_urb,GFP_KERNEL);
3707	if (status < 0) {
3708	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3709	"Failed to submit read-control URB status=%d",
3710	status);
3711	hdw->ctl_read_pend_flag = 0;
3712	goto done;
3713	}
3714	}
3715
3716	/* Start timer */
3717	add_timer(timer: &timer.timer);
3718
3719	/* Now wait for all I/O to complete */
3720	hdw->cmd_debug_state = 4;
3721	while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3722	wait_for_completion(&hdw->ctl_done);
3723	}
3724	hdw->cmd_debug_state = 5;
3725
3726	/* Stop timer */
3727	del_timer_sync(timer: &timer.timer);
3728
3729	hdw->cmd_debug_state = 6;
3730	status = 0;
3731
3732	if (hdw->ctl_timeout_flag) {
3733	status = -ETIMEDOUT;
3734	if (!probe_fl) {
3735	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3736	"Timed out control-write");
3737	}
3738	goto done;
3739	}
3740
3741	if (write_len) {
3742	/* Validate results of write request */
3743	if ((hdw->ctl_write_urb->status != 0) &&
3744	(hdw->ctl_write_urb->status != -ENOENT) &&
3745	(hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3746	(hdw->ctl_write_urb->status != -ECONNRESET)) {
3747	/* USB subsystem is reporting some kind of failure
3748	on the write */
3749	status = hdw->ctl_write_urb->status;
3750	if (!probe_fl) {
3751	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3752	"control-write URB failure, status=%d",
3753	status);
3754	}
3755	goto done;
3756	}
3757	if (hdw->ctl_write_urb->actual_length < write_len) {
3758	/* Failed to write enough data */
3759	status = -EIO;
3760	if (!probe_fl) {
3761	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762	"control-write URB short, expected=%d got=%d",
3763	write_len,
3764	hdw->ctl_write_urb->actual_length);
3765	}
3766	goto done;
3767	}
3768	}
3769	if (read_len && read_data) {
3770	/* Validate results of read request */
3771	if ((hdw->ctl_read_urb->status != 0) &&
3772	(hdw->ctl_read_urb->status != -ENOENT) &&
3773	(hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3774	(hdw->ctl_read_urb->status != -ECONNRESET)) {
3775	/* USB subsystem is reporting some kind of failure
3776	on the read */
3777	status = hdw->ctl_read_urb->status;
3778	if (!probe_fl) {
3779	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3780	"control-read URB failure, status=%d",
3781	status);
3782	}
3783	goto done;
3784	}
3785	if (hdw->ctl_read_urb->actual_length < read_len) {
3786	/* Failed to read enough data */
3787	status = -EIO;
3788	if (!probe_fl) {
3789	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3790	"control-read URB short, expected=%d got=%d",
3791	read_len,
3792	hdw->ctl_read_urb->actual_length);
3793	}
3794	goto done;
3795	}
3796	/* Transfer retrieved data out from internal buffer */
3797	for (idx = 0; idx < read_len; idx++) {
3798	((unsigned char *)read_data)[idx] =
3799	hdw->ctl_read_buffer[idx];
3800	}
3801	}
3802
3803	done:
3804
3805	hdw->cmd_debug_state = 0;
3806	if ((status < 0) && (!probe_fl)) {
3807	pvr2_hdw_render_useless(hdw);
3808	}
3809	destroy_timer_on_stack(timer: &timer.timer);
3810
3811	return status;
3812	}
3813
3814
3815	int pvr2_send_request(struct pvr2_hdw *hdw,
3816	void *write_data,unsigned int write_len,
3817	void *read_data,unsigned int read_len)
3818	{
3819	return pvr2_send_request_ex(hdw,HZ*4,probe_fl: 0,
3820	write_data,write_len,
3821	read_data,read_len);
3822	}
3823
3824
3825	static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3826	{
3827	int ret;
3828	unsigned int cnt = 1;
3829	unsigned int args = 0;
3830	LOCK_TAKE(hdw->ctl_lock);
3831	hdw->cmd_buffer[0] = cmdcode & 0xffu;
3832	args = (cmdcode >> 8) & 0xffu;
3833	args = (args > 2) ? 2 : args;
3834	if (args) {
3835	cnt += args;
3836	hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3837	if (args > 1) {
3838	hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3839	}
3840	}
3841	if (pvrusb2_debug & PVR2_TRACE_INIT) {
3842	unsigned int idx;
3843	unsigned int ccnt,bcnt;
3844	char tbuf[50];
3845	cmdcode &= 0xffu;
3846	bcnt = 0;
3847	ccnt = scnprintf(buf: tbuf+bcnt,
3848	size: sizeof(tbuf)-bcnt,
3849	fmt: "Sending FX2 command 0x%x",cmdcode);
3850	bcnt += ccnt;
3851	for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3852	if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3853	ccnt = scnprintf(buf: tbuf+bcnt,
3854	size: sizeof(tbuf)-bcnt,
3855	fmt: " \"%s\"",
3856	pvr2_fx2cmd_desc[idx].desc);
3857	bcnt += ccnt;
3858	break;
3859	}
3860	}
3861	if (args) {
3862	ccnt = scnprintf(buf: tbuf+bcnt,
3863	size: sizeof(tbuf)-bcnt,
3864	fmt: " (%u",hdw->cmd_buffer[1]);
3865	bcnt += ccnt;
3866	if (args > 1) {
3867	ccnt = scnprintf(buf: tbuf+bcnt,
3868	size: sizeof(tbuf)-bcnt,
3869	fmt: ",%u",hdw->cmd_buffer[2]);
3870	bcnt += ccnt;
3871	}
3872	ccnt = scnprintf(buf: tbuf+bcnt,
3873	size: sizeof(tbuf)-bcnt,
3874	fmt: ")");
3875	bcnt += ccnt;
3876	}
3877	pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3878	}
3879	ret = pvr2_send_request(hdw,write_data: hdw->cmd_buffer,write_len: cnt,NULL,read_len: 0);
3880	LOCK_GIVE(hdw->ctl_lock);
3881	return ret;
3882	}
3883
3884
3885	int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3886	{
3887	int ret;
3888
3889	LOCK_TAKE(hdw->ctl_lock);
3890
3891	hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3892	PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3893	hdw->cmd_buffer[5] = 0;
3894	hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3895	hdw->cmd_buffer[7] = reg & 0xff;
3896
3897
3898	ret = pvr2_send_request(hdw, write_data: hdw->cmd_buffer, write_len: 8, read_data: hdw->cmd_buffer, read_len: 0);
3899
3900	LOCK_GIVE(hdw->ctl_lock);
3901
3902	return ret;
3903	}
3904
3905
3906	static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3907	{
3908	int ret = 0;
3909
3910	LOCK_TAKE(hdw->ctl_lock);
3911
3912	hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3913	hdw->cmd_buffer[1] = 0;
3914	hdw->cmd_buffer[2] = 0;
3915	hdw->cmd_buffer[3] = 0;
3916	hdw->cmd_buffer[4] = 0;
3917	hdw->cmd_buffer[5] = 0;
3918	hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3919	hdw->cmd_buffer[7] = reg & 0xff;
3920
3921	ret |= pvr2_send_request(hdw, write_data: hdw->cmd_buffer, write_len: 8, read_data: hdw->cmd_buffer, read_len: 4);
3922	*data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3923
3924	LOCK_GIVE(hdw->ctl_lock);
3925
3926	return ret;
3927	}
3928
3929
3930	void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3931	{
3932	if (!hdw->flag_ok) return;
3933	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3934	"Device being rendered inoperable");
3935	if (hdw->vid_stream) {
3936	pvr2_stream_setup(hdw->vid_stream,NULL,endpoint: 0,tolerance: 0);
3937	}
3938	hdw->flag_ok = 0;
3939	trace_stbit(name: "flag_ok",val: hdw->flag_ok);
3940	pvr2_hdw_state_sched(hdw);
3941	}
3942
3943
3944	void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3945	{
3946	int ret;
3947	pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3948	ret = usb_lock_device_for_reset(udev: hdw->usb_dev,NULL);
3949	if (ret == 0) {
3950	ret = usb_reset_device(dev: hdw->usb_dev);
3951	usb_unlock_device(hdw->usb_dev);
3952	} else {
3953	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3954	"Failed to lock USB device ret=%d",ret);
3955	}
3956	if (init_pause_msec) {
3957	pvr2_trace(PVR2_TRACE_INFO,
3958	"Waiting %u msec for hardware to settle",
3959	init_pause_msec);
3960	msleep(msecs: init_pause_msec);
3961	}
3962
3963	}
3964
3965
3966	void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3967	{
3968	char *da;
3969	unsigned int pipe;
3970	int ret;
3971
3972	if (!hdw->usb_dev) return;
3973
3974	da = kmalloc(size: 16, GFP_KERNEL);
3975
3976	if (da == NULL) {
3977	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3978	"Unable to allocate memory to control CPU reset");
3979	return;
3980	}
3981
3982	pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3983
3984	da[0] = val ? 0x01 : 0x00;
3985
3986	/* Write the CPUCS register on the 8051. The lsb of the register
3987	is the reset bit; a 1 asserts reset while a 0 clears it. */
3988	pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3989	ret = usb_control_msg(dev: hdw->usb_dev,pipe,request: 0xa0,requesttype: 0x40,value: 0xe600,index: 0,data: da,size: 1,timeout: 1000);
3990	if (ret < 0) {
3991	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3992	"cpureset_assert(%d) error=%d",val,ret);
3993	pvr2_hdw_render_useless(hdw);
3994	}
3995
3996	kfree(objp: da);
3997	}
3998
3999
4000	int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4001	{
4002	return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4003	}
4004
4005
4006	int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4007	{
4008	return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4009	}
4010
4011
4012
4013	int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4014	{
4015	pvr2_trace(PVR2_TRACE_INIT,
4016	"Requesting decoder reset");
4017	if (hdw->decoder_client_id) {
4018	v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4019	core, reset, 0);
4020	pvr2_hdw_cx25840_vbi_hack(hdw);
4021	return 0;
4022	}
4023	pvr2_trace(PVR2_TRACE_INIT,
4024	"Unable to reset decoder: nothing attached");
4025	return -ENOTTY;
4026	}
4027
4028
4029	static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4030	{
4031	hdw->flag_ok = !0;
4032
4033	/* Use this for Hauppauge 160xxx only */
4034	if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
4035	(le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
4036	le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
4037	pr_debug("%s(): resetting demod on Hauppauge 160xxx platform skipped\n",
4038	__func__);
4039	/* Can't reset 160xxx or it will trash Demod tristate */
4040	return pvr2_issue_simple_cmd(hdw,
4041	FX2CMD_HCW_MAKO_SLEEP_PIN |
4042	(1 << 8) |
4043	((onoff ? 1 : 0) << 16));
4044	}
4045
4046	return pvr2_issue_simple_cmd(hdw,
4047	FX2CMD_HCW_DEMOD_RESETIN |
4048	(1 << 8) |
4049	((onoff ? 1 : 0) << 16));
4050	}
4051
4052
4053	static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4054	{
4055	hdw->flag_ok = !0;
4056	return pvr2_issue_simple_cmd(hdw,cmdcode: (onoff ?
4057	FX2CMD_ONAIR_DTV_POWER_ON :
4058	FX2CMD_ONAIR_DTV_POWER_OFF));
4059	}
4060
4061
4062	static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4063	int onoff)
4064	{
4065	return pvr2_issue_simple_cmd(hdw,cmdcode: (onoff ?
4066	FX2CMD_ONAIR_DTV_STREAMING_ON :
4067	FX2CMD_ONAIR_DTV_STREAMING_OFF));
4068	}
4069
4070
4071	static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4072	{
4073	int cmode;
4074	/* Compare digital/analog desired setting with current setting. If
4075	they don't match, fix it... */
4076	cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4077	if (cmode == hdw->pathway_state) {
4078	/* They match; nothing to do */
4079	return;
4080	}
4081
4082	switch (hdw->hdw_desc->digital_control_scheme) {
4083	case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4084	pvr2_hdw_cmd_hcw_demod_reset(hdw,onoff: digitalFl);
4085	if (cmode == PVR2_PATHWAY_ANALOG) {
4086	/* If moving to analog mode, also force the decoder
4087	to reset. If no decoder is attached, then it's
4088	ok to ignore this because if/when the decoder
4089	attaches, it will reset itself at that time. */
4090	pvr2_hdw_cmd_decoder_reset(hdw);
4091	}
4092	break;
4093	case PVR2_DIGITAL_SCHEME_ONAIR:
4094	/* Supposedly we should always have the power on whether in
4095	digital or analog mode. But for now do what appears to
4096	work... */
4097	pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,onoff: digitalFl);
4098	break;
4099	default: break;
4100	}
4101
4102	pvr2_hdw_untrip_unlocked(hdw);
4103	hdw->pathway_state = cmode;
4104	}
4105
4106
4107	static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4108	{
4109	/* change some GPIO data
4110	*
4111	* note: bit d7 of dir appears to control the LED,
4112	* so we shut it off here.
4113	*
4114	*/
4115	if (onoff) {
4116	pvr2_hdw_gpio_chg_dir(hdw, msk: 0xffffffff, val: 0x00000481);
4117	} else {
4118	pvr2_hdw_gpio_chg_dir(hdw, msk: 0xffffffff, val: 0x00000401);
4119	}
4120	pvr2_hdw_gpio_chg_out(hdw, msk: 0xffffffff, val: 0x00000000);
4121	}
4122
4123
4124	typedef void (*led_method_func)(struct pvr2_hdw *,int);
4125
4126	static led_method_func led_methods[] = {
4127	[PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4128	};
4129
4130
4131	/* Toggle LED */
4132	static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4133	{
4134	unsigned int scheme_id;
4135	led_method_func fp;
4136
4137	if ((!onoff) == (!hdw->led_on)) return;
4138
4139	hdw->led_on = onoff != 0;
4140
4141	scheme_id = hdw->hdw_desc->led_scheme;
4142	if (scheme_id < ARRAY_SIZE(led_methods)) {
4143	fp = led_methods[scheme_id];
4144	} else {
4145	fp = NULL;
4146	}
4147
4148	if (fp) (*fp)(hdw,onoff);
4149	}
4150
4151
4152	/* Stop / start video stream transport */
4153	static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4154	{
4155	int ret;
4156
4157	/* If we're in analog mode, then just issue the usual analog
4158	command. */
4159	if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4160	return pvr2_issue_simple_cmd(hdw,
4161	cmdcode: (runFl ?
4162	FX2CMD_STREAMING_ON :
4163	FX2CMD_STREAMING_OFF));
4164	/*Note: Not reached */
4165	}
4166
4167	if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4168	/* Whoops, we don't know what mode we're in... */
4169	return -EINVAL;
4170	}
4171
4172	/* To get here we have to be in digital mode. The mechanism here
4173	is unfortunately different for different vendors. So we switch
4174	on the device's digital scheme attribute in order to figure out
4175	what to do. */
4176	switch (hdw->hdw_desc->digital_control_scheme) {
4177	case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4178	return pvr2_issue_simple_cmd(hdw,
4179	cmdcode: (runFl ?
4180	FX2CMD_HCW_DTV_STREAMING_ON :
4181	FX2CMD_HCW_DTV_STREAMING_OFF));
4182	case PVR2_DIGITAL_SCHEME_ONAIR:
4183	ret = pvr2_issue_simple_cmd(hdw,
4184	cmdcode: (runFl ?
4185	FX2CMD_STREAMING_ON :
4186	FX2CMD_STREAMING_OFF));
4187	if (ret) return ret;
4188	return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,onoff: runFl);
4189	default:
4190	return -EINVAL;
4191	}
4192	}
4193
4194
4195	/* Evaluate whether or not state_pathway_ok can change */
4196	static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4197	{
4198	if (hdw->state_pathway_ok) {
4199	/* Nothing to do if pathway is already ok */
4200	return 0;
4201	}
4202	if (!hdw->state_pipeline_idle) {
4203	/* Not allowed to change anything if pipeline is not idle */
4204	return 0;
4205	}
4206	pvr2_hdw_cmd_modeswitch(hdw,digitalFl: hdw->input_val == PVR2_CVAL_INPUT_DTV);
4207	hdw->state_pathway_ok = !0;
4208	trace_stbit(name: "state_pathway_ok",val: hdw->state_pathway_ok);
4209	return !0;
4210	}
4211
4212
4213	/* Evaluate whether or not state_encoder_ok can change */
4214	static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4215	{
4216	if (hdw->state_encoder_ok) return 0;
4217	if (hdw->flag_tripped) return 0;
4218	if (hdw->state_encoder_run) return 0;
4219	if (hdw->state_encoder_config) return 0;
4220	if (hdw->state_decoder_run) return 0;
4221	if (hdw->state_usbstream_run) return 0;
4222	if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4223	if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4224	} else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4225	return 0;
4226	}
4227
4228	if (pvr2_upload_firmware2(hdw) < 0) {
4229	hdw->flag_tripped = !0;
4230	trace_stbit(name: "flag_tripped",val: hdw->flag_tripped);
4231	return !0;
4232	}
4233	hdw->state_encoder_ok = !0;
4234	trace_stbit(name: "state_encoder_ok",val: hdw->state_encoder_ok);
4235	return !0;
4236	}
4237
4238
4239	/* Evaluate whether or not state_encoder_config can change */
4240	static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4241	{
4242	if (hdw->state_encoder_config) {
4243	if (hdw->state_encoder_ok) {
4244	if (hdw->state_pipeline_req &&
4245	!hdw->state_pipeline_pause) return 0;
4246	}
4247	hdw->state_encoder_config = 0;
4248	hdw->state_encoder_waitok = 0;
4249	trace_stbit(name: "state_encoder_waitok",val: hdw->state_encoder_waitok);
4250	/* paranoia - solve race if timer just completed */
4251	del_timer_sync(timer: &hdw->encoder_wait_timer);
4252	} else {
4253	if (!hdw->state_pathway_ok ||
4254	(hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4255	!hdw->state_encoder_ok ||
4256	!hdw->state_pipeline_idle ||
4257	hdw->state_pipeline_pause ||
4258	!hdw->state_pipeline_req ||
4259	!hdw->state_pipeline_config) {
4260	/* We must reset the enforced wait interval if
4261	anything has happened that might have disturbed
4262	the encoder. This should be a rare case. */
4263	if (timer_pending(timer: &hdw->encoder_wait_timer)) {
4264	del_timer_sync(timer: &hdw->encoder_wait_timer);
4265	}
4266	if (hdw->state_encoder_waitok) {
4267	/* Must clear the state - therefore we did
4268	something to a state bit and must also
4269	return true. */
4270	hdw->state_encoder_waitok = 0;
4271	trace_stbit(name: "state_encoder_waitok",
4272	val: hdw->state_encoder_waitok);
4273	return !0;
4274	}
4275	return 0;
4276	}
4277	if (!hdw->state_encoder_waitok) {
4278	if (!timer_pending(timer: &hdw->encoder_wait_timer)) {
4279	/* waitok flag wasn't set and timer isn't
4280	running. Check flag once more to avoid
4281	a race then start the timer. This is
4282	the point when we measure out a minimal
4283	quiet interval before doing something to
4284	the encoder. */
4285	if (!hdw->state_encoder_waitok) {
4286	hdw->encoder_wait_timer.expires =
4287	jiffies + msecs_to_jiffies(
4288	TIME_MSEC_ENCODER_WAIT);
4289	add_timer(timer: &hdw->encoder_wait_timer);
4290	}
4291	}
4292	/* We can't continue until we know we have been
4293	quiet for the interval measured by this
4294	timer. */
4295	return 0;
4296	}
4297	pvr2_encoder_configure(hdw);
4298	if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4299	}
4300	trace_stbit(name: "state_encoder_config",val: hdw->state_encoder_config);
4301	return !0;
4302	}
4303
4304
4305	/* Return true if the encoder should not be running. */
4306	static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4307	{
4308	if (!hdw->state_encoder_ok) {
4309	/* Encoder isn't healthy at the moment, so stop it. */
4310	return !0;
4311	}
4312	if (!hdw->state_pathway_ok) {
4313	/* Mode is not understood at the moment (i.e. it wants to
4314	change), so encoder must be stopped. */
4315	return !0;
4316	}
4317
4318	switch (hdw->pathway_state) {
4319	case PVR2_PATHWAY_ANALOG:
4320	if (!hdw->state_decoder_run) {
4321	/* We're in analog mode and the decoder is not
4322	running; thus the encoder should be stopped as
4323	well. */
4324	return !0;
4325	}
4326	break;
4327	case PVR2_PATHWAY_DIGITAL:
4328	if (hdw->state_encoder_runok) {
4329	/* This is a funny case. We're in digital mode so
4330	really the encoder should be stopped. However
4331	if it really is running, only kill it after
4332	runok has been set. This gives a chance for the
4333	onair quirk to function (encoder must run
4334	briefly first, at least once, before onair
4335	digital streaming can work). */
4336	return !0;
4337	}
4338	break;
4339	default:
4340	/* Unknown mode; so encoder should be stopped. */
4341	return !0;
4342	}
4343
4344	/* If we get here, we haven't found a reason to stop the
4345	encoder. */
4346	return 0;
4347	}
4348
4349
4350	/* Return true if the encoder should be running. */
4351	static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4352	{
4353	if (!hdw->state_encoder_ok) {
4354	/* Don't run the encoder if it isn't healthy... */
4355	return 0;
4356	}
4357	if (!hdw->state_pathway_ok) {
4358	/* Don't run the encoder if we don't (yet) know what mode
4359	we need to be in... */
4360	return 0;
4361	}
4362
4363	switch (hdw->pathway_state) {
4364	case PVR2_PATHWAY_ANALOG:
4365	if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4366	/* In analog mode, if the decoder is running, then
4367	run the encoder. */
4368	return !0;
4369	}
4370	break;
4371	case PVR2_PATHWAY_DIGITAL:
4372	if ((hdw->hdw_desc->digital_control_scheme ==
4373	PVR2_DIGITAL_SCHEME_ONAIR) &&
4374	!hdw->state_encoder_runok) {
4375	/* This is a quirk. OnAir hardware won't stream
4376	digital until the encoder has been run at least
4377	once, for a minimal period of time (empiricially
4378	measured to be 1/4 second). So if we're on
4379	OnAir hardware and the encoder has never been
4380	run at all, then start the encoder. Normal
4381	state machine logic in the driver will
4382	automatically handle the remaining bits. */
4383	return !0;
4384	}
4385	break;
4386	default:
4387	/* For completeness (unknown mode; encoder won't run ever) */
4388	break;
4389	}
4390	/* If we get here, then we haven't found any reason to run the
4391	encoder, so don't run it. */
4392	return 0;
4393	}
4394
4395
4396	/* Evaluate whether or not state_encoder_run can change */
4397	static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4398	{
4399	if (hdw->state_encoder_run) {
4400	if (!state_check_disable_encoder_run(hdw)) return 0;
4401	if (hdw->state_encoder_ok) {
4402	del_timer_sync(timer: &hdw->encoder_run_timer);
4403	if (pvr2_encoder_stop(hdw) < 0) return !0;
4404	}
4405	hdw->state_encoder_run = 0;
4406	} else {
4407	if (!state_check_enable_encoder_run(hdw)) return 0;
4408	if (pvr2_encoder_start(hdw) < 0) return !0;
4409	hdw->state_encoder_run = !0;
4410	if (!hdw->state_encoder_runok) {
4411	hdw->encoder_run_timer.expires = jiffies +
4412	msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4413	add_timer(timer: &hdw->encoder_run_timer);
4414	}
4415	}
4416	trace_stbit(name: "state_encoder_run",val: hdw->state_encoder_run);
4417	return !0;
4418	}
4419
4420
4421	/* Timeout function for quiescent timer. */
4422	static void pvr2_hdw_quiescent_timeout(struct timer_list *t)
4423	{
4424	struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
4425	hdw->state_decoder_quiescent = !0;
4426	trace_stbit(name: "state_decoder_quiescent",val: hdw->state_decoder_quiescent);
4427	hdw->state_stale = !0;
4428	schedule_work(work: &hdw->workpoll);
4429	}
4430
4431
4432	/* Timeout function for decoder stabilization timer. */
4433	static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t)
4434	{
4435	struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
4436	hdw->state_decoder_ready = !0;
4437	trace_stbit(name: "state_decoder_ready", val: hdw->state_decoder_ready);
4438	hdw->state_stale = !0;
4439	schedule_work(work: &hdw->workpoll);
4440	}
4441
4442
4443	/* Timeout function for encoder wait timer. */
4444	static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t)
4445	{
4446	struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
4447	hdw->state_encoder_waitok = !0;
4448	trace_stbit(name: "state_encoder_waitok",val: hdw->state_encoder_waitok);
4449	hdw->state_stale = !0;
4450	schedule_work(work: &hdw->workpoll);
4451	}
4452
4453
4454	/* Timeout function for encoder run timer. */
4455	static void pvr2_hdw_encoder_run_timeout(struct timer_list *t)
4456	{
4457	struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
4458	if (!hdw->state_encoder_runok) {
4459	hdw->state_encoder_runok = !0;
4460	trace_stbit(name: "state_encoder_runok",val: hdw->state_encoder_runok);
4461	hdw->state_stale = !0;
4462	schedule_work(work: &hdw->workpoll);
4463	}
4464	}
4465
4466
4467	/* Evaluate whether or not state_decoder_run can change */
4468	static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4469	{
4470	if (hdw->state_decoder_run) {
4471	if (hdw->state_encoder_ok) {
4472	if (hdw->state_pipeline_req &&
4473	!hdw->state_pipeline_pause &&
4474	hdw->state_pathway_ok) return 0;
4475	}
4476	if (!hdw->flag_decoder_missed) {
4477	pvr2_decoder_enable(hdw,enablefl: 0);
4478	}
4479	hdw->state_decoder_quiescent = 0;
4480	hdw->state_decoder_run = 0;
4481	/* paranoia - solve race if timer(s) just completed */
4482	del_timer_sync(timer: &hdw->quiescent_timer);
4483	/* Kill the stabilization timer, in case we're killing the
4484	encoder before the previous stabilization interval has
4485	been properly timed. */
4486	del_timer_sync(timer: &hdw->decoder_stabilization_timer);
4487	hdw->state_decoder_ready = 0;
4488	} else {
4489	if (!hdw->state_decoder_quiescent) {
4490	if (!timer_pending(timer: &hdw->quiescent_timer)) {
4491	/* We don't do something about the
4492	quiescent timer until right here because
4493	we also want to catch cases where the
4494	decoder was already not running (like
4495	after initialization) as opposed to
4496	knowing that we had just stopped it.
4497	The second flag check is here to cover a
4498	race - the timer could have run and set
4499	this flag just after the previous check
4500	but before we did the pending check. */
4501	if (!hdw->state_decoder_quiescent) {
4502	hdw->quiescent_timer.expires =
4503	jiffies + msecs_to_jiffies(
4504	TIME_MSEC_DECODER_WAIT);
4505	add_timer(timer: &hdw->quiescent_timer);
4506	}
4507	}
4508	/* Don't allow decoder to start again until it has
4509	been quiesced first. This little detail should
4510	hopefully further stabilize the encoder. */
4511	return 0;
4512	}
4513	if (!hdw->state_pathway_ok ||
4514	(hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4515	!hdw->state_pipeline_req ||
4516	hdw->state_pipeline_pause ||
4517	!hdw->state_pipeline_config ||
4518	!hdw->state_encoder_config ||
4519	!hdw->state_encoder_ok) return 0;
4520	del_timer_sync(timer: &hdw->quiescent_timer);
4521	if (hdw->flag_decoder_missed) return 0;
4522	if (pvr2_decoder_enable(hdw,enablefl: !0) < 0) return 0;
4523	hdw->state_decoder_quiescent = 0;
4524	hdw->state_decoder_ready = 0;
4525	hdw->state_decoder_run = !0;
4526	if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4527	hdw->decoder_stabilization_timer.expires =
4528	jiffies + msecs_to_jiffies(
4529	TIME_MSEC_DECODER_STABILIZATION_WAIT);
4530	add_timer(timer: &hdw->decoder_stabilization_timer);
4531	} else {
4532	hdw->state_decoder_ready = !0;
4533	}
4534	}
4535	trace_stbit(name: "state_decoder_quiescent",val: hdw->state_decoder_quiescent);
4536	trace_stbit(name: "state_decoder_run",val: hdw->state_decoder_run);
4537	trace_stbit(name: "state_decoder_ready", val: hdw->state_decoder_ready);
4538	return !0;
4539	}
4540
4541
4542	/* Evaluate whether or not state_usbstream_run can change */
4543	static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4544	{
4545	if (hdw->state_usbstream_run) {
4546	int fl = !0;
4547	if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4548	fl = (hdw->state_encoder_ok &&
4549	hdw->state_encoder_run);
4550	} else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4551	(hdw->hdw_desc->flag_digital_requires_cx23416)) {
4552	fl = hdw->state_encoder_ok;
4553	}
4554	if (fl &&
4555	hdw->state_pipeline_req &&
4556	!hdw->state_pipeline_pause &&
4557	hdw->state_pathway_ok) {
4558	return 0;
4559	}
4560	pvr2_hdw_cmd_usbstream(hdw,runFl: 0);
4561	hdw->state_usbstream_run = 0;
4562	} else {
4563	if (!hdw->state_pipeline_req ||
4564	hdw->state_pipeline_pause ||
4565	!hdw->state_pathway_ok) return 0;
4566	if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4567	if (!hdw->state_encoder_ok ||
4568	!hdw->state_encoder_run) return 0;
4569	} else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4570	(hdw->hdw_desc->flag_digital_requires_cx23416)) {
4571	if (!hdw->state_encoder_ok) return 0;
4572	if (hdw->state_encoder_run) return 0;
4573	if (hdw->hdw_desc->digital_control_scheme ==
4574	PVR2_DIGITAL_SCHEME_ONAIR) {
4575	/* OnAir digital receivers won't stream
4576	unless the analog encoder has run first.
4577	Why? I have no idea. But don't even
4578	try until we know the analog side is
4579	known to have run. */
4580	if (!hdw->state_encoder_runok) return 0;
4581	}
4582	}
4583	if (pvr2_hdw_cmd_usbstream(hdw,runFl: !0) < 0) return 0;
4584	hdw->state_usbstream_run = !0;
4585	}
4586	trace_stbit(name: "state_usbstream_run",val: hdw->state_usbstream_run);
4587	return !0;
4588	}
4589
4590
4591	/* Attempt to configure pipeline, if needed */
4592	static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4593	{
4594	if (hdw->state_pipeline_config ||
4595	hdw->state_pipeline_pause) return 0;
4596	pvr2_hdw_commit_execute(hdw);
4597	return !0;
4598	}
4599
4600
4601	/* Update pipeline idle and pipeline pause tracking states based on other
4602	inputs. This must be called whenever the other relevant inputs have
4603	changed. */
4604	static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4605	{
4606	unsigned int st;
4607	int updatedFl = 0;
4608	/* Update pipeline state */
4609	st = !(hdw->state_encoder_run ||
4610	hdw->state_decoder_run ||
4611	hdw->state_usbstream_run ||
4612	(!hdw->state_decoder_quiescent));
4613	if (!st != !hdw->state_pipeline_idle) {
4614	hdw->state_pipeline_idle = st;
4615	updatedFl = !0;
4616	}
4617	if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4618	hdw->state_pipeline_pause = 0;
4619	updatedFl = !0;
4620	}
4621	return updatedFl;
4622	}
4623
4624
4625	typedef int (*state_eval_func)(struct pvr2_hdw *);
4626
4627	/* Set of functions to be run to evaluate various states in the driver. */
4628	static const state_eval_func eval_funcs[] = {
4629	state_eval_pathway_ok,
4630	state_eval_pipeline_config,
4631	state_eval_encoder_ok,
4632	state_eval_encoder_config,
4633	state_eval_decoder_run,
4634	state_eval_encoder_run,
4635	state_eval_usbstream_run,
4636	};
4637
4638
4639	/* Process various states and return true if we did anything interesting. */
4640	static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4641	{
4642	unsigned int i;
4643	int state_updated = 0;
4644	int check_flag;
4645
4646	if (!hdw->state_stale) return 0;
4647	if ((hdw->fw1_state != FW1_STATE_OK) ||
4648	!hdw->flag_ok) {
4649	hdw->state_stale = 0;
4650	return !0;
4651	}
4652	/* This loop is the heart of the entire driver. It keeps trying to
4653	evaluate various bits of driver state until nothing changes for
4654	one full iteration. Each "bit of state" tracks some global
4655	aspect of the driver, e.g. whether decoder should run, if
4656	pipeline is configured, usb streaming is on, etc. We separately
4657	evaluate each of those questions based on other driver state to
4658	arrive at the correct running configuration. */
4659	do {
4660	check_flag = 0;
4661	state_update_pipeline_state(hdw);
4662	/* Iterate over each bit of state */
4663	for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4664	if ((*eval_funcs[i])(hdw)) {
4665	check_flag = !0;
4666	state_updated = !0;
4667	state_update_pipeline_state(hdw);
4668	}
4669	}
4670	} while (check_flag && hdw->flag_ok);
4671	hdw->state_stale = 0;
4672	trace_stbit(name: "state_stale",val: hdw->state_stale);
4673	return state_updated;
4674	}
4675
4676
4677	static unsigned int print_input_mask(unsigned int msk,
4678	char *buf,unsigned int acnt)
4679	{
4680	unsigned int idx,ccnt;
4681	unsigned int tcnt = 0;
4682	for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4683	if (!((1UL << idx) & msk)) continue;
4684	ccnt = scnprintf(buf: buf+tcnt,
4685	size: acnt-tcnt,
4686	fmt: "%s%s",
4687	(tcnt ? ", " : ""),
4688	control_values_input[idx]);
4689	tcnt += ccnt;
4690	}
4691	return tcnt;
4692	}
4693
4694
4695	static const char *pvr2_pathway_state_name(int id)
4696	{
4697	switch (id) {
4698	case PVR2_PATHWAY_ANALOG: return "analog";
4699	case PVR2_PATHWAY_DIGITAL: return "digital";
4700	default: return "unknown";
4701	}
4702	}
4703
4704
4705	static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4706	char *buf,unsigned int acnt)
4707	{
4708	switch (which) {
4709	case 0:
4710	return scnprintf(
4711	buf,size: acnt,
4712	fmt: "driver:%s%s%s%s%s <mode=%s>",
4713	(hdw->flag_ok ? " <ok>" : " <fail>"),
4714	(hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4715	(hdw->flag_disconnected ? " <disconnected>" :
4716	" <connected>"),
4717	(hdw->flag_tripped ? " <tripped>" : ""),
4718	(hdw->flag_decoder_missed ? " <no decoder>" : ""),
4719	pvr2_pathway_state_name(id: hdw->pathway_state));
4720
4721	case 1:
4722	return scnprintf(
4723	buf,size: acnt,
4724	fmt: "pipeline:%s%s%s%s",
4725	(hdw->state_pipeline_idle ? " <idle>" : ""),
4726	(hdw->state_pipeline_config ?
4727	" <configok>" : " <stale>"),
4728	(hdw->state_pipeline_req ? " <req>" : ""),
4729	(hdw->state_pipeline_pause ? " <pause>" : ""));
4730	case 2:
4731	return scnprintf(
4732	buf,size: acnt,
4733	fmt: "worker:%s%s%s%s%s%s%s",
4734	(hdw->state_decoder_run ?
4735	(hdw->state_decoder_ready ?
4736	"<decode:run>" : " <decode:start>") :
4737	(hdw->state_decoder_quiescent ?
4738	"" : " <decode:stop>")),
4739	(hdw->state_decoder_quiescent ?
4740	" <decode:quiescent>" : ""),
4741	(hdw->state_encoder_ok ?
4742	"" : " <encode:init>"),
4743	(hdw->state_encoder_run ?
4744	(hdw->state_encoder_runok ?
4745	" <encode:run>" :
4746	" <encode:firstrun>") :
4747	(hdw->state_encoder_runok ?
4748	" <encode:stop>" :
4749	" <encode:virgin>")),
4750	(hdw->state_encoder_config ?
4751	" <encode:configok>" :
4752	(hdw->state_encoder_waitok ?
4753	"" : " <encode:waitok>")),
4754	(hdw->state_usbstream_run ?
4755	" <usb:run>" : " <usb:stop>"),
4756	(hdw->state_pathway_ok ?
4757	" <pathway:ok>" : ""));
4758	case 3:
4759	return scnprintf(
4760	buf,size: acnt,
4761	fmt: "state: %s",
4762	pvr2_get_state_name(st: hdw->master_state));
4763	case 4: {
4764	unsigned int tcnt = 0;
4765	unsigned int ccnt;
4766
4767	ccnt = scnprintf(buf,
4768	size: acnt,
4769	fmt: "Hardware supported inputs: ");
4770	tcnt += ccnt;
4771	tcnt += print_input_mask(msk: hdw->input_avail_mask,
4772	buf: buf+tcnt,
4773	acnt: acnt-tcnt);
4774	if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4775	ccnt = scnprintf(buf: buf+tcnt,
4776	size: acnt-tcnt,
4777	fmt: "; allowed inputs: ");
4778	tcnt += ccnt;
4779	tcnt += print_input_mask(msk: hdw->input_allowed_mask,
4780	buf: buf+tcnt,
4781	acnt: acnt-tcnt);
4782	}
4783	return tcnt;
4784	}
4785	case 5: {
4786	struct pvr2_stream_stats stats;
4787	if (!hdw->vid_stream) break;
4788	pvr2_stream_get_stats(hdw->vid_stream,
4789	&stats,
4790	zero_counts: 0);
4791	return scnprintf(
4792	buf,size: acnt,
4793	fmt: "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
4794	stats.bytes_processed,
4795	stats.buffers_in_queue,
4796	stats.buffers_in_idle,
4797	stats.buffers_in_ready,
4798	stats.buffers_processed,
4799	stats.buffers_failed);
4800	}
4801	case 6: {
4802	unsigned int id = hdw->ir_scheme_active;
4803	return scnprintf(buf, size: acnt, fmt: "ir scheme: id=%d %s", id,
4804	(id >= ARRAY_SIZE(ir_scheme_names) ?
4805	"?" : ir_scheme_names[id]));
4806	}
4807	default: break;
4808	}
4809	return 0;
4810	}
4811
4812
4813	/* Generate report containing info about attached sub-devices and attached
4814	i2c clients, including an indication of which attached i2c clients are
4815	actually sub-devices. */
4816	static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4817	char *buf, unsigned int acnt)
4818	{
4819	struct v4l2_subdev *sd;
4820	unsigned int tcnt = 0;
4821	unsigned int ccnt;
4822	struct i2c_client *client;
4823	const char *p;
4824	unsigned int id;
4825
4826	ccnt = scnprintf(buf, size: acnt, fmt: "Associated v4l2-subdev drivers and I2C clients:\n");
4827	tcnt += ccnt;
4828	v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4829	id = sd->grp_id;
4830	p = NULL;
4831	if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4832	if (p) {
4833	ccnt = scnprintf(buf: buf + tcnt, size: acnt - tcnt, fmt: " %s:", p);
4834	tcnt += ccnt;
4835	} else {
4836	ccnt = scnprintf(buf: buf + tcnt, size: acnt - tcnt,
4837	fmt: " (unknown id=%u):", id);
4838	tcnt += ccnt;
4839	}
4840	client = v4l2_get_subdevdata(sd);
4841	if (client) {
4842	ccnt = scnprintf(buf: buf + tcnt, size: acnt - tcnt,
4843	fmt: " %s @ %02x\n", client->name,
4844	client->addr);
4845	tcnt += ccnt;
4846	} else {
4847	ccnt = scnprintf(buf: buf + tcnt, size: acnt - tcnt,
4848	fmt: " no i2c client\n");
4849	tcnt += ccnt;
4850	}
4851	}
4852	return tcnt;
4853	}
4854
4855
4856	unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4857	char *buf,unsigned int acnt)
4858	{
4859	unsigned int bcnt,ccnt,idx;
4860	bcnt = 0;
4861	LOCK_TAKE(hdw->big_lock);
4862	for (idx = 0; ; idx++) {
4863	ccnt = pvr2_hdw_report_unlocked(hdw,which: idx,buf,acnt);
4864	if (!ccnt) break;
4865	bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4866	if (!acnt) break;
4867	buf[0] = '\n'; ccnt = 1;
4868	bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4869	}
4870	ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4871	bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4872	LOCK_GIVE(hdw->big_lock);
4873	return bcnt;
4874	}
4875
4876
4877	static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4878	{
4879	char buf[256];
4880	unsigned int idx, ccnt;
4881	unsigned int lcnt, ucnt;
4882
4883	for (idx = 0; ; idx++) {
4884	ccnt = pvr2_hdw_report_unlocked(hdw,which: idx,buf,acnt: sizeof(buf));
4885	if (!ccnt) break;
4886	pr_info("%s %.*s\n", hdw->name, ccnt, buf);
4887	}
4888	ccnt = pvr2_hdw_report_clients(hdw, buf, acnt: sizeof(buf));
4889	if (ccnt >= sizeof(buf))
4890	ccnt = sizeof(buf);
4891
4892	ucnt = 0;
4893	while (ucnt < ccnt) {
4894	lcnt = 0;
4895	while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4896	lcnt++;
4897	}
4898	pr_info("%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4899	ucnt += lcnt + 1;
4900	}
4901	}
4902
4903
4904	/* Evaluate and update the driver's current state, taking various actions
4905	as appropriate for the update. */
4906	static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4907	{
4908	unsigned int st;
4909	int state_updated = 0;
4910	int callback_flag = 0;
4911	int analog_mode;
4912
4913	pvr2_trace(PVR2_TRACE_STBITS,
4914	"Drive state check START");
4915	if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4916	pvr2_hdw_state_log_state(hdw);
4917	}
4918
4919	/* Process all state and get back over disposition */
4920	state_updated = pvr2_hdw_state_update(hdw);
4921
4922	analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4923
4924	/* Update master state based upon all other states. */
4925	if (!hdw->flag_ok) {
4926	st = PVR2_STATE_DEAD;
4927	} else if (hdw->fw1_state != FW1_STATE_OK) {
4928	st = PVR2_STATE_COLD;
4929	} else if ((analog_mode ||
4930	hdw->hdw_desc->flag_digital_requires_cx23416) &&
4931	!hdw->state_encoder_ok) {
4932	st = PVR2_STATE_WARM;
4933	} else if (hdw->flag_tripped ||
4934	(analog_mode && hdw->flag_decoder_missed)) {
4935	st = PVR2_STATE_ERROR;
4936	} else if (hdw->state_usbstream_run &&
4937	(!analog_mode ||
4938	(hdw->state_encoder_run && hdw->state_decoder_run))) {
4939	st = PVR2_STATE_RUN;
4940	} else {
4941	st = PVR2_STATE_READY;
4942	}
4943	if (hdw->master_state != st) {
4944	pvr2_trace(PVR2_TRACE_STATE,
4945	"Device state change from %s to %s",
4946	pvr2_get_state_name(hdw->master_state),
4947	pvr2_get_state_name(st));
4948	pvr2_led_ctrl(hdw,onoff: st == PVR2_STATE_RUN);
4949	hdw->master_state = st;
4950	state_updated = !0;
4951	callback_flag = !0;
4952	}
4953	if (state_updated) {
4954	/* Trigger anyone waiting on any state changes here. */
4955	wake_up(&hdw->state_wait_data);
4956	}
4957
4958	if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4959	pvr2_hdw_state_log_state(hdw);
4960	}
4961	pvr2_trace(PVR2_TRACE_STBITS,
4962	"Drive state check DONE callback=%d",callback_flag);
4963
4964	return callback_flag;
4965	}
4966
4967
4968	/* Cause kernel thread to check / update driver state */
4969	static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4970	{
4971	if (hdw->state_stale) return;
4972	hdw->state_stale = !0;
4973	trace_stbit(name: "state_stale",val: hdw->state_stale);
4974	schedule_work(work: &hdw->workpoll);
4975	}
4976
4977
4978	int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4979	{
4980	return pvr2_read_register(hdw,PVR2_GPIO_DIR,data: dp);
4981	}
4982
4983
4984	int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4985	{
4986	return pvr2_read_register(hdw,PVR2_GPIO_OUT,data: dp);
4987	}
4988
4989
4990	int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4991	{
4992	return pvr2_read_register(hdw,PVR2_GPIO_IN,data: dp);
4993	}
4994
4995
4996	int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4997	{
4998	u32 cval,nval;
4999	int ret;
5000	if (~msk) {
5001	ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,data: &cval);
5002	if (ret) return ret;
5003	nval = (cval & ~msk) | (val & msk);
5004	pvr2_trace(PVR2_TRACE_GPIO,
5005	"GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
5006	msk,val,cval,nval);
5007	} else {
5008	nval = val;
5009	pvr2_trace(PVR2_TRACE_GPIO,
5010	"GPIO direction changing to 0x%x",nval);
5011	}
5012	return pvr2_write_register(hdw,PVR2_GPIO_DIR,data: nval);
5013	}
5014
5015
5016	int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5017	{
5018	u32 cval,nval;
5019	int ret;
5020	if (~msk) {
5021	ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,data: &cval);
5022	if (ret) return ret;
5023	nval = (cval & ~msk) | (val & msk);
5024	pvr2_trace(PVR2_TRACE_GPIO,
5025	"GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5026	msk,val,cval,nval);
5027	} else {
5028	nval = val;
5029	pvr2_trace(PVR2_TRACE_GPIO,
5030	"GPIO output changing to 0x%x",nval);
5031	}
5032	return pvr2_write_register(hdw,PVR2_GPIO_OUT,data: nval);
5033	}
5034
5035
5036	void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5037	{
5038	struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5039	memset(vtp, 0, sizeof(*vtp));
5040	vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5041	V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5042	hdw->tuner_signal_stale = 0;
5043	/* Note: There apparently is no replacement for VIDIOC_CROPCAP
5044	using v4l2-subdev - therefore we can't support that AT ALL right
5045	now. (Of course, no sub-drivers seem to implement it either.
5046	But now it's a chicken and egg problem...) */
5047	v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5048	pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
5049	vtp->type,
5050	vtp->signal, vtp->rxsubchans, vtp->capability,
5051	vtp->rangelow, vtp->rangehigh);
5052
5053	/* We have to do this to avoid getting into constant polling if
5054	there's nobody to answer a poll of cropcap info. */
5055	hdw->cropcap_stale = 0;
5056	}
5057
5058
5059	unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5060	{
5061	return hdw->input_avail_mask;
5062	}
5063
5064
5065	unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5066	{
5067	return hdw->input_allowed_mask;
5068	}
5069
5070
5071	static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5072	{
5073	if (hdw->input_val != v) {
5074	hdw->input_val = v;
5075	hdw->input_dirty = !0;
5076	}
5077
5078	/* Handle side effects - if we switch to a mode that needs the RF
5079	tuner, then select the right frequency choice as well and mark
5080	it dirty. */
5081	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5082	hdw->freqSelector = 0;
5083	hdw->freqDirty = !0;
5084	} else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5085	(hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5086	hdw->freqSelector = 1;
5087	hdw->freqDirty = !0;
5088	}
5089	return 0;
5090	}
5091
5092
5093	int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5094	unsigned int change_mask,
5095	unsigned int change_val)
5096	{
5097	int ret = 0;
5098	unsigned int nv,m,idx;
5099	LOCK_TAKE(hdw->big_lock);
5100	do {
5101	nv = hdw->input_allowed_mask & ~change_mask;
5102	nv |= (change_val & change_mask);
5103	nv &= hdw->input_avail_mask;
5104	if (!nv) {
5105	/* No legal modes left; return error instead. */
5106	ret = -EPERM;
5107	break;
5108	}
5109	hdw->input_allowed_mask = nv;
5110	if ((1UL << hdw->input_val) & hdw->input_allowed_mask) {
5111	/* Current mode is still in the allowed mask, so
5112	we're done. */
5113	break;
5114	}
5115	/* Select and switch to a mode that is still in the allowed
5116	mask */
5117	if (!hdw->input_allowed_mask) {
5118	/* Nothing legal; give up */
5119	break;
5120	}
5121	m = hdw->input_allowed_mask;
5122	for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5123	if (!((1UL << idx) & m)) continue;
5124	pvr2_hdw_set_input(hdw,v: idx);
5125	break;
5126	}
5127	} while (0);
5128	LOCK_GIVE(hdw->big_lock);
5129	return ret;
5130	}
5131
5132
5133	/* Find I2C address of eeprom */
5134	static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5135	{
5136	int result;
5137	LOCK_TAKE(hdw->ctl_lock); do {
5138	hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5139	result = pvr2_send_request(hdw,
5140	write_data: hdw->cmd_buffer,write_len: 1,
5141	read_data: hdw->cmd_buffer,read_len: 1);
5142	if (result < 0) break;
5143	result = hdw->cmd_buffer[0];
5144	} while(0); LOCK_GIVE(hdw->ctl_lock);
5145	return result;
5146	}
5147