1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Tegra20 External Memory Controller driver |
4 | * |
5 | * Author: Dmitry Osipenko <digetx@gmail.com> |
6 | */ |
7 | |
8 | #include <linux/bitfield.h> |
9 | #include <linux/clk.h> |
10 | #include <linux/clk/tegra.h> |
11 | #include <linux/debugfs.h> |
12 | #include <linux/devfreq.h> |
13 | #include <linux/err.h> |
14 | #include <linux/interconnect-provider.h> |
15 | #include <linux/interrupt.h> |
16 | #include <linux/io.h> |
17 | #include <linux/iopoll.h> |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> |
20 | #include <linux/mutex.h> |
21 | #include <linux/of.h> |
22 | #include <linux/platform_device.h> |
23 | #include <linux/pm_opp.h> |
24 | #include <linux/slab.h> |
25 | #include <linux/sort.h> |
26 | #include <linux/types.h> |
27 | |
28 | #include <soc/tegra/common.h> |
29 | #include <soc/tegra/fuse.h> |
30 | |
31 | #include "../jedec_ddr.h" |
32 | #include "../of_memory.h" |
33 | |
34 | #include "mc.h" |
35 | |
36 | #define EMC_INTSTATUS 0x000 |
37 | #define EMC_INTMASK 0x004 |
38 | #define EMC_DBG 0x008 |
39 | #define EMC_ADR_CFG_0 0x010 |
40 | #define EMC_TIMING_CONTROL 0x028 |
41 | #define EMC_RC 0x02c |
42 | #define EMC_RFC 0x030 |
43 | #define EMC_RAS 0x034 |
44 | #define EMC_RP 0x038 |
45 | #define EMC_R2W 0x03c |
46 | #define EMC_W2R 0x040 |
47 | #define EMC_R2P 0x044 |
48 | #define EMC_W2P 0x048 |
49 | #define EMC_RD_RCD 0x04c |
50 | #define EMC_WR_RCD 0x050 |
51 | #define EMC_RRD 0x054 |
52 | #define EMC_REXT 0x058 |
53 | #define EMC_WDV 0x05c |
54 | #define EMC_QUSE 0x060 |
55 | #define EMC_QRST 0x064 |
56 | #define EMC_QSAFE 0x068 |
57 | #define EMC_RDV 0x06c |
58 | #define EMC_REFRESH 0x070 |
59 | #define EMC_BURST_REFRESH_NUM 0x074 |
60 | #define EMC_PDEX2WR 0x078 |
61 | #define EMC_PDEX2RD 0x07c |
62 | #define EMC_PCHG2PDEN 0x080 |
63 | #define EMC_ACT2PDEN 0x084 |
64 | #define EMC_AR2PDEN 0x088 |
65 | #define EMC_RW2PDEN 0x08c |
66 | #define EMC_TXSR 0x090 |
67 | #define EMC_TCKE 0x094 |
68 | #define EMC_TFAW 0x098 |
69 | #define EMC_TRPAB 0x09c |
70 | #define EMC_TCLKSTABLE 0x0a0 |
71 | #define EMC_TCLKSTOP 0x0a4 |
72 | #define EMC_TREFBW 0x0a8 |
73 | #define 0x0ac |
74 | #define EMC_ODT_WRITE 0x0b0 |
75 | #define EMC_ODT_READ 0x0b4 |
76 | #define EMC_MRR 0x0ec |
77 | #define EMC_FBIO_CFG5 0x104 |
78 | #define EMC_FBIO_CFG6 0x114 |
79 | #define EMC_STAT_CONTROL 0x160 |
80 | #define EMC_STAT_LLMC_CONTROL 0x178 |
81 | #define EMC_STAT_PWR_CLOCK_LIMIT 0x198 |
82 | #define EMC_STAT_PWR_CLOCKS 0x19c |
83 | #define EMC_STAT_PWR_COUNT 0x1a0 |
84 | #define EMC_AUTO_CAL_INTERVAL 0x2a8 |
85 | #define EMC_CFG_2 0x2b8 |
86 | #define EMC_CFG_DIG_DLL 0x2bc |
87 | #define EMC_DLL_XFORM_DQS 0x2c0 |
88 | #define EMC_DLL_XFORM_QUSE 0x2c4 |
89 | #define EMC_ZCAL_REF_CNT 0x2e0 |
90 | #define EMC_ZCAL_WAIT_CNT 0x2e4 |
91 | #define EMC_CFG_CLKTRIM_0 0x2d0 |
92 | #define EMC_CFG_CLKTRIM_1 0x2d4 |
93 | #define EMC_CFG_CLKTRIM_2 0x2d8 |
94 | |
95 | #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) |
96 | #define EMC_CLKCHANGE_PD_ENABLE BIT(1) |
97 | #define EMC_CLKCHANGE_SR_ENABLE BIT(2) |
98 | |
99 | #define EMC_TIMING_UPDATE BIT(0) |
100 | |
101 | #define EMC_REFRESH_OVERFLOW_INT BIT(3) |
102 | #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) |
103 | #define EMC_MRR_DIVLD_INT BIT(5) |
104 | |
105 | #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) |
106 | #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) |
107 | #define EMC_DBG_FORCE_UPDATE BIT(2) |
108 | #define EMC_DBG_READ_DQM_CTRL BIT(9) |
109 | #define EMC_DBG_CFG_PRIORITY BIT(24) |
110 | |
111 | #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) |
112 | #define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0) |
113 | |
114 | #define EMC_MRR_DEV_SELECTN GENMASK(31, 30) |
115 | #define EMC_MRR_MRR_MA GENMASK(23, 16) |
116 | #define EMC_MRR_MRR_DATA GENMASK(15, 0) |
117 | |
118 | #define EMC_ADR_CFG_0_EMEM_NUMDEV GENMASK(25, 24) |
119 | |
120 | #define EMC_PWR_GATHER_CLEAR (1 << 8) |
121 | #define EMC_PWR_GATHER_DISABLE (2 << 8) |
122 | #define EMC_PWR_GATHER_ENABLE (3 << 8) |
123 | |
124 | enum emc_dram_type { |
125 | DRAM_TYPE_RESERVED, |
126 | DRAM_TYPE_DDR1, |
127 | DRAM_TYPE_LPDDR2, |
128 | DRAM_TYPE_DDR2, |
129 | }; |
130 | |
131 | static const u16 emc_timing_registers[] = { |
132 | EMC_RC, |
133 | EMC_RFC, |
134 | EMC_RAS, |
135 | EMC_RP, |
136 | EMC_R2W, |
137 | EMC_W2R, |
138 | EMC_R2P, |
139 | EMC_W2P, |
140 | EMC_RD_RCD, |
141 | EMC_WR_RCD, |
142 | EMC_RRD, |
143 | EMC_REXT, |
144 | EMC_WDV, |
145 | EMC_QUSE, |
146 | EMC_QRST, |
147 | EMC_QSAFE, |
148 | EMC_RDV, |
149 | EMC_REFRESH, |
150 | EMC_BURST_REFRESH_NUM, |
151 | EMC_PDEX2WR, |
152 | EMC_PDEX2RD, |
153 | EMC_PCHG2PDEN, |
154 | EMC_ACT2PDEN, |
155 | EMC_AR2PDEN, |
156 | EMC_RW2PDEN, |
157 | EMC_TXSR, |
158 | EMC_TCKE, |
159 | EMC_TFAW, |
160 | EMC_TRPAB, |
161 | EMC_TCLKSTABLE, |
162 | EMC_TCLKSTOP, |
163 | EMC_TREFBW, |
164 | EMC_QUSE_EXTRA, |
165 | EMC_FBIO_CFG6, |
166 | EMC_ODT_WRITE, |
167 | EMC_ODT_READ, |
168 | EMC_FBIO_CFG5, |
169 | EMC_CFG_DIG_DLL, |
170 | EMC_DLL_XFORM_DQS, |
171 | EMC_DLL_XFORM_QUSE, |
172 | EMC_ZCAL_REF_CNT, |
173 | EMC_ZCAL_WAIT_CNT, |
174 | EMC_AUTO_CAL_INTERVAL, |
175 | EMC_CFG_CLKTRIM_0, |
176 | EMC_CFG_CLKTRIM_1, |
177 | EMC_CFG_CLKTRIM_2, |
178 | }; |
179 | |
180 | struct emc_timing { |
181 | unsigned long rate; |
182 | u32 data[ARRAY_SIZE(emc_timing_registers)]; |
183 | }; |
184 | |
185 | enum emc_rate_request_type { |
186 | EMC_RATE_DEVFREQ, |
187 | EMC_RATE_DEBUG, |
188 | EMC_RATE_ICC, |
189 | EMC_RATE_TYPE_MAX, |
190 | }; |
191 | |
192 | struct emc_rate_request { |
193 | unsigned long min_rate; |
194 | unsigned long max_rate; |
195 | }; |
196 | |
197 | struct tegra_emc { |
198 | struct device *dev; |
199 | struct tegra_mc *mc; |
200 | struct icc_provider provider; |
201 | struct notifier_block clk_nb; |
202 | struct clk *clk; |
203 | void __iomem *regs; |
204 | unsigned int dram_bus_width; |
205 | |
206 | struct emc_timing *timings; |
207 | unsigned int num_timings; |
208 | |
209 | struct { |
210 | struct dentry *root; |
211 | unsigned long min_rate; |
212 | unsigned long max_rate; |
213 | } debugfs; |
214 | |
215 | /* |
216 | * There are multiple sources in the EMC driver which could request |
217 | * a min/max clock rate, these rates are contained in this array. |
218 | */ |
219 | struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; |
220 | |
221 | /* protect shared rate-change code path */ |
222 | struct mutex rate_lock; |
223 | |
224 | struct devfreq_simple_ondemand_data ondemand_data; |
225 | |
226 | /* memory chip identity information */ |
227 | union lpddr2_basic_config4 basic_conf4; |
228 | unsigned int manufacturer_id; |
229 | unsigned int revision_id1; |
230 | unsigned int revision_id2; |
231 | |
232 | bool mrr_error; |
233 | }; |
234 | |
235 | static irqreturn_t tegra_emc_isr(int irq, void *data) |
236 | { |
237 | struct tegra_emc *emc = data; |
238 | u32 intmask = EMC_REFRESH_OVERFLOW_INT; |
239 | u32 status; |
240 | |
241 | status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; |
242 | if (!status) |
243 | return IRQ_NONE; |
244 | |
245 | /* notify about HW problem */ |
246 | if (status & EMC_REFRESH_OVERFLOW_INT) |
247 | dev_err_ratelimited(emc->dev, |
248 | "refresh request overflow timeout\n" ); |
249 | |
250 | /* clear interrupts */ |
251 | writel_relaxed(status, emc->regs + EMC_INTSTATUS); |
252 | |
253 | return IRQ_HANDLED; |
254 | } |
255 | |
256 | static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, |
257 | unsigned long rate) |
258 | { |
259 | struct emc_timing *timing = NULL; |
260 | unsigned int i; |
261 | |
262 | for (i = 0; i < emc->num_timings; i++) { |
263 | if (emc->timings[i].rate >= rate) { |
264 | timing = &emc->timings[i]; |
265 | break; |
266 | } |
267 | } |
268 | |
269 | if (!timing) { |
270 | dev_err(emc->dev, "no timing for rate %lu\n" , rate); |
271 | return NULL; |
272 | } |
273 | |
274 | return timing; |
275 | } |
276 | |
277 | static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) |
278 | { |
279 | struct emc_timing *timing = tegra_emc_find_timing(emc, rate); |
280 | unsigned int i; |
281 | |
282 | if (!timing) |
283 | return -EINVAL; |
284 | |
285 | dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n" , |
286 | __func__, timing->rate, rate); |
287 | |
288 | /* program shadow registers */ |
289 | for (i = 0; i < ARRAY_SIZE(timing->data); i++) |
290 | writel_relaxed(timing->data[i], |
291 | emc->regs + emc_timing_registers[i]); |
292 | |
293 | /* wait until programming has settled */ |
294 | readl_relaxed(emc->regs + emc_timing_registers[i - 1]); |
295 | |
296 | return 0; |
297 | } |
298 | |
299 | static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) |
300 | { |
301 | int err; |
302 | u32 v; |
303 | |
304 | dev_dbg(emc->dev, "%s: flush %d\n" , __func__, flush); |
305 | |
306 | if (flush) { |
307 | /* manually initiate memory timing update */ |
308 | writel_relaxed(EMC_TIMING_UPDATE, |
309 | emc->regs + EMC_TIMING_CONTROL); |
310 | return 0; |
311 | } |
312 | |
313 | err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, |
314 | v & EMC_CLKCHANGE_COMPLETE_INT, |
315 | 1, 100); |
316 | if (err) { |
317 | dev_err(emc->dev, "emc-car handshake timeout: %d\n" , err); |
318 | return err; |
319 | } |
320 | |
321 | return 0; |
322 | } |
323 | |
324 | static int tegra_emc_clk_change_notify(struct notifier_block *nb, |
325 | unsigned long msg, void *data) |
326 | { |
327 | struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); |
328 | struct clk_notifier_data *cnd = data; |
329 | int err; |
330 | |
331 | switch (msg) { |
332 | case PRE_RATE_CHANGE: |
333 | err = emc_prepare_timing_change(emc, rate: cnd->new_rate); |
334 | break; |
335 | |
336 | case ABORT_RATE_CHANGE: |
337 | err = emc_prepare_timing_change(emc, rate: cnd->old_rate); |
338 | if (err) |
339 | break; |
340 | |
341 | err = emc_complete_timing_change(emc, flush: true); |
342 | break; |
343 | |
344 | case POST_RATE_CHANGE: |
345 | err = emc_complete_timing_change(emc, flush: false); |
346 | break; |
347 | |
348 | default: |
349 | return NOTIFY_DONE; |
350 | } |
351 | |
352 | return notifier_from_errno(err); |
353 | } |
354 | |
355 | static int load_one_timing_from_dt(struct tegra_emc *emc, |
356 | struct emc_timing *timing, |
357 | struct device_node *node) |
358 | { |
359 | u32 rate; |
360 | int err; |
361 | |
362 | if (!of_device_is_compatible(device: node, "nvidia,tegra20-emc-table" )) { |
363 | dev_err(emc->dev, "incompatible DT node: %pOF\n" , node); |
364 | return -EINVAL; |
365 | } |
366 | |
367 | err = of_property_read_u32(np: node, propname: "clock-frequency" , out_value: &rate); |
368 | if (err) { |
369 | dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n" , |
370 | node, err); |
371 | return err; |
372 | } |
373 | |
374 | err = of_property_read_u32_array(np: node, propname: "nvidia,emc-registers" , |
375 | out_values: timing->data, |
376 | ARRAY_SIZE(emc_timing_registers)); |
377 | if (err) { |
378 | dev_err(emc->dev, |
379 | "timing %pOF: failed to read emc timing data: %d\n" , |
380 | node, err); |
381 | return err; |
382 | } |
383 | |
384 | /* |
385 | * The EMC clock rate is twice the bus rate, and the bus rate is |
386 | * measured in kHz. |
387 | */ |
388 | timing->rate = rate * 2 * 1000; |
389 | |
390 | dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n" , |
391 | __func__, node, timing->rate); |
392 | |
393 | return 0; |
394 | } |
395 | |
396 | static int cmp_timings(const void *_a, const void *_b) |
397 | { |
398 | const struct emc_timing *a = _a; |
399 | const struct emc_timing *b = _b; |
400 | |
401 | if (a->rate < b->rate) |
402 | return -1; |
403 | |
404 | if (a->rate > b->rate) |
405 | return 1; |
406 | |
407 | return 0; |
408 | } |
409 | |
410 | static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, |
411 | struct device_node *node) |
412 | { |
413 | struct device_node *child; |
414 | struct emc_timing *timing; |
415 | int child_count; |
416 | int err; |
417 | |
418 | child_count = of_get_child_count(np: node); |
419 | if (!child_count) { |
420 | dev_err(emc->dev, "no memory timings in DT node: %pOF\n" , node); |
421 | return -EINVAL; |
422 | } |
423 | |
424 | emc->timings = devm_kcalloc(dev: emc->dev, n: child_count, size: sizeof(*timing), |
425 | GFP_KERNEL); |
426 | if (!emc->timings) |
427 | return -ENOMEM; |
428 | |
429 | timing = emc->timings; |
430 | |
431 | for_each_child_of_node(node, child) { |
432 | if (of_node_name_eq(np: child, name: "lpddr2" )) |
433 | continue; |
434 | |
435 | err = load_one_timing_from_dt(emc, timing: timing++, node: child); |
436 | if (err) { |
437 | of_node_put(node: child); |
438 | return err; |
439 | } |
440 | |
441 | emc->num_timings++; |
442 | } |
443 | |
444 | sort(base: emc->timings, num: emc->num_timings, size: sizeof(*timing), cmp_func: cmp_timings, |
445 | NULL); |
446 | |
447 | dev_info_once(emc->dev, |
448 | "got %u timings for RAM code %u (min %luMHz max %luMHz)\n" , |
449 | emc->num_timings, |
450 | tegra_read_ram_code(), |
451 | emc->timings[0].rate / 1000000, |
452 | emc->timings[emc->num_timings - 1].rate / 1000000); |
453 | |
454 | return 0; |
455 | } |
456 | |
457 | static struct device_node * |
458 | tegra_emc_find_node_by_ram_code(struct tegra_emc *emc) |
459 | { |
460 | struct device *dev = emc->dev; |
461 | struct device_node *np; |
462 | u32 value, ram_code; |
463 | int err; |
464 | |
465 | if (emc->mrr_error) { |
466 | dev_warn(dev, "memory timings skipped due to MRR error\n" ); |
467 | return NULL; |
468 | } |
469 | |
470 | if (of_get_child_count(np: dev->of_node) == 0) { |
471 | dev_info_once(dev, "device-tree doesn't have memory timings\n" ); |
472 | return NULL; |
473 | } |
474 | |
475 | if (!of_property_read_bool(np: dev->of_node, propname: "nvidia,use-ram-code" )) |
476 | return of_node_get(node: dev->of_node); |
477 | |
478 | ram_code = tegra_read_ram_code(); |
479 | |
480 | for (np = of_find_node_by_name(from: dev->of_node, name: "emc-tables" ); np; |
481 | np = of_find_node_by_name(from: np, name: "emc-tables" )) { |
482 | err = of_property_read_u32(np, propname: "nvidia,ram-code" , out_value: &value); |
483 | if (err || value != ram_code) { |
484 | struct device_node *lpddr2_np; |
485 | bool cfg_mismatches = false; |
486 | |
487 | lpddr2_np = of_find_node_by_name(from: np, name: "lpddr2" ); |
488 | if (lpddr2_np) { |
489 | const struct lpddr2_info *info; |
490 | |
491 | info = of_lpddr2_get_info(np: lpddr2_np, dev); |
492 | if (info) { |
493 | if (info->manufacturer_id >= 0 && |
494 | info->manufacturer_id != emc->manufacturer_id) |
495 | cfg_mismatches = true; |
496 | |
497 | if (info->revision_id1 >= 0 && |
498 | info->revision_id1 != emc->revision_id1) |
499 | cfg_mismatches = true; |
500 | |
501 | if (info->revision_id2 >= 0 && |
502 | info->revision_id2 != emc->revision_id2) |
503 | cfg_mismatches = true; |
504 | |
505 | if (info->density != emc->basic_conf4.density) |
506 | cfg_mismatches = true; |
507 | |
508 | if (info->io_width != emc->basic_conf4.io_width) |
509 | cfg_mismatches = true; |
510 | |
511 | if (info->arch_type != emc->basic_conf4.arch_type) |
512 | cfg_mismatches = true; |
513 | } else { |
514 | dev_err(dev, "failed to parse %pOF\n" , lpddr2_np); |
515 | cfg_mismatches = true; |
516 | } |
517 | |
518 | of_node_put(node: lpddr2_np); |
519 | } else { |
520 | cfg_mismatches = true; |
521 | } |
522 | |
523 | if (cfg_mismatches) { |
524 | of_node_put(node: np); |
525 | continue; |
526 | } |
527 | } |
528 | |
529 | return np; |
530 | } |
531 | |
532 | dev_err(dev, "no memory timings for RAM code %u found in device tree\n" , |
533 | ram_code); |
534 | |
535 | return NULL; |
536 | } |
537 | |
538 | static int emc_read_lpddr_mode_register(struct tegra_emc *emc, |
539 | unsigned int emem_dev, |
540 | unsigned int register_addr, |
541 | unsigned int *register_data) |
542 | { |
543 | u32 memory_dev = emem_dev ? 1 : 2; |
544 | u32 val, mr_mask = 0xff; |
545 | int err; |
546 | |
547 | /* clear data-valid interrupt status */ |
548 | writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); |
549 | |
550 | /* issue mode register read request */ |
551 | val = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev); |
552 | val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr); |
553 | |
554 | writel_relaxed(val, emc->regs + EMC_MRR); |
555 | |
556 | /* wait for the LPDDR2 data-valid interrupt */ |
557 | err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, |
558 | val & EMC_MRR_DIVLD_INT, |
559 | 1, 100); |
560 | if (err) { |
561 | dev_err(emc->dev, "mode register %u read failed: %d\n" , |
562 | register_addr, err); |
563 | emc->mrr_error = true; |
564 | return err; |
565 | } |
566 | |
567 | /* read out mode register data */ |
568 | val = readl_relaxed(emc->regs + EMC_MRR); |
569 | *register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask; |
570 | |
571 | return 0; |
572 | } |
573 | |
574 | static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, |
575 | unsigned int emem_dev, |
576 | bool print_out) |
577 | { |
578 | /* these registers are standard for all LPDDR JEDEC memory chips */ |
579 | emc_read_lpddr_mode_register(emc, emem_dev, register_addr: 5, register_data: &emc->manufacturer_id); |
580 | emc_read_lpddr_mode_register(emc, emem_dev, register_addr: 6, register_data: &emc->revision_id1); |
581 | emc_read_lpddr_mode_register(emc, emem_dev, register_addr: 7, register_data: &emc->revision_id2); |
582 | emc_read_lpddr_mode_register(emc, emem_dev, register_addr: 8, register_data: &emc->basic_conf4.value); |
583 | |
584 | if (!print_out) |
585 | return; |
586 | |
587 | dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n" , |
588 | emem_dev, emc->manufacturer_id, |
589 | lpddr2_jedec_manufacturer(emc->manufacturer_id), |
590 | emc->revision_id1, emc->revision_id2, |
591 | 4 >> emc->basic_conf4.arch_type, |
592 | 64 << emc->basic_conf4.density, |
593 | 32 >> emc->basic_conf4.io_width); |
594 | } |
595 | |
596 | static int emc_setup_hw(struct tegra_emc *emc) |
597 | { |
598 | u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg; |
599 | u32 intmask = EMC_REFRESH_OVERFLOW_INT; |
600 | static bool print_sdram_info_once; |
601 | enum emc_dram_type dram_type; |
602 | const char *dram_type_str; |
603 | unsigned int emem_numdev; |
604 | |
605 | emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); |
606 | |
607 | /* |
608 | * Depending on a memory type, DRAM should enter either self-refresh |
609 | * or power-down state on EMC clock change. |
610 | */ |
611 | if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && |
612 | !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { |
613 | dev_err(emc->dev, |
614 | "bootloader didn't specify DRAM auto-suspend mode\n" ); |
615 | return -EINVAL; |
616 | } |
617 | |
618 | /* enable EMC and CAR to handshake on PLL divider/source changes */ |
619 | emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; |
620 | writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); |
621 | |
622 | /* initialize interrupt */ |
623 | writel_relaxed(intmask, emc->regs + EMC_INTMASK); |
624 | writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); |
625 | |
626 | /* ensure that unwanted debug features are disabled */ |
627 | emc_dbg = readl_relaxed(emc->regs + EMC_DBG); |
628 | emc_dbg |= EMC_DBG_CFG_PRIORITY; |
629 | emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; |
630 | emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; |
631 | emc_dbg &= ~EMC_DBG_FORCE_UPDATE; |
632 | writel_relaxed(emc_dbg, emc->regs + EMC_DBG); |
633 | |
634 | emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); |
635 | |
636 | if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16) |
637 | emc->dram_bus_width = 16; |
638 | else |
639 | emc->dram_bus_width = 32; |
640 | |
641 | dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio); |
642 | |
643 | switch (dram_type) { |
644 | case DRAM_TYPE_RESERVED: |
645 | dram_type_str = "INVALID" ; |
646 | break; |
647 | case DRAM_TYPE_DDR1: |
648 | dram_type_str = "DDR1" ; |
649 | break; |
650 | case DRAM_TYPE_LPDDR2: |
651 | dram_type_str = "LPDDR2" ; |
652 | break; |
653 | case DRAM_TYPE_DDR2: |
654 | dram_type_str = "DDR2" ; |
655 | break; |
656 | } |
657 | |
658 | emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0); |
659 | emem_numdev = FIELD_GET(EMC_ADR_CFG_0_EMEM_NUMDEV, emc_adr_cfg) + 1; |
660 | |
661 | dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n" , |
662 | emc->dram_bus_width, emem_numdev, dram_type_str, |
663 | emem_numdev == 2 ? "devices" : "device" ); |
664 | |
665 | if (dram_type == DRAM_TYPE_LPDDR2) { |
666 | while (emem_numdev--) |
667 | emc_read_lpddr_sdram_info(emc, emem_dev: emem_numdev, |
668 | print_out: !print_sdram_info_once); |
669 | print_sdram_info_once = true; |
670 | } |
671 | |
672 | return 0; |
673 | } |
674 | |
675 | static long emc_round_rate(unsigned long rate, |
676 | unsigned long min_rate, |
677 | unsigned long max_rate, |
678 | void *arg) |
679 | { |
680 | struct emc_timing *timing = NULL; |
681 | struct tegra_emc *emc = arg; |
682 | unsigned int i; |
683 | |
684 | if (!emc->num_timings) |
685 | return clk_get_rate(clk: emc->clk); |
686 | |
687 | min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); |
688 | |
689 | for (i = 0; i < emc->num_timings; i++) { |
690 | if (emc->timings[i].rate < rate && i != emc->num_timings - 1) |
691 | continue; |
692 | |
693 | if (emc->timings[i].rate > max_rate) { |
694 | i = max(i, 1u) - 1; |
695 | |
696 | if (emc->timings[i].rate < min_rate) |
697 | break; |
698 | } |
699 | |
700 | if (emc->timings[i].rate < min_rate) |
701 | continue; |
702 | |
703 | timing = &emc->timings[i]; |
704 | break; |
705 | } |
706 | |
707 | if (!timing) { |
708 | dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n" , |
709 | rate, min_rate, max_rate); |
710 | return -EINVAL; |
711 | } |
712 | |
713 | return timing->rate; |
714 | } |
715 | |
716 | static void tegra_emc_rate_requests_init(struct tegra_emc *emc) |
717 | { |
718 | unsigned int i; |
719 | |
720 | for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { |
721 | emc->requested_rate[i].min_rate = 0; |
722 | emc->requested_rate[i].max_rate = ULONG_MAX; |
723 | } |
724 | } |
725 | |
726 | static int emc_request_rate(struct tegra_emc *emc, |
727 | unsigned long new_min_rate, |
728 | unsigned long new_max_rate, |
729 | enum emc_rate_request_type type) |
730 | { |
731 | struct emc_rate_request *req = emc->requested_rate; |
732 | unsigned long min_rate = 0, max_rate = ULONG_MAX; |
733 | unsigned int i; |
734 | int err; |
735 | |
736 | /* select minimum and maximum rates among the requested rates */ |
737 | for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { |
738 | if (i == type) { |
739 | min_rate = max(new_min_rate, min_rate); |
740 | max_rate = min(new_max_rate, max_rate); |
741 | } else { |
742 | min_rate = max(req->min_rate, min_rate); |
743 | max_rate = min(req->max_rate, max_rate); |
744 | } |
745 | } |
746 | |
747 | if (min_rate > max_rate) { |
748 | dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n" , |
749 | __func__, type, min_rate, max_rate); |
750 | return -ERANGE; |
751 | } |
752 | |
753 | /* |
754 | * EMC rate-changes should go via OPP API because it manages voltage |
755 | * changes. |
756 | */ |
757 | err = dev_pm_opp_set_rate(dev: emc->dev, target_freq: min_rate); |
758 | if (err) |
759 | return err; |
760 | |
761 | emc->requested_rate[type].min_rate = new_min_rate; |
762 | emc->requested_rate[type].max_rate = new_max_rate; |
763 | |
764 | return 0; |
765 | } |
766 | |
767 | static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, |
768 | enum emc_rate_request_type type) |
769 | { |
770 | struct emc_rate_request *req = &emc->requested_rate[type]; |
771 | int ret; |
772 | |
773 | mutex_lock(&emc->rate_lock); |
774 | ret = emc_request_rate(emc, new_min_rate: rate, new_max_rate: req->max_rate, type); |
775 | mutex_unlock(lock: &emc->rate_lock); |
776 | |
777 | return ret; |
778 | } |
779 | |
780 | static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, |
781 | enum emc_rate_request_type type) |
782 | { |
783 | struct emc_rate_request *req = &emc->requested_rate[type]; |
784 | int ret; |
785 | |
786 | mutex_lock(&emc->rate_lock); |
787 | ret = emc_request_rate(emc, new_min_rate: req->min_rate, new_max_rate: rate, type); |
788 | mutex_unlock(lock: &emc->rate_lock); |
789 | |
790 | return ret; |
791 | } |
792 | |
793 | /* |
794 | * debugfs interface |
795 | * |
796 | * The memory controller driver exposes some files in debugfs that can be used |
797 | * to control the EMC frequency. The top-level directory can be found here: |
798 | * |
799 | * /sys/kernel/debug/emc |
800 | * |
801 | * It contains the following files: |
802 | * |
803 | * - available_rates: This file contains a list of valid, space-separated |
804 | * EMC frequencies. |
805 | * |
806 | * - min_rate: Writing a value to this file sets the given frequency as the |
807 | * floor of the permitted range. If this is higher than the currently |
808 | * configured EMC frequency, this will cause the frequency to be |
809 | * increased so that it stays within the valid range. |
810 | * |
811 | * - max_rate: Similarily to the min_rate file, writing a value to this file |
812 | * sets the given frequency as the ceiling of the permitted range. If |
813 | * the value is lower than the currently configured EMC frequency, this |
814 | * will cause the frequency to be decreased so that it stays within the |
815 | * valid range. |
816 | */ |
817 | |
818 | static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) |
819 | { |
820 | unsigned int i; |
821 | |
822 | for (i = 0; i < emc->num_timings; i++) |
823 | if (rate == emc->timings[i].rate) |
824 | return true; |
825 | |
826 | return false; |
827 | } |
828 | |
829 | static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) |
830 | { |
831 | struct tegra_emc *emc = s->private; |
832 | const char *prefix = "" ; |
833 | unsigned int i; |
834 | |
835 | for (i = 0; i < emc->num_timings; i++) { |
836 | seq_printf(m: s, fmt: "%s%lu" , prefix, emc->timings[i].rate); |
837 | prefix = " " ; |
838 | } |
839 | |
840 | seq_puts(m: s, s: "\n" ); |
841 | |
842 | return 0; |
843 | } |
844 | DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates); |
845 | |
846 | static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) |
847 | { |
848 | struct tegra_emc *emc = data; |
849 | |
850 | *rate = emc->debugfs.min_rate; |
851 | |
852 | return 0; |
853 | } |
854 | |
855 | static int tegra_emc_debug_min_rate_set(void *data, u64 rate) |
856 | { |
857 | struct tegra_emc *emc = data; |
858 | int err; |
859 | |
860 | if (!tegra_emc_validate_rate(emc, rate)) |
861 | return -EINVAL; |
862 | |
863 | err = emc_set_min_rate(emc, rate, type: EMC_RATE_DEBUG); |
864 | if (err < 0) |
865 | return err; |
866 | |
867 | emc->debugfs.min_rate = rate; |
868 | |
869 | return 0; |
870 | } |
871 | |
872 | DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops, |
873 | tegra_emc_debug_min_rate_get, |
874 | tegra_emc_debug_min_rate_set, "%llu\n" ); |
875 | |
876 | static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) |
877 | { |
878 | struct tegra_emc *emc = data; |
879 | |
880 | *rate = emc->debugfs.max_rate; |
881 | |
882 | return 0; |
883 | } |
884 | |
885 | static int tegra_emc_debug_max_rate_set(void *data, u64 rate) |
886 | { |
887 | struct tegra_emc *emc = data; |
888 | int err; |
889 | |
890 | if (!tegra_emc_validate_rate(emc, rate)) |
891 | return -EINVAL; |
892 | |
893 | err = emc_set_max_rate(emc, rate, type: EMC_RATE_DEBUG); |
894 | if (err < 0) |
895 | return err; |
896 | |
897 | emc->debugfs.max_rate = rate; |
898 | |
899 | return 0; |
900 | } |
901 | |
902 | DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops, |
903 | tegra_emc_debug_max_rate_get, |
904 | tegra_emc_debug_max_rate_set, "%llu\n" ); |
905 | |
906 | static void tegra_emc_debugfs_init(struct tegra_emc *emc) |
907 | { |
908 | struct device *dev = emc->dev; |
909 | unsigned int i; |
910 | int err; |
911 | |
912 | emc->debugfs.min_rate = ULONG_MAX; |
913 | emc->debugfs.max_rate = 0; |
914 | |
915 | for (i = 0; i < emc->num_timings; i++) { |
916 | if (emc->timings[i].rate < emc->debugfs.min_rate) |
917 | emc->debugfs.min_rate = emc->timings[i].rate; |
918 | |
919 | if (emc->timings[i].rate > emc->debugfs.max_rate) |
920 | emc->debugfs.max_rate = emc->timings[i].rate; |
921 | } |
922 | |
923 | if (!emc->num_timings) { |
924 | emc->debugfs.min_rate = clk_get_rate(clk: emc->clk); |
925 | emc->debugfs.max_rate = emc->debugfs.min_rate; |
926 | } |
927 | |
928 | err = clk_set_rate_range(clk: emc->clk, min: emc->debugfs.min_rate, |
929 | max: emc->debugfs.max_rate); |
930 | if (err < 0) { |
931 | dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n" , |
932 | emc->debugfs.min_rate, emc->debugfs.max_rate, |
933 | emc->clk); |
934 | } |
935 | |
936 | emc->debugfs.root = debugfs_create_dir(name: "emc" , NULL); |
937 | |
938 | debugfs_create_file(name: "available_rates" , mode: 0444, parent: emc->debugfs.root, |
939 | data: emc, fops: &tegra_emc_debug_available_rates_fops); |
940 | debugfs_create_file(name: "min_rate" , mode: 0644, parent: emc->debugfs.root, |
941 | data: emc, fops: &tegra_emc_debug_min_rate_fops); |
942 | debugfs_create_file(name: "max_rate" , mode: 0644, parent: emc->debugfs.root, |
943 | data: emc, fops: &tegra_emc_debug_max_rate_fops); |
944 | } |
945 | |
946 | static inline struct tegra_emc * |
947 | to_tegra_emc_provider(struct icc_provider *provider) |
948 | { |
949 | return container_of(provider, struct tegra_emc, provider); |
950 | } |
951 | |
952 | static struct icc_node_data * |
953 | emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data) |
954 | { |
955 | struct icc_provider *provider = data; |
956 | struct icc_node_data *ndata; |
957 | struct icc_node *node; |
958 | |
959 | /* External Memory is the only possible ICC route */ |
960 | list_for_each_entry(node, &provider->nodes, node_list) { |
961 | if (node->id != TEGRA_ICC_EMEM) |
962 | continue; |
963 | |
964 | ndata = kzalloc(size: sizeof(*ndata), GFP_KERNEL); |
965 | if (!ndata) |
966 | return ERR_PTR(error: -ENOMEM); |
967 | |
968 | /* |
969 | * SRC and DST nodes should have matching TAG in order to have |
970 | * it set by default for a requested path. |
971 | */ |
972 | ndata->tag = TEGRA_MC_ICC_TAG_ISO; |
973 | ndata->node = node; |
974 | |
975 | return ndata; |
976 | } |
977 | |
978 | return ERR_PTR(error: -EPROBE_DEFER); |
979 | } |
980 | |
981 | static int emc_icc_set(struct icc_node *src, struct icc_node *dst) |
982 | { |
983 | struct tegra_emc *emc = to_tegra_emc_provider(provider: dst->provider); |
984 | unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); |
985 | unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); |
986 | unsigned long long rate = max(avg_bw, peak_bw); |
987 | unsigned int dram_data_bus_width_bytes; |
988 | int err; |
989 | |
990 | /* |
991 | * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data |
992 | * is sampled on both clock edges. This means that EMC clock rate |
993 | * equals to the peak data-rate. |
994 | */ |
995 | dram_data_bus_width_bytes = emc->dram_bus_width / 8; |
996 | do_div(rate, dram_data_bus_width_bytes); |
997 | rate = min_t(u64, rate, U32_MAX); |
998 | |
999 | err = emc_set_min_rate(emc, rate, type: EMC_RATE_ICC); |
1000 | if (err) |
1001 | return err; |
1002 | |
1003 | return 0; |
1004 | } |
1005 | |
1006 | static int tegra_emc_interconnect_init(struct tegra_emc *emc) |
1007 | { |
1008 | const struct tegra_mc_soc *soc; |
1009 | struct icc_node *node; |
1010 | int err; |
1011 | |
1012 | emc->mc = devm_tegra_memory_controller_get(dev: emc->dev); |
1013 | if (IS_ERR(ptr: emc->mc)) |
1014 | return PTR_ERR(ptr: emc->mc); |
1015 | |
1016 | soc = emc->mc->soc; |
1017 | |
1018 | emc->provider.dev = emc->dev; |
1019 | emc->provider.set = emc_icc_set; |
1020 | emc->provider.data = &emc->provider; |
1021 | emc->provider.aggregate = soc->icc_ops->aggregate; |
1022 | emc->provider.xlate_extended = emc_of_icc_xlate_extended; |
1023 | |
1024 | icc_provider_init(provider: &emc->provider); |
1025 | |
1026 | /* create External Memory Controller node */ |
1027 | node = icc_node_create(TEGRA_ICC_EMC); |
1028 | if (IS_ERR(ptr: node)) { |
1029 | err = PTR_ERR(ptr: node); |
1030 | goto err_msg; |
1031 | } |
1032 | |
1033 | node->name = "External Memory Controller" ; |
1034 | icc_node_add(node, provider: &emc->provider); |
1035 | |
1036 | /* link External Memory Controller to External Memory (DRAM) */ |
1037 | err = icc_link_create(node, TEGRA_ICC_EMEM); |
1038 | if (err) |
1039 | goto remove_nodes; |
1040 | |
1041 | /* create External Memory node */ |
1042 | node = icc_node_create(TEGRA_ICC_EMEM); |
1043 | if (IS_ERR(ptr: node)) { |
1044 | err = PTR_ERR(ptr: node); |
1045 | goto remove_nodes; |
1046 | } |
1047 | |
1048 | node->name = "External Memory (DRAM)" ; |
1049 | icc_node_add(node, provider: &emc->provider); |
1050 | |
1051 | err = icc_provider_register(provider: &emc->provider); |
1052 | if (err) |
1053 | goto remove_nodes; |
1054 | |
1055 | return 0; |
1056 | |
1057 | remove_nodes: |
1058 | icc_nodes_remove(provider: &emc->provider); |
1059 | err_msg: |
1060 | dev_err(emc->dev, "failed to initialize ICC: %d\n" , err); |
1061 | |
1062 | return err; |
1063 | } |
1064 | |
1065 | static void devm_tegra_emc_unset_callback(void *data) |
1066 | { |
1067 | tegra20_clk_set_emc_round_callback(NULL, NULL); |
1068 | } |
1069 | |
1070 | static void devm_tegra_emc_unreg_clk_notifier(void *data) |
1071 | { |
1072 | struct tegra_emc *emc = data; |
1073 | |
1074 | clk_notifier_unregister(clk: emc->clk, nb: &emc->clk_nb); |
1075 | } |
1076 | |
1077 | static int tegra_emc_init_clk(struct tegra_emc *emc) |
1078 | { |
1079 | int err; |
1080 | |
1081 | tegra20_clk_set_emc_round_callback(round_cb: emc_round_rate, cb_arg: emc); |
1082 | |
1083 | err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, |
1084 | NULL); |
1085 | if (err) |
1086 | return err; |
1087 | |
1088 | emc->clk = devm_clk_get(dev: emc->dev, NULL); |
1089 | if (IS_ERR(ptr: emc->clk)) { |
1090 | dev_err(emc->dev, "failed to get EMC clock: %pe\n" , emc->clk); |
1091 | return PTR_ERR(ptr: emc->clk); |
1092 | } |
1093 | |
1094 | err = clk_notifier_register(clk: emc->clk, nb: &emc->clk_nb); |
1095 | if (err) { |
1096 | dev_err(emc->dev, "failed to register clk notifier: %d\n" , err); |
1097 | return err; |
1098 | } |
1099 | |
1100 | err = devm_add_action_or_reset(emc->dev, |
1101 | devm_tegra_emc_unreg_clk_notifier, emc); |
1102 | if (err) |
1103 | return err; |
1104 | |
1105 | return 0; |
1106 | } |
1107 | |
1108 | static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq, |
1109 | u32 flags) |
1110 | { |
1111 | struct tegra_emc *emc = dev_get_drvdata(dev); |
1112 | struct dev_pm_opp *opp; |
1113 | unsigned long rate; |
1114 | |
1115 | opp = devfreq_recommended_opp(dev, freq, flags); |
1116 | if (IS_ERR(ptr: opp)) { |
1117 | dev_err(dev, "failed to find opp for %lu Hz\n" , *freq); |
1118 | return PTR_ERR(ptr: opp); |
1119 | } |
1120 | |
1121 | rate = dev_pm_opp_get_freq(opp); |
1122 | dev_pm_opp_put(opp); |
1123 | |
1124 | return emc_set_min_rate(emc, rate, type: EMC_RATE_DEVFREQ); |
1125 | } |
1126 | |
1127 | static int tegra_emc_devfreq_get_dev_status(struct device *dev, |
1128 | struct devfreq_dev_status *stat) |
1129 | { |
1130 | struct tegra_emc *emc = dev_get_drvdata(dev); |
1131 | |
1132 | /* freeze counters */ |
1133 | writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); |
1134 | |
1135 | /* |
1136 | * busy_time: number of clocks EMC request was accepted |
1137 | * total_time: number of clocks PWR_GATHER control was set to ENABLE |
1138 | */ |
1139 | stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); |
1140 | stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); |
1141 | stat->current_frequency = clk_get_rate(clk: emc->clk); |
1142 | |
1143 | /* clear counters and restart */ |
1144 | writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); |
1145 | writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); |
1146 | |
1147 | return 0; |
1148 | } |
1149 | |
1150 | static struct devfreq_dev_profile tegra_emc_devfreq_profile = { |
1151 | .polling_ms = 30, |
1152 | .target = tegra_emc_devfreq_target, |
1153 | .get_dev_status = tegra_emc_devfreq_get_dev_status, |
1154 | }; |
1155 | |
1156 | static int tegra_emc_devfreq_init(struct tegra_emc *emc) |
1157 | { |
1158 | struct devfreq *devfreq; |
1159 | |
1160 | /* |
1161 | * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold |
1162 | * should be less than 50. Secondly, multiple active memory clients |
1163 | * may cause over 20% of lost clock cycles due to stalls caused by |
1164 | * competing memory accesses. This means that threshold should be |
1165 | * set to a less than 30 in order to have a properly working governor. |
1166 | */ |
1167 | emc->ondemand_data.upthreshold = 20; |
1168 | |
1169 | /* |
1170 | * Reset statistic gathers state, select global bandwidth for the |
1171 | * statistics collection mode and set clocks counter saturation |
1172 | * limit to maximum. |
1173 | */ |
1174 | writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); |
1175 | writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); |
1176 | writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); |
1177 | |
1178 | devfreq = devm_devfreq_add_device(dev: emc->dev, profile: &tegra_emc_devfreq_profile, |
1179 | DEVFREQ_GOV_SIMPLE_ONDEMAND, |
1180 | data: &emc->ondemand_data); |
1181 | if (IS_ERR(ptr: devfreq)) { |
1182 | dev_err(emc->dev, "failed to initialize devfreq: %pe" , devfreq); |
1183 | return PTR_ERR(ptr: devfreq); |
1184 | } |
1185 | |
1186 | return 0; |
1187 | } |
1188 | |
1189 | static int tegra_emc_probe(struct platform_device *pdev) |
1190 | { |
1191 | struct tegra_core_opp_params opp_params = {}; |
1192 | struct device_node *np; |
1193 | struct tegra_emc *emc; |
1194 | int irq, err; |
1195 | |
1196 | irq = platform_get_irq(pdev, 0); |
1197 | if (irq < 0) { |
1198 | dev_err(&pdev->dev, "please update your device tree\n" ); |
1199 | return irq; |
1200 | } |
1201 | |
1202 | emc = devm_kzalloc(dev: &pdev->dev, size: sizeof(*emc), GFP_KERNEL); |
1203 | if (!emc) |
1204 | return -ENOMEM; |
1205 | |
1206 | mutex_init(&emc->rate_lock); |
1207 | emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; |
1208 | emc->dev = &pdev->dev; |
1209 | |
1210 | emc->regs = devm_platform_ioremap_resource(pdev, index: 0); |
1211 | if (IS_ERR(ptr: emc->regs)) |
1212 | return PTR_ERR(ptr: emc->regs); |
1213 | |
1214 | err = emc_setup_hw(emc); |
1215 | if (err) |
1216 | return err; |
1217 | |
1218 | np = tegra_emc_find_node_by_ram_code(emc); |
1219 | if (np) { |
1220 | err = tegra_emc_load_timings_from_dt(emc, node: np); |
1221 | of_node_put(node: np); |
1222 | if (err) |
1223 | return err; |
1224 | } |
1225 | |
1226 | err = devm_request_irq(dev: &pdev->dev, irq, handler: tegra_emc_isr, irqflags: 0, |
1227 | devname: dev_name(dev: &pdev->dev), dev_id: emc); |
1228 | if (err) { |
1229 | dev_err(&pdev->dev, "failed to request IRQ: %d\n" , err); |
1230 | return err; |
1231 | } |
1232 | |
1233 | err = tegra_emc_init_clk(emc); |
1234 | if (err) |
1235 | return err; |
1236 | |
1237 | opp_params.init_state = true; |
1238 | |
1239 | err = devm_tegra_core_dev_init_opp_table(dev: &pdev->dev, params: &opp_params); |
1240 | if (err) |
1241 | return err; |
1242 | |
1243 | platform_set_drvdata(pdev, data: emc); |
1244 | tegra_emc_rate_requests_init(emc); |
1245 | tegra_emc_debugfs_init(emc); |
1246 | tegra_emc_interconnect_init(emc); |
1247 | tegra_emc_devfreq_init(emc); |
1248 | |
1249 | /* |
1250 | * Don't allow the kernel module to be unloaded. Unloading adds some |
1251 | * extra complexity which doesn't really worth the effort in a case of |
1252 | * this driver. |
1253 | */ |
1254 | try_module_get(THIS_MODULE); |
1255 | |
1256 | return 0; |
1257 | } |
1258 | |
1259 | static const struct of_device_id tegra_emc_of_match[] = { |
1260 | { .compatible = "nvidia,tegra20-emc" , }, |
1261 | {}, |
1262 | }; |
1263 | MODULE_DEVICE_TABLE(of, tegra_emc_of_match); |
1264 | |
1265 | static struct platform_driver tegra_emc_driver = { |
1266 | .probe = tegra_emc_probe, |
1267 | .driver = { |
1268 | .name = "tegra20-emc" , |
1269 | .of_match_table = tegra_emc_of_match, |
1270 | .suppress_bind_attrs = true, |
1271 | .sync_state = icc_sync_state, |
1272 | }, |
1273 | }; |
1274 | module_platform_driver(tegra_emc_driver); |
1275 | |
1276 | MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>" ); |
1277 | MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver" ); |
1278 | MODULE_SOFTDEP("pre: governor_simpleondemand" ); |
1279 | MODULE_LICENSE("GPL v2" ); |
1280 | |