1	// SPDX-License-Identifier: GPL-2.0
2	//
3	// mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4	//
5	// Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,
6	// Marc Kleine-Budde <kernel@pengutronix.de>
7	//
8	// Based on:
9	//
10	// CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
11	//
12	// Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
13	//
14
15	#include <linux/unaligned.h>
16	#include <linux/bitfield.h>
17	#include <linux/clk.h>
18	#include <linux/device.h>
19	#include <linux/mod_devicetable.h>
20	#include <linux/module.h>
21	#include <linux/pm_runtime.h>
22	#include <linux/property.h>
23
24	#include "mcp251xfd.h"
25
26	#define DEVICE_NAME "mcp251xfd"
27
28	static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
29	.quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
30	MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
31	MCP251XFD_QUIRK_ECC,
32	.model = MCP251XFD_MODEL_MCP2517FD,
33	};
34
35	static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
36	.quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
37	MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
38	.model = MCP251XFD_MODEL_MCP2518FD,
39	};
40
41	static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
42	.quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
43	MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
44	.model = MCP251XFD_MODEL_MCP251863,
45	};
46
47	/* Autodetect model, start with CRC enabled. */
48	static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
49	.quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
50	MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
51	.model = MCP251XFD_MODEL_MCP251XFD,
52	};
53
54	static const struct can_bittiming_const mcp251xfd_bittiming_const = {
55	.name = DEVICE_NAME,
56	.tseg1_min = 2,
57	.tseg1_max = 256,
58	.tseg2_min = 1,
59	.tseg2_max = 128,
60	.sjw_max = 128,
61	.brp_min = 1,
62	.brp_max = 256,
63	.brp_inc = 1,
64	};
65
66	static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
67	.name = DEVICE_NAME,
68	.tseg1_min = 1,
69	.tseg1_max = 32,
70	.tseg2_min = 1,
71	.tseg2_max = 16,
72	.sjw_max = 16,
73	.brp_min = 1,
74	.brp_max = 256,
75	.brp_inc = 1,
76	};
77
78	/* The datasheet of the mcp2518fd (DS20006027B) specifies a range of
79	* [-64,63] for TDCO, indicating a relative TDCO.
80	*
81	* Manual tests have shown, that using a relative TDCO configuration
82	* results in bus off, while an absolute configuration works.
83	*
84	* For TDCO use the max value (63) from the data sheet, but 0 as the
85	* minimum.
86	*/
87	static const struct can_tdc_const mcp251xfd_tdc_const = {
88	.tdcv_min = 0,
89	.tdcv_max = 63,
90	.tdco_min = 0,
91	.tdco_max = 63,
92	.tdcf_min = 0,
93	.tdcf_max = 0,
94	};
95
96	static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
97	{
98	switch (model) {
99	case MCP251XFD_MODEL_MCP2517FD:
100	return "MCP2517FD";
101	case MCP251XFD_MODEL_MCP2518FD:
102	return "MCP2518FD";
103	case MCP251XFD_MODEL_MCP251863:
104	return "MCP251863";
105	case MCP251XFD_MODEL_MCP251XFD:
106	return "MCP251xFD";
107	}
108
109	return "<unknown>";
110	}
111
112	static inline const char *
113	mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
114	{
115	return __mcp251xfd_get_model_str(model: priv->devtype_data.model);
116	}
117
118	static const char *mcp251xfd_get_mode_str(const u8 mode)
119	{
120	switch (mode) {
121	case MCP251XFD_REG_CON_MODE_MIXED:
122	return "Mixed (CAN FD/CAN 2.0)";
123	case MCP251XFD_REG_CON_MODE_SLEEP:
124	return "Sleep";
125	case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
126	return "Internal Loopback";
127	case MCP251XFD_REG_CON_MODE_LISTENONLY:
128	return "Listen Only";
129	case MCP251XFD_REG_CON_MODE_CONFIG:
130	return "Configuration";
131	case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
132	return "External Loopback";
133	case MCP251XFD_REG_CON_MODE_CAN2_0:
134	return "CAN 2.0";
135	case MCP251XFD_REG_CON_MODE_RESTRICTED:
136	return "Restricted Operation";
137	}
138
139	return "<unknown>";
140	}
141
142	static const char *
143	mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
144	{
145	switch (~osc & osc_reference &
146	(MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
147	case MCP251XFD_REG_OSC_PLLRDY:
148	return "PLL";
149	case MCP251XFD_REG_OSC_OSCRDY:
150	return "Oscillator";
151	case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
152	return "Oscillator/PLL";
153	}
154
155	return "<unknown>";
156	}
157
158	static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
159	{
160	if (!priv->reg_vdd)
161	return 0;
162
163	return regulator_enable(regulator: priv->reg_vdd);
164	}
165
166	static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
167	{
168	if (!priv->reg_vdd)
169	return 0;
170
171	return regulator_disable(regulator: priv->reg_vdd);
172	}
173
174	static inline int
175	mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
176	{
177	if (!priv->reg_xceiver)
178	return 0;
179
180	return regulator_enable(regulator: priv->reg_xceiver);
181	}
182
183	static inline int
184	mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
185	{
186	if (!priv->reg_xceiver)
187	return 0;
188
189	return regulator_disable(regulator: priv->reg_xceiver);
190	}
191
192	static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
193	{
194	int err;
195
196	err = clk_prepare_enable(clk: priv->clk);
197	if (err)
198	return err;
199
200	err = mcp251xfd_vdd_enable(priv);
201	if (err)
202	clk_disable_unprepare(clk: priv->clk);
203
204	/* Wait for oscillator stabilisation time after power up */
205	usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
206	max: 2 * MCP251XFD_OSC_STAB_SLEEP_US);
207
208	return err;
209	}
210
211	static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
212	{
213	int err;
214
215	err = mcp251xfd_vdd_disable(priv);
216	if (err)
217	return err;
218
219	clk_disable_unprepare(clk: priv->clk);
220
221	return 0;
222	}
223
224	static inline bool mcp251xfd_reg_invalid(u32 reg)
225	{
226	return reg == 0x0 || reg == 0xffffffff;
227	}
228
229	static inline int
230	mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
231	{
232	u32 val;
233	int err;
234
235	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_CON, val: &val);
236	if (err)
237	return err;
238
239	*mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
240
241	return 0;
242	}
243
244	static int
245	__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
246	const u8 mode_req, bool nowait)
247	{
248	const struct can_bittiming *bt = &priv->can.bittiming;
249	unsigned long timeout_us = MCP251XFD_POLL_TIMEOUT_US;
250	u32 con = 0, con_reqop, osc = 0;
251	u8 mode;
252	int err;
253
254	con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
255	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_CON,
256	MCP251XFD_REG_CON_REQOP_MASK, val: con_reqop);
257	if (err == -EBADMSG) {
258	netdev_err(dev: priv->ndev,
259	format: "Failed to set Requested Operation Mode.\n");
260
261	return -ENODEV;
262	} else if (err) {
263	return err;
264	}
265
266	if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
267	return 0;
268
269	if (bt->bitrate)
270	timeout_us = max_t(unsigned long, timeout_us,
271	MCP251XFD_FRAME_LEN_MAX_BITS * USEC_PER_SEC /
272	bt->bitrate);
273
274	err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
275	!mcp251xfd_reg_invalid(con) &&
276	FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
277	con) == mode_req,
278	MCP251XFD_POLL_SLEEP_US, timeout_us);
279	if (err != -ETIMEDOUT && err != -EBADMSG)
280	return err;
281
282	/* Ignore return value.
283	* Print below error messages, even if this fails.
284	*/
285	regmap_read(map: priv->map_reg, MCP251XFD_REG_OSC, val: &osc);
286
287	if (mcp251xfd_reg_invalid(reg: con)) {
288	netdev_err(dev: priv->ndev,
289	format: "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
290	con, osc);
291
292	return -ENODEV;
293	}
294
295	mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
296	netdev_err(dev: priv->ndev,
297	format: "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
298	mcp251xfd_get_mode_str(mode: mode_req), mode_req,
299	mcp251xfd_get_mode_str(mode), mode,
300	con, osc);
301
302	return -ETIMEDOUT;
303	}
304
305	static inline int
306	mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
307	const u8 mode_req)
308	{
309	return __mcp251xfd_chip_set_mode(priv, mode_req, nowait: false);
310	}
311
312	static inline int __maybe_unused
313	mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
314	const u8 mode_req)
315	{
316	return __mcp251xfd_chip_set_mode(priv, mode_req, nowait: true);
317	}
318
319	static int
320	mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
321	u32 osc_reference, u32 osc_mask)
322	{
323	u32 osc;
324	int err;
325
326	err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
327	!mcp251xfd_reg_invalid(osc) &&
328	(osc & osc_mask) == osc_reference,
329	MCP251XFD_OSC_STAB_SLEEP_US,
330	MCP251XFD_OSC_STAB_TIMEOUT_US);
331	if (err != -ETIMEDOUT)
332	return err;
333
334	if (mcp251xfd_reg_invalid(reg: osc)) {
335	netdev_err(dev: priv->ndev,
336	format: "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
337	osc);
338	return -ENODEV;
339	}
340
341	netdev_err(dev: priv->ndev,
342	format: "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
343	mcp251xfd_get_osc_str(osc, osc_reference),
344	osc, osc_reference, osc_mask);
345
346	return -ETIMEDOUT;
347	}
348
349	static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
350	{
351	u32 osc, osc_reference, osc_mask;
352	int err;
353
354	/* For normal sleep on MCP2517FD and MCP2518FD, clearing
355	* "Oscillator Disable" will wake the chip. For low power mode
356	* on MCP2518FD, asserting the chip select will wake the
357	* chip. Writing to the Oscillator register will wake it in
358	* both cases.
359	*/
360	osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
361	MCP251XFD_REG_OSC_CLKODIV_10);
362
363	/* We cannot check for the PLL ready bit (either set or
364	* unset), as the PLL might be enabled. This can happen if the
365	* system reboots, while the mcp251xfd stays powered.
366	*/
367	osc_reference = MCP251XFD_REG_OSC_OSCRDY;
368	osc_mask = MCP251XFD_REG_OSC_OSCRDY;
369
370	/* If the controller is in Sleep Mode the following write only
371	* removes the "Oscillator Disable" bit and powers it up. All
372	* other bits are unaffected.
373	*/
374	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_OSC, val: osc);
375	if (err)
376	return err;
377
378	/* Sometimes the PLL is stuck enabled, the controller never
379	* sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
380	* caller takes care of retry.
381	*/
382	return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
383	}
384
385	static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
386	{
387	if (priv->pll_enable) {
388	u32 osc;
389	int err;
390
391	/* Turn off PLL */
392	osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
393	MCP251XFD_REG_OSC_CLKODIV_10);
394	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_OSC, val: osc);
395	if (err)
396	netdev_err(dev: priv->ndev,
397	format: "Failed to disable PLL.\n");
398
399	priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
400	}
401
402	return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
403	}
404
405	static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
406	{
407	const __be16 cmd = mcp251xfd_cmd_reset();
408	int err;
409
410	/* The Set Mode and SPI Reset command only works if the
411	* controller is not in Sleep Mode.
412	*/
413	err = mcp251xfd_chip_wake(priv);
414	if (err)
415	return err;
416
417	err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
418	if (err)
419	return err;
420
421	/* spi_write_then_read() works with non DMA-safe buffers */
422	return spi_write_then_read(spi: priv->spi, txbuf: &cmd, n_tx: sizeof(cmd), NULL, n_rx: 0);
423	}
424
425	static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
426	{
427	u32 osc_reference, osc_mask;
428	u8 mode;
429	int err;
430
431	/* Check for reset defaults of OSC reg.
432	* This will take care of stabilization period.
433	*/
434	osc_reference = MCP251XFD_REG_OSC_OSCRDY |
435	FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
436	MCP251XFD_REG_OSC_CLKODIV_10);
437	osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
438	err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
439	if (err)
440	return err;
441
442	err = mcp251xfd_chip_get_mode(priv, mode: &mode);
443	if (err)
444	return err;
445
446	if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
447	netdev_info(dev: priv->ndev,
448	format: "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
449	mcp251xfd_get_mode_str(mode), mode);
450	return -ETIMEDOUT;
451	}
452
453	return 0;
454	}
455
456	static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
457	{
458	int err, i;
459
460	for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
461	if (i)
462	netdev_info(dev: priv->ndev,
463	format: "Retrying to reset controller.\n");
464
465	err = mcp251xfd_chip_softreset_do(priv);
466	if (err == -ETIMEDOUT)
467	continue;
468	if (err)
469	return err;
470
471	err = mcp251xfd_chip_softreset_check(priv);
472	if (err == -ETIMEDOUT)
473	continue;
474	if (err)
475	return err;
476
477	return 0;
478	}
479
480	return err;
481	}
482
483	static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
484	{
485	u32 osc, osc_reference, osc_mask;
486	int err;
487
488	/* Activate Low Power Mode on Oscillator Disable. This only
489	* works on the MCP2518FD. The MCP2517FD will go into normal
490	* Sleep Mode instead.
491	*/
492	osc = MCP251XFD_REG_OSC_LPMEN |
493	FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
494	MCP251XFD_REG_OSC_CLKODIV_10);
495	osc_reference = MCP251XFD_REG_OSC_OSCRDY;
496	osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
497
498	if (priv->pll_enable) {
499	osc |= MCP251XFD_REG_OSC_PLLEN;
500	osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
501	}
502
503	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_OSC, val: osc);
504	if (err)
505	return err;
506
507	err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
508	if (err)
509	return err;
510
511	priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
512
513	return 0;
514	}
515
516	static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
517	{
518	/* Set Time Base Counter Prescaler to 1.
519	*
520	* This means an overflow of the 32 bit Time Base Counter
521	* register at 40 MHz every 107 seconds.
522	*/
523	return regmap_write(map: priv->map_reg, MCP251XFD_REG_TSCON,
524	MCP251XFD_REG_TSCON_TBCEN);
525	}
526
527	static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
528	{
529	const struct can_bittiming *bt = &priv->can.bittiming;
530	const struct can_bittiming *dbt = &priv->can.fd.data_bittiming;
531	u32 tdcmod, val = 0;
532	int err;
533
534	/* CAN Control Register
535	*
536	* - no transmit bandwidth sharing
537	* - config mode
538	* - disable transmit queue
539	* - store in transmit FIFO event
540	* - transition to restricted operation mode on system error
541	* - ESI is transmitted recessive when ESI of message is high or
542	* CAN controller error passive
543	* - restricted retransmission attempts,
544	* use TQXCON_TXAT and FIFOCON_TXAT
545	* - wake-up filter bits T11FILTER
546	* - use CAN bus line filter for wakeup
547	* - protocol exception is treated as a form error
548	* - Do not compare data bytes
549	*/
550	val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
551	MCP251XFD_REG_CON_MODE_CONFIG) |
552	MCP251XFD_REG_CON_STEF |
553	MCP251XFD_REG_CON_ESIGM |
554	MCP251XFD_REG_CON_RTXAT |
555	FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
556	MCP251XFD_REG_CON_WFT_T11FILTER) |
557	MCP251XFD_REG_CON_WAKFIL |
558	MCP251XFD_REG_CON_PXEDIS;
559
560	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
561	val |= MCP251XFD_REG_CON_ISOCRCEN;
562
563	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_CON, val);
564	if (err)
565	return err;
566
567	/* Nominal Bit Time */
568	val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
569	FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
570	bt->prop_seg + bt->phase_seg1 - 1) |
571	FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
572	bt->phase_seg2 - 1) |
573	FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
574
575	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_NBTCFG, val);
576	if (err)
577	return err;
578
579	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
580	return 0;
581
582	/* Data Bit Time */
583	val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
584	FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
585	dbt->prop_seg + dbt->phase_seg1 - 1) |
586	FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
587	dbt->phase_seg2 - 1) |
588	FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
589
590	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_DBTCFG, val);
591	if (err)
592	return err;
593
594	/* Transmitter Delay Compensation */
595	if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_AUTO)
596	tdcmod = MCP251XFD_REG_TDC_TDCMOD_AUTO;
597	else if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_MANUAL)
598	tdcmod = MCP251XFD_REG_TDC_TDCMOD_MANUAL;
599	else
600	tdcmod = MCP251XFD_REG_TDC_TDCMOD_DISABLED;
601
602	val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, tdcmod) |
603	FIELD_PREP(MCP251XFD_REG_TDC_TDCV_MASK, priv->can.fd.tdc.tdcv) |
604	FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, priv->can.fd.tdc.tdco);
605
606	return regmap_write(map: priv->map_reg, MCP251XFD_REG_TDC, val);
607	}
608
609	static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
610	{
611	u32 val, mask;
612
613	if (!priv->rx_int)
614	return 0;
615
616	/* Configure PIN1 as RX Interrupt:
617	*
618	* PIN1 must be Input, otherwise there is a glitch on the
619	* rx-INT line. It happens between setting the PIN as output
620	* (in the first byte of the SPI transfer) and configuring the
621	* PIN as interrupt (in the last byte of the SPI transfer).
622	*/
623	val = MCP251XFD_REG_IOCON_TRIS(1);
624	mask = MCP251XFD_REG_IOCON_TRIS(1) | MCP251XFD_REG_IOCON_PM(1);
625	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON, mask, val);
626	}
627
628	static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
629	{
630	u32 val;
631
632	if (!priv->rx_int)
633	return 0;
634
635	/* Configure PIN1 as GPIO Input */
636	val = MCP251XFD_REG_IOCON_PM(1) | MCP251XFD_REG_IOCON_TRIS(1);
637	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON, mask: val, val);
638	}
639
640	static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
641	{
642	struct mcp251xfd_ecc *ecc = &priv->ecc;
643	void *ram;
644	u32 val = 0;
645	int err;
646
647	ecc->ecc_stat = 0;
648
649	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
650	val = MCP251XFD_REG_ECCCON_ECCEN;
651
652	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_ECCCON,
653	MCP251XFD_REG_ECCCON_ECCEN, val);
654	if (err)
655	return err;
656
657	ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
658	if (!ram)
659	return -ENOMEM;
660
661	err = regmap_raw_write(map: priv->map_reg, MCP251XFD_RAM_START, val: ram,
662	MCP251XFD_RAM_SIZE);
663	kfree(objp: ram);
664
665	return err;
666	}
667
668	static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
669	{
670	u8 mode;
671
672	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
673	mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
674	else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
675	mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
676	else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
677	mode = MCP251XFD_REG_CON_MODE_MIXED;
678	else
679	mode = MCP251XFD_REG_CON_MODE_CAN2_0;
680
681	return mode;
682	}
683
684	static int
685	__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
686	bool nowait)
687	{
688	u8 mode;
689
690	mode = mcp251xfd_get_normal_mode(priv);
691
692	return __mcp251xfd_chip_set_mode(priv, mode_req: mode, nowait);
693	}
694
695	static inline int
696	mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
697	{
698	return __mcp251xfd_chip_set_normal_mode(priv, nowait: false);
699	}
700
701	static inline int
702	mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
703	{
704	return __mcp251xfd_chip_set_normal_mode(priv, nowait: true);
705	}
706
707	static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
708	{
709	u32 val;
710	int err;
711
712	val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
713	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_CRC, val);
714	if (err)
715	return err;
716
717	val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
718	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_ECCCON, mask: val, val);
719	if (err)
720	return err;
721
722	val = MCP251XFD_REG_INT_CERRIE |
723	MCP251XFD_REG_INT_SERRIE |
724	MCP251XFD_REG_INT_RXOVIE |
725	MCP251XFD_REG_INT_TXATIE |
726	MCP251XFD_REG_INT_SPICRCIE |
727	MCP251XFD_REG_INT_ECCIE |
728	MCP251XFD_REG_INT_TEFIE |
729	MCP251XFD_REG_INT_MODIE |
730	MCP251XFD_REG_INT_RXIE;
731
732	if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
733	val |= MCP251XFD_REG_INT_IVMIE;
734
735	return regmap_write(map: priv->map_reg, MCP251XFD_REG_INT, val);
736	}
737
738	static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
739	{
740	int err;
741	u32 mask;
742
743	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_INT, val: 0);
744	if (err)
745	return err;
746
747	mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
748	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_ECCCON,
749	mask, val: 0x0);
750	if (err)
751	return err;
752
753	return regmap_write(map: priv->map_reg, MCP251XFD_REG_CRC, val: 0);
754	}
755
756	static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
757	const enum can_state state)
758	{
759	priv->can.state = state;
760
761	mcp251xfd_chip_interrupts_disable(priv);
762	mcp251xfd_chip_rx_int_disable(priv);
763	mcp251xfd_timestamp_stop(priv);
764	mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
765	}
766
767	static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
768	{
769	int err;
770
771	err = mcp251xfd_chip_timestamp_init(priv);
772	if (err)
773	goto out_chip_stop;
774
775	mcp251xfd_timestamp_start(priv);
776
777	err = mcp251xfd_set_bittiming(priv);
778	if (err)
779	goto out_chip_stop;
780
781	err = mcp251xfd_chip_rx_int_enable(priv);
782	if (err)
783	goto out_chip_stop;
784
785	err = mcp251xfd_chip_ecc_init(priv);
786	if (err)
787	goto out_chip_stop;
788
789	err = mcp251xfd_ring_init(priv);
790	if (err)
791	goto out_chip_stop;
792
793	err = mcp251xfd_chip_fifo_init(priv);
794	if (err)
795	goto out_chip_stop;
796
797	priv->can.state = CAN_STATE_ERROR_ACTIVE;
798
799	err = mcp251xfd_chip_set_normal_mode(priv);
800	if (err)
801	goto out_chip_stop;
802
803	return 0;
804
805	out_chip_stop:
806	mcp251xfd_dump(priv);
807	mcp251xfd_chip_stop(priv, state: CAN_STATE_STOPPED);
808
809	return err;
810	}
811
812	static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
813	{
814	struct mcp251xfd_priv *priv = netdev_priv(dev: ndev);
815	int err;
816
817	switch (mode) {
818	case CAN_MODE_START:
819	err = mcp251xfd_chip_start(priv);
820	if (err)
821	return err;
822
823	err = mcp251xfd_chip_interrupts_enable(priv);
824	if (err) {
825	mcp251xfd_chip_stop(priv, state: CAN_STATE_STOPPED);
826	return err;
827	}
828
829	netif_wake_queue(dev: ndev);
830	break;
831
832	default:
833	return -EOPNOTSUPP;
834	}
835
836	return 0;
837	}
838
839	static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
840	struct can_berr_counter *bec)
841	{
842	const struct mcp251xfd_priv *priv = netdev_priv(dev: ndev);
843	u32 trec;
844	int err;
845
846	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_TREC, val: &trec);
847	if (err)
848	return err;
849
850	if (trec & MCP251XFD_REG_TREC_TXBO)
851	bec->txerr = CAN_BUS_OFF_THRESHOLD;
852	else
853	bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
854	bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
855
856	return 0;
857	}
858
859	static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
860	struct can_berr_counter *bec)
861	{
862	const struct mcp251xfd_priv *priv = netdev_priv(dev: ndev);
863
864	/* Avoid waking up the controller if the interface is down */
865	if (!(ndev->flags & IFF_UP))
866	return 0;
867
868	/* The controller is powered down during Bus Off, use saved
869	* bec values.
870	*/
871	if (priv->can.state == CAN_STATE_BUS_OFF) {
872	*bec = priv->bec;
873	return 0;
874	}
875
876	return __mcp251xfd_get_berr_counter(ndev, bec);
877	}
878
879	static struct sk_buff *
880	mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
881	struct can_frame **cf, u32 *ts_raw)
882	{
883	struct sk_buff *skb;
884	int err;
885
886	err = mcp251xfd_get_timestamp_raw(priv, ts_raw);
887	if (err)
888	return NULL;
889
890	skb = alloc_can_err_skb(dev: priv->ndev, cf);
891	if (skb)
892	mcp251xfd_skb_set_timestamp_raw(priv, skb, ts_raw: *ts_raw);
893
894	return skb;
895	}
896
897	static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
898	{
899	struct net_device_stats *stats = &priv->ndev->stats;
900	struct mcp251xfd_rx_ring *ring;
901	struct sk_buff *skb;
902	struct can_frame *cf;
903	u32 ts_raw, rxovif;
904	int err, i;
905
906	stats->rx_over_errors++;
907	stats->rx_errors++;
908
909	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_RXOVIF, val: &rxovif);
910	if (err)
911	return err;
912
913	mcp251xfd_for_each_rx_ring(priv, ring, i) {
914	if (!(rxovif & BIT(ring->fifo_nr)))
915	continue;
916
917	/* If SERRIF is active, there was a RX MAB overflow. */
918	if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
919	if (net_ratelimit())
920	netdev_dbg(priv->ndev,
921	"RX-%d: MAB overflow detected.\n",
922	ring->nr);
923	} else {
924	if (net_ratelimit())
925	netdev_dbg(priv->ndev,
926	"RX-%d: FIFO overflow.\n",
927	ring->nr);
928	}
929
930	err = regmap_update_bits(map: priv->map_reg,
931	MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
932	MCP251XFD_REG_FIFOSTA_RXOVIF,
933	val: 0x0);
934	if (err)
935	return err;
936	}
937
938	skb = mcp251xfd_alloc_can_err_skb(priv, cf: &cf, ts_raw: &ts_raw);
939	if (!skb)
940	return 0;
941
942	cf->can_id |= CAN_ERR_CRTL;
943	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
944
945	err = can_rx_offload_queue_timestamp(offload: &priv->offload, skb, timestamp: ts_raw);
946	if (err)
947	stats->rx_fifo_errors++;
948
949	return 0;
950	}
951
952	static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
953	{
954	netdev_info(dev: priv->ndev, format: "%s\n", __func__);
955
956	return 0;
957	}
958
959	static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
960	{
961	struct net_device_stats *stats = &priv->ndev->stats;
962	u32 bdiag1, ts_raw;
963	struct sk_buff *skb;
964	struct can_frame *cf = NULL;
965	int err;
966
967	err = mcp251xfd_get_timestamp_raw(priv, ts_raw: &ts_raw);
968	if (err)
969	return err;
970
971	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_BDIAG1, val: &bdiag1);
972	if (err)
973	return err;
974
975	/* Write 0s to clear error bits, don't write 1s to non active
976	* bits, as they will be set.
977	*/
978	err = regmap_write(map: priv->map_reg, MCP251XFD_REG_BDIAG1, val: 0x0);
979	if (err)
980	return err;
981
982	priv->can.can_stats.bus_error++;
983
984	skb = alloc_can_err_skb(dev: priv->ndev, cf: &cf);
985	if (cf)
986	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
987
988	/* Controller misconfiguration */
989	if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
990	netdev_err(dev: priv->ndev,
991	format: "recv'd DLC is larger than PLSIZE of FIFO element.");
992
993	/* RX errors */
994	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
995	MCP251XFD_REG_BDIAG1_NCRCERR)) {
996	netdev_dbg(priv->ndev, "CRC error\n");
997
998	stats->rx_errors++;
999	if (cf)
1000	cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1001	}
1002	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
1003	MCP251XFD_REG_BDIAG1_NSTUFERR)) {
1004	netdev_dbg(priv->ndev, "Stuff error\n");
1005
1006	stats->rx_errors++;
1007	if (cf)
1008	cf->data[2] |= CAN_ERR_PROT_STUFF;
1009	}
1010	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
1011	MCP251XFD_REG_BDIAG1_NFORMERR)) {
1012	netdev_dbg(priv->ndev, "Format error\n");
1013
1014	stats->rx_errors++;
1015	if (cf)
1016	cf->data[2] |= CAN_ERR_PROT_FORM;
1017	}
1018
1019	/* TX errors */
1020	if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1021	netdev_dbg(priv->ndev, "NACK error\n");
1022
1023	stats->tx_errors++;
1024	if (cf) {
1025	cf->can_id |= CAN_ERR_ACK;
1026	cf->data[2] |= CAN_ERR_PROT_TX;
1027	}
1028	}
1029	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1030	MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1031	netdev_dbg(priv->ndev, "Bit1 error\n");
1032
1033	stats->tx_errors++;
1034	if (cf)
1035	cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1036	}
1037	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1038	MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1039	netdev_dbg(priv->ndev, "Bit0 error\n");
1040
1041	stats->tx_errors++;
1042	if (cf)
1043	cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1044	}
1045
1046	if (!cf)
1047	return 0;
1048
1049	mcp251xfd_skb_set_timestamp_raw(priv, skb, ts_raw);
1050	err = can_rx_offload_queue_timestamp(offload: &priv->offload, skb, timestamp: ts_raw);
1051	if (err)
1052	stats->rx_fifo_errors++;
1053
1054	return 0;
1055	}
1056
1057	static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1058	{
1059	struct net_device_stats *stats = &priv->ndev->stats;
1060	struct sk_buff *skb;
1061	struct can_frame *cf = NULL;
1062	enum can_state new_state, rx_state, tx_state;
1063	u32 trec, ts_raw;
1064	int err;
1065
1066	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_TREC, val: &trec);
1067	if (err)
1068	return err;
1069
1070	if (trec & MCP251XFD_REG_TREC_TXBO)
1071	tx_state = CAN_STATE_BUS_OFF;
1072	else if (trec & MCP251XFD_REG_TREC_TXBP)
1073	tx_state = CAN_STATE_ERROR_PASSIVE;
1074	else if (trec & MCP251XFD_REG_TREC_TXWARN)
1075	tx_state = CAN_STATE_ERROR_WARNING;
1076	else
1077	tx_state = CAN_STATE_ERROR_ACTIVE;
1078
1079	if (trec & MCP251XFD_REG_TREC_RXBP)
1080	rx_state = CAN_STATE_ERROR_PASSIVE;
1081	else if (trec & MCP251XFD_REG_TREC_RXWARN)
1082	rx_state = CAN_STATE_ERROR_WARNING;
1083	else
1084	rx_state = CAN_STATE_ERROR_ACTIVE;
1085
1086	new_state = max(tx_state, rx_state);
1087	if (new_state == priv->can.state)
1088	return 0;
1089
1090	/* The skb allocation might fail, but can_change_state()
1091	* handles cf == NULL.
1092	*/
1093	skb = mcp251xfd_alloc_can_err_skb(priv, cf: &cf, ts_raw: &ts_raw);
1094	can_change_state(dev: priv->ndev, cf, tx_state, rx_state);
1095
1096	if (new_state == CAN_STATE_BUS_OFF) {
1097	/* As we're going to switch off the chip now, let's
1098	* save the error counters and return them to
1099	* userspace, if do_get_berr_counter() is called while
1100	* the chip is in Bus Off.
1101	*/
1102	err = __mcp251xfd_get_berr_counter(ndev: priv->ndev, bec: &priv->bec);
1103	if (err)
1104	return err;
1105
1106	mcp251xfd_chip_stop(priv, state: CAN_STATE_BUS_OFF);
1107	can_bus_off(dev: priv->ndev);
1108	}
1109
1110	if (!skb)
1111	return 0;
1112
1113	if (new_state != CAN_STATE_BUS_OFF) {
1114	struct can_berr_counter bec;
1115
1116	err = mcp251xfd_get_berr_counter(ndev: priv->ndev, bec: &bec);
1117	if (err)
1118	return err;
1119	cf->can_id |= CAN_ERR_CNT;
1120	cf->data[6] = bec.txerr;
1121	cf->data[7] = bec.rxerr;
1122	}
1123
1124	err = can_rx_offload_queue_timestamp(offload: &priv->offload, skb, timestamp: ts_raw);
1125	if (err)
1126	stats->rx_fifo_errors++;
1127
1128	return 0;
1129	}
1130
1131	static int
1132	mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1133	{
1134	const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1135	u8 mode;
1136	int err;
1137
1138	err = mcp251xfd_chip_get_mode(priv, mode: &mode);
1139	if (err)
1140	return err;
1141
1142	if (mode == mode_reference) {
1143	netdev_dbg(priv->ndev,
1144	"Controller changed into %s Mode (%u).\n",
1145	mcp251xfd_get_mode_str(mode), mode);
1146	return 0;
1147	}
1148
1149	/* According to MCP2517FD errata DS80000792C 1., during a TX
1150	* MAB underflow, the controller will transition to Restricted
1151	* Operation Mode or Listen Only Mode (depending on SERR2LOM).
1152	*
1153	* However this is not always the case. If SERR2LOM is
1154	* configured for Restricted Operation Mode (SERR2LOM not set)
1155	* the MCP2517FD will sometimes transition to Listen Only Mode
1156	* first. When polling this bit we see that it will transition
1157	* to Restricted Operation Mode shortly after.
1158	*/
1159	if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1160	(mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1161	mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1162	netdev_dbg(priv->ndev,
1163	"Controller changed into %s Mode (%u).\n",
1164	mcp251xfd_get_mode_str(mode), mode);
1165	else
1166	netdev_err(dev: priv->ndev,
1167	format: "Controller changed into %s Mode (%u).\n",
1168	mcp251xfd_get_mode_str(mode), mode);
1169
1170	/* After the application requests Normal mode, the controller
1171	* will automatically attempt to retransmit the message that
1172	* caused the TX MAB underflow.
1173	*
1174	* However, if there is an ECC error in the TX-RAM, we first
1175	* have to reload the tx-object before requesting Normal
1176	* mode. This is done later in mcp251xfd_handle_eccif().
1177	*/
1178	if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1179	*set_normal_mode = true;
1180	return 0;
1181	}
1182
1183	return mcp251xfd_chip_set_normal_mode_nowait(priv);
1184	}
1185
1186	static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1187	{
1188	struct mcp251xfd_ecc *ecc = &priv->ecc;
1189	struct net_device_stats *stats = &priv->ndev->stats;
1190	bool handled = false;
1191
1192	/* TX MAB underflow
1193	*
1194	* According to MCP2517FD Errata DS80000792C 1. a TX MAB
1195	* underflow is indicated by SERRIF and MODIF.
1196	*
1197	* In addition to the effects mentioned in the Errata, there
1198	* are Bus Errors due to the aborted CAN frame, so a IVMIF
1199	* will be seen as well.
1200	*
1201	* Sometimes there is an ECC error in the TX-RAM, which leads
1202	* to a TX MAB underflow.
1203	*
1204	* However, probably due to a race condition, there is no
1205	* associated MODIF pending.
1206	*
1207	* Further, there are situations, where the SERRIF is caused
1208	* by an ECC error in the TX-RAM, but not even the ECCIF is
1209	* set. This only seems to happen _after_ the first occurrence
1210	* of a ECCIF (which is tracked in ecc->cnt).
1211	*
1212	* Treat all as a known system errors..
1213	*/
1214	if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1215	priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1216	priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1217	ecc->cnt) {
1218	const char *msg;
1219
1220	if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1221	ecc->cnt)
1222	msg = "TX MAB underflow due to ECC error detected.";
1223	else
1224	msg = "TX MAB underflow detected.";
1225
1226	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1227	netdev_dbg(priv->ndev, "%s\n", msg);
1228	else
1229	netdev_info(dev: priv->ndev, format: "%s\n", msg);
1230
1231	stats->tx_aborted_errors++;
1232	stats->tx_errors++;
1233	handled = true;
1234	}
1235
1236	/* RX MAB overflow
1237	*
1238	* According to MCP2517FD Errata DS80000792C 1. a RX MAB
1239	* overflow is indicated by SERRIF.
1240	*
1241	* In addition to the effects mentioned in the Errata, (most
1242	* of the times) a RXOVIF is raised, if the FIFO that is being
1243	* received into has the RXOVIE activated (and we have enabled
1244	* RXOVIE on all FIFOs).
1245	*
1246	* Sometimes there is no RXOVIF just a RXIF is pending.
1247	*
1248	* Treat all as a known system errors..
1249	*/
1250	if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1251	priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1252	stats->rx_dropped++;
1253	handled = true;
1254	}
1255
1256	if (!handled)
1257	netdev_err(dev: priv->ndev,
1258	format: "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1259	priv->regs_status.intf);
1260
1261	return 0;
1262	}
1263
1264	static int
1265	mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1266	{
1267	struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1268	struct mcp251xfd_ecc *ecc = &priv->ecc;
1269	struct mcp251xfd_tx_obj *tx_obj;
1270	u8 chip_tx_tail, tx_tail, offset;
1271	u16 addr;
1272	int err;
1273
1274	addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1275
1276	err = mcp251xfd_tx_tail_get_from_chip(priv, tx_tail: &chip_tx_tail);
1277	if (err)
1278	return err;
1279
1280	tx_tail = mcp251xfd_get_tx_tail(ring: tx_ring);
1281	offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1282
1283	/* Bail out if one of the following is met:
1284	* - tx_tail information is inconsistent
1285	* - for mcp2517fd: offset not 0
1286	* - for mcp2518fd: offset not 0 or 1
1287	*/
1288	if (chip_tx_tail != tx_tail ||
1289	!(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1290	mcp251xfd_is_251863(priv))))) {
1291	netdev_err(dev: priv->ndev,
1292	format: "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1293	addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1294	offset);
1295	return -EINVAL;
1296	}
1297
1298	netdev_info(dev: priv->ndev,
1299	format: "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1300	ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1301	"Single" : "Double",
1302	addr, nr, tx_ring->tail, tx_tail, offset);
1303
1304	/* reload tx_obj into controller RAM ... */
1305	tx_obj = &tx_ring->obj[nr];
1306	err = spi_sync_transfer(spi: priv->spi, xfers: tx_obj->xfer, num_xfers: 1);
1307	if (err)
1308	return err;
1309
1310	/* ... and trigger retransmit */
1311	return mcp251xfd_chip_set_normal_mode(priv);
1312	}
1313
1314	static int
1315	mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1316	{
1317	struct mcp251xfd_ecc *ecc = &priv->ecc;
1318	const char *msg;
1319	bool in_tx_ram;
1320	u32 ecc_stat;
1321	u16 addr;
1322	u8 nr;
1323	int err;
1324
1325	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_ECCSTAT, val: &ecc_stat);
1326	if (err)
1327	return err;
1328
1329	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_ECCSTAT,
1330	MCP251XFD_REG_ECCSTAT_IF_MASK, val: ~ecc_stat);
1331	if (err)
1332	return err;
1333
1334	/* Check if ECC error occurred in TX-RAM */
1335	addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1336	err = mcp251xfd_get_tx_nr_by_addr(tx_ring: priv->tx, nr: &nr, addr);
1337	if (!err)
1338	in_tx_ram = true;
1339	else if (err == -ENOENT)
1340	in_tx_ram = false;
1341	else
1342	return err;
1343
1344	/* Errata Reference:
1345	* mcp2517fd: DS80000789C 3., mcp2518fd: DS80000792E 2.,
1346	* mcp251863: DS80000984A 2.
1347	*
1348	* ECC single error correction does not work in all cases:
1349	*
1350	* Fix/Work Around:
1351	* Enable single error correction and double error detection
1352	* interrupts by setting SECIE and DEDIE. Handle SECIF as a
1353	* detection interrupt and do not rely on the error
1354	* correction. Instead, handle both interrupts as a
1355	* notification that the RAM word at ERRADDR was corrupted.
1356	*/
1357	if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1358	msg = "Single ECC Error detected at address";
1359	else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1360	msg = "Double ECC Error detected at address";
1361	else
1362	return -EINVAL;
1363
1364	if (!in_tx_ram) {
1365	ecc->ecc_stat = 0;
1366
1367	netdev_notice(dev: priv->ndev, format: "%s 0x%04x.\n", msg, addr);
1368	} else {
1369	/* Re-occurring error? */
1370	if (ecc->ecc_stat == ecc_stat) {
1371	ecc->cnt++;
1372	} else {
1373	ecc->ecc_stat = ecc_stat;
1374	ecc->cnt = 1;
1375	}
1376
1377	netdev_info(dev: priv->ndev,
1378	format: "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1379	msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1380
1381	if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1382	return mcp251xfd_handle_eccif_recover(priv, nr);
1383	}
1384
1385	if (set_normal_mode)
1386	return mcp251xfd_chip_set_normal_mode_nowait(priv);
1387
1388	return 0;
1389	}
1390
1391	static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1392	{
1393	int err;
1394	u32 crc;
1395
1396	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_CRC, val: &crc);
1397	if (err)
1398	return err;
1399
1400	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_CRC,
1401	MCP251XFD_REG_CRC_IF_MASK,
1402	val: ~crc);
1403	if (err)
1404	return err;
1405
1406	if (crc & MCP251XFD_REG_CRC_FERRIF)
1407	netdev_notice(dev: priv->ndev, format: "CRC write command format error.\n");
1408	else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1409	netdev_notice(dev: priv->ndev,
1410	format: "CRC write error detected. CRC=0x%04lx.\n",
1411	FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1412
1413	return 0;
1414	}
1415
1416	static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1417	{
1418	const int val_bytes = regmap_get_val_bytes(map: priv->map_reg);
1419	size_t len;
1420
1421	if (priv->rx_ring_num == 1)
1422	len = sizeof(priv->regs_status.intf);
1423	else
1424	len = sizeof(priv->regs_status);
1425
1426	return regmap_bulk_read(map: priv->map_reg, MCP251XFD_REG_INT,
1427	val: &priv->regs_status, val_count: len / val_bytes);
1428	}
1429
1430	#define mcp251xfd_handle(priv, irq, ...) \
1431	({ \
1432	struct mcp251xfd_priv *_priv = (priv); \
1433	int err; \
1434	\
1435	err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1436	if (err) \
1437	netdev_err(_priv->ndev, \
1438	"IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1439	__stringify(irq), err); \
1440	err; \
1441	})
1442
1443	static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1444	{
1445	struct mcp251xfd_priv *priv = dev_id;
1446	irqreturn_t handled = IRQ_NONE;
1447	int err;
1448
1449	if (priv->rx_int)
1450	do {
1451	int rx_pending;
1452
1453	rx_pending = gpiod_get_value_cansleep(desc: priv->rx_int);
1454	if (!rx_pending)
1455	break;
1456
1457	/* Assume 1st RX-FIFO pending, if other FIFOs
1458	* are pending the main IRQ handler will take
1459	* care.
1460	*/
1461	priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1462	err = mcp251xfd_handle(priv, rxif);
1463	if (err)
1464	goto out_fail;
1465
1466	handled = IRQ_HANDLED;
1467
1468	/* We don't know which RX-FIFO is pending, but only
1469	* handle the 1st RX-FIFO. Leave loop here if we have
1470	* more than 1 RX-FIFO to avoid starvation.
1471	*/
1472	} while (priv->rx_ring_num == 1);
1473
1474	do {
1475	u32 intf_pending, intf_pending_clearable;
1476	bool set_normal_mode = false;
1477
1478	err = mcp251xfd_read_regs_status(priv);
1479	if (err)
1480	goto out_fail;
1481
1482	intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1483	priv->regs_status.intf) &
1484	FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1485	priv->regs_status.intf);
1486
1487	if (!(intf_pending)) {
1488	can_rx_offload_threaded_irq_finish(offload: &priv->offload);
1489	return handled;
1490	}
1491
1492	/* Some interrupts must be ACKed in the
1493	* MCP251XFD_REG_INT register.
1494	* - First ACK then handle, to avoid lost-IRQ race
1495	* condition on fast re-occurring interrupts.
1496	* - Write "0" to clear active IRQs, "1" to all other,
1497	* to avoid r/m/w race condition on the
1498	* MCP251XFD_REG_INT register.
1499	*/
1500	intf_pending_clearable = intf_pending &
1501	MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1502	if (intf_pending_clearable) {
1503	err = regmap_update_bits(map: priv->map_reg,
1504	MCP251XFD_REG_INT,
1505	MCP251XFD_REG_INT_IF_MASK,
1506	val: ~intf_pending_clearable);
1507	if (err)
1508	goto out_fail;
1509	}
1510
1511	if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1512	err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1513	if (err)
1514	goto out_fail;
1515	}
1516
1517	if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1518	err = mcp251xfd_handle(priv, rxif);
1519	if (err)
1520	goto out_fail;
1521	}
1522
1523	if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1524	err = mcp251xfd_handle(priv, tefif);
1525	if (err)
1526	goto out_fail;
1527	}
1528
1529	if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1530	err = mcp251xfd_handle(priv, rxovif);
1531	if (err)
1532	goto out_fail;
1533	}
1534
1535	if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1536	err = mcp251xfd_handle(priv, txatif);
1537	if (err)
1538	goto out_fail;
1539	}
1540
1541	if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1542	err = mcp251xfd_handle(priv, ivmif);
1543	if (err)
1544	goto out_fail;
1545	}
1546
1547	if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1548	err = mcp251xfd_handle(priv, serrif);
1549	if (err)
1550	goto out_fail;
1551	}
1552
1553	if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1554	err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1555	if (err)
1556	goto out_fail;
1557	}
1558
1559	if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1560	err = mcp251xfd_handle(priv, spicrcif);
1561	if (err)
1562	goto out_fail;
1563	}
1564
1565	/* On the MCP2527FD and MCP2518FD, we don't get a
1566	* CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1567	* ERROR_ACTIVE.
1568	*/
1569	if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1570	priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1571	err = mcp251xfd_handle(priv, cerrif);
1572	if (err)
1573	goto out_fail;
1574
1575	/* In Bus Off we completely shut down the
1576	* controller. Every subsequent register read
1577	* will read bogus data, and if
1578	* MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1579	* check will fail, too. So leave IRQ handler
1580	* directly.
1581	*/
1582	if (priv->can.state == CAN_STATE_BUS_OFF) {
1583	can_rx_offload_threaded_irq_finish(offload: &priv->offload);
1584	return IRQ_HANDLED;
1585	}
1586	}
1587
1588	handled = IRQ_HANDLED;
1589	} while (1);
1590
1591	out_fail:
1592	can_rx_offload_threaded_irq_finish(offload: &priv->offload);
1593
1594	netdev_err(dev: priv->ndev, format: "IRQ handler returned %d (intf=0x%08x).\n",
1595	err, priv->regs_status.intf);
1596	mcp251xfd_dump(priv);
1597	mcp251xfd_chip_interrupts_disable(priv);
1598	mcp251xfd_timestamp_stop(priv);
1599
1600	return handled;
1601	}
1602
1603	static int mcp251xfd_open(struct net_device *ndev)
1604	{
1605	struct mcp251xfd_priv *priv = netdev_priv(dev: ndev);
1606	const struct spi_device *spi = priv->spi;
1607	int err;
1608
1609	err = open_candev(dev: ndev);
1610	if (err)
1611	return err;
1612
1613	err = pm_runtime_resume_and_get(dev: ndev->dev.parent);
1614	if (err) {
1615	if (err == -ETIMEDOUT || err == -ENODEV)
1616	pm_runtime_set_suspended(dev: ndev->dev.parent);
1617	goto out_close_candev;
1618	}
1619
1620	err = mcp251xfd_ring_alloc(priv);
1621	if (err)
1622	goto out_pm_runtime_put;
1623
1624	err = mcp251xfd_transceiver_enable(priv);
1625	if (err)
1626	goto out_mcp251xfd_ring_free;
1627
1628	mcp251xfd_timestamp_init(priv);
1629
1630	err = mcp251xfd_chip_start(priv);
1631	if (err)
1632	goto out_transceiver_disable;
1633
1634	clear_bit(nr: MCP251XFD_FLAGS_DOWN, addr: priv->flags);
1635	can_rx_offload_enable(offload: &priv->offload);
1636
1637	priv->wq = alloc_ordered_workqueue("%s-mcp251xfd_wq",
1638	WQ_FREEZABLE | WQ_MEM_RECLAIM,
1639	dev_name(&spi->dev));
1640	if (!priv->wq) {
1641	err = -ENOMEM;
1642	goto out_can_rx_offload_disable;
1643	}
1644	INIT_WORK(&priv->tx_work, mcp251xfd_tx_obj_write_sync);
1645
1646	err = request_threaded_irq(irq: spi->irq, NULL, thread_fn: mcp251xfd_irq,
1647	IRQF_SHARED | IRQF_ONESHOT,
1648	name: dev_name(dev: &spi->dev), dev: priv);
1649	if (err)
1650	goto out_destroy_workqueue;
1651
1652	err = mcp251xfd_chip_interrupts_enable(priv);
1653	if (err)
1654	goto out_free_irq;
1655
1656	netif_start_queue(dev: ndev);
1657
1658	return 0;
1659
1660	out_free_irq:
1661	free_irq(spi->irq, priv);
1662	out_destroy_workqueue:
1663	destroy_workqueue(wq: priv->wq);
1664	out_can_rx_offload_disable:
1665	can_rx_offload_disable(offload: &priv->offload);
1666	set_bit(nr: MCP251XFD_FLAGS_DOWN, addr: priv->flags);
1667	out_transceiver_disable:
1668	mcp251xfd_transceiver_disable(priv);
1669	out_mcp251xfd_ring_free:
1670	mcp251xfd_ring_free(priv);
1671	out_pm_runtime_put:
1672	mcp251xfd_chip_stop(priv, state: CAN_STATE_STOPPED);
1673	pm_runtime_put(dev: ndev->dev.parent);
1674	out_close_candev:
1675	close_candev(dev: ndev);
1676
1677	return err;
1678	}
1679
1680	static int mcp251xfd_stop(struct net_device *ndev)
1681	{
1682	struct mcp251xfd_priv *priv = netdev_priv(dev: ndev);
1683
1684	netif_stop_queue(dev: ndev);
1685	set_bit(nr: MCP251XFD_FLAGS_DOWN, addr: priv->flags);
1686	hrtimer_cancel(timer: &priv->rx_irq_timer);
1687	hrtimer_cancel(timer: &priv->tx_irq_timer);
1688	mcp251xfd_chip_interrupts_disable(priv);
1689	free_irq(ndev->irq, priv);
1690	destroy_workqueue(wq: priv->wq);
1691	can_rx_offload_disable(offload: &priv->offload);
1692	mcp251xfd_chip_stop(priv, state: CAN_STATE_STOPPED);
1693	mcp251xfd_transceiver_disable(priv);
1694	mcp251xfd_ring_free(priv);
1695	close_candev(dev: ndev);
1696
1697	pm_runtime_put(dev: ndev->dev.parent);
1698
1699	return 0;
1700	}
1701
1702	static const struct net_device_ops mcp251xfd_netdev_ops = {
1703	.ndo_open = mcp251xfd_open,
1704	.ndo_stop = mcp251xfd_stop,
1705	.ndo_start_xmit = mcp251xfd_start_xmit,
1706	.ndo_hwtstamp_get = can_hwtstamp_get,
1707	.ndo_hwtstamp_set = can_hwtstamp_set,
1708	};
1709
1710	static void
1711	mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1712	{
1713	const struct spi_device *spi = priv->spi;
1714	const struct spi_controller *ctlr = spi->controller;
1715
1716	if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1717	priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1718	}
1719
1720	static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1721	{
1722	const struct net_device *ndev = priv->ndev;
1723	const struct mcp251xfd_devtype_data *devtype_data;
1724	u32 osc;
1725	int err;
1726
1727	/* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1728	* so use it to autodetect the model.
1729	*/
1730	err = regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_OSC,
1731	MCP251XFD_REG_OSC_LPMEN,
1732	MCP251XFD_REG_OSC_LPMEN);
1733	if (err)
1734	return err;
1735
1736	err = regmap_read(map: priv->map_reg, MCP251XFD_REG_OSC, val: &osc);
1737	if (err)
1738	return err;
1739
1740	if (osc & MCP251XFD_REG_OSC_LPMEN) {
1741	/* We cannot distinguish between MCP2518FD and
1742	* MCP251863. If firmware specifies MCP251863, keep
1743	* it, otherwise set to MCP2518FD.
1744	*/
1745	if (mcp251xfd_is_251863(priv))
1746	devtype_data = &mcp251xfd_devtype_data_mcp251863;
1747	else
1748	devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1749	} else {
1750	devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1751	}
1752
1753	if (!mcp251xfd_is_251XFD(priv) &&
1754	priv->devtype_data.model != devtype_data->model) {
1755	netdev_info(dev: ndev,
1756	format: "Detected %s, but firmware specifies a %s. Fixing up.\n",
1757	__mcp251xfd_get_model_str(model: devtype_data->model),
1758	mcp251xfd_get_model_str(priv));
1759	}
1760	priv->devtype_data = *devtype_data;
1761
1762	/* We need to preserve the Half Duplex Quirk. */
1763	mcp251xfd_register_quirks(priv);
1764
1765	/* Re-init regmap with quirks of detected model. */
1766	return mcp251xfd_regmap_init(priv);
1767	}
1768
1769	static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1770	{
1771	int err, rx_pending;
1772
1773	if (!priv->rx_int)
1774	return 0;
1775
1776	err = mcp251xfd_chip_rx_int_enable(priv);
1777	if (err)
1778	return err;
1779
1780	/* Check if RX_INT is properly working. The RX_INT should not
1781	* be active after a softreset.
1782	*/
1783	rx_pending = gpiod_get_value_cansleep(desc: priv->rx_int);
1784
1785	err = mcp251xfd_chip_rx_int_disable(priv);
1786	if (err)
1787	return err;
1788
1789	if (!rx_pending)
1790	return 0;
1791
1792	netdev_info(dev: priv->ndev,
1793	format: "RX_INT active after softreset, disabling RX_INT support.\n");
1794	devm_gpiod_put(dev: &priv->spi->dev, desc: priv->rx_int);
1795	priv->rx_int = NULL;
1796
1797	return 0;
1798	}
1799
1800	static const char * const mcp251xfd_gpio_names[] = { "GPIO0", "GPIO1" };
1801
1802	static int mcp251xfd_gpio_request(struct gpio_chip *chip, unsigned int offset)
1803	{
1804	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1805	u32 pin_mask = MCP251XFD_REG_IOCON_PM(offset);
1806	int ret;
1807
1808	if (priv->rx_int && offset == 1) {
1809	netdev_err(dev: priv->ndev, format: "Can't use GPIO 1 with RX-INT!\n");
1810	return -EINVAL;
1811	}
1812
1813	ret = pm_runtime_resume_and_get(dev: priv->ndev->dev.parent);
1814	if (ret)
1815	return ret;
1816
1817	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON, mask: pin_mask, val: pin_mask);
1818	}
1819
1820	static void mcp251xfd_gpio_free(struct gpio_chip *chip, unsigned int offset)
1821	{
1822	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1823
1824	pm_runtime_put(dev: priv->ndev->dev.parent);
1825	}
1826
1827	static int mcp251xfd_gpio_get_direction(struct gpio_chip *chip,
1828	unsigned int offset)
1829	{
1830	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1831	u32 mask = MCP251XFD_REG_IOCON_TRIS(offset);
1832	u32 val;
1833	int ret;
1834
1835	ret = regmap_read(map: priv->map_reg, MCP251XFD_REG_IOCON, val: &val);
1836	if (ret)
1837	return ret;
1838
1839	if (mask & val)
1840	return GPIO_LINE_DIRECTION_IN;
1841
1842	return GPIO_LINE_DIRECTION_OUT;
1843	}
1844
1845	static int mcp251xfd_gpio_get(struct gpio_chip *chip, unsigned int offset)
1846	{
1847	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1848	u32 mask = MCP251XFD_REG_IOCON_GPIO(offset);
1849	u32 val;
1850	int ret;
1851
1852	ret = regmap_read(map: priv->map_reg, MCP251XFD_REG_IOCON, val: &val);
1853	if (ret)
1854	return ret;
1855
1856	return !!(mask & val);
1857	}
1858
1859	static int mcp251xfd_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1860	unsigned long *bit)
1861	{
1862	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1863	u32 val;
1864	int ret;
1865
1866	ret = regmap_read(map: priv->map_reg, MCP251XFD_REG_IOCON, val: &val);
1867	if (ret)
1868	return ret;
1869
1870	*bit = FIELD_GET(MCP251XFD_REG_IOCON_GPIO_MASK, val) & *mask;
1871
1872	return 0;
1873	}
1874
1875	static int mcp251xfd_gpio_direction_output(struct gpio_chip *chip,
1876	unsigned int offset, int value)
1877	{
1878	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1879	u32 dir_mask = MCP251XFD_REG_IOCON_TRIS(offset);
1880	u32 val_mask = MCP251XFD_REG_IOCON_LAT(offset);
1881	u32 val;
1882
1883	if (value)
1884	val = val_mask;
1885	else
1886	val = 0;
1887
1888	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON,
1889	mask: dir_mask | val_mask, val);
1890	}
1891
1892	static int mcp251xfd_gpio_direction_input(struct gpio_chip *chip,
1893	unsigned int offset)
1894	{
1895	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1896	u32 dir_mask = MCP251XFD_REG_IOCON_TRIS(offset);
1897
1898	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON, mask: dir_mask, val: dir_mask);
1899	}
1900
1901	static int mcp251xfd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1902	{
1903	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1904	u32 val_mask = MCP251XFD_REG_IOCON_LAT(offset);
1905	u32 val;
1906
1907	if (value)
1908	val = val_mask;
1909	else
1910	val = 0;
1911
1912	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON, mask: val_mask, val);
1913	}
1914
1915	static int mcp251xfd_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1916	unsigned long *bits)
1917	{
1918	struct mcp251xfd_priv *priv = gpiochip_get_data(gc: chip);
1919	u32 val;
1920
1921	val = FIELD_PREP(MCP251XFD_REG_IOCON_LAT_MASK, *bits);
1922
1923	return regmap_update_bits(map: priv->map_reg, MCP251XFD_REG_IOCON,
1924	MCP251XFD_REG_IOCON_LAT_MASK, val);
1925	}
1926
1927	static int mcp251fdx_gpio_setup(struct mcp251xfd_priv *priv)
1928	{
1929	struct gpio_chip *gc = &priv->gc;
1930
1931	if (!device_property_present(dev: &priv->spi->dev, propname: "gpio-controller"))
1932	return 0;
1933
1934	gc->label = dev_name(dev: &priv->spi->dev);
1935	gc->parent = &priv->spi->dev;
1936	gc->owner = THIS_MODULE;
1937	gc->request = mcp251xfd_gpio_request;
1938	gc->free = mcp251xfd_gpio_free;
1939	gc->get_direction = mcp251xfd_gpio_get_direction;
1940	gc->direction_output = mcp251xfd_gpio_direction_output;
1941	gc->direction_input = mcp251xfd_gpio_direction_input;
1942	gc->get = mcp251xfd_gpio_get;
1943	gc->get_multiple = mcp251xfd_gpio_get_multiple;
1944	gc->set = mcp251xfd_gpio_set;
1945	gc->set_multiple = mcp251xfd_gpio_set_multiple;
1946	gc->base = -1;
1947	gc->can_sleep = true;
1948	gc->ngpio = ARRAY_SIZE(mcp251xfd_gpio_names);
1949	gc->names = mcp251xfd_gpio_names;
1950
1951	return devm_gpiochip_add_data(&priv->spi->dev, gc, priv);
1952	}
1953
1954	static int
1955	mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1956	u32 *effective_speed_hz_slow,
1957	u32 *effective_speed_hz_fast)
1958	{
1959	struct mcp251xfd_map_buf_nocrc *buf_rx;
1960	struct mcp251xfd_map_buf_nocrc *buf_tx;
1961	struct spi_transfer xfer[2] = { };
1962	int err;
1963
1964	buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1965	if (!buf_rx)
1966	return -ENOMEM;
1967
1968	buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1969	if (!buf_tx) {
1970	err = -ENOMEM;
1971	goto out_kfree_buf_rx;
1972	}
1973
1974	xfer[0].tx_buf = buf_tx;
1975	xfer[0].len = sizeof(buf_tx->cmd);
1976	xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1977	xfer[1].rx_buf = buf_rx->data;
1978	xfer[1].len = sizeof(*dev_id);
1979	xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1980
1981	mcp251xfd_spi_cmd_read_nocrc(cmd: &buf_tx->cmd, MCP251XFD_REG_DEVID);
1982
1983	err = spi_sync_transfer(spi: priv->spi, xfers: xfer, ARRAY_SIZE(xfer));
1984	if (err)
1985	goto out_kfree_buf_tx;
1986
1987	*dev_id = get_unaligned_le32(p: buf_rx->data);
1988	*effective_speed_hz_slow = xfer[0].effective_speed_hz;
1989	*effective_speed_hz_fast = xfer[1].effective_speed_hz;
1990
1991	out_kfree_buf_tx:
1992	kfree(objp: buf_tx);
1993	out_kfree_buf_rx:
1994	kfree(objp: buf_rx);
1995
1996	return err;
1997	}
1998
1999	#define MCP251XFD_QUIRK_ACTIVE(quirk) \
2000	(priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
2001
2002	static int
2003	mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
2004	{
2005	u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
2006	unsigned long clk_rate;
2007	int err;
2008
2009	err = mcp251xfd_register_get_dev_id(priv, dev_id: &dev_id,
2010	effective_speed_hz_slow: &effective_speed_hz_slow,
2011	effective_speed_hz_fast: &effective_speed_hz_fast);
2012	if (err)
2013	return err;
2014
2015	clk_rate = clk_get_rate(clk: priv->clk);
2016
2017	netdev_info(dev: priv->ndev,
2018	format: "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
2019	mcp251xfd_get_model_str(priv),
2020	FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
2021	FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
2022	priv->rx_int ? '+' : '-',
2023	priv->pll_enable ? '+' : '-',
2024	MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
2025	MCP251XFD_QUIRK_ACTIVE(CRC_REG),
2026	MCP251XFD_QUIRK_ACTIVE(CRC_RX),
2027	MCP251XFD_QUIRK_ACTIVE(CRC_TX),
2028	MCP251XFD_QUIRK_ACTIVE(ECC),
2029	MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
2030	clk_rate / 1000000,
2031	clk_rate % 1000000 / 1000 / 10,
2032	priv->can.clock.freq / 1000000,
2033	priv->can.clock.freq % 1000000 / 1000 / 10,
2034	priv->spi_max_speed_hz_orig / 1000000,
2035	priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
2036	priv->spi_max_speed_hz_slow / 1000000,
2037	priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
2038	effective_speed_hz_slow / 1000000,
2039	effective_speed_hz_slow % 1000000 / 1000 / 10,
2040	priv->spi_max_speed_hz_fast / 1000000,
2041	priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
2042	effective_speed_hz_fast / 1000000,
2043	effective_speed_hz_fast % 1000000 / 1000 / 10);
2044
2045	return 0;
2046	}
2047
2048	static int mcp251xfd_register(struct mcp251xfd_priv *priv)
2049	{
2050	struct net_device *ndev = priv->ndev;
2051	int err;
2052
2053	mcp251xfd_register_quirks(priv);
2054
2055	err = mcp251xfd_clks_and_vdd_enable(priv);
2056	if (err)
2057	return err;
2058
2059	err = mcp251xfd_chip_softreset(priv);
2060	if (err == -ENODEV)
2061	goto out_clks_and_vdd_disable;
2062	if (err)
2063	goto out_chip_sleep;
2064
2065	err = mcp251xfd_chip_clock_init(priv);
2066	if (err == -ENODEV)
2067	goto out_clks_and_vdd_disable;
2068	if (err)
2069	goto out_chip_sleep;
2070
2071	pm_runtime_get_noresume(dev: ndev->dev.parent);
2072	err = pm_runtime_set_active(dev: ndev->dev.parent);
2073	if (err)
2074	goto out_runtime_put_noidle;
2075	pm_runtime_enable(dev: ndev->dev.parent);
2076
2077	err = mcp251xfd_register_chip_detect(priv);
2078	if (err)
2079	goto out_runtime_disable;
2080
2081	err = mcp251xfd_register_check_rx_int(priv);
2082	if (err)
2083	goto out_runtime_disable;
2084
2085	mcp251xfd_ethtool_init(priv);
2086
2087	err = mcp251fdx_gpio_setup(priv);
2088	if (err) {
2089	dev_err_probe(dev: &priv->spi->dev, err, fmt: "Failed to register gpio-controller.\n");
2090	goto out_runtime_disable;
2091	}
2092
2093	err = register_candev(dev: ndev);
2094	if (err)
2095	goto out_runtime_disable;
2096
2097	err = mcp251xfd_register_done(priv);
2098	if (err)
2099	goto out_unregister_candev;
2100
2101	/* Put controller into Config mode and let pm_runtime_put()
2102	* put in sleep mode, disable the clocks and vdd. If CONFIG_PM
2103	* is not enabled, the clocks and vdd will stay powered.
2104	*/
2105	err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
2106	if (err)
2107	goto out_unregister_candev;
2108
2109	pm_runtime_put(dev: ndev->dev.parent);
2110
2111	return 0;
2112
2113	out_unregister_candev:
2114	unregister_candev(dev: ndev);
2115	out_runtime_disable:
2116	pm_runtime_disable(dev: ndev->dev.parent);
2117	out_runtime_put_noidle:
2118	pm_runtime_put_noidle(dev: ndev->dev.parent);
2119	out_chip_sleep:
2120	mcp251xfd_chip_sleep(priv);
2121	out_clks_and_vdd_disable:
2122	mcp251xfd_clks_and_vdd_disable(priv);
2123
2124	return err;
2125	}
2126
2127	static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
2128	{
2129	struct net_device *ndev = priv->ndev;
2130
2131	unregister_candev(dev: ndev);
2132
2133	if (pm_runtime_enabled(dev: ndev->dev.parent)) {
2134	pm_runtime_disable(dev: ndev->dev.parent);
2135	} else {
2136	mcp251xfd_chip_sleep(priv);
2137	mcp251xfd_clks_and_vdd_disable(priv);
2138	}
2139	}
2140
2141	static const struct of_device_id mcp251xfd_of_match[] = {
2142	{
2143	.compatible = "microchip,mcp2517fd",
2144	.data = &mcp251xfd_devtype_data_mcp2517fd,
2145	}, {
2146	.compatible = "microchip,mcp2518fd",
2147	.data = &mcp251xfd_devtype_data_mcp2518fd,
2148	}, {
2149	.compatible = "microchip,mcp251863",
2150	.data = &mcp251xfd_devtype_data_mcp251863,
2151	}, {
2152	.compatible = "microchip,mcp251xfd",
2153	.data = &mcp251xfd_devtype_data_mcp251xfd,
2154	}, {
2155	/* sentinel */
2156	},
2157	};
2158	MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
2159
2160	static const struct spi_device_id mcp251xfd_id_table[] = {
2161	{
2162	.name = "mcp2517fd",
2163	.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
2164	}, {
2165	.name = "mcp2518fd",
2166	.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
2167	}, {
2168	.name = "mcp251863",
2169	.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
2170	}, {
2171	.name = "mcp251xfd",
2172	.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
2173	}, {
2174	/* sentinel */
2175	},
2176	};
2177	MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
2178
2179	static int mcp251xfd_probe(struct spi_device *spi)
2180	{
2181	struct net_device *ndev;
2182	struct mcp251xfd_priv *priv;
2183	struct gpio_desc *rx_int;
2184	struct regulator *reg_vdd, *reg_xceiver;
2185	struct clk *clk;
2186	bool pll_enable = false;
2187	u32 freq = 0;
2188	int err;
2189
2190	if (!spi->irq)
2191	return dev_err_probe(dev: &spi->dev, err: -ENXIO,
2192	fmt: "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
2193
2194	rx_int = devm_gpiod_get_optional(dev: &spi->dev, con_id: "microchip,rx-int",
2195	flags: GPIOD_IN);
2196	if (IS_ERR(ptr: rx_int))
2197	return dev_err_probe(dev: &spi->dev, err: PTR_ERR(ptr: rx_int),
2198	fmt: "Failed to get RX-INT!\n");
2199
2200	reg_vdd = devm_regulator_get_optional(dev: &spi->dev, id: "vdd");
2201	if (PTR_ERR(ptr: reg_vdd) == -ENODEV)
2202	reg_vdd = NULL;
2203	else if (IS_ERR(ptr: reg_vdd))
2204	return dev_err_probe(dev: &spi->dev, err: PTR_ERR(ptr: reg_vdd),
2205	fmt: "Failed to get VDD regulator!\n");
2206
2207	reg_xceiver = devm_regulator_get_optional(dev: &spi->dev, id: "xceiver");
2208	if (PTR_ERR(ptr: reg_xceiver) == -ENODEV)
2209	reg_xceiver = NULL;
2210	else if (IS_ERR(ptr: reg_xceiver))
2211	return dev_err_probe(dev: &spi->dev, err: PTR_ERR(ptr: reg_xceiver),
2212	fmt: "Failed to get Transceiver regulator!\n");
2213
2214	clk = devm_clk_get_optional(dev: &spi->dev, NULL);
2215	if (IS_ERR(ptr: clk))
2216	return dev_err_probe(dev: &spi->dev, err: PTR_ERR(ptr: clk),
2217	fmt: "Failed to get Oscillator (clock)!\n");
2218	if (clk) {
2219	freq = clk_get_rate(clk);
2220	} else {
2221	err = device_property_read_u32(dev: &spi->dev, propname: "clock-frequency",
2222	val: &freq);
2223	if (err)
2224	return dev_err_probe(dev: &spi->dev, err,
2225	fmt: "Failed to get clock-frequency!\n");
2226	}
2227
2228	/* Sanity check */
2229	if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2230	freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2231	dev_err(&spi->dev,
2232	"Oscillator frequency (%u Hz) is too low or high.\n",
2233	freq);
2234	return -ERANGE;
2235	}
2236
2237	if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2238	pll_enable = true;
2239
2240	ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2241	MCP251XFD_TX_OBJ_NUM_MAX);
2242	if (!ndev)
2243	return -ENOMEM;
2244
2245	SET_NETDEV_DEV(ndev, &spi->dev);
2246
2247	ndev->netdev_ops = &mcp251xfd_netdev_ops;
2248	ndev->irq = spi->irq;
2249	ndev->flags |= IFF_ECHO;
2250
2251	priv = netdev_priv(dev: ndev);
2252	spi_set_drvdata(spi, data: priv);
2253	priv->can.clock.freq = freq;
2254	if (pll_enable)
2255	priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2256	priv->can.do_set_mode = mcp251xfd_set_mode;
2257	priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2258	priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2259	priv->can.fd.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2260	priv->can.fd.tdc_const = &mcp251xfd_tdc_const;
2261	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2262	CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2263	CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2264	CAN_CTRLMODE_CC_LEN8_DLC | CAN_CTRLMODE_TDC_AUTO |
2265	CAN_CTRLMODE_TDC_MANUAL;
2266	set_bit(nr: MCP251XFD_FLAGS_DOWN, addr: priv->flags);
2267	priv->ndev = ndev;
2268	priv->spi = spi;
2269	priv->rx_int = rx_int;
2270	priv->clk = clk;
2271	priv->pll_enable = pll_enable;
2272	priv->reg_vdd = reg_vdd;
2273	priv->reg_xceiver = reg_xceiver;
2274	priv->devtype_data = *(struct mcp251xfd_devtype_data *)spi_get_device_match_data(sdev: spi);
2275
2276	/* Errata Reference:
2277	* mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789E 4.,
2278	* mcp251863: DS80000984A 4.
2279	*
2280	* The SPI can write corrupted data to the RAM at fast SPI
2281	* speeds:
2282	*
2283	* Simultaneous activity on the CAN bus while writing data to
2284	* RAM via the SPI interface, with high SCK frequency, can
2285	* lead to corrupted data being written to RAM.
2286	*
2287	* Fix/Work Around:
2288	* Ensure that FSCK is less than or equal to 0.85 *
2289	* (FSYSCLK/2).
2290	*
2291	* Known good combinations are:
2292	*
2293	* MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config
2294	*
2295	* 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2296	* 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2297	* 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2298	* 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2299	* 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default
2300	* 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2301	*
2302	*/
2303	priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2304	priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2305	freq / 2 / 1000 * 850);
2306	if (priv->pll_enable)
2307	priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2308	freq *
2309	MCP251XFD_OSC_PLL_MULTIPLIER /
2310	2 / 1000 * 850);
2311	else
2312	priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2313	spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2314	spi->bits_per_word = 8;
2315	spi->rt = true;
2316	err = spi_setup(spi);
2317	if (err)
2318	goto out_free_candev;
2319
2320	err = mcp251xfd_regmap_init(priv);
2321	if (err)
2322	goto out_free_candev;
2323
2324	err = can_rx_offload_add_manual(dev: ndev, offload: &priv->offload,
2325	MCP251XFD_NAPI_WEIGHT);
2326	if (err)
2327	goto out_free_candev;
2328
2329	err = mcp251xfd_register(priv);
2330	if (err) {
2331	dev_err_probe(dev: &spi->dev, err, fmt: "Failed to detect %s.\n",
2332	mcp251xfd_get_model_str(priv));
2333	goto out_can_rx_offload_del;
2334	}
2335
2336	return 0;
2337
2338	out_can_rx_offload_del:
2339	can_rx_offload_del(offload: &priv->offload);
2340	out_free_candev:
2341	spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2342
2343	free_candev(dev: ndev);
2344
2345	return err;
2346	}
2347
2348	static void mcp251xfd_remove(struct spi_device *spi)
2349	{
2350	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2351	struct net_device *ndev = priv->ndev;
2352
2353	mcp251xfd_unregister(priv);
2354	can_rx_offload_del(offload: &priv->offload);
2355	spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2356	free_candev(dev: ndev);
2357	}
2358
2359	static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2360	{
2361	struct mcp251xfd_priv *priv = dev_get_drvdata(dev: device);
2362
2363	mcp251xfd_chip_sleep(priv);
2364	return mcp251xfd_clks_and_vdd_disable(priv);
2365	}
2366
2367	static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2368	{
2369	struct mcp251xfd_priv *priv = dev_get_drvdata(dev: device);
2370	int err;
2371
2372	err = mcp251xfd_clks_and_vdd_enable(priv);
2373	if (err)
2374	return err;
2375
2376	err = mcp251xfd_chip_softreset(priv);
2377	if (err == -ENODEV)
2378	goto out_clks_and_vdd_disable;
2379	if (err)
2380	goto out_chip_sleep;
2381
2382	err = mcp251xfd_chip_clock_init(priv);
2383	if (err == -ENODEV)
2384	goto out_clks_and_vdd_disable;
2385	if (err)
2386	goto out_chip_sleep;
2387
2388	return 0;
2389
2390	out_chip_sleep:
2391	mcp251xfd_chip_sleep(priv);
2392	out_clks_and_vdd_disable:
2393	mcp251xfd_clks_and_vdd_disable(priv);
2394
2395	return err;
2396	}
2397
2398	static const struct dev_pm_ops mcp251xfd_pm_ops = {
2399	SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2400	mcp251xfd_runtime_resume, NULL)
2401	};
2402
2403	static struct spi_driver mcp251xfd_driver = {
2404	.driver = {
2405	.name = DEVICE_NAME,
2406	.pm = &mcp251xfd_pm_ops,
2407	.of_match_table = mcp251xfd_of_match,
2408	},
2409	.probe = mcp251xfd_probe,
2410	.remove = mcp251xfd_remove,
2411	.id_table = mcp251xfd_id_table,
2412	};
2413	module_spi_driver(mcp251xfd_driver);
2414
2415	MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2416	MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2417	MODULE_LICENSE("GPL v2");
2418