1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/clk.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/of_net.h>
22#include <linux/of_mdio.h>
23#include <net/dsa.h>
24#include <linux/ethtool.h>
25#include <linux/if_bridge.h>
26#include <linux/brcmphy.h>
27#include <linux/etherdevice.h>
28#include <linux/platform_data/b53.h>
29
30#include "bcm_sf2.h"
31#include "bcm_sf2_regs.h"
32#include "b53/b53_priv.h"
33#include "b53/b53_regs.h"
34
35static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
36{
37 switch (priv->type) {
38 case BCM4908_DEVICE_ID:
39 switch (port) {
40 case 7:
41 return REG_RGMII_11_CNTRL;
42 default:
43 break;
44 }
45 break;
46 default:
47 switch (port) {
48 case 0:
49 return REG_RGMII_0_CNTRL;
50 case 1:
51 return REG_RGMII_1_CNTRL;
52 case 2:
53 return REG_RGMII_2_CNTRL;
54 default:
55 break;
56 }
57 }
58
59 WARN_ONCE(1, "Unsupported port %d\n", port);
60
61 /* RO fallback reg */
62 return REG_SWITCH_STATUS;
63}
64
65static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
66{
67 switch (port) {
68 case 0:
69 return REG_LED_0_CNTRL;
70 case 1:
71 return REG_LED_1_CNTRL;
72 case 2:
73 return REG_LED_2_CNTRL;
74 }
75
76 switch (priv->type) {
77 case BCM4908_DEVICE_ID:
78 switch (port) {
79 case 3:
80 return REG_LED_3_CNTRL;
81 case 7:
82 return REG_LED_4_CNTRL;
83 default:
84 break;
85 }
86 break;
87 default:
88 break;
89 }
90
91 WARN_ONCE(1, "Unsupported port %d\n", port);
92
93 /* RO fallback reg */
94 return REG_SWITCH_STATUS;
95}
96
97static u32 bcm_sf2_port_override_offset(struct bcm_sf2_priv *priv, int port)
98{
99 switch (priv->type) {
100 case BCM4908_DEVICE_ID:
101 case BCM7445_DEVICE_ID:
102 return port == 8 ? CORE_STS_OVERRIDE_IMP :
103 CORE_STS_OVERRIDE_GMIIP_PORT(port);
104 case BCM7278_DEVICE_ID:
105 return port == 8 ? CORE_STS_OVERRIDE_IMP2 :
106 CORE_STS_OVERRIDE_GMIIP2_PORT(port);
107 default:
108 WARN_ONCE(1, "Unsupported device: %d\n", priv->type);
109 }
110
111 /* RO fallback register */
112 return REG_SWITCH_STATUS;
113}
114
115/* Return the number of active ports, not counting the IMP (CPU) port */
116static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
117{
118 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
119 unsigned int port, count = 0;
120
121 for (port = 0; port < ds->num_ports; port++) {
122 if (dsa_is_cpu_port(ds, p: port))
123 continue;
124 if (priv->port_sts[port].enabled)
125 count++;
126 }
127
128 return count;
129}
130
131static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
132{
133 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
134 unsigned long new_rate;
135 unsigned int ports_active;
136 /* Frequenty in Mhz */
137 static const unsigned long rate_table[] = {
138 59220000,
139 60820000,
140 62500000,
141 62500000,
142 };
143
144 ports_active = bcm_sf2_num_active_ports(ds);
145 if (ports_active == 0 || !priv->clk_mdiv)
146 return;
147
148 /* If we overflow our table, just use the recommended operational
149 * frequency
150 */
151 if (ports_active > ARRAY_SIZE(rate_table))
152 new_rate = 90000000;
153 else
154 new_rate = rate_table[ports_active - 1];
155 clk_set_rate(clk: priv->clk_mdiv, rate: new_rate);
156}
157
158static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
159{
160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
161 unsigned int i;
162 u32 reg;
163
164 /* Enable the port memories */
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 reg &= ~P_TXQ_PSM_VDD(port);
167 core_writel(priv, val: reg, CORE_MEM_PSM_VDD_CTRL);
168
169 /* Enable forwarding */
170 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
171
172 /* Enable IMP port in dumb mode */
173 reg = core_readl(priv, CORE_SWITCH_CTRL);
174 reg |= MII_DUMB_FWDG_EN;
175 core_writel(priv, val: reg, CORE_SWITCH_CTRL);
176
177 /* Configure Traffic Class to QoS mapping, allow each priority to map
178 * to a different queue number
179 */
180 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
181 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
182 reg |= i << (PRT_TO_QID_SHIFT * i);
183 core_writel(priv, val: reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
184
185 b53_brcm_hdr_setup(ds, port);
186
187 if (port == 8) {
188 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
189 reg = core_readl(priv, CORE_IMP_CTL);
190 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
191 reg &= ~(RX_DIS | TX_DIS);
192 core_writel(priv, val: reg, CORE_IMP_CTL);
193 } else {
194 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
195 reg &= ~(RX_DIS | TX_DIS);
196 core_writel(priv, val: reg, CORE_G_PCTL_PORT(port));
197 }
198
199 priv->port_sts[port].enabled = true;
200}
201
202static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
203{
204 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
205 u32 reg;
206
207 reg = reg_readl(priv, off: REG_SPHY_CNTRL);
208 if (enable) {
209 reg |= PHY_RESET;
210 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
211 reg_writel(priv, val: reg, off: REG_SPHY_CNTRL);
212 udelay(21);
213 reg = reg_readl(priv, off: REG_SPHY_CNTRL);
214 reg &= ~PHY_RESET;
215 } else {
216 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
217 reg_writel(priv, val: reg, off: REG_SPHY_CNTRL);
218 mdelay(1);
219 reg |= CK25_DIS;
220 }
221 reg_writel(priv, val: reg, off: REG_SPHY_CNTRL);
222
223 /* Use PHY-driven LED signaling */
224 if (!enable) {
225 u16 led_ctrl = bcm_sf2_reg_led_base(priv, port: 0);
226
227 if (priv->type == BCM7278_DEVICE_ID ||
228 priv->type == BCM7445_DEVICE_ID) {
229 reg = reg_led_readl(priv, off: led_ctrl, reg: 0);
230 reg |= LED_CNTRL_SPDLNK_SRC_SEL;
231 reg_led_writel(priv, val: reg, off: led_ctrl, reg: 0);
232 }
233 }
234}
235
236static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
237 int port)
238{
239 unsigned int off;
240
241 switch (port) {
242 case 7:
243 off = P7_IRQ_OFF;
244 break;
245 case 0:
246 /* Port 0 interrupts are located on the first bank */
247 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
248 return;
249 default:
250 off = P_IRQ_OFF(port);
251 break;
252 }
253
254 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
255}
256
257static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
258 int port)
259{
260 unsigned int off;
261
262 switch (port) {
263 case 7:
264 off = P7_IRQ_OFF;
265 break;
266 case 0:
267 /* Port 0 interrupts are located on the first bank */
268 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
269 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
270 return;
271 default:
272 off = P_IRQ_OFF(port);
273 break;
274 }
275
276 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
277 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
278}
279
280static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
281 struct phy_device *phy)
282{
283 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
284 unsigned int i;
285 u32 reg;
286
287 if (!dsa_is_user_port(ds, p: port))
288 return 0;
289
290 priv->port_sts[port].enabled = true;
291
292 bcm_sf2_recalc_clock(ds);
293
294 /* Clear the memory power down */
295 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
296 reg &= ~P_TXQ_PSM_VDD(port);
297 core_writel(priv, val: reg, CORE_MEM_PSM_VDD_CTRL);
298
299 /* Enable Broadcom tags for that port if requested */
300 if (priv->brcm_tag_mask & BIT(port))
301 b53_brcm_hdr_setup(ds, port);
302
303 /* Configure Traffic Class to QoS mapping, allow each priority to map
304 * to a different queue number
305 */
306 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
307 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
308 reg |= i << (PRT_TO_QID_SHIFT * i);
309 core_writel(priv, val: reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
310
311 /* Re-enable the GPHY and re-apply workarounds */
312 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
313 bcm_sf2_gphy_enable_set(ds, enable: true);
314 if (phy) {
315 /* if phy_stop() has been called before, phy
316 * will be in halted state, and phy_start()
317 * will call resume.
318 *
319 * the resume path does not configure back
320 * autoneg settings, and since we hard reset
321 * the phy manually here, we need to reset the
322 * state machine also.
323 */
324 phy->state = PHY_READY;
325 phy_init_hw(phydev: phy);
326 }
327 }
328
329 /* Enable MoCA port interrupts to get notified */
330 if (port == priv->moca_port)
331 bcm_sf2_port_intr_enable(priv, port);
332
333 /* Set per-queue pause threshold to 32 */
334 core_writel(priv, val: 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
335
336 /* Set ACB threshold to 24 */
337 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
338 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
339 SF2_NUM_EGRESS_QUEUES + i));
340 reg &= ~XOFF_THRESHOLD_MASK;
341 reg |= 24;
342 acb_writel(priv, val: reg, ACB_QUEUE_CFG(port *
343 SF2_NUM_EGRESS_QUEUES + i));
344 }
345
346 return b53_enable_port(ds, port, phy);
347}
348
349static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
350{
351 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
352 u32 reg;
353
354 /* Disable learning while in WoL mode */
355 if (priv->wol_ports_mask & (1 << port)) {
356 reg = core_readl(priv, CORE_DIS_LEARN);
357 reg |= BIT(port);
358 core_writel(priv, val: reg, CORE_DIS_LEARN);
359 return;
360 }
361
362 if (port == priv->moca_port)
363 bcm_sf2_port_intr_disable(priv, port);
364
365 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
366 bcm_sf2_gphy_enable_set(ds, enable: false);
367
368 b53_disable_port(ds, port);
369
370 /* Power down the port memory */
371 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
372 reg |= P_TXQ_PSM_VDD(port);
373 core_writel(priv, val: reg, CORE_MEM_PSM_VDD_CTRL);
374
375 priv->port_sts[port].enabled = false;
376
377 bcm_sf2_recalc_clock(ds);
378}
379
380
381static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
382 int regnum, u16 val)
383{
384 int ret = 0;
385 u32 reg;
386
387 reg = reg_readl(priv, off: REG_SWITCH_CNTRL);
388 reg |= MDIO_MASTER_SEL;
389 reg_writel(priv, val: reg, off: REG_SWITCH_CNTRL);
390
391 /* Page << 8 | offset */
392 reg = 0x70;
393 reg <<= 2;
394 core_writel(priv, val: addr, off: reg);
395
396 /* Page << 8 | offset */
397 reg = 0x80 << 8 | regnum << 1;
398 reg <<= 2;
399
400 if (op)
401 ret = core_readl(priv, off: reg);
402 else
403 core_writel(priv, val, off: reg);
404
405 reg = reg_readl(priv, off: REG_SWITCH_CNTRL);
406 reg &= ~MDIO_MASTER_SEL;
407 reg_writel(priv, val: reg, off: REG_SWITCH_CNTRL);
408
409 return ret & 0xffff;
410}
411
412static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
413{
414 struct bcm_sf2_priv *priv = bus->priv;
415
416 /* Intercept reads from Broadcom pseudo-PHY address, else, send
417 * them to our master MDIO bus controller
418 */
419 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
420 return bcm_sf2_sw_indir_rw(priv, op: 1, addr, regnum, val: 0);
421 else
422 return mdiobus_read_nested(bus: priv->master_mii_bus, addr, regnum);
423}
424
425static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
426 u16 val)
427{
428 struct bcm_sf2_priv *priv = bus->priv;
429
430 /* Intercept writes to the Broadcom pseudo-PHY address, else,
431 * send them to our master MDIO bus controller
432 */
433 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
434 return bcm_sf2_sw_indir_rw(priv, op: 0, addr, regnum, val);
435 else
436 return mdiobus_write_nested(bus: priv->master_mii_bus, addr,
437 regnum, val);
438}
439
440static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
441{
442 struct dsa_switch *ds = dev_id;
443 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
444
445 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
446 ~priv->irq0_mask;
447 intrl2_0_writel(priv, val: priv->irq0_stat, INTRL2_CPU_CLEAR);
448
449 return IRQ_HANDLED;
450}
451
452static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
453{
454 struct dsa_switch *ds = dev_id;
455 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
456
457 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
458 ~priv->irq1_mask;
459 intrl2_1_writel(priv, val: priv->irq1_stat, INTRL2_CPU_CLEAR);
460
461 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
462 priv->port_sts[7].link = true;
463 dsa_port_phylink_mac_change(ds, port: 7, up: true);
464 }
465 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
466 priv->port_sts[7].link = false;
467 dsa_port_phylink_mac_change(ds, port: 7, up: false);
468 }
469
470 return IRQ_HANDLED;
471}
472
473static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
474{
475 unsigned int timeout = 1000;
476 u32 reg;
477 int ret;
478
479 /* The watchdog reset does not work on 7278, we need to hit the
480 * "external" reset line through the reset controller.
481 */
482 if (priv->type == BCM7278_DEVICE_ID) {
483 ret = reset_control_assert(rstc: priv->rcdev);
484 if (ret)
485 return ret;
486
487 return reset_control_deassert(rstc: priv->rcdev);
488 }
489
490 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
491 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
492 core_writel(priv, val: reg, CORE_WATCHDOG_CTRL);
493
494 do {
495 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
496 if (!(reg & SOFTWARE_RESET))
497 break;
498
499 usleep_range(min: 1000, max: 2000);
500 } while (timeout-- > 0);
501
502 if (timeout == 0)
503 return -ETIMEDOUT;
504
505 return 0;
506}
507
508static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
509{
510 struct device *dev = priv->dev->ds->dev;
511 int shift;
512 u32 mask;
513 u32 reg;
514 int i;
515
516 mask = BIT(priv->num_crossbar_int_ports) - 1;
517
518 reg = reg_readl(priv, off: REG_CROSSBAR);
519 switch (priv->type) {
520 case BCM4908_DEVICE_ID:
521 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
522 reg &= ~(mask << shift);
523 if (0) /* FIXME */
524 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
525 else if (priv->int_phy_mask & BIT(7))
526 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
527 else if (phy_interface_mode_is_rgmii(mode: priv->port_sts[7].mode))
528 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
529 else if (WARN(1, "Invalid port mode\n"))
530 return;
531 break;
532 default:
533 return;
534 }
535 reg_writel(priv, val: reg, off: REG_CROSSBAR);
536
537 reg = reg_readl(priv, off: REG_CROSSBAR);
538 for (i = 0; i < priv->num_crossbar_int_ports; i++) {
539 shift = i * priv->num_crossbar_int_ports;
540
541 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
542 (reg >> shift) & mask);
543 }
544}
545
546static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
547{
548 intrl2_0_mask_set(priv, mask: 0xffffffff);
549 intrl2_0_writel(priv, val: 0xffffffff, INTRL2_CPU_CLEAR);
550 intrl2_1_mask_set(priv, mask: 0xffffffff);
551 intrl2_1_writel(priv, val: 0xffffffff, INTRL2_CPU_CLEAR);
552}
553
554static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
555 struct device_node *dn)
556{
557 struct device *dev = priv->dev->ds->dev;
558 struct bcm_sf2_port_status *port_st;
559 struct device_node *port;
560 unsigned int port_num;
561 struct property *prop;
562 int err;
563
564 priv->moca_port = -1;
565
566 for_each_available_child_of_node(dn, port) {
567 if (of_property_read_u32(np: port, propname: "reg", out_value: &port_num))
568 continue;
569
570 if (port_num >= DSA_MAX_PORTS) {
571 dev_err(dev, "Invalid port number %d\n", port_num);
572 continue;
573 }
574
575 port_st = &priv->port_sts[port_num];
576
577 /* Internal PHYs get assigned a specific 'phy-mode' property
578 * value: "internal" to help flag them before MDIO probing
579 * has completed, since they might be turned off at that
580 * time
581 */
582 err = of_get_phy_mode(np: port, interface: &port_st->mode);
583 if (err)
584 continue;
585
586 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
587 priv->int_phy_mask |= 1 << port_num;
588
589 if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
590 priv->moca_port = port_num;
591
592 if (of_property_read_bool(np: port, propname: "brcm,use-bcm-hdr"))
593 priv->brcm_tag_mask |= 1 << port_num;
594
595 /* Ensure that port 5 is not picked up as a DSA CPU port
596 * flavour but a regular port instead. We should be using
597 * devlink to be able to set the port flavour.
598 */
599 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
600 prop = of_find_property(np: port, name: "ethernet", NULL);
601 if (prop)
602 of_remove_property(np: port, prop);
603 }
604 }
605}
606
607static int bcm_sf2_mdio_register(struct dsa_switch *ds)
608{
609 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
610 struct device_node *dn, *child;
611 struct phy_device *phydev;
612 struct property *prop;
613 static int index;
614 int err, reg;
615
616 /* Find our integrated MDIO bus node */
617 dn = of_find_compatible_node(NULL, NULL, compat: "brcm,unimac-mdio");
618 priv->master_mii_bus = of_mdio_find_bus(mdio_np: dn);
619 if (!priv->master_mii_bus) {
620 err = -EPROBE_DEFER;
621 goto err_of_node_put;
622 }
623
624 priv->user_mii_bus = mdiobus_alloc();
625 if (!priv->user_mii_bus) {
626 err = -ENOMEM;
627 goto err_put_master_mii_bus_dev;
628 }
629
630 priv->user_mii_bus->priv = priv;
631 priv->user_mii_bus->name = "sf2 user mii";
632 priv->user_mii_bus->read = bcm_sf2_sw_mdio_read;
633 priv->user_mii_bus->write = bcm_sf2_sw_mdio_write;
634 snprintf(buf: priv->user_mii_bus->id, MII_BUS_ID_SIZE, fmt: "sf2-%d",
635 index++);
636
637 /* Include the pseudo-PHY address to divert reads towards our
638 * workaround. This is only required for 7445D0, since 7445E0
639 * disconnects the internal switch pseudo-PHY such that we can use the
640 * regular SWITCH_MDIO master controller instead.
641 *
642 * Here we flag the pseudo PHY as needing special treatment and would
643 * otherwise make all other PHY read/writes go to the master MDIO bus
644 * controller that comes with this switch backed by the "mdio-unimac"
645 * driver.
646 */
647 if (of_machine_is_compatible(compat: "brcm,bcm7445d0"))
648 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
649 else
650 priv->indir_phy_mask = 0;
651
652 ds->phys_mii_mask = priv->indir_phy_mask;
653 ds->user_mii_bus = priv->user_mii_bus;
654 priv->user_mii_bus->parent = ds->dev->parent;
655 priv->user_mii_bus->phy_mask = ~priv->indir_phy_mask;
656
657 /* We need to make sure that of_phy_connect() will not work by
658 * removing the 'phandle' and 'linux,phandle' properties and
659 * unregister the existing PHY device that was already registered.
660 */
661 for_each_available_child_of_node(dn, child) {
662 if (of_property_read_u32(np: child, propname: "reg", out_value: &reg) ||
663 reg >= PHY_MAX_ADDR)
664 continue;
665
666 if (!(priv->indir_phy_mask & BIT(reg)))
667 continue;
668
669 prop = of_find_property(np: child, name: "phandle", NULL);
670 if (prop)
671 of_remove_property(np: child, prop);
672
673 prop = of_find_property(np: child, name: "linux,phandle", NULL);
674 if (prop)
675 of_remove_property(np: child, prop);
676
677 phydev = of_phy_find_device(phy_np: child);
678 if (phydev)
679 phy_device_remove(phydev);
680 }
681
682 err = mdiobus_register(priv->user_mii_bus);
683 if (err)
684 goto err_free_user_mii_bus;
685
686 of_node_put(node: dn);
687
688 return 0;
689
690err_free_user_mii_bus:
691 mdiobus_free(bus: priv->user_mii_bus);
692err_put_master_mii_bus_dev:
693 put_device(dev: &priv->master_mii_bus->dev);
694err_of_node_put:
695 of_node_put(node: dn);
696 return err;
697}
698
699static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
700{
701 mdiobus_unregister(bus: priv->user_mii_bus);
702 mdiobus_free(bus: priv->user_mii_bus);
703 put_device(dev: &priv->master_mii_bus->dev);
704}
705
706static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
707{
708 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
709
710 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
711 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
712 * the REG_PHY_REVISION register layout is.
713 */
714 if (priv->int_phy_mask & BIT(port))
715 return priv->hw_params.gphy_rev;
716 else
717 return PHY_BRCM_AUTO_PWRDWN_ENABLE |
718 PHY_BRCM_DIS_TXCRXC_NOENRGY |
719 PHY_BRCM_IDDQ_SUSPEND;
720}
721
722static void bcm_sf2_sw_get_caps(struct dsa_switch *ds, int port,
723 struct phylink_config *config)
724{
725 unsigned long *interfaces = config->supported_interfaces;
726 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
727
728 if (priv->int_phy_mask & BIT(port)) {
729 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);
730 } else if (priv->moca_port == port) {
731 __set_bit(PHY_INTERFACE_MODE_MOCA, interfaces);
732 } else {
733 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);
734 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
735 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
736 phy_interface_set_rgmii(intf: interfaces);
737 }
738
739 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
740 MAC_10 | MAC_100 | MAC_1000;
741}
742
743static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
744 unsigned int mode,
745 const struct phylink_link_state *state)
746{
747 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
748 u32 id_mode_dis = 0, port_mode;
749 u32 reg_rgmii_ctrl;
750 u32 reg;
751
752 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
753 return;
754
755 switch (state->interface) {
756 case PHY_INTERFACE_MODE_RGMII:
757 id_mode_dis = 1;
758 fallthrough;
759 case PHY_INTERFACE_MODE_RGMII_TXID:
760 port_mode = EXT_GPHY;
761 break;
762 case PHY_INTERFACE_MODE_MII:
763 port_mode = EXT_EPHY;
764 break;
765 case PHY_INTERFACE_MODE_REVMII:
766 port_mode = EXT_REVMII;
767 break;
768 default:
769 /* Nothing required for all other PHYs: internal and MoCA */
770 return;
771 }
772
773 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
774
775 /* Clear id_mode_dis bit, and the existing port mode, let
776 * RGMII_MODE_EN bet set by mac_link_{up,down}
777 */
778 reg = reg_readl(priv, off: reg_rgmii_ctrl);
779 reg &= ~ID_MODE_DIS;
780 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
781
782 reg |= port_mode;
783 if (id_mode_dis)
784 reg |= ID_MODE_DIS;
785
786 reg_writel(priv, val: reg, off: reg_rgmii_ctrl);
787}
788
789static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
790 phy_interface_t interface, bool link)
791{
792 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
793 u32 reg_rgmii_ctrl;
794 u32 reg;
795
796 if (!phy_interface_mode_is_rgmii(mode: interface) &&
797 interface != PHY_INTERFACE_MODE_MII &&
798 interface != PHY_INTERFACE_MODE_REVMII)
799 return;
800
801 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
802
803 /* If the link is down, just disable the interface to conserve power */
804 reg = reg_readl(priv, off: reg_rgmii_ctrl);
805 if (link)
806 reg |= RGMII_MODE_EN;
807 else
808 reg &= ~RGMII_MODE_EN;
809 reg_writel(priv, val: reg, off: reg_rgmii_ctrl);
810}
811
812static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
813 unsigned int mode,
814 phy_interface_t interface)
815{
816 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
817 u32 reg, offset;
818
819 if (priv->wol_ports_mask & BIT(port))
820 return;
821
822 offset = bcm_sf2_port_override_offset(priv, port);
823 reg = core_readl(priv, off: offset);
824 reg &= ~LINK_STS;
825 core_writel(priv, val: reg, off: offset);
826
827 bcm_sf2_sw_mac_link_set(ds, port, interface, link: false);
828}
829
830static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
831 unsigned int mode,
832 phy_interface_t interface,
833 struct phy_device *phydev,
834 int speed, int duplex,
835 bool tx_pause, bool rx_pause)
836{
837 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
838 struct ethtool_keee *p = &priv->dev->ports[port].eee;
839 u32 reg_rgmii_ctrl = 0;
840 u32 reg, offset;
841
842 bcm_sf2_sw_mac_link_set(ds, port, interface, link: true);
843
844 offset = bcm_sf2_port_override_offset(priv, port);
845
846 if (phy_interface_mode_is_rgmii(mode: interface) ||
847 interface == PHY_INTERFACE_MODE_MII ||
848 interface == PHY_INTERFACE_MODE_REVMII) {
849 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
850 reg = reg_readl(priv, off: reg_rgmii_ctrl);
851 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
852
853 if (tx_pause)
854 reg |= TX_PAUSE_EN;
855 if (rx_pause)
856 reg |= RX_PAUSE_EN;
857
858 reg_writel(priv, val: reg, off: reg_rgmii_ctrl);
859 }
860
861 reg = LINK_STS;
862 if (port == 8) {
863 if (priv->type == BCM4908_DEVICE_ID)
864 reg |= GMII_SPEED_UP_2G;
865 reg |= MII_SW_OR;
866 } else {
867 reg |= SW_OVERRIDE;
868 }
869
870 switch (speed) {
871 case SPEED_1000:
872 reg |= SPDSTS_1000 << SPEED_SHIFT;
873 break;
874 case SPEED_100:
875 reg |= SPDSTS_100 << SPEED_SHIFT;
876 break;
877 }
878
879 if (duplex == DUPLEX_FULL)
880 reg |= DUPLX_MODE;
881
882 if (tx_pause)
883 reg |= TXFLOW_CNTL;
884 if (rx_pause)
885 reg |= RXFLOW_CNTL;
886
887 core_writel(priv, val: reg, off: offset);
888
889 if (mode == MLO_AN_PHY && phydev)
890 p->eee_enabled = b53_eee_init(ds, port, phy: phydev);
891}
892
893static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
894 struct phylink_link_state *status)
895{
896 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
897
898 status->link = false;
899
900 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
901 * which means that we need to force the link at the port override
902 * level to get the data to flow. We do use what the interrupt handler
903 * did determine before.
904 *
905 * For the other ports, we just force the link status, since this is
906 * a fixed PHY device.
907 */
908 if (port == priv->moca_port) {
909 status->link = priv->port_sts[port].link;
910 /* For MoCA interfaces, also force a link down notification
911 * since some version of the user-space daemon (mocad) use
912 * cmd->autoneg to force the link, which messes up the PHY
913 * state machine and make it go in PHY_FORCING state instead.
914 */
915 if (!status->link)
916 netif_carrier_off(dev: dsa_to_port(ds, p: port)->user);
917 status->duplex = DUPLEX_FULL;
918 } else {
919 status->link = true;
920 }
921}
922
923static void bcm_sf2_enable_acb(struct dsa_switch *ds)
924{
925 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
926 u32 reg;
927
928 /* Enable ACB globally */
929 reg = acb_readl(priv, ACB_CONTROL);
930 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
931 acb_writel(priv, val: reg, ACB_CONTROL);
932 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
933 reg |= ACB_EN | ACB_ALGORITHM;
934 acb_writel(priv, val: reg, ACB_CONTROL);
935}
936
937static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
938{
939 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
940 unsigned int port;
941
942 bcm_sf2_intr_disable(priv);
943
944 /* Disable all ports physically present including the IMP
945 * port, the other ones have already been disabled during
946 * bcm_sf2_sw_setup
947 */
948 for (port = 0; port < ds->num_ports; port++) {
949 if (dsa_is_user_port(ds, p: port) || dsa_is_cpu_port(ds, p: port))
950 bcm_sf2_port_disable(ds, port);
951 }
952
953 if (!priv->wol_ports_mask)
954 clk_disable_unprepare(clk: priv->clk);
955
956 return 0;
957}
958
959static int bcm_sf2_sw_resume(struct dsa_switch *ds)
960{
961 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
962 int ret;
963
964 if (!priv->wol_ports_mask)
965 clk_prepare_enable(clk: priv->clk);
966
967 ret = bcm_sf2_sw_rst(priv);
968 if (ret) {
969 pr_err("%s: failed to software reset switch\n", __func__);
970 return ret;
971 }
972
973 bcm_sf2_crossbar_setup(priv);
974
975 ret = bcm_sf2_cfp_resume(ds);
976 if (ret)
977 return ret;
978
979 if (priv->hw_params.num_gphy == 1)
980 bcm_sf2_gphy_enable_set(ds, enable: true);
981
982 ds->ops->setup(ds);
983
984 return 0;
985}
986
987static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
988 struct ethtool_wolinfo *wol)
989{
990 struct net_device *p = dsa_port_to_conduit(dp: dsa_to_port(ds, p: port));
991 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
992 struct ethtool_wolinfo pwol = { };
993
994 /* Get the parent device WoL settings */
995 if (p->ethtool_ops->get_wol)
996 p->ethtool_ops->get_wol(p, &pwol);
997
998 /* Advertise the parent device supported settings */
999 wol->supported = pwol.supported;
1000 memset(&wol->sopass, 0, sizeof(wol->sopass));
1001
1002 if (pwol.wolopts & WAKE_MAGICSECURE)
1003 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1004
1005 if (priv->wol_ports_mask & (1 << port))
1006 wol->wolopts = pwol.wolopts;
1007 else
1008 wol->wolopts = 0;
1009}
1010
1011static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1012 struct ethtool_wolinfo *wol)
1013{
1014 struct net_device *p = dsa_port_to_conduit(dp: dsa_to_port(ds, p: port));
1015 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1016 s8 cpu_port = dsa_to_port(ds, p: port)->cpu_dp->index;
1017 struct ethtool_wolinfo pwol = { };
1018
1019 if (p->ethtool_ops->get_wol)
1020 p->ethtool_ops->get_wol(p, &pwol);
1021 if (wol->wolopts & ~pwol.supported)
1022 return -EINVAL;
1023
1024 if (wol->wolopts)
1025 priv->wol_ports_mask |= (1 << port);
1026 else
1027 priv->wol_ports_mask &= ~(1 << port);
1028
1029 /* If we have at least one port enabled, make sure the CPU port
1030 * is also enabled. If the CPU port is the last one enabled, we disable
1031 * it since this configuration does not make sense.
1032 */
1033 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1034 priv->wol_ports_mask |= (1 << cpu_port);
1035 else
1036 priv->wol_ports_mask &= ~(1 << cpu_port);
1037
1038 return p->ethtool_ops->set_wol(p, wol);
1039}
1040
1041static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1042{
1043 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1044 unsigned int port;
1045
1046 /* Enable all valid ports and disable those unused */
1047 for (port = 0; port < priv->hw_params.num_ports; port++) {
1048 /* IMP port receives special treatment */
1049 if (dsa_is_user_port(ds, p: port))
1050 bcm_sf2_port_setup(ds, port, NULL);
1051 else if (dsa_is_cpu_port(ds, p: port))
1052 bcm_sf2_imp_setup(ds, port);
1053 else
1054 bcm_sf2_port_disable(ds, port);
1055 }
1056
1057 b53_configure_vlan(ds);
1058 bcm_sf2_enable_acb(ds);
1059
1060 return b53_setup_devlink_resources(ds);
1061}
1062
1063static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1064{
1065 dsa_devlink_resources_unregister(ds);
1066}
1067
1068/* The SWITCH_CORE register space is managed by b53 but operates on a page +
1069 * register basis so we need to translate that into an address that the
1070 * bus-glue understands.
1071 */
1072#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1073
1074static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1075 u8 *val)
1076{
1077 struct bcm_sf2_priv *priv = dev->priv;
1078
1079 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1080
1081 return 0;
1082}
1083
1084static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1085 u16 *val)
1086{
1087 struct bcm_sf2_priv *priv = dev->priv;
1088
1089 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1090
1091 return 0;
1092}
1093
1094static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1095 u32 *val)
1096{
1097 struct bcm_sf2_priv *priv = dev->priv;
1098
1099 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1100
1101 return 0;
1102}
1103
1104static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1105 u64 *val)
1106{
1107 struct bcm_sf2_priv *priv = dev->priv;
1108
1109 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1110
1111 return 0;
1112}
1113
1114static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1115 u8 value)
1116{
1117 struct bcm_sf2_priv *priv = dev->priv;
1118
1119 core_writel(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1120
1121 return 0;
1122}
1123
1124static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1125 u16 value)
1126{
1127 struct bcm_sf2_priv *priv = dev->priv;
1128
1129 core_writel(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1130
1131 return 0;
1132}
1133
1134static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1135 u32 value)
1136{
1137 struct bcm_sf2_priv *priv = dev->priv;
1138
1139 core_writel(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1140
1141 return 0;
1142}
1143
1144static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1145 u64 value)
1146{
1147 struct bcm_sf2_priv *priv = dev->priv;
1148
1149 core_writeq(priv, val: value, SF2_PAGE_REG_MKADDR(page, reg));
1150
1151 return 0;
1152}
1153
1154static const struct b53_io_ops bcm_sf2_io_ops = {
1155 .read8 = bcm_sf2_core_read8,
1156 .read16 = bcm_sf2_core_read16,
1157 .read32 = bcm_sf2_core_read32,
1158 .read48 = bcm_sf2_core_read64,
1159 .read64 = bcm_sf2_core_read64,
1160 .write8 = bcm_sf2_core_write8,
1161 .write16 = bcm_sf2_core_write16,
1162 .write32 = bcm_sf2_core_write32,
1163 .write48 = bcm_sf2_core_write64,
1164 .write64 = bcm_sf2_core_write64,
1165};
1166
1167static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1168 u32 stringset, uint8_t *data)
1169{
1170 int cnt = b53_get_sset_count(ds, port, sset: stringset);
1171
1172 b53_get_strings(ds, port, stringset, data);
1173 bcm_sf2_cfp_get_strings(ds, port, stringset,
1174 data: data + cnt * ETH_GSTRING_LEN);
1175}
1176
1177static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1178 uint64_t *data)
1179{
1180 int cnt = b53_get_sset_count(ds, port, sset: ETH_SS_STATS);
1181
1182 b53_get_ethtool_stats(ds, port, data);
1183 bcm_sf2_cfp_get_ethtool_stats(ds, port, data: data + cnt);
1184}
1185
1186static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1187 int sset)
1188{
1189 int cnt = b53_get_sset_count(ds, port, sset);
1190
1191 if (cnt < 0)
1192 return cnt;
1193
1194 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1195
1196 return cnt;
1197}
1198
1199static const struct dsa_switch_ops bcm_sf2_ops = {
1200 .get_tag_protocol = b53_get_tag_protocol,
1201 .setup = bcm_sf2_sw_setup,
1202 .teardown = bcm_sf2_sw_teardown,
1203 .get_strings = bcm_sf2_sw_get_strings,
1204 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1205 .get_sset_count = bcm_sf2_sw_get_sset_count,
1206 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1207 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1208 .phylink_get_caps = bcm_sf2_sw_get_caps,
1209 .phylink_mac_config = bcm_sf2_sw_mac_config,
1210 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1211 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1212 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1213 .suspend = bcm_sf2_sw_suspend,
1214 .resume = bcm_sf2_sw_resume,
1215 .get_wol = bcm_sf2_sw_get_wol,
1216 .set_wol = bcm_sf2_sw_set_wol,
1217 .port_enable = bcm_sf2_port_setup,
1218 .port_disable = bcm_sf2_port_disable,
1219 .get_mac_eee = b53_get_mac_eee,
1220 .set_mac_eee = b53_set_mac_eee,
1221 .port_bridge_join = b53_br_join,
1222 .port_bridge_leave = b53_br_leave,
1223 .port_pre_bridge_flags = b53_br_flags_pre,
1224 .port_bridge_flags = b53_br_flags,
1225 .port_stp_state_set = b53_br_set_stp_state,
1226 .port_fast_age = b53_br_fast_age,
1227 .port_vlan_filtering = b53_vlan_filtering,
1228 .port_vlan_add = b53_vlan_add,
1229 .port_vlan_del = b53_vlan_del,
1230 .port_fdb_dump = b53_fdb_dump,
1231 .port_fdb_add = b53_fdb_add,
1232 .port_fdb_del = b53_fdb_del,
1233 .get_rxnfc = bcm_sf2_get_rxnfc,
1234 .set_rxnfc = bcm_sf2_set_rxnfc,
1235 .port_mirror_add = b53_mirror_add,
1236 .port_mirror_del = b53_mirror_del,
1237 .port_mdb_add = b53_mdb_add,
1238 .port_mdb_del = b53_mdb_del,
1239};
1240
1241struct bcm_sf2_of_data {
1242 u32 type;
1243 const u16 *reg_offsets;
1244 unsigned int core_reg_align;
1245 unsigned int num_cfp_rules;
1246 unsigned int num_crossbar_int_ports;
1247};
1248
1249static const u16 bcm_sf2_4908_reg_offsets[] = {
1250 [REG_SWITCH_CNTRL] = 0x00,
1251 [REG_SWITCH_STATUS] = 0x04,
1252 [REG_DIR_DATA_WRITE] = 0x08,
1253 [REG_DIR_DATA_READ] = 0x0c,
1254 [REG_SWITCH_REVISION] = 0x10,
1255 [REG_PHY_REVISION] = 0x14,
1256 [REG_SPHY_CNTRL] = 0x24,
1257 [REG_CROSSBAR] = 0xc8,
1258 [REG_RGMII_11_CNTRL] = 0x014c,
1259 [REG_LED_0_CNTRL] = 0x40,
1260 [REG_LED_1_CNTRL] = 0x4c,
1261 [REG_LED_2_CNTRL] = 0x58,
1262 [REG_LED_3_CNTRL] = 0x64,
1263 [REG_LED_4_CNTRL] = 0x88,
1264 [REG_LED_5_CNTRL] = 0xa0,
1265 [REG_LED_AGGREGATE_CTRL] = 0xb8,
1266
1267};
1268
1269static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1270 .type = BCM4908_DEVICE_ID,
1271 .core_reg_align = 0,
1272 .reg_offsets = bcm_sf2_4908_reg_offsets,
1273 .num_cfp_rules = 256,
1274 .num_crossbar_int_ports = 2,
1275};
1276
1277/* Register offsets for the SWITCH_REG_* block */
1278static const u16 bcm_sf2_7445_reg_offsets[] = {
1279 [REG_SWITCH_CNTRL] = 0x00,
1280 [REG_SWITCH_STATUS] = 0x04,
1281 [REG_DIR_DATA_WRITE] = 0x08,
1282 [REG_DIR_DATA_READ] = 0x0C,
1283 [REG_SWITCH_REVISION] = 0x18,
1284 [REG_PHY_REVISION] = 0x1C,
1285 [REG_SPHY_CNTRL] = 0x2C,
1286 [REG_RGMII_0_CNTRL] = 0x34,
1287 [REG_RGMII_1_CNTRL] = 0x40,
1288 [REG_RGMII_2_CNTRL] = 0x4c,
1289 [REG_LED_0_CNTRL] = 0x90,
1290 [REG_LED_1_CNTRL] = 0x94,
1291 [REG_LED_2_CNTRL] = 0x98,
1292};
1293
1294static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1295 .type = BCM7445_DEVICE_ID,
1296 .core_reg_align = 0,
1297 .reg_offsets = bcm_sf2_7445_reg_offsets,
1298 .num_cfp_rules = 256,
1299};
1300
1301static const u16 bcm_sf2_7278_reg_offsets[] = {
1302 [REG_SWITCH_CNTRL] = 0x00,
1303 [REG_SWITCH_STATUS] = 0x04,
1304 [REG_DIR_DATA_WRITE] = 0x08,
1305 [REG_DIR_DATA_READ] = 0x0c,
1306 [REG_SWITCH_REVISION] = 0x10,
1307 [REG_PHY_REVISION] = 0x14,
1308 [REG_SPHY_CNTRL] = 0x24,
1309 [REG_RGMII_0_CNTRL] = 0xe0,
1310 [REG_RGMII_1_CNTRL] = 0xec,
1311 [REG_RGMII_2_CNTRL] = 0xf8,
1312 [REG_LED_0_CNTRL] = 0x40,
1313 [REG_LED_1_CNTRL] = 0x4c,
1314 [REG_LED_2_CNTRL] = 0x58,
1315};
1316
1317static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1318 .type = BCM7278_DEVICE_ID,
1319 .core_reg_align = 1,
1320 .reg_offsets = bcm_sf2_7278_reg_offsets,
1321 .num_cfp_rules = 128,
1322};
1323
1324static const struct of_device_id bcm_sf2_of_match[] = {
1325 { .compatible = "brcm,bcm4908-switch",
1326 .data = &bcm_sf2_4908_data
1327 },
1328 { .compatible = "brcm,bcm7445-switch-v4.0",
1329 .data = &bcm_sf2_7445_data
1330 },
1331 { .compatible = "brcm,bcm7278-switch-v4.0",
1332 .data = &bcm_sf2_7278_data
1333 },
1334 { .compatible = "brcm,bcm7278-switch-v4.8",
1335 .data = &bcm_sf2_7278_data
1336 },
1337 { /* sentinel */ },
1338};
1339MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1340
1341static int bcm_sf2_sw_probe(struct platform_device *pdev)
1342{
1343 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1344 struct device_node *dn = pdev->dev.of_node;
1345 const struct of_device_id *of_id = NULL;
1346 const struct bcm_sf2_of_data *data;
1347 struct b53_platform_data *pdata;
1348 struct dsa_switch_ops *ops;
1349 struct device_node *ports;
1350 struct bcm_sf2_priv *priv;
1351 struct b53_device *dev;
1352 struct dsa_switch *ds;
1353 void __iomem **base;
1354 unsigned int i;
1355 u32 reg, rev;
1356 int ret;
1357
1358 priv = devm_kzalloc(dev: &pdev->dev, size: sizeof(*priv), GFP_KERNEL);
1359 if (!priv)
1360 return -ENOMEM;
1361
1362 ops = devm_kzalloc(dev: &pdev->dev, size: sizeof(*ops), GFP_KERNEL);
1363 if (!ops)
1364 return -ENOMEM;
1365
1366 dev = b53_switch_alloc(base: &pdev->dev, ops: &bcm_sf2_io_ops, priv);
1367 if (!dev)
1368 return -ENOMEM;
1369
1370 pdata = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pdata), GFP_KERNEL);
1371 if (!pdata)
1372 return -ENOMEM;
1373
1374 of_id = of_match_node(matches: bcm_sf2_of_match, node: dn);
1375 if (!of_id || !of_id->data)
1376 return -EINVAL;
1377
1378 data = of_id->data;
1379
1380 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1381 priv->type = data->type;
1382 priv->reg_offsets = data->reg_offsets;
1383 priv->core_reg_align = data->core_reg_align;
1384 priv->num_cfp_rules = data->num_cfp_rules;
1385 priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1386
1387 priv->rcdev = devm_reset_control_get_optional_exclusive(dev: &pdev->dev,
1388 id: "switch");
1389 if (IS_ERR(ptr: priv->rcdev))
1390 return PTR_ERR(ptr: priv->rcdev);
1391
1392 /* Auto-detection using standard registers will not work, so
1393 * provide an indication of what kind of device we are for
1394 * b53_common to work with
1395 */
1396 pdata->chip_id = priv->type;
1397 dev->pdata = pdata;
1398
1399 priv->dev = dev;
1400 ds = dev->ds;
1401 ds->ops = &bcm_sf2_ops;
1402
1403 /* Advertise the 8 egress queues */
1404 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1405
1406 dev_set_drvdata(dev: &pdev->dev, data: priv);
1407
1408 spin_lock_init(&priv->indir_lock);
1409 mutex_init(&priv->cfp.lock);
1410 INIT_LIST_HEAD(list: &priv->cfp.rules_list);
1411
1412 /* CFP rule #0 cannot be used for specific classifications, flag it as
1413 * permanently used
1414 */
1415 set_bit(nr: 0, addr: priv->cfp.used);
1416 set_bit(nr: 0, addr: priv->cfp.unique);
1417
1418 /* Balance of_node_put() done by of_find_node_by_name() */
1419 of_node_get(node: dn);
1420 ports = of_find_node_by_name(from: dn, name: "ports");
1421 if (ports) {
1422 bcm_sf2_identify_ports(priv, dn: ports);
1423 of_node_put(node: ports);
1424 }
1425
1426 priv->irq0 = irq_of_parse_and_map(node: dn, index: 0);
1427 priv->irq1 = irq_of_parse_and_map(node: dn, index: 1);
1428
1429 base = &priv->core;
1430 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1431 *base = devm_platform_ioremap_resource(pdev, index: i);
1432 if (IS_ERR(ptr: *base)) {
1433 pr_err("unable to find register: %s\n", reg_names[i]);
1434 return PTR_ERR(ptr: *base);
1435 }
1436 base++;
1437 }
1438
1439 priv->clk = devm_clk_get_optional(dev: &pdev->dev, id: "sw_switch");
1440 if (IS_ERR(ptr: priv->clk))
1441 return PTR_ERR(ptr: priv->clk);
1442
1443 ret = clk_prepare_enable(clk: priv->clk);
1444 if (ret)
1445 return ret;
1446
1447 priv->clk_mdiv = devm_clk_get_optional(dev: &pdev->dev, id: "sw_switch_mdiv");
1448 if (IS_ERR(ptr: priv->clk_mdiv)) {
1449 ret = PTR_ERR(ptr: priv->clk_mdiv);
1450 goto out_clk;
1451 }
1452
1453 ret = clk_prepare_enable(clk: priv->clk_mdiv);
1454 if (ret)
1455 goto out_clk;
1456
1457 ret = bcm_sf2_sw_rst(priv);
1458 if (ret) {
1459 pr_err("unable to software reset switch: %d\n", ret);
1460 goto out_clk_mdiv;
1461 }
1462
1463 bcm_sf2_crossbar_setup(priv);
1464
1465 bcm_sf2_gphy_enable_set(ds: priv->dev->ds, enable: true);
1466
1467 ret = bcm_sf2_mdio_register(ds);
1468 if (ret) {
1469 pr_err("failed to register MDIO bus\n");
1470 goto out_clk_mdiv;
1471 }
1472
1473 bcm_sf2_gphy_enable_set(ds: priv->dev->ds, enable: false);
1474
1475 ret = bcm_sf2_cfp_rst(priv);
1476 if (ret) {
1477 pr_err("failed to reset CFP\n");
1478 goto out_mdio;
1479 }
1480
1481 /* Disable all interrupts and request them */
1482 bcm_sf2_intr_disable(priv);
1483
1484 ret = devm_request_irq(dev: &pdev->dev, irq: priv->irq0, handler: bcm_sf2_switch_0_isr, irqflags: 0,
1485 devname: "switch_0", dev_id: ds);
1486 if (ret < 0) {
1487 pr_err("failed to request switch_0 IRQ\n");
1488 goto out_mdio;
1489 }
1490
1491 ret = devm_request_irq(dev: &pdev->dev, irq: priv->irq1, handler: bcm_sf2_switch_1_isr, irqflags: 0,
1492 devname: "switch_1", dev_id: ds);
1493 if (ret < 0) {
1494 pr_err("failed to request switch_1 IRQ\n");
1495 goto out_mdio;
1496 }
1497
1498 /* Reset the MIB counters */
1499 reg = core_readl(priv, CORE_GMNCFGCFG);
1500 reg |= RST_MIB_CNT;
1501 core_writel(priv, val: reg, CORE_GMNCFGCFG);
1502 reg &= ~RST_MIB_CNT;
1503 core_writel(priv, val: reg, CORE_GMNCFGCFG);
1504
1505 /* Get the maximum number of ports for this switch */
1506 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1507 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1508 priv->hw_params.num_ports = DSA_MAX_PORTS;
1509
1510 /* Assume a single GPHY setup if we can't read that property */
1511 if (of_property_read_u32(np: dn, propname: "brcm,num-gphy",
1512 out_value: &priv->hw_params.num_gphy))
1513 priv->hw_params.num_gphy = 1;
1514
1515 rev = reg_readl(priv, off: REG_SWITCH_REVISION);
1516 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1517 SWITCH_TOP_REV_MASK;
1518 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1519
1520 rev = reg_readl(priv, off: REG_PHY_REVISION);
1521 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1522
1523 ret = b53_switch_register(dev);
1524 if (ret)
1525 goto out_mdio;
1526
1527 dev_info(&pdev->dev,
1528 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1529 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1530 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1531 priv->irq0, priv->irq1);
1532
1533 return 0;
1534
1535out_mdio:
1536 bcm_sf2_mdio_unregister(priv);
1537out_clk_mdiv:
1538 clk_disable_unprepare(clk: priv->clk_mdiv);
1539out_clk:
1540 clk_disable_unprepare(clk: priv->clk);
1541 return ret;
1542}
1543
1544static void bcm_sf2_sw_remove(struct platform_device *pdev)
1545{
1546 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1547
1548 if (!priv)
1549 return;
1550
1551 priv->wol_ports_mask = 0;
1552 /* Disable interrupts */
1553 bcm_sf2_intr_disable(priv);
1554 dsa_unregister_switch(ds: priv->dev->ds);
1555 bcm_sf2_cfp_exit(ds: priv->dev->ds);
1556 bcm_sf2_mdio_unregister(priv);
1557 clk_disable_unprepare(clk: priv->clk_mdiv);
1558 clk_disable_unprepare(clk: priv->clk);
1559 if (priv->type == BCM7278_DEVICE_ID)
1560 reset_control_assert(rstc: priv->rcdev);
1561}
1562
1563static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1564{
1565 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1566
1567 if (!priv)
1568 return;
1569
1570 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1571 * successful MDIO bus scan to occur. If we did turn off the GPHY
1572 * before (e.g: port_disable), this will also power it back on.
1573 *
1574 * Do not rely on kexec_in_progress, just power the PHY on.
1575 */
1576 if (priv->hw_params.num_gphy == 1)
1577 bcm_sf2_gphy_enable_set(ds: priv->dev->ds, enable: true);
1578
1579 dsa_switch_shutdown(ds: priv->dev->ds);
1580
1581 platform_set_drvdata(pdev, NULL);
1582}
1583
1584#ifdef CONFIG_PM_SLEEP
1585static int bcm_sf2_suspend(struct device *dev)
1586{
1587 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1588
1589 return dsa_switch_suspend(ds: priv->dev->ds);
1590}
1591
1592static int bcm_sf2_resume(struct device *dev)
1593{
1594 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1595
1596 return dsa_switch_resume(ds: priv->dev->ds);
1597}
1598#endif /* CONFIG_PM_SLEEP */
1599
1600static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1601 bcm_sf2_suspend, bcm_sf2_resume);
1602
1603
1604static struct platform_driver bcm_sf2_driver = {
1605 .probe = bcm_sf2_sw_probe,
1606 .remove_new = bcm_sf2_sw_remove,
1607 .shutdown = bcm_sf2_sw_shutdown,
1608 .driver = {
1609 .name = "brcm-sf2",
1610 .of_match_table = bcm_sf2_of_match,
1611 .pm = &bcm_sf2_pm_ops,
1612 },
1613};
1614module_platform_driver(bcm_sf2_driver);
1615
1616MODULE_AUTHOR("Broadcom Corporation");
1617MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1618MODULE_LICENSE("GPL");
1619MODULE_ALIAS("platform:brcm-sf2");
1620

source code of linux/drivers/net/dsa/bcm_sf2.c