1/* SPDX-License-Identifier: GPL-2.0 */
2/* Microchip switch driver common header
3 *
4 * Copyright (C) 2017-2025 Microchip Technology Inc.
5 */
6
7#ifndef __KSZ_COMMON_H
8#define __KSZ_COMMON_H
9
10#include <linux/etherdevice.h>
11#include <linux/kernel.h>
12#include <linux/mutex.h>
13#include <linux/pcs/pcs-xpcs.h>
14#include <linux/phy.h>
15#include <linux/regmap.h>
16#include <net/dsa.h>
17#include <linux/irq.h>
18#include <linux/platform_data/microchip-ksz.h>
19
20#include "ksz_ptp.h"
21
22#define KSZ_MAX_NUM_PORTS 8
23/* all KSZ switches count ports from 1 */
24#define KSZ_PORT_1 0
25#define KSZ_PORT_2 1
26#define KSZ_PORT_4 3
27
28struct ksz_device;
29struct ksz_port;
30struct phylink_mac_ops;
31
32enum ksz_regmap_width {
33 KSZ_REGMAP_8,
34 KSZ_REGMAP_16,
35 KSZ_REGMAP_32,
36 __KSZ_NUM_REGMAPS,
37};
38
39struct vlan_table {
40 u32 table[3];
41};
42
43struct ksz_port_mib {
44 struct mutex cnt_mutex; /* structure access */
45 u8 cnt_ptr;
46 u64 *counters;
47 struct rtnl_link_stats64 stats64;
48 struct ethtool_pause_stats pause_stats;
49 struct spinlock stats64_lock;
50};
51
52struct ksz_mib_names {
53 int index;
54 char string[ETH_GSTRING_LEN];
55};
56
57struct ksz_chip_data {
58 u32 chip_id;
59 const char *dev_name;
60 int num_vlans;
61 int num_alus;
62 int num_statics;
63 int cpu_ports;
64 int port_cnt;
65 u8 port_nirqs;
66 u8 num_tx_queues;
67 u8 num_ipms; /* number of Internal Priority Maps */
68 bool tc_cbs_supported;
69
70 /**
71 * @phy_side_mdio_supported: Indicates if the chip supports an additional
72 * side MDIO channel for accessing integrated PHYs.
73 */
74 bool phy_side_mdio_supported;
75 const struct ksz_dev_ops *ops;
76 const struct phylink_mac_ops *phylink_mac_ops;
77 bool phy_errata_9477;
78 bool ksz87xx_eee_link_erratum;
79 const struct ksz_mib_names *mib_names;
80 int mib_cnt;
81 u8 reg_mib_cnt;
82 const u16 *regs;
83 const u32 *masks;
84 const u8 *shifts;
85 const u8 *xmii_ctrl0;
86 const u8 *xmii_ctrl1;
87 int stp_ctrl_reg;
88 int broadcast_ctrl_reg;
89 int multicast_ctrl_reg;
90 int start_ctrl_reg;
91 bool supports_mii[KSZ_MAX_NUM_PORTS];
92 bool supports_rmii[KSZ_MAX_NUM_PORTS];
93 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
94 bool internal_phy[KSZ_MAX_NUM_PORTS];
95 bool gbit_capable[KSZ_MAX_NUM_PORTS];
96 bool ptp_capable;
97 u8 sgmii_port;
98 const struct regmap_access_table *wr_table;
99 const struct regmap_access_table *rd_table;
100};
101
102struct ksz_irq {
103 u16 masked;
104 u16 reg_mask;
105 u16 reg_status;
106 struct irq_domain *domain;
107 int nirqs;
108 int irq_num;
109 char name[16];
110 struct ksz_device *dev;
111};
112
113struct ksz_ptp_irq {
114 struct ksz_port *port;
115 u16 ts_reg;
116 bool ts_en;
117 char name[16];
118 int num;
119};
120
121struct ksz_switch_macaddr {
122 unsigned char addr[ETH_ALEN];
123 refcount_t refcount;
124};
125
126struct ksz_port {
127 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
128 bool learning;
129 bool isolated;
130 int stp_state;
131 struct phy_device phydev;
132
133 u32 fiber:1; /* port is fiber */
134 u32 force:1;
135 u32 read:1; /* read MIB counters in background */
136 u32 freeze:1; /* MIB counter freeze is enabled */
137 u32 sgmii_adv_write:1;
138
139 struct ksz_port_mib mib;
140 phy_interface_t interface;
141 u32 rgmii_tx_val;
142 u32 rgmii_rx_val;
143 struct ksz_device *ksz_dev;
144 void *acl_priv;
145 struct ksz_irq pirq;
146 u8 num;
147 struct phylink_pcs *pcs;
148#if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
149 struct kernel_hwtstamp_config tstamp_config;
150 bool hwts_tx_en;
151 bool hwts_rx_en;
152 struct ksz_irq ptpirq;
153 struct ksz_ptp_irq ptpmsg_irq[3];
154 ktime_t tstamp_msg;
155 struct completion tstamp_msg_comp;
156#endif
157 bool manual_flow;
158};
159
160struct ksz_device {
161 struct dsa_switch *ds;
162 struct ksz_platform_data *pdata;
163 const struct ksz_chip_data *info;
164
165 struct mutex dev_mutex; /* device access */
166 struct mutex regmap_mutex; /* regmap access */
167 struct mutex alu_mutex; /* ALU access */
168 struct mutex vlan_mutex; /* vlan access */
169 const struct ksz_dev_ops *dev_ops;
170
171 struct device *dev;
172 struct regmap *regmap[__KSZ_NUM_REGMAPS];
173
174 void *priv;
175 int irq;
176
177 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
178
179 /* chip specific data */
180 u32 chip_id;
181 u8 chip_rev;
182 int cpu_port; /* port connected to CPU */
183 int phy_port_cnt;
184 phy_interface_t compat_interface;
185 bool synclko_125;
186 bool synclko_disable;
187 bool wakeup_source;
188 bool pme_active_high;
189
190 struct vlan_table *vlan_cache;
191
192 struct ksz_port *ports;
193 struct delayed_work mib_read;
194 unsigned long mib_read_interval;
195 u16 mirror_rx;
196 u16 mirror_tx;
197 u16 port_mask;
198 struct mutex lock_irq; /* IRQ Access */
199 struct ksz_irq girq;
200 struct ksz_ptp_data ptp_data;
201
202 struct ksz_switch_macaddr *switch_macaddr;
203 struct net_device *hsr_dev; /* HSR */
204 u8 hsr_ports;
205
206 /**
207 * @phy_addr_map: Array mapping switch ports to their corresponding PHY
208 * addresses.
209 */
210 u8 phy_addr_map[KSZ_MAX_NUM_PORTS];
211
212 /**
213 * @parent_mdio_bus: Pointer to the external MDIO bus controller.
214 *
215 * This points to an external MDIO bus controller that is used to access
216 * the PHYs integrated within the switch. Unlike an integrated MDIO
217 * bus, this external controller provides a direct path for managing
218 * the switch’s internal PHYs, bypassing the main SPI interface.
219 */
220 struct mii_bus *parent_mdio_bus;
221};
222
223/* List of supported models */
224enum ksz_model {
225 KSZ8563,
226 KSZ8567,
227 KSZ8795,
228 KSZ8794,
229 KSZ8765,
230 KSZ88X3,
231 KSZ8864,
232 KSZ8895,
233 KSZ9477,
234 KSZ9896,
235 KSZ9897,
236 KSZ9893,
237 KSZ9563,
238 KSZ9567,
239 LAN9370,
240 LAN9371,
241 LAN9372,
242 LAN9373,
243 LAN9374,
244 LAN9646,
245};
246
247enum ksz_regs {
248 REG_SW_MAC_ADDR,
249 REG_IND_CTRL_0,
250 REG_IND_DATA_8,
251 REG_IND_DATA_CHECK,
252 REG_IND_DATA_HI,
253 REG_IND_DATA_LO,
254 REG_IND_MIB_CHECK,
255 REG_IND_BYTE,
256 P_FORCE_CTRL,
257 P_LINK_STATUS,
258 P_LOCAL_CTRL,
259 P_NEG_RESTART_CTRL,
260 P_REMOTE_STATUS,
261 P_SPEED_STATUS,
262 S_TAIL_TAG_CTRL,
263 P_STP_CTRL,
264 S_START_CTRL,
265 S_BROADCAST_CTRL,
266 S_MULTICAST_CTRL,
267 P_XMII_CTRL_0,
268 P_XMII_CTRL_1,
269 REG_SW_PME_CTRL,
270 REG_PORT_PME_STATUS,
271 REG_PORT_PME_CTRL,
272};
273
274enum ksz_masks {
275 PORT_802_1P_REMAPPING,
276 SW_TAIL_TAG_ENABLE,
277 MIB_COUNTER_OVERFLOW,
278 MIB_COUNTER_VALID,
279 VLAN_TABLE_FID,
280 VLAN_TABLE_MEMBERSHIP,
281 VLAN_TABLE_VALID,
282 STATIC_MAC_TABLE_VALID,
283 STATIC_MAC_TABLE_USE_FID,
284 STATIC_MAC_TABLE_FID,
285 STATIC_MAC_TABLE_OVERRIDE,
286 STATIC_MAC_TABLE_FWD_PORTS,
287 DYNAMIC_MAC_TABLE_ENTRIES_H,
288 DYNAMIC_MAC_TABLE_MAC_EMPTY,
289 DYNAMIC_MAC_TABLE_NOT_READY,
290 DYNAMIC_MAC_TABLE_ENTRIES,
291 DYNAMIC_MAC_TABLE_FID,
292 DYNAMIC_MAC_TABLE_SRC_PORT,
293 DYNAMIC_MAC_TABLE_TIMESTAMP,
294 ALU_STAT_WRITE,
295 ALU_STAT_READ,
296 P_MII_TX_FLOW_CTRL,
297 P_MII_RX_FLOW_CTRL,
298};
299
300enum ksz_shifts {
301 VLAN_TABLE_MEMBERSHIP_S,
302 VLAN_TABLE,
303 STATIC_MAC_FWD_PORTS,
304 STATIC_MAC_FID,
305 DYNAMIC_MAC_ENTRIES_H,
306 DYNAMIC_MAC_ENTRIES,
307 DYNAMIC_MAC_FID,
308 DYNAMIC_MAC_TIMESTAMP,
309 DYNAMIC_MAC_SRC_PORT,
310 ALU_STAT_INDEX,
311};
312
313enum ksz_xmii_ctrl0 {
314 P_MII_100MBIT,
315 P_MII_10MBIT,
316 P_MII_FULL_DUPLEX,
317 P_MII_HALF_DUPLEX,
318};
319
320enum ksz_xmii_ctrl1 {
321 P_RGMII_SEL,
322 P_RMII_SEL,
323 P_GMII_SEL,
324 P_MII_SEL,
325 P_GMII_1GBIT,
326 P_GMII_NOT_1GBIT,
327};
328
329struct alu_struct {
330 /* entry 1 */
331 u8 is_static:1;
332 u8 is_src_filter:1;
333 u8 is_dst_filter:1;
334 u8 prio_age:3;
335 u32 _reserv_0_1:23;
336 u8 mstp:3;
337 /* entry 2 */
338 u8 is_override:1;
339 u8 is_use_fid:1;
340 u32 _reserv_1_1:23;
341 u8 port_forward:7;
342 /* entry 3 & 4*/
343 u32 _reserv_2_1:9;
344 u8 fid:7;
345 u8 mac[ETH_ALEN];
346};
347
348struct ksz_dev_ops {
349 int (*setup)(struct dsa_switch *ds);
350 void (*teardown)(struct dsa_switch *ds);
351 u32 (*get_port_addr)(int port, int offset);
352 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
353 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
354 void (*port_cleanup)(struct ksz_device *dev, int port);
355 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
356 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
357
358 /**
359 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus
360 * for accessing PHYs.
361 * @dev: Pointer to device structure.
362 * @side_mdio: Boolean indicating if the PHYs are accessed over a side
363 * MDIO bus.
364 *
365 * This function pointer is used to configure the MDIO bus for PHY
366 * access before initiating regular PHY operations. It enables either
367 * SPI/I2C or side MDIO access modes by unlocking necessary registers
368 * and setting up access permissions for the selected mode.
369 *
370 * Return:
371 * - 0 on success.
372 * - Negative error code on failure.
373 */
374 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio);
375
376 /**
377 * @create_phy_addr_map: Function pointer to create a port-to-PHY
378 * address map.
379 * @dev: Pointer to device structure.
380 * @side_mdio: Boolean indicating if the PHYs are accessed over a side
381 * MDIO bus.
382 *
383 * This function pointer is responsible for mapping switch ports to PHY
384 * addresses according to the configured access mode (SPI or side MDIO)
385 * and the device’s strap configuration. The mapping setup may vary
386 * depending on the chip variant and configuration. Ensures the correct
387 * address mapping for PHY communication.
388 *
389 * Return:
390 * - 0 on success.
391 * - Negative error code on failure (e.g., invalid configuration).
392 */
393 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio);
394 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
395 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
396 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
397 u64 *cnt);
398 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
399 u64 *dropped, u64 *cnt);
400 void (*r_mib_stat64)(struct ksz_device *dev, int port);
401 int (*vlan_filtering)(struct ksz_device *dev, int port,
402 bool flag, struct netlink_ext_ack *extack);
403 int (*vlan_add)(struct ksz_device *dev, int port,
404 const struct switchdev_obj_port_vlan *vlan,
405 struct netlink_ext_ack *extack);
406 int (*vlan_del)(struct ksz_device *dev, int port,
407 const struct switchdev_obj_port_vlan *vlan);
408 int (*mirror_add)(struct ksz_device *dev, int port,
409 struct dsa_mall_mirror_tc_entry *mirror,
410 bool ingress, struct netlink_ext_ack *extack);
411 void (*mirror_del)(struct ksz_device *dev, int port,
412 struct dsa_mall_mirror_tc_entry *mirror);
413 int (*fdb_add)(struct ksz_device *dev, int port,
414 const unsigned char *addr, u16 vid, struct dsa_db db);
415 int (*fdb_del)(struct ksz_device *dev, int port,
416 const unsigned char *addr, u16 vid, struct dsa_db db);
417 int (*fdb_dump)(struct ksz_device *dev, int port,
418 dsa_fdb_dump_cb_t *cb, void *data);
419 int (*mdb_add)(struct ksz_device *dev, int port,
420 const struct switchdev_obj_port_mdb *mdb,
421 struct dsa_db db);
422 int (*mdb_del)(struct ksz_device *dev, int port,
423 const struct switchdev_obj_port_mdb *mdb,
424 struct dsa_db db);
425 void (*get_caps)(struct ksz_device *dev, int port,
426 struct phylink_config *config);
427 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
428 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value);
429 int (*pme_pread8)(struct ksz_device *dev, int port, int offset,
430 u8 *data);
431 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset,
432 u8 data);
433 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
434 void (*port_init_cnt)(struct ksz_device *dev, int port);
435 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
436 unsigned int mode,
437 phy_interface_t interface,
438 struct phy_device *phydev, int speed,
439 int duplex, bool tx_pause, bool rx_pause);
440 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
441 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
442 void (*config_cpu_port)(struct dsa_switch *ds);
443 int (*enable_stp_addr)(struct ksz_device *dev);
444 int (*reset)(struct ksz_device *dev);
445 int (*init)(struct ksz_device *dev);
446 void (*exit)(struct ksz_device *dev);
447
448 int (*pcs_create)(struct ksz_device *dev);
449};
450
451struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
452int ksz_switch_register(struct ksz_device *dev);
453void ksz_switch_remove(struct ksz_device *dev);
454int ksz_switch_suspend(struct device *dev);
455int ksz_switch_resume(struct device *dev);
456
457void ksz_init_mib_timer(struct ksz_device *dev);
458bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port);
459void ksz_r_mib_stats64(struct ksz_device *dev, int port);
460void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
461void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
462bool ksz_get_gbit(struct ksz_device *dev, int port);
463phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
464extern const struct ksz_chip_data ksz_switch_chips[];
465int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
466 struct netlink_ext_ack *extack);
467void ksz_switch_macaddr_put(struct dsa_switch *ds);
468void ksz_switch_shutdown(struct ksz_device *dev);
469int ksz_handle_wake_reason(struct ksz_device *dev, int port);
470
471/* Common register access functions */
472static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
473{
474 return dev->regmap[KSZ_REGMAP_8];
475}
476
477static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
478{
479 return dev->regmap[KSZ_REGMAP_16];
480}
481
482static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
483{
484 return dev->regmap[KSZ_REGMAP_32];
485}
486
487static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
488{
489 unsigned int value;
490 int ret = regmap_read(map: ksz_regmap_8(dev), reg, val: &value);
491
492 if (ret)
493 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
494 ERR_PTR(ret));
495
496 *val = value;
497 return ret;
498}
499
500static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
501{
502 unsigned int value;
503 int ret = regmap_read(map: ksz_regmap_16(dev), reg, val: &value);
504
505 if (ret)
506 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
507 ERR_PTR(ret));
508
509 *val = value;
510 return ret;
511}
512
513static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
514{
515 unsigned int value;
516 int ret = regmap_read(map: ksz_regmap_32(dev), reg, val: &value);
517
518 if (ret)
519 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
520 ERR_PTR(ret));
521
522 *val = value;
523 return ret;
524}
525
526static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
527{
528 u32 value[2];
529 int ret;
530
531 ret = regmap_bulk_read(map: ksz_regmap_32(dev), reg, val: value, val_count: 2);
532 if (ret)
533 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
534 ERR_PTR(ret));
535 else
536 *val = (u64)value[0] << 32 | value[1];
537
538 return ret;
539}
540
541static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
542{
543 int ret;
544
545 ret = regmap_write(map: ksz_regmap_8(dev), reg, val: value);
546 if (ret)
547 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
548 ERR_PTR(ret));
549
550 return ret;
551}
552
553static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
554{
555 int ret;
556
557 ret = regmap_write(map: ksz_regmap_16(dev), reg, val: value);
558 if (ret)
559 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
560 ERR_PTR(ret));
561
562 return ret;
563}
564
565static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
566{
567 int ret;
568
569 ret = regmap_write(map: ksz_regmap_32(dev), reg, val: value);
570 if (ret)
571 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
572 ERR_PTR(ret));
573
574 return ret;
575}
576
577static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
578 u16 value)
579{
580 int ret;
581
582 ret = regmap_update_bits(map: ksz_regmap_16(dev), reg, mask, val: value);
583 if (ret)
584 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
585 ERR_PTR(ret));
586
587 return ret;
588}
589
590static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
591 u32 value)
592{
593 int ret;
594
595 ret = regmap_update_bits(map: ksz_regmap_32(dev), reg, mask, val: value);
596 if (ret)
597 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
598 ERR_PTR(ret));
599
600 return ret;
601}
602
603static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
604{
605 u32 val[2];
606
607 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
608 value = swab64(value);
609 val[0] = swab32(value & 0xffffffffULL);
610 val[1] = swab32(value >> 32ULL);
611
612 return regmap_bulk_write(map: ksz_regmap_32(dev), reg, val, val_count: 2);
613}
614
615static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
616{
617 int ret;
618
619 ret = regmap_update_bits(map: ksz_regmap_8(dev), reg: offset, mask, val);
620 if (ret)
621 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
622 ERR_PTR(ret));
623
624 return ret;
625}
626
627static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
628 u8 *data)
629{
630 return ksz_read8(dev, reg: dev->dev_ops->get_port_addr(port, offset), val: data);
631}
632
633static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
634 u16 *data)
635{
636 return ksz_read16(dev, reg: dev->dev_ops->get_port_addr(port, offset), val: data);
637}
638
639static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
640 u32 *data)
641{
642 return ksz_read32(dev, reg: dev->dev_ops->get_port_addr(port, offset), val: data);
643}
644
645static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
646 u8 data)
647{
648 return ksz_write8(dev, reg: dev->dev_ops->get_port_addr(port, offset), value: data);
649}
650
651static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
652 u16 data)
653{
654 return ksz_write16(dev, reg: dev->dev_ops->get_port_addr(port, offset),
655 value: data);
656}
657
658static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
659 u32 data)
660{
661 return ksz_write32(dev, reg: dev->dev_ops->get_port_addr(port, offset),
662 value: data);
663}
664
665static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
666 u8 mask, u8 val)
667{
668 return ksz_rmw8(dev, offset: dev->dev_ops->get_port_addr(port, offset),
669 mask, val);
670}
671
672static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
673 u32 mask, u32 val)
674{
675 return ksz_rmw32(dev, reg: dev->dev_ops->get_port_addr(port, offset),
676 mask, value: val);
677}
678
679static inline void ksz_regmap_lock(void *__mtx)
680{
681 struct mutex *mtx = __mtx;
682 mutex_lock(mtx);
683}
684
685static inline void ksz_regmap_unlock(void *__mtx)
686{
687 struct mutex *mtx = __mtx;
688 mutex_unlock(lock: mtx);
689}
690
691static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
692{
693 return dev->chip_id == KSZ8795_CHIP_ID ||
694 dev->chip_id == KSZ8794_CHIP_ID ||
695 dev->chip_id == KSZ8765_CHIP_ID;
696}
697
698static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
699{
700 return dev->chip_id == KSZ88X3_CHIP_ID;
701}
702
703static inline bool ksz_is_8895_family(struct ksz_device *dev)
704{
705 return dev->chip_id == KSZ8895_CHIP_ID ||
706 dev->chip_id == KSZ8864_CHIP_ID;
707}
708
709static inline bool is_ksz8(struct ksz_device *dev)
710{
711 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) ||
712 ksz_is_8895_family(dev);
713}
714
715static inline bool is_ksz88xx(struct ksz_device *dev)
716{
717 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev);
718}
719
720static inline bool is_ksz9477(struct ksz_device *dev)
721{
722 return dev->chip_id == KSZ9477_CHIP_ID;
723}
724
725static inline int is_lan937x(struct ksz_device *dev)
726{
727 return dev->chip_id == LAN9370_CHIP_ID ||
728 dev->chip_id == LAN9371_CHIP_ID ||
729 dev->chip_id == LAN9372_CHIP_ID ||
730 dev->chip_id == LAN9373_CHIP_ID ||
731 dev->chip_id == LAN9374_CHIP_ID;
732}
733
734static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port)
735{
736 return (dev->chip_id == LAN9371_CHIP_ID ||
737 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4;
738}
739
740static inline int ksz_get_sgmii_port(struct ksz_device *dev)
741{
742 return dev->info->sgmii_port - 1;
743}
744
745static inline bool ksz_has_sgmii_port(struct ksz_device *dev)
746{
747 return dev->info->sgmii_port > 0;
748}
749
750static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port)
751{
752 return dev->info->sgmii_port == port + 1;
753}
754
755/* STP State Defines */
756#define PORT_TX_ENABLE BIT(2)
757#define PORT_RX_ENABLE BIT(1)
758#define PORT_LEARN_DISABLE BIT(0)
759
760/* Switch ID Defines */
761#define REG_CHIP_ID0 0x00
762
763#define SW_FAMILY_ID_M GENMASK(15, 8)
764#define KSZ87_FAMILY_ID 0x87
765#define KSZ88_FAMILY_ID 0x88
766#define KSZ8895_FAMILY_ID 0x95
767
768#define KSZ8_PORT_STATUS_0 0x08
769#define KSZ8_PORT_FIBER_MODE BIT(7)
770
771#define SW_CHIP_ID_M GENMASK(7, 4)
772#define KSZ87_CHIP_ID_94 0x6
773#define KSZ87_CHIP_ID_95 0x9
774#define KSZ88_CHIP_ID_63 0x3
775#define KSZ8895_CHIP_ID_95 0x4
776#define KSZ8895_CHIP_ID_95R 0x6
777
778/* KSZ8895 specific register */
779#define REG_KSZ8864_CHIP_ID 0xFE
780#define SW_KSZ8864 BIT(7)
781
782#define SW_REV_ID_M GENMASK(7, 4)
783
784/* KSZ9893, KSZ9563, KSZ8563 specific register */
785#define REG_CHIP_ID4 0x0f
786#define SKU_ID_KSZ8563 0x3c
787#define SKU_ID_KSZ9563 0x1c
788
789/* Driver set switch broadcast storm protection at 10% rate. */
790#define BROADCAST_STORM_PROT_RATE 10
791
792/* 148,800 frames * 67 ms / 100 */
793#define BROADCAST_STORM_VALUE 9969
794
795#define BROADCAST_STORM_RATE_HI 0x07
796#define BROADCAST_STORM_RATE_LO 0xFF
797#define BROADCAST_STORM_RATE 0x07FF
798
799#define MULTICAST_STORM_DISABLE BIT(6)
800
801#define SW_START 0x01
802
803/* xMII configuration */
804#define P_MII_DUPLEX_M BIT(6)
805#define P_MII_100MBIT_M BIT(4)
806
807#define P_GMII_1GBIT_M BIT(6)
808#define P_RGMII_ID_IG_ENABLE BIT(4)
809#define P_RGMII_ID_EG_ENABLE BIT(3)
810#define P_MII_MAC_MODE BIT(2)
811#define P_MII_SEL_M 0x3
812
813/* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */
814#define PME_WOL_MAGICPKT BIT(2)
815#define PME_WOL_LINKUP BIT(1)
816#define PME_WOL_ENERGY BIT(0)
817
818#define PME_ENABLE BIT(1)
819#define PME_POLARITY BIT(0)
820
821#define KSZ87XX_REG_INT_EN 0x7D
822#define KSZ87XX_INT_PME_MASK BIT(4)
823
824/* Interrupt */
825#define REG_SW_PORT_INT_STATUS__1 0x001B
826#define REG_SW_PORT_INT_MASK__1 0x001F
827
828#define REG_PORT_INT_STATUS 0x001B
829#define REG_PORT_INT_MASK 0x001F
830
831#define PORT_SRC_PHY_INT 1
832#define PORT_SRC_PTP_INT 2
833
834#define KSZ8795_HUGE_PACKET_SIZE 2000
835#define KSZ8863_HUGE_PACKET_SIZE 1916
836#define KSZ8863_NORMAL_PACKET_SIZE 1536
837#define KSZ8_LEGAL_PACKET_SIZE 1518
838#define KSZ9477_MAX_FRAME_SIZE 9000
839
840#define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
841/* Drive Strength of I/O Pad
842 * 0: 8mA, 1: 16mA
843 */
844#define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
845
846#define KSZ8795_REG_SW_CTRL_20 0xa3
847#define KSZ9477_REG_SW_IO_STRENGTH 0x010d
848#define SW_DRIVE_STRENGTH_M 0x7
849#define SW_DRIVE_STRENGTH_2MA 0
850#define SW_DRIVE_STRENGTH_4MA 1
851#define SW_DRIVE_STRENGTH_8MA 2
852#define SW_DRIVE_STRENGTH_12MA 3
853#define SW_DRIVE_STRENGTH_16MA 4
854#define SW_DRIVE_STRENGTH_20MA 5
855#define SW_DRIVE_STRENGTH_24MA 6
856#define SW_DRIVE_STRENGTH_28MA 7
857#define SW_HI_SPEED_DRIVE_STRENGTH_S 4
858#define SW_LO_SPEED_DRIVE_STRENGTH_S 0
859
860/* TXQ Split Control Register for per-port, per-queue configuration.
861 * Register 0xAF is TXQ Split for Q3 on Port 1.
862 * Register offset formula: 0xAF + (port * 4) + (3 - queue)
863 * where: port = 0..2, queue = 0..3
864 */
865#define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \
866 (0xAF + ((port) * 4) + (3 - (queue)))
867
868/* Bit 7 selects between:
869 * 0 = Strict priority mode (highest-priority queue first)
870 * 1 = Weighted Fair Queuing (WFQ) mode:
871 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1
872 * If any queues are empty, weight is redistributed.
873 *
874 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873
875 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs.
876 */
877#define KSZ8873_TXQ_WFQ_ENABLE BIT(7)
878
879#define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
880#define KSZ9477_OUT_RATE_NO_LIMIT 0
881
882#define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
883
884#define KSZ9477_PORT_TC_MAP_S 4
885
886/* CBS related registers */
887#define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
888
889#define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
890
891#define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
892#define MTI_SCHEDULE_STRICT_PRIO 0
893#define MTI_SCHEDULE_WRR 2
894#define MTI_SHAPING_M GENMASK(5, 4)
895#define MTI_SHAPING_OFF 0
896#define MTI_SHAPING_SRP 1
897#define MTI_SHAPING_TIME_AWARE 2
898
899#define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
900#define KSZ9477_DEFAULT_WRR_WEIGHT 1
901
902#define REG_PORT_MTI_HI_WATER_MARK 0x0916
903#define REG_PORT_MTI_LO_WATER_MARK 0x0918
904
905/* Regmap tables generation */
906#define KSZ_SPI_OP_RD 3
907#define KSZ_SPI_OP_WR 2
908
909#define swabnot_used(x) 0
910
911#define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
912 swab##swp((opcode) << ((regbits) + (regpad)))
913
914#define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
915 { \
916 .name = #width, \
917 .val_bits = (width), \
918 .reg_stride = 1, \
919 .reg_bits = (regbits) + (regalign), \
920 .pad_bits = (regpad), \
921 .max_register = BIT(regbits) - 1, \
922 .cache_type = REGCACHE_NONE, \
923 .read_flag_mask = \
924 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
925 regbits, regpad), \
926 .write_flag_mask = \
927 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
928 regbits, regpad), \
929 .lock = ksz_regmap_lock, \
930 .unlock = ksz_regmap_unlock, \
931 .reg_format_endian = REGMAP_ENDIAN_BIG, \
932 .val_format_endian = REGMAP_ENDIAN_BIG \
933 }
934
935#define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
936 static const struct regmap_config ksz##_regmap_config[] = { \
937 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
938 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
939 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
940 }
941
942#endif
943

source code of linux/drivers/net/dsa/microchip/ksz_common.h