1	// SPDX-License-Identifier: GPL-2.0
2	/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4	/* 82562G 10/100 Network Connection
5	* 82562G-2 10/100 Network Connection
6	* 82562GT 10/100 Network Connection
7	* 82562GT-2 10/100 Network Connection
8	* 82562V 10/100 Network Connection
9	* 82562V-2 10/100 Network Connection
10	* 82566DC-2 Gigabit Network Connection
11	* 82566DC Gigabit Network Connection
12	* 82566DM-2 Gigabit Network Connection
13	* 82566DM Gigabit Network Connection
14	* 82566MC Gigabit Network Connection
15	* 82566MM Gigabit Network Connection
16	* 82567LM Gigabit Network Connection
17	* 82567LF Gigabit Network Connection
18	* 82567V Gigabit Network Connection
19	* 82567LM-2 Gigabit Network Connection
20	* 82567LF-2 Gigabit Network Connection
21	* 82567V-2 Gigabit Network Connection
22	* 82567LF-3 Gigabit Network Connection
23	* 82567LM-3 Gigabit Network Connection
24	* 82567LM-4 Gigabit Network Connection
25	* 82577LM Gigabit Network Connection
26	* 82577LC Gigabit Network Connection
27	* 82578DM Gigabit Network Connection
28	* 82578DC Gigabit Network Connection
29	* 82579LM Gigabit Network Connection
30	* 82579V Gigabit Network Connection
31	* Ethernet Connection I217-LM
32	* Ethernet Connection I217-V
33	* Ethernet Connection I218-V
34	* Ethernet Connection I218-LM
35	* Ethernet Connection (2) I218-LM
36	* Ethernet Connection (2) I218-V
37	* Ethernet Connection (3) I218-LM
38	* Ethernet Connection (3) I218-V
39	*/
40
41	#include "e1000.h"
42
43	/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44	/* Offset 04h HSFSTS */
45	union ich8_hws_flash_status {
46	struct ich8_hsfsts {
47	u16 flcdone:1; /* bit 0 Flash Cycle Done */
48	u16 flcerr:1; /* bit 1 Flash Cycle Error */
49	u16 dael:1; /* bit 2 Direct Access error Log */
50	u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51	u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52	u16 reserved1:2; /* bit 13:6 Reserved */
53	u16 reserved2:6; /* bit 13:6 Reserved */
54	u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55	u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56	} hsf_status;
57	u16 regval;
58	};
59
60	/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61	/* Offset 06h FLCTL */
62	union ich8_hws_flash_ctrl {
63	struct ich8_hsflctl {
64	u16 flcgo:1; /* 0 Flash Cycle Go */
65	u16 flcycle:2; /* 2:1 Flash Cycle */
66	u16 reserved:5; /* 7:3 Reserved */
67	u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68	u16 flockdn:6; /* 15:10 Reserved */
69	} hsf_ctrl;
70	u16 regval;
71	};
72
73	/* ICH Flash Region Access Permissions */
74	union ich8_hws_flash_regacc {
75	struct ich8_flracc {
76	u32 grra:8; /* 0:7 GbE region Read Access */
77	u32 grwa:8; /* 8:15 GbE region Write Access */
78	u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79	u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80	} hsf_flregacc;
81	u16 regval;
82	};
83
84	/* ICH Flash Protected Region */
85	union ich8_flash_protected_range {
86	struct ich8_pr {
87	u32 base:13; /* 0:12 Protected Range Base */
88	u32 reserved1:2; /* 13:14 Reserved */
89	u32 rpe:1; /* 15 Read Protection Enable */
90	u32 limit:13; /* 16:28 Protected Range Limit */
91	u32 reserved2:2; /* 29:30 Reserved */
92	u32 wpe:1; /* 31 Write Protection Enable */
93	} range;
94	u32 regval;
95	};
96
97	static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98	static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99	static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100	static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101	u32 offset, u8 byte);
102	static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103	u8 *data);
104	static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105	u16 *data);
106	static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107	u8 size, u16 *data);
108	static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109	u32 *data);
110	static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111	u32 offset, u32 *data);
112	static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113	u32 offset, u32 data);
114	static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115	u32 offset, u32 dword);
116	static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117	static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118	static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119	static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120	static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121	static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122	static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123	static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124	static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125	static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126	static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127	static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128	static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129	static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130	static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131	static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132	static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133	static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134	static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135	static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136	static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137	static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138	static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139	static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
141	static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142	{
143	return readw(addr: hw->flash_address + reg);
144	}
145
146	static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147	{
148	return readl(addr: hw->flash_address + reg);
149	}
150
151	static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152	{
153	writew(val, addr: hw->flash_address + reg);
154	}
155
156	static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157	{
158	writel(val, addr: hw->flash_address + reg);
159	}
160
161	#define er16flash(reg) __er16flash(hw, (reg))
162	#define er32flash(reg) __er32flash(hw, (reg))
163	#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164	#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166	/**
167	* e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168	* @hw: pointer to the HW structure
169	*
170	* Test access to the PHY registers by reading the PHY ID registers. If
171	* the PHY ID is already known (e.g. resume path) compare it with known ID,
172	* otherwise assume the read PHY ID is correct if it is valid.
173	*
174	* Assumes the sw/fw/hw semaphore is already acquired.
175	**/
176	static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177	{
178	u16 phy_reg = 0;
179	u32 phy_id = 0;
180	s32 ret_val = 0;
181	u16 retry_count;
182	u32 mac_reg = 0;
183
184	for (retry_count = 0; retry_count < 2; retry_count++) {
185	ret_val = e1e_rphy_locked(hw, MII_PHYSID1, data: &phy_reg);
186	if (ret_val || (phy_reg == 0xFFFF))
187	continue;
188	phy_id = (u32)(phy_reg << 16);
189
190	ret_val = e1e_rphy_locked(hw, MII_PHYSID2, data: &phy_reg);
191	if (ret_val || (phy_reg == 0xFFFF)) {
192	phy_id = 0;
193	continue;
194	}
195	phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196	break;
197	}
198
199	if (hw->phy.id) {
200	if (hw->phy.id == phy_id)
201	goto out;
202	} else if (phy_id) {
203	hw->phy.id = phy_id;
204	hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205	goto out;
206	}
207
208	/* In case the PHY needs to be in mdio slow mode,
209	* set slow mode and try to get the PHY id again.
210	*/
211	if (hw->mac.type < e1000_pch_lpt) {
212	hw->phy.ops.release(hw);
213	ret_val = e1000_set_mdio_slow_mode_hv(hw);
214	if (!ret_val)
215	ret_val = e1000e_get_phy_id(hw);
216	hw->phy.ops.acquire(hw);
217	}
218
219	if (ret_val)
220	return false;
221	out:
222	if (hw->mac.type >= e1000_pch_lpt) {
223	/* Only unforce SMBus if ME is not active */
224	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225	/* Unforce SMBus mode in PHY */
226	e1e_rphy_locked(hw, CV_SMB_CTRL, data: &phy_reg);
227	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228	e1e_wphy_locked(hw, CV_SMB_CTRL, data: phy_reg);
229
230	/* Unforce SMBus mode in MAC */
231	mac_reg = er32(CTRL_EXT);
232	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233	ew32(CTRL_EXT, mac_reg);
234	}
235	}
236
237	return true;
238	}
239
240	/**
241	* e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242	* @hw: pointer to the HW structure
243	*
244	* Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245	* used to reset the PHY to a quiescent state when necessary.
246	**/
247	static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248	{
249	u32 mac_reg;
250
251	/* Set Phy Config Counter to 50msec */
252	mac_reg = er32(FEXTNVM3);
253	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255	ew32(FEXTNVM3, mac_reg);
256
257	/* Toggle LANPHYPC Value bit */
258	mac_reg = er32(CTRL);
259	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261	ew32(CTRL, mac_reg);
262	e1e_flush();
263	usleep_range(min: 10, max: 20);
264	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265	ew32(CTRL, mac_reg);
266	e1e_flush();
267
268	if (hw->mac.type < e1000_pch_lpt) {
269	msleep(msecs: 50);
270	} else {
271	u16 count = 20;
272
273	do {
274	usleep_range(min: 5000, max: 6000);
275	} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277	msleep(msecs: 30);
278	}
279	}
280
281	/**
282	* e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283	* @hw: pointer to the HW structure
284	*
285	* Workarounds/flow necessary for PHY initialization during driver load
286	* and resume paths.
287	**/
288	static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289	{
290	struct e1000_adapter *adapter = hw->adapter;
291	u32 mac_reg, fwsm = er32(FWSM);
292	s32 ret_val;
293
294	/* Gate automatic PHY configuration by hardware on managed and
295	* non-managed 82579 and newer adapters.
296	*/
297	e1000_gate_hw_phy_config_ich8lan(hw, gate: true);
298
299	/* It is not possible to be certain of the current state of ULP
300	* so forcibly disable it.
301	*/
302	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303	ret_val = e1000_disable_ulp_lpt_lp(hw, force: true);
304	if (ret_val)
305	e_warn("Failed to disable ULP\n");
306
307	ret_val = hw->phy.ops.acquire(hw);
308	if (ret_val) {
309	e_dbg("Failed to initialize PHY flow\n");
310	goto out;
311	}
312
313	/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314	* inaccessible and resetting the PHY is not blocked, toggle the
315	* LANPHYPC Value bit to force the interconnect to PCIe mode.
316	*/
317	switch (hw->mac.type) {
318	case e1000_pch_lpt:
319	case e1000_pch_spt:
320	case e1000_pch_cnp:
321	case e1000_pch_tgp:
322	case e1000_pch_adp:
323	case e1000_pch_mtp:
324	case e1000_pch_lnp:
325	case e1000_pch_ptp:
326	case e1000_pch_nvp:
327	if (e1000_phy_is_accessible_pchlan(hw))
328	break;
329
330	/* Before toggling LANPHYPC, see if PHY is accessible by
331	* forcing MAC to SMBus mode first.
332	*/
333	mac_reg = er32(CTRL_EXT);
334	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
335	ew32(CTRL_EXT, mac_reg);
336
337	/* Wait 50 milliseconds for MAC to finish any retries
338	* that it might be trying to perform from previous
339	* attempts to acknowledge any phy read requests.
340	*/
341	msleep(msecs: 50);
342
343	fallthrough;
344	case e1000_pch2lan:
345	if (e1000_phy_is_accessible_pchlan(hw))
346	break;
347
348	fallthrough;
349	case e1000_pchlan:
350	if ((hw->mac.type == e1000_pchlan) &&
351	(fwsm & E1000_ICH_FWSM_FW_VALID))
352	break;
353
354	if (hw->phy.ops.check_reset_block(hw)) {
355	e_dbg("Required LANPHYPC toggle blocked by ME\n");
356	ret_val = -E1000_ERR_PHY;
357	break;
358	}
359
360	/* Toggle LANPHYPC Value bit */
361	e1000_toggle_lanphypc_pch_lpt(hw);
362	if (hw->mac.type >= e1000_pch_lpt) {
363	if (e1000_phy_is_accessible_pchlan(hw))
364	break;
365
366	/* Toggling LANPHYPC brings the PHY out of SMBus mode
367	* so ensure that the MAC is also out of SMBus mode
368	*/
369	mac_reg = er32(CTRL_EXT);
370	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
371	ew32(CTRL_EXT, mac_reg);
372
373	if (e1000_phy_is_accessible_pchlan(hw))
374	break;
375
376	ret_val = -E1000_ERR_PHY;
377	}
378	break;
379	default:
380	break;
381	}
382
383	hw->phy.ops.release(hw);
384	if (!ret_val) {
385
386	/* Check to see if able to reset PHY. Print error if not */
387	if (hw->phy.ops.check_reset_block(hw)) {
388	e_err("Reset blocked by ME\n");
389	goto out;
390	}
391
392	/* Reset the PHY before any access to it. Doing so, ensures
393	* that the PHY is in a known good state before we read/write
394	* PHY registers. The generic reset is sufficient here,
395	* because we haven't determined the PHY type yet.
396	*/
397	ret_val = e1000e_phy_hw_reset_generic(hw);
398	if (ret_val)
399	goto out;
400
401	/* On a successful reset, possibly need to wait for the PHY
402	* to quiesce to an accessible state before returning control
403	* to the calling function. If the PHY does not quiesce, then
404	* return E1000E_BLK_PHY_RESET, as this is the condition that
405	* the PHY is in.
406	*/
407	ret_val = hw->phy.ops.check_reset_block(hw);
408	if (ret_val)
409	e_err("ME blocked access to PHY after reset\n");
410	}
411
412	out:
413	/* Ungate automatic PHY configuration on non-managed 82579 */
414	if ((hw->mac.type == e1000_pch2lan) &&
415	!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
416	usleep_range(min: 10000, max: 11000);
417	e1000_gate_hw_phy_config_ich8lan(hw, gate: false);
418	}
419
420	return ret_val;
421	}
422
423	/**
424	* e1000_init_phy_params_pchlan - Initialize PHY function pointers
425	* @hw: pointer to the HW structure
426	*
427	* Initialize family-specific PHY parameters and function pointers.
428	**/
429	static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
430	{
431	struct e1000_phy_info *phy = &hw->phy;
432	s32 ret_val;
433
434	phy->addr = 1;
435	phy->reset_delay_us = 100;
436
437	phy->ops.set_page = e1000_set_page_igp;
438	phy->ops.read_reg = e1000_read_phy_reg_hv;
439	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
440	phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
441	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
442	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
443	phy->ops.write_reg = e1000_write_phy_reg_hv;
444	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
445	phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
446	phy->ops.power_up = e1000_power_up_phy_copper;
447	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
448	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
449
450	phy->id = e1000_phy_unknown;
451
452	ret_val = e1000_init_phy_workarounds_pchlan(hw);
453	if (ret_val)
454	return ret_val;
455
456	if (phy->id == e1000_phy_unknown)
457	switch (hw->mac.type) {
458	default:
459	ret_val = e1000e_get_phy_id(hw);
460	if (ret_val)
461	return ret_val;
462	if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
463	break;
464	fallthrough;
465	case e1000_pch2lan:
466	case e1000_pch_lpt:
467	case e1000_pch_spt:
468	case e1000_pch_cnp:
469	case e1000_pch_tgp:
470	case e1000_pch_adp:
471	case e1000_pch_mtp:
472	case e1000_pch_lnp:
473	case e1000_pch_ptp:
474	case e1000_pch_nvp:
475	/* In case the PHY needs to be in mdio slow mode,
476	* set slow mode and try to get the PHY id again.
477	*/
478	ret_val = e1000_set_mdio_slow_mode_hv(hw);
479	if (ret_val)
480	return ret_val;
481	ret_val = e1000e_get_phy_id(hw);
482	if (ret_val)
483	return ret_val;
484	break;
485	}
486	phy->type = e1000e_get_phy_type_from_id(phy_id: phy->id);
487
488	switch (phy->type) {
489	case e1000_phy_82577:
490	case e1000_phy_82579:
491	case e1000_phy_i217:
492	phy->ops.check_polarity = e1000_check_polarity_82577;
493	phy->ops.force_speed_duplex =
494	e1000_phy_force_speed_duplex_82577;
495	phy->ops.get_cable_length = e1000_get_cable_length_82577;
496	phy->ops.get_info = e1000_get_phy_info_82577;
497	phy->ops.commit = e1000e_phy_sw_reset;
498	break;
499	case e1000_phy_82578:
500	phy->ops.check_polarity = e1000_check_polarity_m88;
501	phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
502	phy->ops.get_cable_length = e1000e_get_cable_length_m88;
503	phy->ops.get_info = e1000e_get_phy_info_m88;
504	break;
505	default:
506	ret_val = -E1000_ERR_PHY;
507	break;
508	}
509
510	return ret_val;
511	}
512
513	/**
514	* e1000_init_phy_params_ich8lan - Initialize PHY function pointers
515	* @hw: pointer to the HW structure
516	*
517	* Initialize family-specific PHY parameters and function pointers.
518	**/
519	static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
520	{
521	struct e1000_phy_info *phy = &hw->phy;
522	s32 ret_val;
523	u16 i = 0;
524
525	phy->addr = 1;
526	phy->reset_delay_us = 100;
527
528	phy->ops.power_up = e1000_power_up_phy_copper;
529	phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
530
531	/* We may need to do this twice - once for IGP and if that fails,
532	* we'll set BM func pointers and try again
533	*/
534	ret_val = e1000e_determine_phy_address(hw);
535	if (ret_val) {
536	phy->ops.write_reg = e1000e_write_phy_reg_bm;
537	phy->ops.read_reg = e1000e_read_phy_reg_bm;
538	ret_val = e1000e_determine_phy_address(hw);
539	if (ret_val) {
540	e_dbg("Cannot determine PHY addr. Erroring out\n");
541	return ret_val;
542	}
543	}
544
545	phy->id = 0;
546	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy_id: phy->id)) &&
547	(i++ < 100)) {
548	usleep_range(min: 1000, max: 1100);
549	ret_val = e1000e_get_phy_id(hw);
550	if (ret_val)
551	return ret_val;
552	}
553
554	/* Verify phy id */
555	switch (phy->id) {
556	case IGP03E1000_E_PHY_ID:
557	phy->type = e1000_phy_igp_3;
558	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
559	phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
560	phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
561	phy->ops.get_info = e1000e_get_phy_info_igp;
562	phy->ops.check_polarity = e1000_check_polarity_igp;
563	phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
564	break;
565	case IFE_E_PHY_ID:
566	case IFE_PLUS_E_PHY_ID:
567	case IFE_C_E_PHY_ID:
568	phy->type = e1000_phy_ife;
569	phy->autoneg_mask = E1000_ALL_NOT_GIG;
570	phy->ops.get_info = e1000_get_phy_info_ife;
571	phy->ops.check_polarity = e1000_check_polarity_ife;
572	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
573	break;
574	case BME1000_E_PHY_ID:
575	phy->type = e1000_phy_bm;
576	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
577	phy->ops.read_reg = e1000e_read_phy_reg_bm;
578	phy->ops.write_reg = e1000e_write_phy_reg_bm;
579	phy->ops.commit = e1000e_phy_sw_reset;
580	phy->ops.get_info = e1000e_get_phy_info_m88;
581	phy->ops.check_polarity = e1000_check_polarity_m88;
582	phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
583	break;
584	default:
585	return -E1000_ERR_PHY;
586	}
587
588	return 0;
589	}
590
591	/**
592	* e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
593	* @hw: pointer to the HW structure
594	*
595	* Initialize family-specific NVM parameters and function
596	* pointers.
597	**/
598	static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
599	{
600	struct e1000_nvm_info *nvm = &hw->nvm;
601	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
602	u32 gfpreg, sector_base_addr, sector_end_addr;
603	u16 i;
604	u32 nvm_size;
605
606	nvm->type = e1000_nvm_flash_sw;
607
608	if (hw->mac.type >= e1000_pch_spt) {
609	/* in SPT, gfpreg doesn't exist. NVM size is taken from the
610	* STRAP register. This is because in SPT the GbE Flash region
611	* is no longer accessed through the flash registers. Instead,
612	* the mechanism has changed, and the Flash region access
613	* registers are now implemented in GbE memory space.
614	*/
615	nvm->flash_base_addr = 0;
616	nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
617	* NVM_SIZE_MULTIPLIER;
618	nvm->flash_bank_size = nvm_size / 2;
619	/* Adjust to word count */
620	nvm->flash_bank_size /= sizeof(u16);
621	/* Set the base address for flash register access */
622	hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
623	} else {
624	/* Can't read flash registers if register set isn't mapped. */
625	if (!hw->flash_address) {
626	e_dbg("ERROR: Flash registers not mapped\n");
627	return -E1000_ERR_CONFIG;
628	}
629
630	gfpreg = er32flash(ICH_FLASH_GFPREG);
631
632	/* sector_X_addr is a "sector"-aligned address (4096 bytes)
633	* Add 1 to sector_end_addr since this sector is included in
634	* the overall size.
635	*/
636	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
638
639	/* flash_base_addr is byte-aligned */
640	nvm->flash_base_addr = sector_base_addr
641	<< FLASH_SECTOR_ADDR_SHIFT;
642
643	/* find total size of the NVM, then cut in half since the total
644	* size represents two separate NVM banks.
645	*/
646	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
647	<< FLASH_SECTOR_ADDR_SHIFT);
648	nvm->flash_bank_size /= 2;
649	/* Adjust to word count */
650	nvm->flash_bank_size /= sizeof(u16);
651	}
652
653	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
654
655	/* Clear shadow ram */
656	for (i = 0; i < nvm->word_size; i++) {
657	dev_spec->shadow_ram[i].modified = false;
658	dev_spec->shadow_ram[i].value = 0xFFFF;
659	}
660
661	return 0;
662	}
663
664	/**
665	* e1000_init_mac_params_ich8lan - Initialize MAC function pointers
666	* @hw: pointer to the HW structure
667	*
668	* Initialize family-specific MAC parameters and function
669	* pointers.
670	**/
671	static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
672	{
673	struct e1000_mac_info *mac = &hw->mac;
674
675	/* Set media type function pointer */
676	hw->phy.media_type = e1000_media_type_copper;
677
678	/* Set mta register count */
679	mac->mta_reg_count = 32;
680	/* Set rar entry count */
681	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
682	if (mac->type == e1000_ich8lan)
683	mac->rar_entry_count--;
684	/* FWSM register */
685	mac->has_fwsm = true;
686	/* ARC subsystem not supported */
687	mac->arc_subsystem_valid = false;
688	/* Adaptive IFS supported */
689	mac->adaptive_ifs = true;
690
691	/* LED and other operations */
692	switch (mac->type) {
693	case e1000_ich8lan:
694	case e1000_ich9lan:
695	case e1000_ich10lan:
696	/* check management mode */
697	mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
698	/* ID LED init */
699	mac->ops.id_led_init = e1000e_id_led_init_generic;
700	/* blink LED */
701	mac->ops.blink_led = e1000e_blink_led_generic;
702	/* setup LED */
703	mac->ops.setup_led = e1000e_setup_led_generic;
704	/* cleanup LED */
705	mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
706	/* turn on/off LED */
707	mac->ops.led_on = e1000_led_on_ich8lan;
708	mac->ops.led_off = e1000_led_off_ich8lan;
709	break;
710	case e1000_pch2lan:
711	mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
712	mac->ops.rar_set = e1000_rar_set_pch2lan;
713	fallthrough;
714	case e1000_pch_lpt:
715	case e1000_pch_spt:
716	case e1000_pch_cnp:
717	case e1000_pch_tgp:
718	case e1000_pch_adp:
719	case e1000_pch_mtp:
720	case e1000_pch_lnp:
721	case e1000_pch_ptp:
722	case e1000_pch_nvp:
723	case e1000_pchlan:
724	/* check management mode */
725	mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
726	/* ID LED init */
727	mac->ops.id_led_init = e1000_id_led_init_pchlan;
728	/* setup LED */
729	mac->ops.setup_led = e1000_setup_led_pchlan;
730	/* cleanup LED */
731	mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
732	/* turn on/off LED */
733	mac->ops.led_on = e1000_led_on_pchlan;
734	mac->ops.led_off = e1000_led_off_pchlan;
735	break;
736	default:
737	break;
738	}
739
740	if (mac->type >= e1000_pch_lpt) {
741	mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
742	mac->ops.rar_set = e1000_rar_set_pch_lpt;
743	mac->ops.setup_physical_interface =
744	e1000_setup_copper_link_pch_lpt;
745	mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
746	}
747
748	/* Enable PCS Lock-loss workaround for ICH8 */
749	if (mac->type == e1000_ich8lan)
750	e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, state: true);
751
752	return 0;
753	}
754
755	/**
756	* __e1000_access_emi_reg_locked - Read/write EMI register
757	* @hw: pointer to the HW structure
758	* @address: EMI address to program
759	* @data: pointer to value to read/write from/to the EMI address
760	* @read: boolean flag to indicate read or write
761	*
762	* This helper function assumes the SW/FW/HW Semaphore is already acquired.
763	**/
764	static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
765	u16 *data, bool read)
766	{
767	s32 ret_val;
768
769	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, data: address);
770	if (ret_val)
771	return ret_val;
772
773	if (read)
774	ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
775	else
776	ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, data: *data);
777
778	return ret_val;
779	}
780
781	/**
782	* e1000_read_emi_reg_locked - Read Extended Management Interface register
783	* @hw: pointer to the HW structure
784	* @addr: EMI address to program
785	* @data: value to be read from the EMI address
786	*
787	* Assumes the SW/FW/HW Semaphore is already acquired.
788	**/
789	s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
790	{
791	return __e1000_access_emi_reg_locked(hw, address: addr, data, read: true);
792	}
793
794	/**
795	* e1000_write_emi_reg_locked - Write Extended Management Interface register
796	* @hw: pointer to the HW structure
797	* @addr: EMI address to program
798	* @data: value to be written to the EMI address
799	*
800	* Assumes the SW/FW/HW Semaphore is already acquired.
801	**/
802	s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
803	{
804	return __e1000_access_emi_reg_locked(hw, address: addr, data: &data, read: false);
805	}
806
807	/**
808	* e1000_set_eee_pchlan - Enable/disable EEE support
809	* @hw: pointer to the HW structure
810	*
811	* Enable/disable EEE based on setting in dev_spec structure, the duplex of
812	* the link and the EEE capabilities of the link partner. The LPI Control
813	* register bits will remain set only if/when link is up.
814	*
815	* EEE LPI must not be asserted earlier than one second after link is up.
816	* On 82579, EEE LPI should not be enabled until such time otherwise there
817	* can be link issues with some switches. Other devices can have EEE LPI
818	* enabled immediately upon link up since they have a timer in hardware which
819	* prevents LPI from being asserted too early.
820	**/
821	s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
822	{
823	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
824	s32 ret_val;
825	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
826
827	switch (hw->phy.type) {
828	case e1000_phy_82579:
829	lpa = I82579_EEE_LP_ABILITY;
830	pcs_status = I82579_EEE_PCS_STATUS;
831	adv_addr = I82579_EEE_ADVERTISEMENT;
832	break;
833	case e1000_phy_i217:
834	lpa = I217_EEE_LP_ABILITY;
835	pcs_status = I217_EEE_PCS_STATUS;
836	adv_addr = I217_EEE_ADVERTISEMENT;
837	break;
838	default:
839	return 0;
840	}
841
842	ret_val = hw->phy.ops.acquire(hw);
843	if (ret_val)
844	return ret_val;
845
846	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, data: &lpi_ctrl);
847	if (ret_val)
848	goto release;
849
850	/* Clear bits that enable EEE in various speeds */
851	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
852
853	/* Enable EEE if not disabled by user */
854	if (!dev_spec->eee_disable) {
855	/* Save off link partner's EEE ability */
856	ret_val = e1000_read_emi_reg_locked(hw, addr: lpa,
857	data: &dev_spec->eee_lp_ability);
858	if (ret_val)
859	goto release;
860
861	/* Read EEE advertisement */
862	ret_val = e1000_read_emi_reg_locked(hw, addr: adv_addr, data: &adv);
863	if (ret_val)
864	goto release;
865
866	/* Enable EEE only for speeds in which the link partner is
867	* EEE capable and for which we advertise EEE.
868	*/
869	if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
870	lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
871
872	if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
873	e1e_rphy_locked(hw, MII_LPA, data: &data);
874	if (data & LPA_100FULL)
875	lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
876	else
877	/* EEE is not supported in 100Half, so ignore
878	* partner's EEE in 100 ability if full-duplex
879	* is not advertised.
880	*/
881	dev_spec->eee_lp_ability &=
882	~I82579_EEE_100_SUPPORTED;
883	}
884	}
885
886	if (hw->phy.type == e1000_phy_82579) {
887	ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
888	data: &data);
889	if (ret_val)
890	goto release;
891
892	data &= ~I82579_LPI_100_PLL_SHUT;
893	ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
894	data);
895	}
896
897	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
898	ret_val = e1000_read_emi_reg_locked(hw, addr: pcs_status, data: &data);
899	if (ret_val)
900	goto release;
901
902	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, data: lpi_ctrl);
903	release:
904	hw->phy.ops.release(hw);
905
906	return ret_val;
907	}
908
909	/**
910	* e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
911	* @hw: pointer to the HW structure
912	* @link: link up bool flag
913	*
914	* When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
915	* preventing further DMA write requests. Workaround the issue by disabling
916	* the de-assertion of the clock request when in 1Gpbs mode.
917	* Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
918	* speeds in order to avoid Tx hangs.
919	**/
920	static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
921	{
922	u32 fextnvm6 = er32(FEXTNVM6);
923	u32 status = er32(STATUS);
924	s32 ret_val = 0;
925	u16 reg;
926
927	if (link && (status & E1000_STATUS_SPEED_1000)) {
928	ret_val = hw->phy.ops.acquire(hw);
929	if (ret_val)
930	return ret_val;
931
932	ret_val =
933	e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
934	data: &reg);
935	if (ret_val)
936	goto release;
937
938	ret_val =
939	e1000e_write_kmrn_reg_locked(hw,
940	E1000_KMRNCTRLSTA_K1_CONFIG,
941	data: reg &
942	~E1000_KMRNCTRLSTA_K1_ENABLE);
943	if (ret_val)
944	goto release;
945
946	usleep_range(min: 10, max: 20);
947
948	ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
949
950	ret_val =
951	e1000e_write_kmrn_reg_locked(hw,
952	E1000_KMRNCTRLSTA_K1_CONFIG,
953	data: reg);
954	release:
955	hw->phy.ops.release(hw);
956	} else {
957	/* clear FEXTNVM6 bit 8 on link down or 10/100 */
958	fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
959
960	if ((hw->phy.revision > 5) || !link ||
961	((status & E1000_STATUS_SPEED_100) &&
962	(status & E1000_STATUS_FD)))
963	goto update_fextnvm6;
964
965	ret_val = e1e_rphy(hw, I217_INBAND_CTRL, data: &reg);
966	if (ret_val)
967	return ret_val;
968
969	/* Clear link status transmit timeout */
970	reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
971
972	if (status & E1000_STATUS_SPEED_100) {
973	/* Set inband Tx timeout to 5x10us for 100Half */
974	reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
975
976	/* Do not extend the K1 entry latency for 100Half */
977	fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
978	} else {
979	/* Set inband Tx timeout to 50x10us for 10Full/Half */
980	reg |= 50 <<
981	I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
982
983	/* Extend the K1 entry latency for 10 Mbps */
984	fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
985	}
986
987	ret_val = e1e_wphy(hw, I217_INBAND_CTRL, data: reg);
988	if (ret_val)
989	return ret_val;
990
991	update_fextnvm6:
992	ew32(FEXTNVM6, fextnvm6);
993	}
994
995	return ret_val;
996	}
997
998	/**
999	* e1000_platform_pm_pch_lpt - Set platform power management values
1000	* @hw: pointer to the HW structure
1001	* @link: bool indicating link status
1002	*
1003	* Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1004	* GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1005	* when link is up (which must not exceed the maximum latency supported
1006	* by the platform), otherwise specify there is no LTR requirement.
1007	* Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1008	* latencies in the LTR Extended Capability Structure in the PCIe Extended
1009	* Capability register set, on this device LTR is set by writing the
1010	* equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1011	* set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1012	* message to the PMC.
1013	**/
1014	static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1015	{
1016	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1017	link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1018	u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1019	u32 lat_enc_d = 0; /* latency decoded */
1020	u16 lat_enc = 0; /* latency encoded */
1021
1022	if (link) {
1023	u16 speed, duplex, scale = 0;
1024	u16 max_snoop, max_nosnoop;
1025	u16 max_ltr_enc; /* max LTR latency encoded */
1026	u64 value;
1027	u32 rxa;
1028
1029	if (!hw->adapter->max_frame_size) {
1030	e_dbg("max_frame_size not set.\n");
1031	return -E1000_ERR_CONFIG;
1032	}
1033
1034	hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1035	if (!speed) {
1036	e_dbg("Speed not set.\n");
1037	return -E1000_ERR_CONFIG;
1038	}
1039
1040	/* Rx Packet Buffer Allocation size (KB) */
1041	rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1042
1043	/* Determine the maximum latency tolerated by the device.
1044	*
1045	* Per the PCIe spec, the tolerated latencies are encoded as
1046	* a 3-bit encoded scale (only 0-5 are valid) multiplied by
1047	* a 10-bit value (0-1023) to provide a range from 1 ns to
1048	* 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1049	* 1=2^5ns, 2=2^10ns,...5=2^25ns.
1050	*/
1051	rxa *= 512;
1052	value = (rxa > hw->adapter->max_frame_size) ?
1053	(rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1054	0;
1055
1056	while (value > PCI_LTR_VALUE_MASK) {
1057	scale++;
1058	value = DIV_ROUND_UP(value, BIT(5));
1059	}
1060	if (scale > E1000_LTRV_SCALE_MAX) {
1061	e_dbg("Invalid LTR latency scale %d\n", scale);
1062	return -E1000_ERR_CONFIG;
1063	}
1064	lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1065
1066	/* Determine the maximum latency tolerated by the platform */
1067	pci_read_config_word(dev: hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1068	val: &max_snoop);
1069	pci_read_config_word(dev: hw->adapter->pdev,
1070	E1000_PCI_LTR_CAP_LPT + 2, val: &max_nosnoop);
1071	max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1072
1073	lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1074	(1U << (E1000_LTRV_SCALE_FACTOR *
1075	((lat_enc & E1000_LTRV_SCALE_MASK)
1076	>> E1000_LTRV_SCALE_SHIFT)));
1077
1078	max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1079	(1U << (E1000_LTRV_SCALE_FACTOR *
1080	((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1081	>> E1000_LTRV_SCALE_SHIFT)));
1082
1083	if (lat_enc_d > max_ltr_enc_d)
1084	lat_enc = max_ltr_enc;
1085	}
1086
1087	/* Set Snoop and No-Snoop latencies the same */
1088	reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1089	ew32(LTRV, reg);
1090
1091	return 0;
1092	}
1093
1094	/**
1095	* e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1096	* @hw: pointer to the HW structure
1097	* @to_sx: boolean indicating a system power state transition to Sx
1098	*
1099	* When link is down, configure ULP mode to significantly reduce the power
1100	* to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1101	* ME firmware to start the ULP configuration. If not on an ME enabled
1102	* system, configure the ULP mode by software.
1103	*/
1104	s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1105	{
1106	u32 mac_reg;
1107	s32 ret_val = 0;
1108	u16 phy_reg;
1109	u16 oem_reg = 0;
1110
1111	if ((hw->mac.type < e1000_pch_lpt) ||
1112	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1113	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1114	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1115	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1116	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1117	return 0;
1118
1119	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1120	/* Request ME configure ULP mode in the PHY */
1121	mac_reg = er32(H2ME);
1122	mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1123	ew32(H2ME, mac_reg);
1124
1125	goto out;
1126	}
1127
1128	if (!to_sx) {
1129	int i = 0;
1130
1131	/* Poll up to 5 seconds for Cable Disconnected indication */
1132	while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1133	/* Bail if link is re-acquired */
1134	if (er32(STATUS) & E1000_STATUS_LU)
1135	return -E1000_ERR_PHY;
1136
1137	if (i++ == 100)
1138	break;
1139
1140	msleep(msecs: 50);
1141	}
1142	e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1143	(er32(FEXT) &
1144	E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1145	}
1146
1147	ret_val = hw->phy.ops.acquire(hw);
1148	if (ret_val)
1149	goto out;
1150
1151	/* Force SMBus mode in PHY */
1152	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, data: &phy_reg);
1153	if (ret_val)
1154	goto release;
1155	phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1156	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, data: phy_reg);
1157
1158	/* Force SMBus mode in MAC */
1159	mac_reg = er32(CTRL_EXT);
1160	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1161	ew32(CTRL_EXT, mac_reg);
1162
1163	/* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1164	* LPLU and disable Gig speed when entering ULP
1165	*/
1166	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1167	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1168	data: &oem_reg);
1169	if (ret_val)
1170	goto release;
1171
1172	phy_reg = oem_reg;
1173	phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1174
1175	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1176	data: phy_reg);
1177
1178	if (ret_val)
1179	goto release;
1180	}
1181
1182	/* Set Inband ULP Exit, Reset to SMBus mode and
1183	* Disable SMBus Release on PERST# in PHY
1184	*/
1185	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: &phy_reg);
1186	if (ret_val)
1187	goto release;
1188	phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1189	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1190	if (to_sx) {
1191	if (er32(WUFC) & E1000_WUFC_LNKC)
1192	phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1193	else
1194	phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1195
1196	phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1197	phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1198	} else {
1199	phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1200	phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1201	phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1202	}
1203	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1204
1205	/* Set Disable SMBus Release on PERST# in MAC */
1206	mac_reg = er32(FEXTNVM7);
1207	mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1208	ew32(FEXTNVM7, mac_reg);
1209
1210	/* Commit ULP changes in PHY by starting auto ULP configuration */
1211	phy_reg |= I218_ULP_CONFIG1_START;
1212	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1213
1214	if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1215	to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1216	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1217	data: oem_reg);
1218	if (ret_val)
1219	goto release;
1220	}
1221
1222	release:
1223	hw->phy.ops.release(hw);
1224	out:
1225	if (ret_val)
1226	e_dbg("Error in ULP enable flow: %d\n", ret_val);
1227	else
1228	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1229
1230	return ret_val;
1231	}
1232
1233	/**
1234	* e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1235	* @hw: pointer to the HW structure
1236	* @force: boolean indicating whether or not to force disabling ULP
1237	*
1238	* Un-configure ULP mode when link is up, the system is transitioned from
1239	* Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1240	* system, poll for an indication from ME that ULP has been un-configured.
1241	* If not on an ME enabled system, un-configure the ULP mode by software.
1242	*
1243	* During nominal operation, this function is called when link is acquired
1244	* to disable ULP mode (force=false); otherwise, for example when unloading
1245	* the driver or during Sx->S0 transitions, this is called with force=true
1246	* to forcibly disable ULP.
1247	*/
1248	static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1249	{
1250	s32 ret_val = 0;
1251	u32 mac_reg;
1252	u16 phy_reg;
1253	int i = 0;
1254
1255	if ((hw->mac.type < e1000_pch_lpt) ||
1256	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1257	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1258	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1259	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1260	(hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1261	return 0;
1262
1263	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1264	struct e1000_adapter *adapter = hw->adapter;
1265	bool firmware_bug = false;
1266
1267	if (force) {
1268	/* Request ME un-configure ULP mode in the PHY */
1269	mac_reg = er32(H2ME);
1270	mac_reg &= ~E1000_H2ME_ULP;
1271	mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1272	ew32(H2ME, mac_reg);
1273	}
1274
1275	/* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1276	* If this takes more than 1 second, show a warning indicating a
1277	* firmware bug
1278	*/
1279	while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1280	if (i++ == 250) {
1281	ret_val = -E1000_ERR_PHY;
1282	goto out;
1283	}
1284	if (i > 100 && !firmware_bug)
1285	firmware_bug = true;
1286
1287	usleep_range(min: 10000, max: 11000);
1288	}
1289	if (firmware_bug)
1290	e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1291	i * 10);
1292	else
1293	e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1294	i * 10);
1295
1296	if (force) {
1297	mac_reg = er32(H2ME);
1298	mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1299	ew32(H2ME, mac_reg);
1300	} else {
1301	/* Clear H2ME.ULP after ME ULP configuration */
1302	mac_reg = er32(H2ME);
1303	mac_reg &= ~E1000_H2ME_ULP;
1304	ew32(H2ME, mac_reg);
1305	}
1306
1307	goto out;
1308	}
1309
1310	ret_val = hw->phy.ops.acquire(hw);
1311	if (ret_val)
1312	goto out;
1313
1314	if (force)
1315	/* Toggle LANPHYPC Value bit */
1316	e1000_toggle_lanphypc_pch_lpt(hw);
1317
1318	/* Unforce SMBus mode in PHY */
1319	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, data: &phy_reg);
1320	if (ret_val) {
1321	/* The MAC might be in PCIe mode, so temporarily force to
1322	* SMBus mode in order to access the PHY.
1323	*/
1324	mac_reg = er32(CTRL_EXT);
1325	mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1326	ew32(CTRL_EXT, mac_reg);
1327
1328	msleep(msecs: 50);
1329
1330	ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1331	data: &phy_reg);
1332	if (ret_val)
1333	goto release;
1334	}
1335	phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1336	e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, data: phy_reg);
1337
1338	/* Unforce SMBus mode in MAC */
1339	mac_reg = er32(CTRL_EXT);
1340	mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1341	ew32(CTRL_EXT, mac_reg);
1342
1343	/* When ULP mode was previously entered, K1 was disabled by the
1344	* hardware. Re-Enable K1 in the PHY when exiting ULP.
1345	*/
1346	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, data: &phy_reg);
1347	if (ret_val)
1348	goto release;
1349	phy_reg |= HV_PM_CTRL_K1_ENABLE;
1350	e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, data: phy_reg);
1351
1352	/* Clear ULP enabled configuration */
1353	ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: &phy_reg);
1354	if (ret_val)
1355	goto release;
1356	phy_reg &= ~(I218_ULP_CONFIG1_IND |
1357	I218_ULP_CONFIG1_STICKY_ULP |
1358	I218_ULP_CONFIG1_RESET_TO_SMBUS |
1359	I218_ULP_CONFIG1_WOL_HOST |
1360	I218_ULP_CONFIG1_INBAND_EXIT |
1361	I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1362	I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1363	I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1364	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1365
1366	/* Commit ULP changes by starting auto ULP configuration */
1367	phy_reg |= I218_ULP_CONFIG1_START;
1368	e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, data: phy_reg);
1369
1370	/* Clear Disable SMBus Release on PERST# in MAC */
1371	mac_reg = er32(FEXTNVM7);
1372	mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1373	ew32(FEXTNVM7, mac_reg);
1374
1375	release:
1376	hw->phy.ops.release(hw);
1377	if (force) {
1378	e1000_phy_hw_reset(hw);
1379	msleep(msecs: 50);
1380	}
1381	out:
1382	if (ret_val)
1383	e_dbg("Error in ULP disable flow: %d\n", ret_val);
1384	else
1385	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1386
1387	return ret_val;
1388	}
1389
1390	/**
1391	* e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1392	* @hw: pointer to the HW structure
1393	*
1394	* Checks to see of the link status of the hardware has changed. If a
1395	* change in link status has been detected, then we read the PHY registers
1396	* to get the current speed/duplex if link exists.
1397	**/
1398	static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1399	{
1400	struct e1000_mac_info *mac = &hw->mac;
1401	s32 ret_val, tipg_reg = 0;
1402	u16 emi_addr, emi_val = 0;
1403	bool link;
1404	u16 phy_reg;
1405
1406	/* We only want to go out to the PHY registers to see if Auto-Neg
1407	* has completed and/or if our link status has changed. The
1408	* get_link_status flag is set upon receiving a Link Status
1409	* Change or Rx Sequence Error interrupt.
1410	*/
1411	if (!mac->get_link_status)
1412	return 0;
1413	mac->get_link_status = false;
1414
1415	/* First we want to see if the MII Status Register reports
1416	* link. If so, then we want to get the current speed/duplex
1417	* of the PHY.
1418	*/
1419	ret_val = e1000e_phy_has_link_generic(hw, iterations: 1, usec_interval: 0, success: &link);
1420	if (ret_val)
1421	goto out;
1422
1423	if (hw->mac.type == e1000_pchlan) {
1424	ret_val = e1000_k1_gig_workaround_hv(hw, link);
1425	if (ret_val)
1426	goto out;
1427	}
1428
1429	/* When connected at 10Mbps half-duplex, some parts are excessively
1430	* aggressive resulting in many collisions. To avoid this, increase
1431	* the IPG and reduce Rx latency in the PHY.
1432	*/
1433	if ((hw->mac.type >= e1000_pch2lan) && link) {
1434	u16 speed, duplex;
1435
1436	e1000e_get_speed_and_duplex_copper(hw, speed: &speed, duplex: &duplex);
1437	tipg_reg = er32(TIPG);
1438	tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1439
1440	if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1441	tipg_reg |= 0xFF;
1442	/* Reduce Rx latency in analog PHY */
1443	emi_val = 0;
1444	} else if (hw->mac.type >= e1000_pch_spt &&
1445	duplex == FULL_DUPLEX && speed != SPEED_1000) {
1446	tipg_reg |= 0xC;
1447	emi_val = 1;
1448	} else {
1449
1450	/* Roll back the default values */
1451	tipg_reg |= 0x08;
1452	emi_val = 1;
1453	}
1454
1455	ew32(TIPG, tipg_reg);
1456
1457	ret_val = hw->phy.ops.acquire(hw);
1458	if (ret_val)
1459	goto out;
1460
1461	if (hw->mac.type == e1000_pch2lan)
1462	emi_addr = I82579_RX_CONFIG;
1463	else
1464	emi_addr = I217_RX_CONFIG;
1465	ret_val = e1000_write_emi_reg_locked(hw, addr: emi_addr, data: emi_val);
1466
1467	if (hw->mac.type >= e1000_pch_lpt) {
1468	u16 phy_reg;
1469
1470	e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, data: &phy_reg);
1471	phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1472	if (speed == SPEED_100 || speed == SPEED_10)
1473	phy_reg |= 0x3E8;
1474	else
1475	phy_reg |= 0xFA;
1476	e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, data: phy_reg);
1477
1478	if (speed == SPEED_1000) {
1479	hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1480	&phy_reg);
1481
1482	phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1483
1484	hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1485	phy_reg);
1486	}
1487	}
1488	hw->phy.ops.release(hw);
1489
1490	if (ret_val)
1491	goto out;
1492
1493	if (hw->mac.type >= e1000_pch_spt) {
1494	u16 data;
1495	u16 ptr_gap;
1496
1497	if (speed == SPEED_1000) {
1498	ret_val = hw->phy.ops.acquire(hw);
1499	if (ret_val)
1500	goto out;
1501
1502	ret_val = e1e_rphy_locked(hw,
1503	PHY_REG(776, 20),
1504	data: &data);
1505	if (ret_val) {
1506	hw->phy.ops.release(hw);
1507	goto out;
1508	}
1509
1510	ptr_gap = (data & (0x3FF << 2)) >> 2;
1511	if (ptr_gap < 0x18) {
1512	data &= ~(0x3FF << 2);
1513	data |= (0x18 << 2);
1514	ret_val =
1515	e1e_wphy_locked(hw,
1516	PHY_REG(776, 20),
1517	data);
1518	}
1519	hw->phy.ops.release(hw);
1520	if (ret_val)
1521	goto out;
1522	} else {
1523	ret_val = hw->phy.ops.acquire(hw);
1524	if (ret_val)
1525	goto out;
1526
1527	ret_val = e1e_wphy_locked(hw,
1528	PHY_REG(776, 20),
1529	data: 0xC023);
1530	hw->phy.ops.release(hw);
1531	if (ret_val)
1532	goto out;
1533
1534	}
1535	}
1536	}
1537
1538	/* I217 Packet Loss issue:
1539	* ensure that FEXTNVM4 Beacon Duration is set correctly
1540	* on power up.
1541	* Set the Beacon Duration for I217 to 8 usec
1542	*/
1543	if (hw->mac.type >= e1000_pch_lpt) {
1544	u32 mac_reg;
1545
1546	mac_reg = er32(FEXTNVM4);
1547	mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1548	mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1549	ew32(FEXTNVM4, mac_reg);
1550	}
1551
1552	/* Work-around I218 hang issue */
1553	if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1554	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1555	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1556	(hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1557	ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1558	if (ret_val)
1559	goto out;
1560	}
1561	if (hw->mac.type >= e1000_pch_lpt) {
1562	/* Set platform power management values for
1563	* Latency Tolerance Reporting (LTR)
1564	*/
1565	ret_val = e1000_platform_pm_pch_lpt(hw, link);
1566	if (ret_val)
1567	goto out;
1568	}
1569
1570	/* Clear link partner's EEE ability */
1571	hw->dev_spec.ich8lan.eee_lp_ability = 0;
1572
1573	if (hw->mac.type >= e1000_pch_lpt) {
1574	u32 fextnvm6 = er32(FEXTNVM6);
1575
1576	if (hw->mac.type == e1000_pch_spt) {
1577	/* FEXTNVM6 K1-off workaround - for SPT only */
1578	u32 pcieanacfg = er32(PCIEANACFG);
1579
1580	if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1581	fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1582	else
1583	fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1584	}
1585
1586	ew32(FEXTNVM6, fextnvm6);
1587	}
1588
1589	if (!link)
1590	goto out;
1591
1592	switch (hw->mac.type) {
1593	case e1000_pch2lan:
1594	ret_val = e1000_k1_workaround_lv(hw);
1595	if (ret_val)
1596	return ret_val;
1597	fallthrough;
1598	case e1000_pchlan:
1599	if (hw->phy.type == e1000_phy_82578) {
1600	ret_val = e1000_link_stall_workaround_hv(hw);
1601	if (ret_val)
1602	return ret_val;
1603	}
1604
1605	/* Workaround for PCHx parts in half-duplex:
1606	* Set the number of preambles removed from the packet
1607	* when it is passed from the PHY to the MAC to prevent
1608	* the MAC from misinterpreting the packet type.
1609	*/
1610	e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, data: &phy_reg);
1611	phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1612
1613	if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1614	phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1615
1616	e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, data: phy_reg);
1617	break;
1618	default:
1619	break;
1620	}
1621
1622	/* Check if there was DownShift, must be checked
1623	* immediately after link-up
1624	*/
1625	e1000e_check_downshift(hw);
1626
1627	/* Enable/Disable EEE after link up */
1628	if (hw->phy.type > e1000_phy_82579) {
1629	ret_val = e1000_set_eee_pchlan(hw);
1630	if (ret_val)
1631	return ret_val;
1632	}
1633
1634	/* If we are forcing speed/duplex, then we simply return since
1635	* we have already determined whether we have link or not.
1636	*/
1637	if (!mac->autoneg)
1638	return -E1000_ERR_CONFIG;
1639
1640	/* Auto-Neg is enabled. Auto Speed Detection takes care
1641	* of MAC speed/duplex configuration. So we only need to
1642	* configure Collision Distance in the MAC.
1643	*/
1644	mac->ops.config_collision_dist(hw);
1645
1646	/* Configure Flow Control now that Auto-Neg has completed.
1647	* First, we need to restore the desired flow control
1648	* settings because we may have had to re-autoneg with a
1649	* different link partner.
1650	*/
1651	ret_val = e1000e_config_fc_after_link_up(hw);
1652	if (ret_val)
1653	e_dbg("Error configuring flow control\n");
1654
1655	return ret_val;
1656
1657	out:
1658	mac->get_link_status = true;
1659	return ret_val;
1660	}
1661
1662	static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1663	{
1664	struct e1000_hw *hw = &adapter->hw;
1665	s32 rc;
1666
1667	rc = e1000_init_mac_params_ich8lan(hw);
1668	if (rc)
1669	return rc;
1670
1671	rc = e1000_init_nvm_params_ich8lan(hw);
1672	if (rc)
1673	return rc;
1674
1675	switch (hw->mac.type) {
1676	case e1000_ich8lan:
1677	case e1000_ich9lan:
1678	case e1000_ich10lan:
1679	rc = e1000_init_phy_params_ich8lan(hw);
1680	break;
1681	case e1000_pchlan:
1682	case e1000_pch2lan:
1683	case e1000_pch_lpt:
1684	case e1000_pch_spt:
1685	case e1000_pch_cnp:
1686	case e1000_pch_tgp:
1687	case e1000_pch_adp:
1688	case e1000_pch_mtp:
1689	case e1000_pch_lnp:
1690	case e1000_pch_ptp:
1691	case e1000_pch_nvp:
1692	rc = e1000_init_phy_params_pchlan(hw);
1693	break;
1694	default:
1695	break;
1696	}
1697	if (rc)
1698	return rc;
1699
1700	/* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1701	* on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1702	*/
1703	if ((adapter->hw.phy.type == e1000_phy_ife) ||
1704	((adapter->hw.mac.type >= e1000_pch2lan) &&
1705	(!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1706	adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1707	adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1708
1709	hw->mac.ops.blink_led = NULL;
1710	}
1711
1712	if ((adapter->hw.mac.type == e1000_ich8lan) &&
1713	(adapter->hw.phy.type != e1000_phy_ife))
1714	adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1715
1716	/* Enable workaround for 82579 w/ ME enabled */
1717	if ((adapter->hw.mac.type == e1000_pch2lan) &&
1718	(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1719	adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1720
1721	return 0;
1722	}
1723
1724	static DEFINE_MUTEX(nvm_mutex);
1725
1726	/**
1727	* e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1728	* @hw: pointer to the HW structure
1729	*
1730	* Acquires the mutex for performing NVM operations.
1731	**/
1732	static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1733	{
1734	mutex_lock(&nvm_mutex);
1735
1736	return 0;
1737	}
1738
1739	/**
1740	* e1000_release_nvm_ich8lan - Release NVM mutex
1741	* @hw: pointer to the HW structure
1742	*
1743	* Releases the mutex used while performing NVM operations.
1744	**/
1745	static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1746	{
1747	mutex_unlock(lock: &nvm_mutex);
1748	}
1749
1750	/**
1751	* e1000_acquire_swflag_ich8lan - Acquire software control flag
1752	* @hw: pointer to the HW structure
1753	*
1754	* Acquires the software control flag for performing PHY and select
1755	* MAC CSR accesses.
1756	**/
1757	static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1758	{
1759	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1760	s32 ret_val = 0;
1761
1762	if (test_and_set_bit(nr: __E1000_ACCESS_SHARED_RESOURCE,
1763	addr: &hw->adapter->state)) {
1764	e_dbg("contention for Phy access\n");
1765	return -E1000_ERR_PHY;
1766	}
1767
1768	while (timeout) {
1769	extcnf_ctrl = er32(EXTCNF_CTRL);
1770	if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1771	break;
1772
1773	mdelay(1);
1774	timeout--;
1775	}
1776
1777	if (!timeout) {
1778	e_dbg("SW has already locked the resource.\n");
1779	ret_val = -E1000_ERR_CONFIG;
1780	goto out;
1781	}
1782
1783	timeout = SW_FLAG_TIMEOUT;
1784
1785	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1786	ew32(EXTCNF_CTRL, extcnf_ctrl);
1787
1788	while (timeout) {
1789	extcnf_ctrl = er32(EXTCNF_CTRL);
1790	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1791	break;
1792
1793	mdelay(1);
1794	timeout--;
1795	}
1796
1797	if (!timeout) {
1798	e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1799	er32(FWSM), extcnf_ctrl);
1800	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1801	ew32(EXTCNF_CTRL, extcnf_ctrl);
1802	ret_val = -E1000_ERR_CONFIG;
1803	goto out;
1804	}
1805
1806	out:
1807	if (ret_val)
1808	clear_bit(nr: __E1000_ACCESS_SHARED_RESOURCE, addr: &hw->adapter->state);
1809
1810	return ret_val;
1811	}
1812
1813	/**
1814	* e1000_release_swflag_ich8lan - Release software control flag
1815	* @hw: pointer to the HW structure
1816	*
1817	* Releases the software control flag for performing PHY and select
1818	* MAC CSR accesses.
1819	**/
1820	static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1821	{
1822	u32 extcnf_ctrl;
1823
1824	extcnf_ctrl = er32(EXTCNF_CTRL);
1825
1826	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1827	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1828	ew32(EXTCNF_CTRL, extcnf_ctrl);
1829	} else {
1830	e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1831	}
1832
1833	clear_bit(nr: __E1000_ACCESS_SHARED_RESOURCE, addr: &hw->adapter->state);
1834	}
1835
1836	/**
1837	* e1000_check_mng_mode_ich8lan - Checks management mode
1838	* @hw: pointer to the HW structure
1839	*
1840	* This checks if the adapter has any manageability enabled.
1841	* This is a function pointer entry point only called by read/write
1842	* routines for the PHY and NVM parts.
1843	**/
1844	static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1845	{
1846	u32 fwsm;
1847
1848	fwsm = er32(FWSM);
1849	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1850	((fwsm & E1000_FWSM_MODE_MASK) ==
1851	(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1852	}
1853
1854	/**
1855	* e1000_check_mng_mode_pchlan - Checks management mode
1856	* @hw: pointer to the HW structure
1857	*
1858	* This checks if the adapter has iAMT enabled.
1859	* This is a function pointer entry point only called by read/write
1860	* routines for the PHY and NVM parts.
1861	**/
1862	static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1863	{
1864	u32 fwsm;
1865
1866	fwsm = er32(FWSM);
1867	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1868	(fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1869	}
1870
1871	/**
1872	* e1000_rar_set_pch2lan - Set receive address register
1873	* @hw: pointer to the HW structure
1874	* @addr: pointer to the receive address
1875	* @index: receive address array register
1876	*
1877	* Sets the receive address array register at index to the address passed
1878	* in by addr. For 82579, RAR[0] is the base address register that is to
1879	* contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1880	* Use SHRA[0-3] in place of those reserved for ME.
1881	**/
1882	static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1883	{
1884	u32 rar_low, rar_high;
1885
1886	/* HW expects these in little endian so we reverse the byte order
1887	* from network order (big endian) to little endian
1888	*/
1889	rar_low = ((u32)addr[0] |
1890	((u32)addr[1] << 8) |
1891	((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1892
1893	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1894
1895	/* If MAC address zero, no need to set the AV bit */
1896	if (rar_low || rar_high)
1897	rar_high |= E1000_RAH_AV;
1898
1899	if (index == 0) {
1900	ew32(RAL(index), rar_low);
1901	e1e_flush();
1902	ew32(RAH(index), rar_high);
1903	e1e_flush();
1904	return 0;
1905	}
1906
1907	/* RAR[1-6] are owned by manageability. Skip those and program the
1908	* next address into the SHRA register array.
1909	*/
1910	if (index < (u32)(hw->mac.rar_entry_count)) {
1911	s32 ret_val;
1912
1913	ret_val = e1000_acquire_swflag_ich8lan(hw);
1914	if (ret_val)
1915	goto out;
1916
1917	ew32(SHRAL(index - 1), rar_low);
1918	e1e_flush();
1919	ew32(SHRAH(index - 1), rar_high);
1920	e1e_flush();
1921
1922	e1000_release_swflag_ich8lan(hw);
1923
1924	/* verify the register updates */
1925	if ((er32(SHRAL(index - 1)) == rar_low) &&
1926	(er32(SHRAH(index - 1)) == rar_high))
1927	return 0;
1928
1929	e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1930	(index - 1), er32(FWSM));
1931	}
1932
1933	out:
1934	e_dbg("Failed to write receive address at index %d\n", index);
1935	return -E1000_ERR_CONFIG;
1936	}
1937
1938	/**
1939	* e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1940	* @hw: pointer to the HW structure
1941	*
1942	* Get the number of available receive registers that the Host can
1943	* program. SHRA[0-10] are the shared receive address registers
1944	* that are shared between the Host and manageability engine (ME).
1945	* ME can reserve any number of addresses and the host needs to be
1946	* able to tell how many available registers it has access to.
1947	**/
1948	static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1949	{
1950	u32 wlock_mac;
1951	u32 num_entries;
1952
1953	wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1954	wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1955
1956	switch (wlock_mac) {
1957	case 0:
1958	/* All SHRA[0..10] and RAR[0] available */
1959	num_entries = hw->mac.rar_entry_count;
1960	break;
1961	case 1:
1962	/* Only RAR[0] available */
1963	num_entries = 1;
1964	break;
1965	default:
1966	/* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1967	num_entries = wlock_mac + 1;
1968	break;
1969	}
1970
1971	return num_entries;
1972	}
1973
1974	/**
1975	* e1000_rar_set_pch_lpt - Set receive address registers
1976	* @hw: pointer to the HW structure
1977	* @addr: pointer to the receive address
1978	* @index: receive address array register
1979	*
1980	* Sets the receive address register array at index to the address passed
1981	* in by addr. For LPT, RAR[0] is the base address register that is to
1982	* contain the MAC address. SHRA[0-10] are the shared receive address
1983	* registers that are shared between the Host and manageability engine (ME).
1984	**/
1985	static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1986	{
1987	u32 rar_low, rar_high;
1988	u32 wlock_mac;
1989
1990	/* HW expects these in little endian so we reverse the byte order
1991	* from network order (big endian) to little endian
1992	*/
1993	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1994	((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1995
1996	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1997
1998	/* If MAC address zero, no need to set the AV bit */
1999	if (rar_low || rar_high)
2000	rar_high |= E1000_RAH_AV;
2001
2002	if (index == 0) {
2003	ew32(RAL(index), rar_low);
2004	e1e_flush();
2005	ew32(RAH(index), rar_high);
2006	e1e_flush();
2007	return 0;
2008	}
2009
2010	/* The manageability engine (ME) can lock certain SHRAR registers that
2011	* it is using - those registers are unavailable for use.
2012	*/
2013	if (index < hw->mac.rar_entry_count) {
2014	wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2015	wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2016
2017	/* Check if all SHRAR registers are locked */
2018	if (wlock_mac == 1)
2019	goto out;
2020
2021	if ((wlock_mac == 0) || (index <= wlock_mac)) {
2022	s32 ret_val;
2023
2024	ret_val = e1000_acquire_swflag_ich8lan(hw);
2025
2026	if (ret_val)
2027	goto out;
2028
2029	ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2030	e1e_flush();
2031	ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2032	e1e_flush();
2033
2034	e1000_release_swflag_ich8lan(hw);
2035
2036	/* verify the register updates */
2037	if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2038	(er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2039	return 0;
2040	}
2041	}
2042
2043	out:
2044	e_dbg("Failed to write receive address at index %d\n", index);
2045	return -E1000_ERR_CONFIG;
2046	}
2047
2048	/**
2049	* e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2050	* @hw: pointer to the HW structure
2051	*
2052	* Checks if firmware is blocking the reset of the PHY.
2053	* This is a function pointer entry point only called by
2054	* reset routines.
2055	**/
2056	static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2057	{
2058	bool blocked = false;
2059	int i = 0;
2060
2061	while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2062	(i++ < 30))
2063	usleep_range(min: 10000, max: 11000);
2064	return blocked ? E1000_BLK_PHY_RESET : 0;
2065	}
2066
2067	/**
2068	* e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2069	* @hw: pointer to the HW structure
2070	*
2071	* Assumes semaphore already acquired.
2072	*
2073	**/
2074	static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2075	{
2076	u16 phy_data;
2077	u32 strap = er32(STRAP);
2078	u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2079	E1000_STRAP_SMT_FREQ_SHIFT;
2080	s32 ret_val;
2081
2082	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2083
2084	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, data: &phy_data);
2085	if (ret_val)
2086	return ret_val;
2087
2088	phy_data &= ~HV_SMB_ADDR_MASK;
2089	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2090	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2091
2092	if (hw->phy.type == e1000_phy_i217) {
2093	/* Restore SMBus frequency */
2094	if (freq--) {
2095	phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2096	phy_data |= (freq & BIT(0)) <<
2097	HV_SMB_ADDR_FREQ_LOW_SHIFT;
2098	phy_data |= (freq & BIT(1)) <<
2099	(HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2100	} else {
2101	e_dbg("Unsupported SMB frequency in PHY\n");
2102	}
2103	}
2104
2105	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, data: phy_data);
2106	}
2107
2108	/**
2109	* e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2110	* @hw: pointer to the HW structure
2111	*
2112	* SW should configure the LCD from the NVM extended configuration region
2113	* as a workaround for certain parts.
2114	**/
2115	static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2116	{
2117	struct e1000_phy_info *phy = &hw->phy;
2118	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2119	s32 ret_val = 0;
2120	u16 word_addr, reg_data, reg_addr, phy_page = 0;
2121
2122	/* Initialize the PHY from the NVM on ICH platforms. This
2123	* is needed due to an issue where the NVM configuration is
2124	* not properly autoloaded after power transitions.
2125	* Therefore, after each PHY reset, we will load the
2126	* configuration data out of the NVM manually.
2127	*/
2128	switch (hw->mac.type) {
2129	case e1000_ich8lan:
2130	if (phy->type != e1000_phy_igp_3)
2131	return ret_val;
2132
2133	if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2134	(hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2135	sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2136	break;
2137	}
2138	fallthrough;
2139	case e1000_pchlan:
2140	case e1000_pch2lan:
2141	case e1000_pch_lpt:
2142	case e1000_pch_spt:
2143	case e1000_pch_cnp:
2144	case e1000_pch_tgp:
2145	case e1000_pch_adp:
2146	case e1000_pch_mtp:
2147	case e1000_pch_lnp:
2148	case e1000_pch_ptp:
2149	case e1000_pch_nvp:
2150	sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2151	break;
2152	default:
2153	return ret_val;
2154	}
2155
2156	ret_val = hw->phy.ops.acquire(hw);
2157	if (ret_val)
2158	return ret_val;
2159
2160	data = er32(FEXTNVM);
2161	if (!(data & sw_cfg_mask))
2162	goto release;
2163
2164	/* Make sure HW does not configure LCD from PHY
2165	* extended configuration before SW configuration
2166	*/
2167	data = er32(EXTCNF_CTRL);
2168	if ((hw->mac.type < e1000_pch2lan) &&
2169	(data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2170	goto release;
2171
2172	cnf_size = er32(EXTCNF_SIZE);
2173	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2174	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2175	if (!cnf_size)
2176	goto release;
2177
2178	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2179	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2180
2181	if (((hw->mac.type == e1000_pchlan) &&
2182	!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2183	(hw->mac.type > e1000_pchlan)) {
2184	/* HW configures the SMBus address and LEDs when the
2185	* OEM and LCD Write Enable bits are set in the NVM.
2186	* When both NVM bits are cleared, SW will configure
2187	* them instead.
2188	*/
2189	ret_val = e1000_write_smbus_addr(hw);
2190	if (ret_val)
2191	goto release;
2192
2193	data = er32(LEDCTL);
2194	ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2195	data: (u16)data);
2196	if (ret_val)
2197	goto release;
2198	}
2199
2200	/* Configure LCD from extended configuration region. */
2201
2202	/* cnf_base_addr is in DWORD */
2203	word_addr = (u16)(cnf_base_addr << 1);
2204
2205	for (i = 0; i < cnf_size; i++) {
2206	ret_val = e1000_read_nvm(hw, offset: (word_addr + i * 2), words: 1, data: &reg_data);
2207	if (ret_val)
2208	goto release;
2209
2210	ret_val = e1000_read_nvm(hw, offset: (word_addr + i * 2 + 1),
2211	words: 1, data: &reg_addr);
2212	if (ret_val)
2213	goto release;
2214
2215	/* Save off the PHY page for future writes. */
2216	if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2217	phy_page = reg_data;
2218	continue;
2219	}
2220
2221	reg_addr &= PHY_REG_MASK;
2222	reg_addr |= phy_page;
2223
2224	ret_val = e1e_wphy_locked(hw, offset: (u32)reg_addr, data: reg_data);
2225	if (ret_val)
2226	goto release;
2227	}
2228
2229	release:
2230	hw->phy.ops.release(hw);
2231	return ret_val;
2232	}
2233
2234	/**
2235	* e1000_k1_gig_workaround_hv - K1 Si workaround
2236	* @hw: pointer to the HW structure
2237	* @link: link up bool flag
2238	*
2239	* If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2240	* from a lower speed. This workaround disables K1 whenever link is at 1Gig
2241	* If link is down, the function will restore the default K1 setting located
2242	* in the NVM.
2243	**/
2244	static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2245	{
2246	s32 ret_val = 0;
2247	u16 status_reg = 0;
2248	bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2249
2250	if (hw->mac.type != e1000_pchlan)
2251	return 0;
2252
2253	/* Wrap the whole flow with the sw flag */
2254	ret_val = hw->phy.ops.acquire(hw);
2255	if (ret_val)
2256	return ret_val;
2257
2258	/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2259	if (link) {
2260	if (hw->phy.type == e1000_phy_82578) {
2261	ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2262	data: &status_reg);
2263	if (ret_val)
2264	goto release;
2265
2266	status_reg &= (BM_CS_STATUS_LINK_UP |
2267	BM_CS_STATUS_RESOLVED |
2268	BM_CS_STATUS_SPEED_MASK);
2269
2270	if (status_reg == (BM_CS_STATUS_LINK_UP |
2271	BM_CS_STATUS_RESOLVED |
2272	BM_CS_STATUS_SPEED_1000))
2273	k1_enable = false;
2274	}
2275
2276	if (hw->phy.type == e1000_phy_82577) {
2277	ret_val = e1e_rphy_locked(hw, HV_M_STATUS, data: &status_reg);
2278	if (ret_val)
2279	goto release;
2280
2281	status_reg &= (HV_M_STATUS_LINK_UP |
2282	HV_M_STATUS_AUTONEG_COMPLETE |
2283	HV_M_STATUS_SPEED_MASK);
2284
2285	if (status_reg == (HV_M_STATUS_LINK_UP |
2286	HV_M_STATUS_AUTONEG_COMPLETE |
2287	HV_M_STATUS_SPEED_1000))
2288	k1_enable = false;
2289	}
2290
2291	/* Link stall fix for link up */
2292	ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), data: 0x0100);
2293	if (ret_val)
2294	goto release;
2295
2296	} else {
2297	/* Link stall fix for link down */
2298	ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), data: 0x4100);
2299	if (ret_val)
2300	goto release;
2301	}
2302
2303	ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2304
2305	release:
2306	hw->phy.ops.release(hw);
2307
2308	return ret_val;
2309	}
2310
2311	/**
2312	* e1000_configure_k1_ich8lan - Configure K1 power state
2313	* @hw: pointer to the HW structure
2314	* @k1_enable: K1 state to configure
2315	*
2316	* Configure the K1 power state based on the provided parameter.
2317	* Assumes semaphore already acquired.
2318	*
2319	* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2320	**/
2321	s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2322	{
2323	s32 ret_val;
2324	u32 ctrl_reg = 0;
2325	u32 ctrl_ext = 0;
2326	u32 reg = 0;
2327	u16 kmrn_reg = 0;
2328
2329	ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2330	data: &kmrn_reg);
2331	if (ret_val)
2332	return ret_val;
2333
2334	if (k1_enable)
2335	kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2336	else
2337	kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2338
2339	ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2340	data: kmrn_reg);
2341	if (ret_val)
2342	return ret_val;
2343
2344	usleep_range(min: 20, max: 40);
2345	ctrl_ext = er32(CTRL_EXT);
2346	ctrl_reg = er32(CTRL);
2347
2348	reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2349	reg |= E1000_CTRL_FRCSPD;
2350	ew32(CTRL, reg);
2351
2352	ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2353	e1e_flush();
2354	usleep_range(min: 20, max: 40);
2355	ew32(CTRL, ctrl_reg);
2356	ew32(CTRL_EXT, ctrl_ext);
2357	e1e_flush();
2358	usleep_range(min: 20, max: 40);
2359
2360	return 0;
2361	}
2362
2363	/**
2364	* e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2365	* @hw: pointer to the HW structure
2366	* @d0_state: boolean if entering d0 or d3 device state
2367	*
2368	* SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2369	* collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2370	* in NVM determines whether HW should configure LPLU and Gbe Disable.
2371	**/
2372	static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2373	{
2374	s32 ret_val = 0;
2375	u32 mac_reg;
2376	u16 oem_reg;
2377
2378	if (hw->mac.type < e1000_pchlan)
2379	return ret_val;
2380
2381	ret_val = hw->phy.ops.acquire(hw);
2382	if (ret_val)
2383	return ret_val;
2384
2385	if (hw->mac.type == e1000_pchlan) {
2386	mac_reg = er32(EXTCNF_CTRL);
2387	if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2388	goto release;
2389	}
2390
2391	mac_reg = er32(FEXTNVM);
2392	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2393	goto release;
2394
2395	mac_reg = er32(PHY_CTRL);
2396
2397	ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, data: &oem_reg);
2398	if (ret_val)
2399	goto release;
2400
2401	oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2402
2403	if (d0_state) {
2404	if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2405	oem_reg |= HV_OEM_BITS_GBE_DIS;
2406
2407	if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2408	oem_reg |= HV_OEM_BITS_LPLU;
2409	} else {
2410	if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2411	E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2412	oem_reg |= HV_OEM_BITS_GBE_DIS;
2413
2414	if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2415	E1000_PHY_CTRL_NOND0A_LPLU))
2416	oem_reg |= HV_OEM_BITS_LPLU;
2417	}
2418
2419	/* Set Restart auto-neg to activate the bits */
2420	if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2421	!hw->phy.ops.check_reset_block(hw))
2422	oem_reg |= HV_OEM_BITS_RESTART_AN;
2423
2424	ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, data: oem_reg);
2425
2426	release:
2427	hw->phy.ops.release(hw);
2428
2429	return ret_val;
2430	}
2431
2432	/**
2433	* e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2434	* @hw: pointer to the HW structure
2435	**/
2436	static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2437	{
2438	s32 ret_val;
2439	u16 data;
2440
2441	ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, data: &data);
2442	if (ret_val)
2443	return ret_val;
2444
2445	data |= HV_KMRN_MDIO_SLOW;
2446
2447	ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2448
2449	return ret_val;
2450	}
2451
2452	/**
2453	* e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2454	* @hw: pointer to the HW structure
2455	*
2456	* A series of PHY workarounds to be done after every PHY reset.
2457	**/
2458	static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2459	{
2460	s32 ret_val = 0;
2461	u16 phy_data;
2462
2463	if (hw->mac.type != e1000_pchlan)
2464	return 0;
2465
2466	/* Set MDIO slow mode before any other MDIO access */
2467	if (hw->phy.type == e1000_phy_82577) {
2468	ret_val = e1000_set_mdio_slow_mode_hv(hw);
2469	if (ret_val)
2470	return ret_val;
2471	}
2472
2473	if (((hw->phy.type == e1000_phy_82577) &&
2474	((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2475	((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2476	/* Disable generation of early preamble */
2477	ret_val = e1e_wphy(hw, PHY_REG(769, 25), data: 0x4431);
2478	if (ret_val)
2479	return ret_val;
2480
2481	/* Preamble tuning for SSC */
2482	ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, data: 0xA204);
2483	if (ret_val)
2484	return ret_val;
2485	}
2486
2487	if (hw->phy.type == e1000_phy_82578) {
2488	/* Return registers to default by doing a soft reset then
2489	* writing 0x3140 to the control register.
2490	*/
2491	if (hw->phy.revision < 2) {
2492	e1000e_phy_sw_reset(hw);
2493	ret_val = e1e_wphy(hw, MII_BMCR, data: 0x3140);
2494	if (ret_val)
2495	return ret_val;
2496	}
2497	}
2498
2499	/* Select page 0 */
2500	ret_val = hw->phy.ops.acquire(hw);
2501	if (ret_val)
2502	return ret_val;
2503
2504	hw->phy.addr = 1;
2505	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, data: 0);
2506	hw->phy.ops.release(hw);
2507	if (ret_val)
2508	return ret_val;
2509
2510	/* Configure the K1 Si workaround during phy reset assuming there is
2511	* link so that it disables K1 if link is in 1Gbps.
2512	*/
2513	ret_val = e1000_k1_gig_workaround_hv(hw, link: true);
2514	if (ret_val)
2515	return ret_val;
2516
2517	/* Workaround for link disconnects on a busy hub in half duplex */
2518	ret_val = hw->phy.ops.acquire(hw);
2519	if (ret_val)
2520	return ret_val;
2521	ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, data: &phy_data);
2522	if (ret_val)
2523	goto release;
2524	ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, data: phy_data & 0x00FF);
2525	if (ret_val)
2526	goto release;
2527
2528	/* set MSE higher to enable link to stay up when noise is high */
2529	ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, data: 0x0034);
2530	release:
2531	hw->phy.ops.release(hw);
2532
2533	return ret_val;
2534	}
2535
2536	/**
2537	* e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2538	* @hw: pointer to the HW structure
2539	**/
2540	void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2541	{
2542	u32 mac_reg;
2543	u16 i, phy_reg = 0;
2544	s32 ret_val;
2545
2546	ret_val = hw->phy.ops.acquire(hw);
2547	if (ret_val)
2548	return;
2549	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, phy_reg: &phy_reg);
2550	if (ret_val)
2551	goto release;
2552
2553	/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2554	for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2555	mac_reg = er32(RAL(i));
2556	hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2557	(u16)(mac_reg & 0xFFFF));
2558	hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2559	(u16)((mac_reg >> 16) & 0xFFFF));
2560
2561	mac_reg = er32(RAH(i));
2562	hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2563	(u16)(mac_reg & 0xFFFF));
2564	hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2565	(u16)((mac_reg & E1000_RAH_AV)
2566	>> 16));
2567	}
2568
2569	e1000_disable_phy_wakeup_reg_access_bm(hw, phy_reg: &phy_reg);
2570
2571	release:
2572	hw->phy.ops.release(hw);
2573	}
2574
2575	/**
2576	* e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2577	* with 82579 PHY
2578	* @hw: pointer to the HW structure
2579	* @enable: flag to enable/disable workaround when enabling/disabling jumbos
2580	**/
2581	s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2582	{
2583	s32 ret_val = 0;
2584	u16 phy_reg, data;
2585	u32 mac_reg;
2586	u16 i;
2587
2588	if (hw->mac.type < e1000_pch2lan)
2589	return 0;
2590
2591	/* disable Rx path while enabling/disabling workaround */
2592	e1e_rphy(hw, PHY_REG(769, 20), data: &phy_reg);
2593	ret_val = e1e_wphy(hw, PHY_REG(769, 20), data: phy_reg | BIT(14));
2594	if (ret_val)
2595	return ret_val;
2596
2597	if (enable) {
2598	/* Write Rx addresses (rar_entry_count for RAL/H, and
2599	* SHRAL/H) and initial CRC values to the MAC
2600	*/
2601	for (i = 0; i < hw->mac.rar_entry_count; i++) {
2602	u8 mac_addr[ETH_ALEN] = { 0 };
2603	u32 addr_high, addr_low;
2604
2605	addr_high = er32(RAH(i));
2606	if (!(addr_high & E1000_RAH_AV))
2607	continue;
2608	addr_low = er32(RAL(i));
2609	mac_addr[0] = (addr_low & 0xFF);
2610	mac_addr[1] = ((addr_low >> 8) & 0xFF);
2611	mac_addr[2] = ((addr_low >> 16) & 0xFF);
2612	mac_addr[3] = ((addr_low >> 24) & 0xFF);
2613	mac_addr[4] = (addr_high & 0xFF);
2614	mac_addr[5] = ((addr_high >> 8) & 0xFF);
2615
2616	ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2617	}
2618
2619	/* Write Rx addresses to the PHY */
2620	e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2621
2622	/* Enable jumbo frame workaround in the MAC */
2623	mac_reg = er32(FFLT_DBG);
2624	mac_reg &= ~BIT(14);
2625	mac_reg |= (7 << 15);
2626	ew32(FFLT_DBG, mac_reg);
2627
2628	mac_reg = er32(RCTL);
2629	mac_reg |= E1000_RCTL_SECRC;
2630	ew32(RCTL, mac_reg);
2631
2632	ret_val = e1000e_read_kmrn_reg(hw,
2633	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2634	data: &data);
2635	if (ret_val)
2636	return ret_val;
2637	ret_val = e1000e_write_kmrn_reg(hw,
2638	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2639	data: data | BIT(0));
2640	if (ret_val)
2641	return ret_val;
2642	ret_val = e1000e_read_kmrn_reg(hw,
2643	E1000_KMRNCTRLSTA_HD_CTRL,
2644	data: &data);
2645	if (ret_val)
2646	return ret_val;
2647	data &= ~(0xF << 8);
2648	data |= (0xB << 8);
2649	ret_val = e1000e_write_kmrn_reg(hw,
2650	E1000_KMRNCTRLSTA_HD_CTRL,
2651	data);
2652	if (ret_val)
2653	return ret_val;
2654
2655	/* Enable jumbo frame workaround in the PHY */
2656	e1e_rphy(hw, PHY_REG(769, 23), data: &data);
2657	data &= ~(0x7F << 5);
2658	data |= (0x37 << 5);
2659	ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2660	if (ret_val)
2661	return ret_val;
2662	e1e_rphy(hw, PHY_REG(769, 16), data: &data);
2663	data &= ~BIT(13);
2664	ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2665	if (ret_val)
2666	return ret_val;
2667	e1e_rphy(hw, PHY_REG(776, 20), data: &data);
2668	data &= ~(0x3FF << 2);
2669	data |= (E1000_TX_PTR_GAP << 2);
2670	ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2671	if (ret_val)
2672	return ret_val;
2673	ret_val = e1e_wphy(hw, PHY_REG(776, 23), data: 0xF100);
2674	if (ret_val)
2675	return ret_val;
2676	e1e_rphy(hw, HV_PM_CTRL, data: &data);
2677	ret_val = e1e_wphy(hw, HV_PM_CTRL, data: data | BIT(10));
2678	if (ret_val)
2679	return ret_val;
2680	} else {
2681	/* Write MAC register values back to h/w defaults */
2682	mac_reg = er32(FFLT_DBG);
2683	mac_reg &= ~(0xF << 14);
2684	ew32(FFLT_DBG, mac_reg);
2685
2686	mac_reg = er32(RCTL);
2687	mac_reg &= ~E1000_RCTL_SECRC;
2688	ew32(RCTL, mac_reg);
2689
2690	ret_val = e1000e_read_kmrn_reg(hw,
2691	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2692	data: &data);
2693	if (ret_val)
2694	return ret_val;
2695	ret_val = e1000e_write_kmrn_reg(hw,
2696	E1000_KMRNCTRLSTA_CTRL_OFFSET,
2697	data: data & ~BIT(0));
2698	if (ret_val)
2699	return ret_val;
2700	ret_val = e1000e_read_kmrn_reg(hw,
2701	E1000_KMRNCTRLSTA_HD_CTRL,
2702	data: &data);
2703	if (ret_val)
2704	return ret_val;
2705	data &= ~(0xF << 8);
2706	data |= (0xB << 8);
2707	ret_val = e1000e_write_kmrn_reg(hw,
2708	E1000_KMRNCTRLSTA_HD_CTRL,
2709	data);
2710	if (ret_val)
2711	return ret_val;
2712
2713	/* Write PHY register values back to h/w defaults */
2714	e1e_rphy(hw, PHY_REG(769, 23), data: &data);
2715	data &= ~(0x7F << 5);
2716	ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2717	if (ret_val)
2718	return ret_val;
2719	e1e_rphy(hw, PHY_REG(769, 16), data: &data);
2720	data |= BIT(13);
2721	ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2722	if (ret_val)
2723	return ret_val;
2724	e1e_rphy(hw, PHY_REG(776, 20), data: &data);
2725	data &= ~(0x3FF << 2);
2726	data |= (0x8 << 2);
2727	ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2728	if (ret_val)
2729	return ret_val;
2730	ret_val = e1e_wphy(hw, PHY_REG(776, 23), data: 0x7E00);
2731	if (ret_val)
2732	return ret_val;
2733	e1e_rphy(hw, HV_PM_CTRL, data: &data);
2734	ret_val = e1e_wphy(hw, HV_PM_CTRL, data: data & ~BIT(10));
2735	if (ret_val)
2736	return ret_val;
2737	}
2738
2739	/* re-enable Rx path after enabling/disabling workaround */
2740	return e1e_wphy(hw, PHY_REG(769, 20), data: phy_reg & ~BIT(14));
2741	}
2742
2743	/**
2744	* e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2745	* @hw: pointer to the HW structure
2746	*
2747	* A series of PHY workarounds to be done after every PHY reset.
2748	**/
2749	static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2750	{
2751	s32 ret_val = 0;
2752
2753	if (hw->mac.type != e1000_pch2lan)
2754	return 0;
2755
2756	/* Set MDIO slow mode before any other MDIO access */
2757	ret_val = e1000_set_mdio_slow_mode_hv(hw);
2758	if (ret_val)
2759	return ret_val;
2760
2761	ret_val = hw->phy.ops.acquire(hw);
2762	if (ret_val)
2763	return ret_val;
2764	/* set MSE higher to enable link to stay up when noise is high */
2765	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, data: 0x0034);
2766	if (ret_val)
2767	goto release;
2768	/* drop link after 5 times MSE threshold was reached */
2769	ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, data: 0x0005);
2770	release:
2771	hw->phy.ops.release(hw);
2772
2773	return ret_val;
2774	}
2775
2776	/**
2777	* e1000_k1_workaround_lv - K1 Si workaround
2778	* @hw: pointer to the HW structure
2779	*
2780	* Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2781	* Disable K1 in 1000Mbps and 100Mbps
2782	**/
2783	static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2784	{
2785	s32 ret_val = 0;
2786	u16 status_reg = 0;
2787
2788	if (hw->mac.type != e1000_pch2lan)
2789	return 0;
2790
2791	/* Set K1 beacon duration based on 10Mbs speed */
2792	ret_val = e1e_rphy(hw, HV_M_STATUS, data: &status_reg);
2793	if (ret_val)
2794	return ret_val;
2795
2796	if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2797	== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2798	if (status_reg &
2799	(HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2800	u16 pm_phy_reg;
2801
2802	/* LV 1G/100 Packet drop issue wa */
2803	ret_val = e1e_rphy(hw, HV_PM_CTRL, data: &pm_phy_reg);
2804	if (ret_val)
2805	return ret_val;
2806	pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2807	ret_val = e1e_wphy(hw, HV_PM_CTRL, data: pm_phy_reg);
2808	if (ret_val)
2809	return ret_val;
2810	} else {
2811	u32 mac_reg;
2812
2813	mac_reg = er32(FEXTNVM4);
2814	mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2815	mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2816	ew32(FEXTNVM4, mac_reg);
2817	}
2818	}
2819
2820	return ret_val;
2821	}
2822
2823	/**
2824	* e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2825	* @hw: pointer to the HW structure
2826	* @gate: boolean set to true to gate, false to ungate
2827	*
2828	* Gate/ungate the automatic PHY configuration via hardware; perform
2829	* the configuration via software instead.
2830	**/
2831	static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2832	{
2833	u32 extcnf_ctrl;
2834
2835	if (hw->mac.type < e1000_pch2lan)
2836	return;
2837
2838	extcnf_ctrl = er32(EXTCNF_CTRL);
2839
2840	if (gate)
2841	extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2842	else
2843	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2844
2845	ew32(EXTCNF_CTRL, extcnf_ctrl);
2846	}
2847
2848	/**
2849	* e1000_lan_init_done_ich8lan - Check for PHY config completion
2850	* @hw: pointer to the HW structure
2851	*
2852	* Check the appropriate indication the MAC has finished configuring the
2853	* PHY after a software reset.
2854	**/
2855	static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2856	{
2857	u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2858
2859	/* Wait for basic configuration completes before proceeding */
2860	do {
2861	data = er32(STATUS);
2862	data &= E1000_STATUS_LAN_INIT_DONE;
2863	usleep_range(min: 100, max: 200);
2864	} while ((!data) && --loop);
2865
2866	/* If basic configuration is incomplete before the above loop
2867	* count reaches 0, loading the configuration from NVM will
2868	* leave the PHY in a bad state possibly resulting in no link.
2869	*/
2870	if (loop == 0)
2871	e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2872
2873	/* Clear the Init Done bit for the next init event */
2874	data = er32(STATUS);
2875	data &= ~E1000_STATUS_LAN_INIT_DONE;
2876	ew32(STATUS, data);
2877	}
2878
2879	/**
2880	* e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2881	* @hw: pointer to the HW structure
2882	**/
2883	static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2884	{
2885	s32 ret_val = 0;
2886	u16 reg;
2887
2888	if (hw->phy.ops.check_reset_block(hw))
2889	return 0;
2890
2891	/* Allow time for h/w to get to quiescent state after reset */
2892	usleep_range(min: 10000, max: 11000);
2893
2894	/* Perform any necessary post-reset workarounds */
2895	switch (hw->mac.type) {
2896	case e1000_pchlan:
2897	ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2898	if (ret_val)
2899	return ret_val;
2900	break;
2901	case e1000_pch2lan:
2902	ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2903	if (ret_val)
2904	return ret_val;
2905	break;
2906	default:
2907	break;
2908	}
2909
2910	/* Clear the host wakeup bit after lcd reset */
2911	if (hw->mac.type >= e1000_pchlan) {
2912	e1e_rphy(hw, BM_PORT_GEN_CFG, data: &reg);
2913	reg &= ~BM_WUC_HOST_WU_BIT;
2914	e1e_wphy(hw, BM_PORT_GEN_CFG, data: reg);
2915	}
2916
2917	/* Configure the LCD with the extended configuration region in NVM */
2918	ret_val = e1000_sw_lcd_config_ich8lan(hw);
2919	if (ret_val)
2920	return ret_val;
2921
2922	/* Configure the LCD with the OEM bits in NVM */
2923	ret_val = e1000_oem_bits_config_ich8lan(hw, d0_state: true);
2924
2925	if (hw->mac.type == e1000_pch2lan) {
2926	/* Ungate automatic PHY configuration on non-managed 82579 */
2927	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2928	usleep_range(min: 10000, max: 11000);
2929	e1000_gate_hw_phy_config_ich8lan(hw, gate: false);
2930	}
2931
2932	/* Set EEE LPI Update Timer to 200usec */
2933	ret_val = hw->phy.ops.acquire(hw);
2934	if (ret_val)
2935	return ret_val;
2936	ret_val = e1000_write_emi_reg_locked(hw,
2937	I82579_LPI_UPDATE_TIMER,
2938	data: 0x1387);
2939	hw->phy.ops.release(hw);
2940	}
2941
2942	return ret_val;
2943	}
2944
2945	/**
2946	* e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2947	* @hw: pointer to the HW structure
2948	*
2949	* Resets the PHY
2950	* This is a function pointer entry point called by drivers
2951	* or other shared routines.
2952	**/
2953	static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2954	{
2955	s32 ret_val = 0;
2956
2957	/* Gate automatic PHY configuration by hardware on non-managed 82579 */
2958	if ((hw->mac.type == e1000_pch2lan) &&
2959	!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2960	e1000_gate_hw_phy_config_ich8lan(hw, gate: true);
2961
2962	ret_val = e1000e_phy_hw_reset_generic(hw);
2963	if (ret_val)
2964	return ret_val;
2965
2966	return e1000_post_phy_reset_ich8lan(hw);
2967	}
2968
2969	/**
2970	* e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2971	* @hw: pointer to the HW structure
2972	* @active: true to enable LPLU, false to disable
2973	*
2974	* Sets the LPLU state according to the active flag. For PCH, if OEM write
2975	* bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2976	* the phy speed. This function will manually set the LPLU bit and restart
2977	* auto-neg as hw would do. D3 and D0 LPLU will call the same function
2978	* since it configures the same bit.
2979	**/
2980	static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2981	{
2982	s32 ret_val;
2983	u16 oem_reg;
2984
2985	ret_val = e1e_rphy(hw, HV_OEM_BITS, data: &oem_reg);
2986	if (ret_val)
2987	return ret_val;
2988
2989	if (active)
2990	oem_reg |= HV_OEM_BITS_LPLU;
2991	else
2992	oem_reg &= ~HV_OEM_BITS_LPLU;
2993
2994	if (!hw->phy.ops.check_reset_block(hw))
2995	oem_reg |= HV_OEM_BITS_RESTART_AN;
2996
2997	return e1e_wphy(hw, HV_OEM_BITS, data: oem_reg);
2998	}
2999
3000	/**
3001	* e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3002	* @hw: pointer to the HW structure
3003	* @active: true to enable LPLU, false to disable
3004	*
3005	* Sets the LPLU D0 state according to the active flag. When
3006	* activating LPLU this function also disables smart speed
3007	* and vice versa. LPLU will not be activated unless the
3008	* device autonegotiation advertisement meets standards of
3009	* either 10 or 10/100 or 10/100/1000 at all duplexes.
3010	* This is a function pointer entry point only called by
3011	* PHY setup routines.
3012	**/
3013	static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3014	{
3015	struct e1000_phy_info *phy = &hw->phy;
3016	u32 phy_ctrl;
3017	s32 ret_val = 0;
3018	u16 data;
3019
3020	if (phy->type == e1000_phy_ife)
3021	return 0;
3022
3023	phy_ctrl = er32(PHY_CTRL);
3024
3025	if (active) {
3026	phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3027	ew32(PHY_CTRL, phy_ctrl);
3028
3029	if (phy->type != e1000_phy_igp_3)
3030	return 0;
3031
3032	/* Call gig speed drop workaround on LPLU before accessing
3033	* any PHY registers
3034	*/
3035	if (hw->mac.type == e1000_ich8lan)
3036	e1000e_gig_downshift_workaround_ich8lan(hw);
3037
3038	/* When LPLU is enabled, we should disable SmartSpeed */
3039	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, data: &data);
3040	if (ret_val)
3041	return ret_val;
3042	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3043	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3044	if (ret_val)
3045	return ret_val;
3046	} else {
3047	phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3048	ew32(PHY_CTRL, phy_ctrl);
3049
3050	if (phy->type != e1000_phy_igp_3)
3051	return 0;
3052
3053	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3054	* during Dx states where the power conservation is most
3055	* important. During driver activity we should enable
3056	* SmartSpeed, so performance is maintained.
3057	*/
3058	if (phy->smart_speed == e1000_smart_speed_on) {
3059	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3060	data: &data);
3061	if (ret_val)
3062	return ret_val;
3063
3064	data |= IGP01E1000_PSCFR_SMART_SPEED;
3065	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3066	data);
3067	if (ret_val)
3068	return ret_val;
3069	} else if (phy->smart_speed == e1000_smart_speed_off) {
3070	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3071	data: &data);
3072	if (ret_val)
3073	return ret_val;
3074
3075	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3076	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3077	data);
3078	if (ret_val)
3079	return ret_val;
3080	}
3081	}
3082
3083	return 0;
3084	}
3085
3086	/**
3087	* e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3088	* @hw: pointer to the HW structure
3089	* @active: true to enable LPLU, false to disable
3090	*
3091	* Sets the LPLU D3 state according to the active flag. When
3092	* activating LPLU this function also disables smart speed
3093	* and vice versa. LPLU will not be activated unless the
3094	* device autonegotiation advertisement meets standards of
3095	* either 10 or 10/100 or 10/100/1000 at all duplexes.
3096	* This is a function pointer entry point only called by
3097	* PHY setup routines.
3098	**/
3099	static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3100	{
3101	struct e1000_phy_info *phy = &hw->phy;
3102	u32 phy_ctrl;
3103	s32 ret_val = 0;
3104	u16 data;
3105
3106	phy_ctrl = er32(PHY_CTRL);
3107
3108	if (!active) {
3109	phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3110	ew32(PHY_CTRL, phy_ctrl);
3111
3112	if (phy->type != e1000_phy_igp_3)
3113	return 0;
3114
3115	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3116	* during Dx states where the power conservation is most
3117	* important. During driver activity we should enable
3118	* SmartSpeed, so performance is maintained.
3119	*/
3120	if (phy->smart_speed == e1000_smart_speed_on) {
3121	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3122	data: &data);
3123	if (ret_val)
3124	return ret_val;
3125
3126	data |= IGP01E1000_PSCFR_SMART_SPEED;
3127	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3128	data);
3129	if (ret_val)
3130	return ret_val;
3131	} else if (phy->smart_speed == e1000_smart_speed_off) {
3132	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3133	data: &data);
3134	if (ret_val)
3135	return ret_val;
3136
3137	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3138	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3139	data);
3140	if (ret_val)
3141	return ret_val;
3142	}
3143	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3144	(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3145	(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3146	phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3147	ew32(PHY_CTRL, phy_ctrl);
3148
3149	if (phy->type != e1000_phy_igp_3)
3150	return 0;
3151
3152	/* Call gig speed drop workaround on LPLU before accessing
3153	* any PHY registers
3154	*/
3155	if (hw->mac.type == e1000_ich8lan)
3156	e1000e_gig_downshift_workaround_ich8lan(hw);
3157
3158	/* When LPLU is enabled, we should disable SmartSpeed */
3159	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, data: &data);
3160	if (ret_val)
3161	return ret_val;
3162
3163	data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3164	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3165	}
3166
3167	return ret_val;
3168	}
3169
3170	/**
3171	* e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3172	* @hw: pointer to the HW structure
3173	* @bank: pointer to the variable that returns the active bank
3174	*
3175	* Reads signature byte from the NVM using the flash access registers.
3176	* Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3177	**/
3178	static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3179	{
3180	u32 eecd;
3181	struct e1000_nvm_info *nvm = &hw->nvm;
3182	u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3183	u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3184	u32 nvm_dword = 0;
3185	u8 sig_byte = 0;
3186	s32 ret_val;
3187
3188	switch (hw->mac.type) {
3189	case e1000_pch_spt:
3190	case e1000_pch_cnp:
3191	case e1000_pch_tgp:
3192	case e1000_pch_adp:
3193	case e1000_pch_mtp:
3194	case e1000_pch_lnp:
3195	case e1000_pch_ptp:
3196	case e1000_pch_nvp:
3197	bank1_offset = nvm->flash_bank_size;
3198	act_offset = E1000_ICH_NVM_SIG_WORD;
3199
3200	/* set bank to 0 in case flash read fails */
3201	*bank = 0;
3202
3203	/* Check bank 0 */
3204	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset,
3205	data: &nvm_dword);
3206	if (ret_val)
3207	return ret_val;
3208	sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3209	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3210	E1000_ICH_NVM_SIG_VALUE) {
3211	*bank = 0;
3212	return 0;
3213	}
3214
3215	/* Check bank 1 */
3216	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset +
3217	bank1_offset,
3218	data: &nvm_dword);
3219	if (ret_val)
3220	return ret_val;
3221	sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3222	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3223	E1000_ICH_NVM_SIG_VALUE) {
3224	*bank = 1;
3225	return 0;
3226	}
3227
3228	e_dbg("ERROR: No valid NVM bank present\n");
3229	return -E1000_ERR_NVM;
3230	case e1000_ich8lan:
3231	case e1000_ich9lan:
3232	eecd = er32(EECD);
3233	if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3234	E1000_EECD_SEC1VAL_VALID_MASK) {
3235	if (eecd & E1000_EECD_SEC1VAL)
3236	*bank = 1;
3237	else
3238	*bank = 0;
3239
3240	return 0;
3241	}
3242	e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3243	fallthrough;
3244	default:
3245	/* set bank to 0 in case flash read fails */
3246	*bank = 0;
3247
3248	/* Check bank 0 */
3249	ret_val = e1000_read_flash_byte_ich8lan(hw, offset: act_offset,
3250	data: &sig_byte);
3251	if (ret_val)
3252	return ret_val;
3253	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3254	E1000_ICH_NVM_SIG_VALUE) {
3255	*bank = 0;
3256	return 0;
3257	}
3258
3259	/* Check bank 1 */
3260	ret_val = e1000_read_flash_byte_ich8lan(hw, offset: act_offset +
3261	bank1_offset,
3262	data: &sig_byte);
3263	if (ret_val)
3264	return ret_val;
3265	if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3266	E1000_ICH_NVM_SIG_VALUE) {
3267	*bank = 1;
3268	return 0;
3269	}
3270
3271	e_dbg("ERROR: No valid NVM bank present\n");
3272	return -E1000_ERR_NVM;
3273	}
3274	}
3275
3276	/**
3277	* e1000_read_nvm_spt - NVM access for SPT
3278	* @hw: pointer to the HW structure
3279	* @offset: The offset (in bytes) of the word(s) to read.
3280	* @words: Size of data to read in words.
3281	* @data: pointer to the word(s) to read at offset.
3282	*
3283	* Reads a word(s) from the NVM
3284	**/
3285	static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3286	u16 *data)
3287	{
3288	struct e1000_nvm_info *nvm = &hw->nvm;
3289	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3290	u32 act_offset;
3291	s32 ret_val = 0;
3292	u32 bank = 0;
3293	u32 dword = 0;
3294	u16 offset_to_read;
3295	u16 i;
3296
3297	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3298	(words == 0)) {
3299	e_dbg("nvm parameter(s) out of bounds\n");
3300	ret_val = -E1000_ERR_NVM;
3301	goto out;
3302	}
3303
3304	nvm->ops.acquire(hw);
3305
3306	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3307	if (ret_val) {
3308	e_dbg("Could not detect valid bank, assuming bank 0\n");
3309	bank = 0;
3310	}
3311
3312	act_offset = (bank) ? nvm->flash_bank_size : 0;
3313	act_offset += offset;
3314
3315	ret_val = 0;
3316
3317	for (i = 0; i < words; i += 2) {
3318	if (words - i == 1) {
3319	if (dev_spec->shadow_ram[offset + i].modified) {
3320	data[i] =
3321	dev_spec->shadow_ram[offset + i].value;
3322	} else {
3323	offset_to_read = act_offset + i -
3324	((act_offset + i) % 2);
3325	ret_val =
3326	e1000_read_flash_dword_ich8lan(hw,
3327	offset: offset_to_read,
3328	data: &dword);
3329	if (ret_val)
3330	break;
3331	if ((act_offset + i) % 2 == 0)
3332	data[i] = (u16)(dword & 0xFFFF);
3333	else
3334	data[i] = (u16)((dword >> 16) & 0xFFFF);
3335	}
3336	} else {
3337	offset_to_read = act_offset + i;
3338	if (!(dev_spec->shadow_ram[offset + i].modified) ||
3339	!(dev_spec->shadow_ram[offset + i + 1].modified)) {
3340	ret_val =
3341	e1000_read_flash_dword_ich8lan(hw,
3342	offset: offset_to_read,
3343	data: &dword);
3344	if (ret_val)
3345	break;
3346	}
3347	if (dev_spec->shadow_ram[offset + i].modified)
3348	data[i] =
3349	dev_spec->shadow_ram[offset + i].value;
3350	else
3351	data[i] = (u16)(dword & 0xFFFF);
3352	if (dev_spec->shadow_ram[offset + i].modified)
3353	data[i + 1] =
3354	dev_spec->shadow_ram[offset + i + 1].value;
3355	else
3356	data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3357	}
3358	}
3359
3360	nvm->ops.release(hw);
3361
3362	out:
3363	if (ret_val)
3364	e_dbg("NVM read error: %d\n", ret_val);
3365
3366	return ret_val;
3367	}
3368
3369	/**
3370	* e1000_read_nvm_ich8lan - Read word(s) from the NVM
3371	* @hw: pointer to the HW structure
3372	* @offset: The offset (in bytes) of the word(s) to read.
3373	* @words: Size of data to read in words
3374	* @data: Pointer to the word(s) to read at offset.
3375	*
3376	* Reads a word(s) from the NVM using the flash access registers.
3377	**/
3378	static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3379	u16 *data)
3380	{
3381	struct e1000_nvm_info *nvm = &hw->nvm;
3382	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3383	u32 act_offset;
3384	s32 ret_val = 0;
3385	u32 bank = 0;
3386	u16 i, word;
3387
3388	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3389	(words == 0)) {
3390	e_dbg("nvm parameter(s) out of bounds\n");
3391	ret_val = -E1000_ERR_NVM;
3392	goto out;
3393	}
3394
3395	nvm->ops.acquire(hw);
3396
3397	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3398	if (ret_val) {
3399	e_dbg("Could not detect valid bank, assuming bank 0\n");
3400	bank = 0;
3401	}
3402
3403	act_offset = (bank) ? nvm->flash_bank_size : 0;
3404	act_offset += offset;
3405
3406	ret_val = 0;
3407	for (i = 0; i < words; i++) {
3408	if (dev_spec->shadow_ram[offset + i].modified) {
3409	data[i] = dev_spec->shadow_ram[offset + i].value;
3410	} else {
3411	ret_val = e1000_read_flash_word_ich8lan(hw,
3412	offset: act_offset + i,
3413	data: &word);
3414	if (ret_val)
3415	break;
3416	data[i] = word;
3417	}
3418	}
3419
3420	nvm->ops.release(hw);
3421
3422	out:
3423	if (ret_val)
3424	e_dbg("NVM read error: %d\n", ret_val);
3425
3426	return ret_val;
3427	}
3428
3429	/**
3430	* e1000_flash_cycle_init_ich8lan - Initialize flash
3431	* @hw: pointer to the HW structure
3432	*
3433	* This function does initial flash setup so that a new read/write/erase cycle
3434	* can be started.
3435	**/
3436	static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3437	{
3438	union ich8_hws_flash_status hsfsts;
3439	s32 ret_val = -E1000_ERR_NVM;
3440
3441	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3442
3443	/* Check if the flash descriptor is valid */
3444	if (!hsfsts.hsf_status.fldesvalid) {
3445	e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3446	return -E1000_ERR_NVM;
3447	}
3448
3449	/* Clear FCERR and DAEL in hw status by writing 1 */
3450	hsfsts.hsf_status.flcerr = 1;
3451	hsfsts.hsf_status.dael = 1;
3452	if (hw->mac.type >= e1000_pch_spt)
3453	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3454	else
3455	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3456
3457	/* Either we should have a hardware SPI cycle in progress
3458	* bit to check against, in order to start a new cycle or
3459	* FDONE bit should be changed in the hardware so that it
3460	* is 1 after hardware reset, which can then be used as an
3461	* indication whether a cycle is in progress or has been
3462	* completed.
3463	*/
3464
3465	if (!hsfsts.hsf_status.flcinprog) {
3466	/* There is no cycle running at present,
3467	* so we can start a cycle.
3468	* Begin by setting Flash Cycle Done.
3469	*/
3470	hsfsts.hsf_status.flcdone = 1;
3471	if (hw->mac.type >= e1000_pch_spt)
3472	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3473	else
3474	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3475	ret_val = 0;
3476	} else {
3477	s32 i;
3478
3479	/* Otherwise poll for sometime so the current
3480	* cycle has a chance to end before giving up.
3481	*/
3482	for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3483	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3484	if (!hsfsts.hsf_status.flcinprog) {
3485	ret_val = 0;
3486	break;
3487	}
3488	udelay(1);
3489	}
3490	if (!ret_val) {
3491	/* Successful in waiting for previous cycle to timeout,
3492	* now set the Flash Cycle Done.
3493	*/
3494	hsfsts.hsf_status.flcdone = 1;
3495	if (hw->mac.type >= e1000_pch_spt)
3496	ew32flash(ICH_FLASH_HSFSTS,
3497	hsfsts.regval & 0xFFFF);
3498	else
3499	ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3500	} else {
3501	e_dbg("Flash controller busy, cannot get access\n");
3502	}
3503	}
3504
3505	return ret_val;
3506	}
3507
3508	/**
3509	* e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3510	* @hw: pointer to the HW structure
3511	* @timeout: maximum time to wait for completion
3512	*
3513	* This function starts a flash cycle and waits for its completion.
3514	**/
3515	static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3516	{
3517	union ich8_hws_flash_ctrl hsflctl;
3518	union ich8_hws_flash_status hsfsts;
3519	u32 i = 0;
3520
3521	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3522	if (hw->mac.type >= e1000_pch_spt)
3523	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3524	else
3525	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3526	hsflctl.hsf_ctrl.flcgo = 1;
3527
3528	if (hw->mac.type >= e1000_pch_spt)
3529	ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3530	else
3531	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3532
3533	/* wait till FDONE bit is set to 1 */
3534	do {
3535	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3536	if (hsfsts.hsf_status.flcdone)
3537	break;
3538	udelay(1);
3539	} while (i++ < timeout);
3540
3541	if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3542	return 0;
3543
3544	return -E1000_ERR_NVM;
3545	}
3546
3547	/**
3548	* e1000_read_flash_dword_ich8lan - Read dword from flash
3549	* @hw: pointer to the HW structure
3550	* @offset: offset to data location
3551	* @data: pointer to the location for storing the data
3552	*
3553	* Reads the flash dword at offset into data. Offset is converted
3554	* to bytes before read.
3555	**/
3556	static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3557	u32 *data)
3558	{
3559	/* Must convert word offset into bytes. */
3560	offset <<= 1;
3561	return e1000_read_flash_data32_ich8lan(hw, offset, data);
3562	}
3563
3564	/**
3565	* e1000_read_flash_word_ich8lan - Read word from flash
3566	* @hw: pointer to the HW structure
3567	* @offset: offset to data location
3568	* @data: pointer to the location for storing the data
3569	*
3570	* Reads the flash word at offset into data. Offset is converted
3571	* to bytes before read.
3572	**/
3573	static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3574	u16 *data)
3575	{
3576	/* Must convert offset into bytes. */
3577	offset <<= 1;
3578
3579	return e1000_read_flash_data_ich8lan(hw, offset, size: 2, data);
3580	}
3581
3582	/**
3583	* e1000_read_flash_byte_ich8lan - Read byte from flash
3584	* @hw: pointer to the HW structure
3585	* @offset: The offset of the byte to read.
3586	* @data: Pointer to a byte to store the value read.
3587	*
3588	* Reads a single byte from the NVM using the flash access registers.
3589	**/
3590	static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3591	u8 *data)
3592	{
3593	s32 ret_val;
3594	u16 word = 0;
3595
3596	/* In SPT, only 32 bits access is supported,
3597	* so this function should not be called.
3598	*/
3599	if (hw->mac.type >= e1000_pch_spt)
3600	return -E1000_ERR_NVM;
3601	else
3602	ret_val = e1000_read_flash_data_ich8lan(hw, offset, size: 1, data: &word);
3603
3604	if (ret_val)
3605	return ret_val;
3606
3607	*data = (u8)word;
3608
3609	return 0;
3610	}
3611
3612	/**
3613	* e1000_read_flash_data_ich8lan - Read byte or word from NVM
3614	* @hw: pointer to the HW structure
3615	* @offset: The offset (in bytes) of the byte or word to read.
3616	* @size: Size of data to read, 1=byte 2=word
3617	* @data: Pointer to the word to store the value read.
3618	*
3619	* Reads a byte or word from the NVM using the flash access registers.
3620	**/
3621	static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3622	u8 size, u16 *data)
3623	{
3624	union ich8_hws_flash_status hsfsts;
3625	union ich8_hws_flash_ctrl hsflctl;
3626	u32 flash_linear_addr;
3627	u32 flash_data = 0;
3628	s32 ret_val = -E1000_ERR_NVM;
3629	u8 count = 0;
3630
3631	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3632	return -E1000_ERR_NVM;
3633
3634	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3635	hw->nvm.flash_base_addr);
3636
3637	do {
3638	udelay(1);
3639	/* Steps */
3640	ret_val = e1000_flash_cycle_init_ich8lan(hw);
3641	if (ret_val)
3642	break;
3643
3644	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3645	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3646	hsflctl.hsf_ctrl.fldbcount = size - 1;
3647	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3648	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3649
3650	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3651
3652	ret_val =
3653	e1000_flash_cycle_ich8lan(hw,
3654	ICH_FLASH_READ_COMMAND_TIMEOUT);
3655
3656	/* Check if FCERR is set to 1, if set to 1, clear it
3657	* and try the whole sequence a few more times, else
3658	* read in (shift in) the Flash Data0, the order is
3659	* least significant byte first msb to lsb
3660	*/
3661	if (!ret_val) {
3662	flash_data = er32flash(ICH_FLASH_FDATA0);
3663	if (size == 1)
3664	*data = (u8)(flash_data & 0x000000FF);
3665	else if (size == 2)
3666	*data = (u16)(flash_data & 0x0000FFFF);
3667	break;
3668	} else {
3669	/* If we've gotten here, then things are probably
3670	* completely hosed, but if the error condition is
3671	* detected, it won't hurt to give it another try...
3672	* ICH_FLASH_CYCLE_REPEAT_COUNT times.
3673	*/
3674	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3675	if (hsfsts.hsf_status.flcerr) {
3676	/* Repeat for some time before giving up. */
3677	continue;
3678	} else if (!hsfsts.hsf_status.flcdone) {
3679	e_dbg("Timeout error - flash cycle did not complete.\n");
3680	break;
3681	}
3682	}
3683	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3684
3685	return ret_val;
3686	}
3687
3688	/**
3689	* e1000_read_flash_data32_ich8lan - Read dword from NVM
3690	* @hw: pointer to the HW structure
3691	* @offset: The offset (in bytes) of the dword to read.
3692	* @data: Pointer to the dword to store the value read.
3693	*
3694	* Reads a byte or word from the NVM using the flash access registers.
3695	**/
3696
3697	static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3698	u32 *data)
3699	{
3700	union ich8_hws_flash_status hsfsts;
3701	union ich8_hws_flash_ctrl hsflctl;
3702	u32 flash_linear_addr;
3703	s32 ret_val = -E1000_ERR_NVM;
3704	u8 count = 0;
3705
3706	if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3707	return -E1000_ERR_NVM;
3708	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3709	hw->nvm.flash_base_addr);
3710
3711	do {
3712	udelay(1);
3713	/* Steps */
3714	ret_val = e1000_flash_cycle_init_ich8lan(hw);
3715	if (ret_val)
3716	break;
3717	/* In SPT, This register is in Lan memory space, not flash.
3718	* Therefore, only 32 bit access is supported
3719	*/
3720	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3721
3722	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3723	hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3724	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3725	/* In SPT, This register is in Lan memory space, not flash.
3726	* Therefore, only 32 bit access is supported
3727	*/
3728	ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3729	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3730
3731	ret_val =
3732	e1000_flash_cycle_ich8lan(hw,
3733	ICH_FLASH_READ_COMMAND_TIMEOUT);
3734
3735	/* Check if FCERR is set to 1, if set to 1, clear it
3736	* and try the whole sequence a few more times, else
3737	* read in (shift in) the Flash Data0, the order is
3738	* least significant byte first msb to lsb
3739	*/
3740	if (!ret_val) {
3741	*data = er32flash(ICH_FLASH_FDATA0);
3742	break;
3743	} else {
3744	/* If we've gotten here, then things are probably
3745	* completely hosed, but if the error condition is
3746	* detected, it won't hurt to give it another try...
3747	* ICH_FLASH_CYCLE_REPEAT_COUNT times.
3748	*/
3749	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3750	if (hsfsts.hsf_status.flcerr) {
3751	/* Repeat for some time before giving up. */
3752	continue;
3753	} else if (!hsfsts.hsf_status.flcdone) {
3754	e_dbg("Timeout error - flash cycle did not complete.\n");
3755	break;
3756	}
3757	}
3758	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3759
3760	return ret_val;
3761	}
3762
3763	/**
3764	* e1000_write_nvm_ich8lan - Write word(s) to the NVM
3765	* @hw: pointer to the HW structure
3766	* @offset: The offset (in bytes) of the word(s) to write.
3767	* @words: Size of data to write in words
3768	* @data: Pointer to the word(s) to write at offset.
3769	*
3770	* Writes a byte or word to the NVM using the flash access registers.
3771	**/
3772	static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3773	u16 *data)
3774	{
3775	struct e1000_nvm_info *nvm = &hw->nvm;
3776	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3777	u16 i;
3778
3779	if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3780	(words == 0)) {
3781	e_dbg("nvm parameter(s) out of bounds\n");
3782	return -E1000_ERR_NVM;
3783	}
3784
3785	nvm->ops.acquire(hw);
3786
3787	for (i = 0; i < words; i++) {
3788	dev_spec->shadow_ram[offset + i].modified = true;
3789	dev_spec->shadow_ram[offset + i].value = data[i];
3790	}
3791
3792	nvm->ops.release(hw);
3793
3794	return 0;
3795	}
3796
3797	/**
3798	* e1000_update_nvm_checksum_spt - Update the checksum for NVM
3799	* @hw: pointer to the HW structure
3800	*
3801	* The NVM checksum is updated by calling the generic update_nvm_checksum,
3802	* which writes the checksum to the shadow ram. The changes in the shadow
3803	* ram are then committed to the EEPROM by processing each bank at a time
3804	* checking for the modified bit and writing only the pending changes.
3805	* After a successful commit, the shadow ram is cleared and is ready for
3806	* future writes.
3807	**/
3808	static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3809	{
3810	struct e1000_nvm_info *nvm = &hw->nvm;
3811	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3812	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3813	s32 ret_val;
3814	u32 dword = 0;
3815
3816	ret_val = e1000e_update_nvm_checksum_generic(hw);
3817	if (ret_val)
3818	goto out;
3819
3820	if (nvm->type != e1000_nvm_flash_sw)
3821	goto out;
3822
3823	nvm->ops.acquire(hw);
3824
3825	/* We're writing to the opposite bank so if we're on bank 1,
3826	* write to bank 0 etc. We also need to erase the segment that
3827	* is going to be written
3828	*/
3829	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3830	if (ret_val) {
3831	e_dbg("Could not detect valid bank, assuming bank 0\n");
3832	bank = 0;
3833	}
3834
3835	if (bank == 0) {
3836	new_bank_offset = nvm->flash_bank_size;
3837	old_bank_offset = 0;
3838	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 1);
3839	if (ret_val)
3840	goto release;
3841	} else {
3842	old_bank_offset = nvm->flash_bank_size;
3843	new_bank_offset = 0;
3844	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 0);
3845	if (ret_val)
3846	goto release;
3847	}
3848	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3849	/* Determine whether to write the value stored
3850	* in the other NVM bank or a modified value stored
3851	* in the shadow RAM
3852	*/
3853	ret_val = e1000_read_flash_dword_ich8lan(hw,
3854	offset: i + old_bank_offset,
3855	data: &dword);
3856
3857	if (dev_spec->shadow_ram[i].modified) {
3858	dword &= 0xffff0000;
3859	dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3860	}
3861	if (dev_spec->shadow_ram[i + 1].modified) {
3862	dword &= 0x0000ffff;
3863	dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3864	<< 16);
3865	}
3866	if (ret_val)
3867	break;
3868
3869	/* If the word is 0x13, then make sure the signature bits
3870	* (15:14) are 11b until the commit has completed.
3871	* This will allow us to write 10b which indicates the
3872	* signature is valid. We want to do this after the write
3873	* has completed so that we don't mark the segment valid
3874	* while the write is still in progress
3875	*/
3876	if (i == E1000_ICH_NVM_SIG_WORD - 1)
3877	dword |= E1000_ICH_NVM_SIG_MASK << 16;
3878
3879	/* Convert offset to bytes. */
3880	act_offset = (i + new_bank_offset) << 1;
3881
3882	usleep_range(min: 100, max: 200);
3883
3884	/* Write the data to the new bank. Offset in words */
3885	act_offset = i + new_bank_offset;
3886	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, offset: act_offset,
3887	dword);
3888	if (ret_val)
3889	break;
3890	}
3891
3892	/* Don't bother writing the segment valid bits if sector
3893	* programming failed.
3894	*/
3895	if (ret_val) {
3896	/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3897	e_dbg("Flash commit failed.\n");
3898	goto release;
3899	}
3900
3901	/* Finally validate the new segment by setting bit 15:14
3902	* to 10b in word 0x13 , this can be done without an
3903	* erase as well since these bits are 11 to start with
3904	* and we need to change bit 14 to 0b
3905	*/
3906	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3907
3908	/*offset in words but we read dword */
3909	--act_offset;
3910	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset, data: &dword);
3911
3912	if (ret_val)
3913	goto release;
3914
3915	dword &= 0xBFFFFFFF;
3916	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, offset: act_offset, dword);
3917
3918	if (ret_val)
3919	goto release;
3920
3921	/* offset in words but we read dword */
3922	act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3923	ret_val = e1000_read_flash_dword_ich8lan(hw, offset: act_offset, data: &dword);
3924
3925	if (ret_val)
3926	goto release;
3927
3928	dword &= 0x00FFFFFF;
3929	ret_val = e1000_retry_write_flash_dword_ich8lan(hw, offset: act_offset, dword);
3930
3931	if (ret_val)
3932	goto release;
3933
3934	/* Great! Everything worked, we can now clear the cached entries. */
3935	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3936	dev_spec->shadow_ram[i].modified = false;
3937	dev_spec->shadow_ram[i].value = 0xFFFF;
3938	}
3939
3940	release:
3941	nvm->ops.release(hw);
3942
3943	/* Reload the EEPROM, or else modifications will not appear
3944	* until after the next adapter reset.
3945	*/
3946	if (!ret_val) {
3947	nvm->ops.reload(hw);
3948	usleep_range(min: 10000, max: 11000);
3949	}
3950
3951	out:
3952	if (ret_val)
3953	e_dbg("NVM update error: %d\n", ret_val);
3954
3955	return ret_val;
3956	}
3957
3958	/**
3959	* e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3960	* @hw: pointer to the HW structure
3961	*
3962	* The NVM checksum is updated by calling the generic update_nvm_checksum,
3963	* which writes the checksum to the shadow ram. The changes in the shadow
3964	* ram are then committed to the EEPROM by processing each bank at a time
3965	* checking for the modified bit and writing only the pending changes.
3966	* After a successful commit, the shadow ram is cleared and is ready for
3967	* future writes.
3968	**/
3969	static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3970	{
3971	struct e1000_nvm_info *nvm = &hw->nvm;
3972	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3973	u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3974	s32 ret_val;
3975	u16 data = 0;
3976
3977	ret_val = e1000e_update_nvm_checksum_generic(hw);
3978	if (ret_val)
3979	goto out;
3980
3981	if (nvm->type != e1000_nvm_flash_sw)
3982	goto out;
3983
3984	nvm->ops.acquire(hw);
3985
3986	/* We're writing to the opposite bank so if we're on bank 1,
3987	* write to bank 0 etc. We also need to erase the segment that
3988	* is going to be written
3989	*/
3990	ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank);
3991	if (ret_val) {
3992	e_dbg("Could not detect valid bank, assuming bank 0\n");
3993	bank = 0;
3994	}
3995
3996	if (bank == 0) {
3997	new_bank_offset = nvm->flash_bank_size;
3998	old_bank_offset = 0;
3999	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 1);
4000	if (ret_val)
4001	goto release;
4002	} else {
4003	old_bank_offset = nvm->flash_bank_size;
4004	new_bank_offset = 0;
4005	ret_val = e1000_erase_flash_bank_ich8lan(hw, bank: 0);
4006	if (ret_val)
4007	goto release;
4008	}
4009	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4010	if (dev_spec->shadow_ram[i].modified) {
4011	data = dev_spec->shadow_ram[i].value;
4012	} else {
4013	ret_val = e1000_read_flash_word_ich8lan(hw, offset: i +
4014	old_bank_offset,
4015	data: &data);
4016	if (ret_val)
4017	break;
4018	}
4019
4020	/* If the word is 0x13, then make sure the signature bits
4021	* (15:14) are 11b until the commit has completed.
4022	* This will allow us to write 10b which indicates the
4023	* signature is valid. We want to do this after the write
4024	* has completed so that we don't mark the segment valid
4025	* while the write is still in progress
4026	*/
4027	if (i == E1000_ICH_NVM_SIG_WORD)
4028	data |= E1000_ICH_NVM_SIG_MASK;
4029
4030	/* Convert offset to bytes. */
4031	act_offset = (i + new_bank_offset) << 1;
4032
4033	usleep_range(min: 100, max: 200);
4034	/* Write the bytes to the new bank. */
4035	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4036	offset: act_offset,
4037	byte: (u8)data);
4038	if (ret_val)
4039	break;
4040
4041	usleep_range(min: 100, max: 200);
4042	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4043	offset: act_offset + 1,
4044	byte: (u8)(data >> 8));
4045	if (ret_val)
4046	break;
4047	}
4048
4049	/* Don't bother writing the segment valid bits if sector
4050	* programming failed.
4051	*/
4052	if (ret_val) {
4053	/* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4054	e_dbg("Flash commit failed.\n");
4055	goto release;
4056	}
4057
4058	/* Finally validate the new segment by setting bit 15:14
4059	* to 10b in word 0x13 , this can be done without an
4060	* erase as well since these bits are 11 to start with
4061	* and we need to change bit 14 to 0b
4062	*/
4063	act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4064	ret_val = e1000_read_flash_word_ich8lan(hw, offset: act_offset, data: &data);
4065	if (ret_val)
4066	goto release;
4067
4068	data &= 0xBFFF;
4069	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4070	offset: act_offset * 2 + 1,
4071	byte: (u8)(data >> 8));
4072	if (ret_val)
4073	goto release;
4074
4075	/* And invalidate the previously valid segment by setting
4076	* its signature word (0x13) high_byte to 0b. This can be
4077	* done without an erase because flash erase sets all bits
4078	* to 1's. We can write 1's to 0's without an erase
4079	*/
4080	act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4081	ret_val = e1000_retry_write_flash_byte_ich8lan(hw, offset: act_offset, byte: 0);
4082	if (ret_val)
4083	goto release;
4084
4085	/* Great! Everything worked, we can now clear the cached entries. */
4086	for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4087	dev_spec->shadow_ram[i].modified = false;
4088	dev_spec->shadow_ram[i].value = 0xFFFF;
4089	}
4090
4091	release:
4092	nvm->ops.release(hw);
4093
4094	/* Reload the EEPROM, or else modifications will not appear
4095	* until after the next adapter reset.
4096	*/
4097	if (!ret_val) {
4098	nvm->ops.reload(hw);
4099	usleep_range(min: 10000, max: 11000);
4100	}
4101
4102	out:
4103	if (ret_val)
4104	e_dbg("NVM update error: %d\n", ret_val);
4105
4106	return ret_val;
4107	}
4108
4109	/**
4110	* e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4111	* @hw: pointer to the HW structure
4112	*
4113	* Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4114	* If the bit is 0, that the EEPROM had been modified, but the checksum was not
4115	* calculated, in which case we need to calculate the checksum and set bit 6.
4116	**/
4117	static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4118	{
4119	s32 ret_val;
4120	u16 data;
4121	u16 word;
4122	u16 valid_csum_mask;
4123
4124	/* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4125	* the checksum needs to be fixed. This bit is an indication that
4126	* the NVM was prepared by OEM software and did not calculate
4127	* the checksum...a likely scenario.
4128	*/
4129	switch (hw->mac.type) {
4130	case e1000_pch_lpt:
4131	case e1000_pch_spt:
4132	case e1000_pch_cnp:
4133	case e1000_pch_tgp:
4134	case e1000_pch_adp:
4135	case e1000_pch_mtp:
4136	case e1000_pch_lnp:
4137	case e1000_pch_ptp:
4138	case e1000_pch_nvp:
4139	word = NVM_COMPAT;
4140	valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4141	break;
4142	default:
4143	word = NVM_FUTURE_INIT_WORD1;
4144	valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4145	break;
4146	}
4147
4148	ret_val = e1000_read_nvm(hw, offset: word, words: 1, data: &data);
4149	if (ret_val)
4150	return ret_val;
4151
4152	if (!(data & valid_csum_mask)) {
4153	e_dbg("NVM Checksum valid bit not set\n");
4154
4155	if (hw->mac.type < e1000_pch_tgp) {
4156	data |= valid_csum_mask;
4157	ret_val = e1000_write_nvm(hw, offset: word, words: 1, data: &data);
4158	if (ret_val)
4159	return ret_val;
4160	ret_val = e1000e_update_nvm_checksum(hw);
4161	if (ret_val)
4162	return ret_val;
4163	}
4164	}
4165
4166	return e1000e_validate_nvm_checksum_generic(hw);
4167	}
4168
4169	/**
4170	* e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4171	* @hw: pointer to the HW structure
4172	*
4173	* To prevent malicious write/erase of the NVM, set it to be read-only
4174	* so that the hardware ignores all write/erase cycles of the NVM via
4175	* the flash control registers. The shadow-ram copy of the NVM will
4176	* still be updated, however any updates to this copy will not stick
4177	* across driver reloads.
4178	**/
4179	void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4180	{
4181	struct e1000_nvm_info *nvm = &hw->nvm;
4182	union ich8_flash_protected_range pr0;
4183	union ich8_hws_flash_status hsfsts;
4184	u32 gfpreg;
4185
4186	nvm->ops.acquire(hw);
4187
4188	gfpreg = er32flash(ICH_FLASH_GFPREG);
4189
4190	/* Write-protect GbE Sector of NVM */
4191	pr0.regval = er32flash(ICH_FLASH_PR0);
4192	pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4193	pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4194	pr0.range.wpe = true;
4195	ew32flash(ICH_FLASH_PR0, pr0.regval);
4196
4197	/* Lock down a subset of GbE Flash Control Registers, e.g.
4198	* PR0 to prevent the write-protection from being lifted.
4199	* Once FLOCKDN is set, the registers protected by it cannot
4200	* be written until FLOCKDN is cleared by a hardware reset.
4201	*/
4202	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4203	hsfsts.hsf_status.flockdn = true;
4204	ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4205
4206	nvm->ops.release(hw);
4207	}
4208
4209	/**
4210	* e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4211	* @hw: pointer to the HW structure
4212	* @offset: The offset (in bytes) of the byte/word to read.
4213	* @size: Size of data to read, 1=byte 2=word
4214	* @data: The byte(s) to write to the NVM.
4215	*
4216	* Writes one/two bytes to the NVM using the flash access registers.
4217	**/
4218	static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4219	u8 size, u16 data)
4220	{
4221	union ich8_hws_flash_status hsfsts;
4222	union ich8_hws_flash_ctrl hsflctl;
4223	u32 flash_linear_addr;
4224	u32 flash_data = 0;
4225	s32 ret_val;
4226	u8 count = 0;
4227
4228	if (hw->mac.type >= e1000_pch_spt) {
4229	if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4230	return -E1000_ERR_NVM;
4231	} else {
4232	if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4233	return -E1000_ERR_NVM;
4234	}
4235
4236	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4237	hw->nvm.flash_base_addr);
4238
4239	do {
4240	udelay(1);
4241	/* Steps */
4242	ret_val = e1000_flash_cycle_init_ich8lan(hw);
4243	if (ret_val)
4244	break;
4245	/* In SPT, This register is in Lan memory space, not
4246	* flash. Therefore, only 32 bit access is supported
4247	*/
4248	if (hw->mac.type >= e1000_pch_spt)
4249	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4250	else
4251	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4252
4253	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4254	hsflctl.hsf_ctrl.fldbcount = size - 1;
4255	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4256	/* In SPT, This register is in Lan memory space,
4257	* not flash. Therefore, only 32 bit access is
4258	* supported
4259	*/
4260	if (hw->mac.type >= e1000_pch_spt)
4261	ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4262	else
4263	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4264
4265	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4266
4267	if (size == 1)
4268	flash_data = (u32)data & 0x00FF;
4269	else
4270	flash_data = (u32)data;
4271
4272	ew32flash(ICH_FLASH_FDATA0, flash_data);
4273
4274	/* check if FCERR is set to 1 , if set to 1, clear it
4275	* and try the whole sequence a few more times else done
4276	*/
4277	ret_val =
4278	e1000_flash_cycle_ich8lan(hw,
4279	ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4280	if (!ret_val)
4281	break;
4282
4283	/* If we're here, then things are most likely
4284	* completely hosed, but if the error condition
4285	* is detected, it won't hurt to give it another
4286	* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4287	*/
4288	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4289	if (hsfsts.hsf_status.flcerr)
4290	/* Repeat for some time before giving up. */
4291	continue;
4292	if (!hsfsts.hsf_status.flcdone) {
4293	e_dbg("Timeout error - flash cycle did not complete.\n");
4294	break;
4295	}
4296	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4297
4298	return ret_val;
4299	}
4300
4301	/**
4302	* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4303	* @hw: pointer to the HW structure
4304	* @offset: The offset (in bytes) of the dwords to read.
4305	* @data: The 4 bytes to write to the NVM.
4306	*
4307	* Writes one/two/four bytes to the NVM using the flash access registers.
4308	**/
4309	static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4310	u32 data)
4311	{
4312	union ich8_hws_flash_status hsfsts;
4313	union ich8_hws_flash_ctrl hsflctl;
4314	u32 flash_linear_addr;
4315	s32 ret_val;
4316	u8 count = 0;
4317
4318	if (hw->mac.type >= e1000_pch_spt) {
4319	if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4320	return -E1000_ERR_NVM;
4321	}
4322	flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4323	hw->nvm.flash_base_addr);
4324	do {
4325	udelay(1);
4326	/* Steps */
4327	ret_val = e1000_flash_cycle_init_ich8lan(hw);
4328	if (ret_val)
4329	break;
4330
4331	/* In SPT, This register is in Lan memory space, not
4332	* flash. Therefore, only 32 bit access is supported
4333	*/
4334	if (hw->mac.type >= e1000_pch_spt)
4335	hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4336	>> 16;
4337	else
4338	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4339
4340	hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4341	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4342
4343	/* In SPT, This register is in Lan memory space,
4344	* not flash. Therefore, only 32 bit access is
4345	* supported
4346	*/
4347	if (hw->mac.type >= e1000_pch_spt)
4348	ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4349	else
4350	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4351
4352	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4353
4354	ew32flash(ICH_FLASH_FDATA0, data);
4355
4356	/* check if FCERR is set to 1 , if set to 1, clear it
4357	* and try the whole sequence a few more times else done
4358	*/
4359	ret_val =
4360	e1000_flash_cycle_ich8lan(hw,
4361	ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4362
4363	if (!ret_val)
4364	break;
4365
4366	/* If we're here, then things are most likely
4367	* completely hosed, but if the error condition
4368	* is detected, it won't hurt to give it another
4369	* try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4370	*/
4371	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4372
4373	if (hsfsts.hsf_status.flcerr)
4374	/* Repeat for some time before giving up. */
4375	continue;
4376	if (!hsfsts.hsf_status.flcdone) {
4377	e_dbg("Timeout error - flash cycle did not complete.\n");
4378	break;
4379	}
4380	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4381
4382	return ret_val;
4383	}
4384
4385	/**
4386	* e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4387	* @hw: pointer to the HW structure
4388	* @offset: The index of the byte to read.
4389	* @data: The byte to write to the NVM.
4390	*
4391	* Writes a single byte to the NVM using the flash access registers.
4392	**/
4393	static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4394	u8 data)
4395	{
4396	u16 word = (u16)data;
4397
4398	return e1000_write_flash_data_ich8lan(hw, offset, size: 1, data: word);
4399	}
4400
4401	/**
4402	* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4403	* @hw: pointer to the HW structure
4404	* @offset: The offset of the word to write.
4405	* @dword: The dword to write to the NVM.
4406	*
4407	* Writes a single dword to the NVM using the flash access registers.
4408	* Goes through a retry algorithm before giving up.
4409	**/
4410	static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4411	u32 offset, u32 dword)
4412	{
4413	s32 ret_val;
4414	u16 program_retries;
4415
4416	/* Must convert word offset into bytes. */
4417	offset <<= 1;
4418	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, data: dword);
4419
4420	if (!ret_val)
4421	return ret_val;
4422	for (program_retries = 0; program_retries < 100; program_retries++) {
4423	e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4424	usleep_range(min: 100, max: 200);
4425	ret_val = e1000_write_flash_data32_ich8lan(hw, offset, data: dword);
4426	if (!ret_val)
4427	break;
4428	}
4429	if (program_retries == 100)
4430	return -E1000_ERR_NVM;
4431
4432	return 0;
4433	}
4434
4435	/**
4436	* e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4437	* @hw: pointer to the HW structure
4438	* @offset: The offset of the byte to write.
4439	* @byte: The byte to write to the NVM.
4440	*
4441	* Writes a single byte to the NVM using the flash access registers.
4442	* Goes through a retry algorithm before giving up.
4443	**/
4444	static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4445	u32 offset, u8 byte)
4446	{
4447	s32 ret_val;
4448	u16 program_retries;
4449
4450	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, data: byte);
4451	if (!ret_val)
4452	return ret_val;
4453
4454	for (program_retries = 0; program_retries < 100; program_retries++) {
4455	e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4456	usleep_range(min: 100, max: 200);
4457	ret_val = e1000_write_flash_byte_ich8lan(hw, offset, data: byte);
4458	if (!ret_val)
4459	break;
4460	}
4461	if (program_retries == 100)
4462	return -E1000_ERR_NVM;
4463
4464	return 0;
4465	}
4466
4467	/**
4468	* e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4469	* @hw: pointer to the HW structure
4470	* @bank: 0 for first bank, 1 for second bank, etc.
4471	*
4472	* Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4473	* bank N is 4096 * N + flash_reg_addr.
4474	**/
4475	static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4476	{
4477	struct e1000_nvm_info *nvm = &hw->nvm;
4478	union ich8_hws_flash_status hsfsts;
4479	union ich8_hws_flash_ctrl hsflctl;
4480	u32 flash_linear_addr;
4481	/* bank size is in 16bit words - adjust to bytes */
4482	u32 flash_bank_size = nvm->flash_bank_size * 2;
4483	s32 ret_val;
4484	s32 count = 0;
4485	s32 j, iteration, sector_size;
4486
4487	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4488
4489	/* Determine HW Sector size: Read BERASE bits of hw flash status
4490	* register
4491	* 00: The Hw sector is 256 bytes, hence we need to erase 16
4492	* consecutive sectors. The start index for the nth Hw sector
4493	* can be calculated as = bank * 4096 + n * 256
4494	* 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4495	* The start index for the nth Hw sector can be calculated
4496	* as = bank * 4096
4497	* 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4498	* (ich9 only, otherwise error condition)
4499	* 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4500	*/
4501	switch (hsfsts.hsf_status.berasesz) {
4502	case 0:
4503	/* Hw sector size 256 */
4504	sector_size = ICH_FLASH_SEG_SIZE_256;
4505	iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4506	break;
4507	case 1:
4508	sector_size = ICH_FLASH_SEG_SIZE_4K;
4509	iteration = 1;
4510	break;
4511	case 2:
4512	sector_size = ICH_FLASH_SEG_SIZE_8K;
4513	iteration = 1;
4514	break;
4515	case 3:
4516	sector_size = ICH_FLASH_SEG_SIZE_64K;
4517	iteration = 1;
4518	break;
4519	default:
4520	return -E1000_ERR_NVM;
4521	}
4522
4523	/* Start with the base address, then add the sector offset. */
4524	flash_linear_addr = hw->nvm.flash_base_addr;
4525	flash_linear_addr += (bank) ? flash_bank_size : 0;
4526
4527	for (j = 0; j < iteration; j++) {
4528	do {
4529	u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4530
4531	/* Steps */
4532	ret_val = e1000_flash_cycle_init_ich8lan(hw);
4533	if (ret_val)
4534	return ret_val;
4535
4536	/* Write a value 11 (block Erase) in Flash
4537	* Cycle field in hw flash control
4538	*/
4539	if (hw->mac.type >= e1000_pch_spt)
4540	hsflctl.regval =
4541	er32flash(ICH_FLASH_HSFSTS) >> 16;
4542	else
4543	hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4544
4545	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4546	if (hw->mac.type >= e1000_pch_spt)
4547	ew32flash(ICH_FLASH_HSFSTS,
4548	hsflctl.regval << 16);
4549	else
4550	ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4551
4552	/* Write the last 24 bits of an index within the
4553	* block into Flash Linear address field in Flash
4554	* Address.
4555	*/
4556	flash_linear_addr += (j * sector_size);
4557	ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4558
4559	ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4560	if (!ret_val)
4561	break;
4562
4563	/* Check if FCERR is set to 1. If 1,
4564	* clear it and try the whole sequence
4565	* a few more times else Done
4566	*/
4567	hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4568	if (hsfsts.hsf_status.flcerr)
4569	/* repeat for some time before giving up */
4570	continue;
4571	else if (!hsfsts.hsf_status.flcdone)
4572	return ret_val;
4573	} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4574	}
4575
4576	return 0;
4577	}
4578
4579	/**
4580	* e1000_valid_led_default_ich8lan - Set the default LED settings
4581	* @hw: pointer to the HW structure
4582	* @data: Pointer to the LED settings
4583	*
4584	* Reads the LED default settings from the NVM to data. If the NVM LED
4585	* settings is all 0's or F's, set the LED default to a valid LED default
4586	* setting.
4587	**/
4588	static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4589	{
4590	s32 ret_val;
4591
4592	ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, words: 1, data);
4593	if (ret_val) {
4594	e_dbg("NVM Read Error\n");
4595	return ret_val;
4596	}
4597
4598	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4599	*data = ID_LED_DEFAULT_ICH8LAN;
4600
4601	return 0;
4602	}
4603
4604	/**
4605	* e1000_id_led_init_pchlan - store LED configurations
4606	* @hw: pointer to the HW structure
4607	*
4608	* PCH does not control LEDs via the LEDCTL register, rather it uses
4609	* the PHY LED configuration register.
4610	*
4611	* PCH also does not have an "always on" or "always off" mode which
4612	* complicates the ID feature. Instead of using the "on" mode to indicate
4613	* in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4614	* use "link_up" mode. The LEDs will still ID on request if there is no
4615	* link based on logic in e1000_led_[on|off]_pchlan().
4616	**/
4617	static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4618	{
4619	struct e1000_mac_info *mac = &hw->mac;
4620	s32 ret_val;
4621	const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4622	const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4623	u16 data, i, temp, shift;
4624
4625	/* Get default ID LED modes */
4626	ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4627	if (ret_val)
4628	return ret_val;
4629
4630	mac->ledctl_default = er32(LEDCTL);
4631	mac->ledctl_mode1 = mac->ledctl_default;
4632	mac->ledctl_mode2 = mac->ledctl_default;
4633
4634	for (i = 0; i < 4; i++) {
4635	temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4636	shift = (i * 5);
4637	switch (temp) {
4638	case ID_LED_ON1_DEF2:
4639	case ID_LED_ON1_ON2:
4640	case ID_LED_ON1_OFF2:
4641	mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4642	mac->ledctl_mode1 |= (ledctl_on << shift);
4643	break;
4644	case ID_LED_OFF1_DEF2:
4645	case ID_LED_OFF1_ON2:
4646	case ID_LED_OFF1_OFF2:
4647	mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4648	mac->ledctl_mode1 |= (ledctl_off << shift);
4649	break;
4650	default:
4651	/* Do nothing */
4652	break;
4653	}
4654	switch (temp) {
4655	case ID_LED_DEF1_ON2:
4656	case ID_LED_ON1_ON2:
4657	case ID_LED_OFF1_ON2:
4658	mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4659	mac->ledctl_mode2 |= (ledctl_on << shift);
4660	break;
4661	case ID_LED_DEF1_OFF2:
4662	case ID_LED_ON1_OFF2:
4663	case ID_LED_OFF1_OFF2:
4664	mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4665	mac->ledctl_mode2 |= (ledctl_off << shift);
4666	break;
4667	default:
4668	/* Do nothing */
4669	break;
4670	}
4671	}
4672
4673	return 0;
4674	}
4675
4676	/**
4677	* e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4678	* @hw: pointer to the HW structure
4679	*
4680	* ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4681	* register, so the bus width is hard coded.
4682	**/
4683	static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4684	{
4685	struct e1000_bus_info *bus = &hw->bus;
4686	s32 ret_val;
4687
4688	ret_val = e1000e_get_bus_info_pcie(hw);
4689
4690	/* ICH devices are "PCI Express"-ish. They have
4691	* a configuration space, but do not contain
4692	* PCI Express Capability registers, so bus width
4693	* must be hardcoded.
4694	*/
4695	if (bus->width == e1000_bus_width_unknown)
4696	bus->width = e1000_bus_width_pcie_x1;
4697
4698	return ret_val;
4699	}
4700
4701	/**
4702	* e1000_reset_hw_ich8lan - Reset the hardware
4703	* @hw: pointer to the HW structure
4704	*
4705	* Does a full reset of the hardware which includes a reset of the PHY and
4706	* MAC.
4707	**/
4708	static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4709	{
4710	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4711	u16 kum_cfg;
4712	u32 ctrl, reg;
4713	s32 ret_val;
4714
4715	/* Prevent the PCI-E bus from sticking if there is no TLP connection
4716	* on the last TLP read/write transaction when MAC is reset.
4717	*/
4718	ret_val = e1000e_disable_pcie_master(hw);
4719	if (ret_val)
4720	e_dbg("PCI-E Master disable polling has failed.\n");
4721
4722	e_dbg("Masking off all interrupts\n");
4723	ew32(IMC, 0xffffffff);
4724
4725	/* Disable the Transmit and Receive units. Then delay to allow
4726	* any pending transactions to complete before we hit the MAC
4727	* with the global reset.
4728	*/
4729	ew32(RCTL, 0);
4730	ew32(TCTL, E1000_TCTL_PSP);
4731	e1e_flush();
4732
4733	usleep_range(min: 10000, max: 11000);
4734
4735	/* Workaround for ICH8 bit corruption issue in FIFO memory */
4736	if (hw->mac.type == e1000_ich8lan) {
4737	/* Set Tx and Rx buffer allocation to 8k apiece. */
4738	ew32(PBA, E1000_PBA_8K);
4739	/* Set Packet Buffer Size to 16k. */
4740	ew32(PBS, E1000_PBS_16K);
4741	}
4742
4743	if (hw->mac.type == e1000_pchlan) {
4744	/* Save the NVM K1 bit setting */
4745	ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, words: 1, data: &kum_cfg);
4746	if (ret_val)
4747	return ret_val;
4748
4749	if (kum_cfg & E1000_NVM_K1_ENABLE)
4750	dev_spec->nvm_k1_enabled = true;
4751	else
4752	dev_spec->nvm_k1_enabled = false;
4753	}
4754
4755	ctrl = er32(CTRL);
4756
4757	if (!hw->phy.ops.check_reset_block(hw)) {
4758	/* Full-chip reset requires MAC and PHY reset at the same
4759	* time to make sure the interface between MAC and the
4760	* external PHY is reset.
4761	*/
4762	ctrl |= E1000_CTRL_PHY_RST;
4763
4764	/* Gate automatic PHY configuration by hardware on
4765	* non-managed 82579
4766	*/
4767	if ((hw->mac.type == e1000_pch2lan) &&
4768	!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4769	e1000_gate_hw_phy_config_ich8lan(hw, gate: true);
4770	}
4771	ret_val = e1000_acquire_swflag_ich8lan(hw);
4772	e_dbg("Issuing a global reset to ich8lan\n");
4773	ew32(CTRL, (ctrl | E1000_CTRL_RST));
4774	/* cannot issue a flush here because it hangs the hardware */
4775	msleep(msecs: 20);
4776
4777	/* Set Phy Config Counter to 50msec */
4778	if (hw->mac.type == e1000_pch2lan) {
4779	reg = er32(FEXTNVM3);
4780	reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4781	reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4782	ew32(FEXTNVM3, reg);
4783	}
4784
4785	if (!ret_val)
4786	clear_bit(nr: __E1000_ACCESS_SHARED_RESOURCE, addr: &hw->adapter->state);
4787
4788	if (ctrl & E1000_CTRL_PHY_RST) {
4789	ret_val = hw->phy.ops.get_cfg_done(hw);
4790	if (ret_val)
4791	return ret_val;
4792
4793	ret_val = e1000_post_phy_reset_ich8lan(hw);
4794	if (ret_val)
4795	return ret_val;
4796	}
4797
4798	/* For PCH, this write will make sure that any noise
4799	* will be detected as a CRC error and be dropped rather than show up
4800	* as a bad packet to the DMA engine.
4801	*/
4802	if (hw->mac.type == e1000_pchlan)
4803	ew32(CRC_OFFSET, 0x65656565);
4804
4805	ew32(IMC, 0xffffffff);
4806	er32(ICR);
4807
4808	reg = er32(KABGTXD);
4809	reg |= E1000_KABGTXD_BGSQLBIAS;
4810	ew32(KABGTXD, reg);
4811
4812	return 0;
4813	}
4814
4815	/**
4816	* e1000_init_hw_ich8lan - Initialize the hardware
4817	* @hw: pointer to the HW structure
4818	*
4819	* Prepares the hardware for transmit and receive by doing the following:
4820	* - initialize hardware bits
4821	* - initialize LED identification
4822	* - setup receive address registers
4823	* - setup flow control
4824	* - setup transmit descriptors
4825	* - clear statistics
4826	**/
4827	static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4828	{
4829	struct e1000_mac_info *mac = &hw->mac;
4830	u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4831	s32 ret_val;
4832	u16 i;
4833
4834	e1000_initialize_hw_bits_ich8lan(hw);
4835
4836	/* Initialize identification LED */
4837	ret_val = mac->ops.id_led_init(hw);
4838	/* An error is not fatal and we should not stop init due to this */
4839	if (ret_val)
4840	e_dbg("Error initializing identification LED\n");
4841
4842	/* Setup the receive address. */
4843	e1000e_init_rx_addrs(hw, rar_count: mac->rar_entry_count);
4844
4845	/* Zero out the Multicast HASH table */
4846	e_dbg("Zeroing the MTA\n");
4847	for (i = 0; i < mac->mta_reg_count; i++)
4848	E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4849
4850	/* The 82578 Rx buffer will stall if wakeup is enabled in host and
4851	* the ME. Disable wakeup by clearing the host wakeup bit.
4852	* Reset the phy after disabling host wakeup to reset the Rx buffer.
4853	*/
4854	if (hw->phy.type == e1000_phy_82578) {
4855	e1e_rphy(hw, BM_PORT_GEN_CFG, data: &i);
4856	i &= ~BM_WUC_HOST_WU_BIT;
4857	e1e_wphy(hw, BM_PORT_GEN_CFG, data: i);
4858	ret_val = e1000_phy_hw_reset_ich8lan(hw);
4859	if (ret_val)
4860	return ret_val;
4861	}
4862
4863	/* Setup link and flow control */
4864	ret_val = mac->ops.setup_link(hw);
4865
4866	/* Set the transmit descriptor write-back policy for both queues */
4867	txdctl = er32(TXDCTL(0));
4868	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4869	E1000_TXDCTL_FULL_TX_DESC_WB);
4870	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4871	E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4872	ew32(TXDCTL(0), txdctl);
4873	txdctl = er32(TXDCTL(1));
4874	txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4875	E1000_TXDCTL_FULL_TX_DESC_WB);
4876	txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4877	E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4878	ew32(TXDCTL(1), txdctl);
4879
4880	/* ICH8 has opposite polarity of no_snoop bits.
4881	* By default, we should use snoop behavior.
4882	*/
4883	if (mac->type == e1000_ich8lan)
4884	snoop = PCIE_ICH8_SNOOP_ALL;
4885	else
4886	snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4887	e1000e_set_pcie_no_snoop(hw, no_snoop: snoop);
4888
4889	/* Enable workaround for packet loss issue on TGP PCH
4890	* Do not gate DMA clock from the modPHY block
4891	*/
4892	if (mac->type >= e1000_pch_tgp) {
4893	fflt_dbg = er32(FFLT_DBG);
4894	fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4895	ew32(FFLT_DBG, fflt_dbg);
4896	}
4897
4898	ctrl_ext = er32(CTRL_EXT);
4899	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4900	ew32(CTRL_EXT, ctrl_ext);
4901
4902	/* Clear all of the statistics registers (clear on read). It is
4903	* important that we do this after we have tried to establish link
4904	* because the symbol error count will increment wildly if there
4905	* is no link.
4906	*/
4907	e1000_clear_hw_cntrs_ich8lan(hw);
4908
4909	return ret_val;
4910	}
4911
4912	/**
4913	* e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4914	* @hw: pointer to the HW structure
4915	*
4916	* Sets/Clears required hardware bits necessary for correctly setting up the
4917	* hardware for transmit and receive.
4918	**/
4919	static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4920	{
4921	u32 reg;
4922
4923	/* Extended Device Control */
4924	reg = er32(CTRL_EXT);
4925	reg |= BIT(22);
4926	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
4927	if (hw->mac.type >= e1000_pchlan)
4928	reg |= E1000_CTRL_EXT_PHYPDEN;
4929	ew32(CTRL_EXT, reg);
4930
4931	/* Transmit Descriptor Control 0 */
4932	reg = er32(TXDCTL(0));
4933	reg |= BIT(22);
4934	ew32(TXDCTL(0), reg);
4935
4936	/* Transmit Descriptor Control 1 */
4937	reg = er32(TXDCTL(1));
4938	reg |= BIT(22);
4939	ew32(TXDCTL(1), reg);
4940
4941	/* Transmit Arbitration Control 0 */
4942	reg = er32(TARC(0));
4943	if (hw->mac.type == e1000_ich8lan)
4944	reg |= BIT(28) | BIT(29);
4945	reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4946	ew32(TARC(0), reg);
4947
4948	/* Transmit Arbitration Control 1 */
4949	reg = er32(TARC(1));
4950	if (er32(TCTL) & E1000_TCTL_MULR)
4951	reg &= ~BIT(28);
4952	else
4953	reg |= BIT(28);
4954	reg |= BIT(24) | BIT(26) | BIT(30);
4955	ew32(TARC(1), reg);
4956
4957	/* Device Status */
4958	if (hw->mac.type == e1000_ich8lan) {
4959	reg = er32(STATUS);
4960	reg &= ~BIT(31);
4961	ew32(STATUS, reg);
4962	}
4963
4964	/* work-around descriptor data corruption issue during nfs v2 udp
4965	* traffic, just disable the nfs filtering capability
4966	*/
4967	reg = er32(RFCTL);
4968	reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4969
4970	/* Disable IPv6 extension header parsing because some malformed
4971	* IPv6 headers can hang the Rx.
4972	*/
4973	if (hw->mac.type == e1000_ich8lan)
4974	reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4975	ew32(RFCTL, reg);
4976
4977	/* Enable ECC on Lynxpoint */
4978	if (hw->mac.type >= e1000_pch_lpt) {
4979	reg = er32(PBECCSTS);
4980	reg |= E1000_PBECCSTS_ECC_ENABLE;
4981	ew32(PBECCSTS, reg);
4982
4983	reg = er32(CTRL);
4984	reg |= E1000_CTRL_MEHE;
4985	ew32(CTRL, reg);
4986	}
4987	}
4988
4989	/**
4990	* e1000_setup_link_ich8lan - Setup flow control and link settings
4991	* @hw: pointer to the HW structure
4992	*
4993	* Determines which flow control settings to use, then configures flow
4994	* control. Calls the appropriate media-specific link configuration
4995	* function. Assuming the adapter has a valid link partner, a valid link
4996	* should be established. Assumes the hardware has previously been reset
4997	* and the transmitter and receiver are not enabled.
4998	**/
4999	static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
5000	{
5001	s32 ret_val;
5002
5003	if (hw->phy.ops.check_reset_block(hw))
5004	return 0;
5005
5006	/* ICH parts do not have a word in the NVM to determine
5007	* the default flow control setting, so we explicitly
5008	* set it to full.
5009	*/
5010	if (hw->fc.requested_mode == e1000_fc_default) {
5011	/* Workaround h/w hang when Tx flow control enabled */
5012	if (hw->mac.type == e1000_pchlan)
5013	hw->fc.requested_mode = e1000_fc_rx_pause;
5014	else
5015	hw->fc.requested_mode = e1000_fc_full;
5016	}
5017
5018	/* Save off the requested flow control mode for use later. Depending
5019	* on the link partner's capabilities, we may or may not use this mode.
5020	*/
5021	hw->fc.current_mode = hw->fc.requested_mode;
5022
5023	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5024
5025	/* Continue to configure the copper link. */
5026	ret_val = hw->mac.ops.setup_physical_interface(hw);
5027	if (ret_val)
5028	return ret_val;
5029
5030	ew32(FCTTV, hw->fc.pause_time);
5031	if ((hw->phy.type == e1000_phy_82578) ||
5032	(hw->phy.type == e1000_phy_82579) ||
5033	(hw->phy.type == e1000_phy_i217) ||
5034	(hw->phy.type == e1000_phy_82577)) {
5035	ew32(FCRTV_PCH, hw->fc.refresh_time);
5036
5037	ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5038	data: hw->fc.pause_time);
5039	if (ret_val)
5040	return ret_val;
5041	}
5042
5043	return e1000e_set_fc_watermarks(hw);
5044	}
5045
5046	/**
5047	* e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5048	* @hw: pointer to the HW structure
5049	*
5050	* Configures the kumeran interface to the PHY to wait the appropriate time
5051	* when polling the PHY, then call the generic setup_copper_link to finish
5052	* configuring the copper link.
5053	**/
5054	static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5055	{
5056	u32 ctrl;
5057	s32 ret_val;
5058	u16 reg_data;
5059
5060	ctrl = er32(CTRL);
5061	ctrl |= E1000_CTRL_SLU;
5062	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5063	ew32(CTRL, ctrl);
5064
5065	/* Set the mac to wait the maximum time between each iteration
5066	* and increase the max iterations when polling the phy;
5067	* this fixes erroneous timeouts at 10Mbps.
5068	*/
5069	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, data: 0xFFFF);
5070	if (ret_val)
5071	return ret_val;
5072	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5073	data: &reg_data);
5074	if (ret_val)
5075	return ret_val;
5076	reg_data |= 0x3F;
5077	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5078	data: reg_data);
5079	if (ret_val)
5080	return ret_val;
5081
5082	switch (hw->phy.type) {
5083	case e1000_phy_igp_3:
5084	ret_val = e1000e_copper_link_setup_igp(hw);
5085	if (ret_val)
5086	return ret_val;
5087	break;
5088	case e1000_phy_bm:
5089	case e1000_phy_82578:
5090	ret_val = e1000e_copper_link_setup_m88(hw);
5091	if (ret_val)
5092	return ret_val;
5093	break;
5094	case e1000_phy_82577:
5095	case e1000_phy_82579:
5096	ret_val = e1000_copper_link_setup_82577(hw);
5097	if (ret_val)
5098	return ret_val;
5099	break;
5100	case e1000_phy_ife:
5101	ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, data: &reg_data);
5102	if (ret_val)
5103	return ret_val;
5104
5105	reg_data &= ~IFE_PMC_AUTO_MDIX;
5106
5107	switch (hw->phy.mdix) {
5108	case 1:
5109	reg_data &= ~IFE_PMC_FORCE_MDIX;
5110	break;
5111	case 2:
5112	reg_data |= IFE_PMC_FORCE_MDIX;
5113	break;
5114	case 0:
5115	default:
5116	reg_data |= IFE_PMC_AUTO_MDIX;
5117	break;
5118	}
5119	ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data: reg_data);
5120	if (ret_val)
5121	return ret_val;
5122	break;
5123	default:
5124	break;
5125	}
5126
5127	return e1000e_setup_copper_link(hw);
5128	}
5129
5130	/**
5131	* e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5132	* @hw: pointer to the HW structure
5133	*
5134	* Calls the PHY specific link setup function and then calls the
5135	* generic setup_copper_link to finish configuring the link for
5136	* Lynxpoint PCH devices
5137	**/
5138	static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5139	{
5140	u32 ctrl;
5141	s32 ret_val;
5142
5143	ctrl = er32(CTRL);
5144	ctrl |= E1000_CTRL_SLU;
5145	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5146	ew32(CTRL, ctrl);
5147
5148	ret_val = e1000_copper_link_setup_82577(hw);
5149	if (ret_val)
5150	return ret_val;
5151
5152	return e1000e_setup_copper_link(hw);
5153	}
5154
5155	/**
5156	* e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5157	* @hw: pointer to the HW structure
5158	* @speed: pointer to store current link speed
5159	* @duplex: pointer to store the current link duplex
5160	*
5161	* Calls the generic get_speed_and_duplex to retrieve the current link
5162	* information and then calls the Kumeran lock loss workaround for links at
5163	* gigabit speeds.
5164	**/
5165	static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5166	u16 *duplex)
5167	{
5168	s32 ret_val;
5169
5170	ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5171	if (ret_val)
5172	return ret_val;
5173
5174	if ((hw->mac.type == e1000_ich8lan) &&
5175	(hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5176	ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5177	}
5178
5179	return ret_val;
5180	}
5181
5182	/**
5183	* e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5184	* @hw: pointer to the HW structure
5185	*
5186	* Work-around for 82566 Kumeran PCS lock loss:
5187	* On link status change (i.e. PCI reset, speed change) and link is up and
5188	* speed is gigabit-
5189	* 0) if workaround is optionally disabled do nothing
5190	* 1) wait 1ms for Kumeran link to come up
5191	* 2) check Kumeran Diagnostic register PCS lock loss bit
5192	* 3) if not set the link is locked (all is good), otherwise...
5193	* 4) reset the PHY
5194	* 5) repeat up to 10 times
5195	* Note: this is only called for IGP3 copper when speed is 1gb.
5196	**/
5197	static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5198	{
5199	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5200	u32 phy_ctrl;
5201	s32 ret_val;
5202	u16 i, data;
5203	bool link;
5204
5205	if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5206	return 0;
5207
5208	/* Make sure link is up before proceeding. If not just return.
5209	* Attempting this while link is negotiating fouled up link
5210	* stability
5211	*/
5212	ret_val = e1000e_phy_has_link_generic(hw, iterations: 1, usec_interval: 0, success: &link);
5213	if (!link)
5214	return 0;
5215
5216	for (i = 0; i < 10; i++) {
5217	/* read once to clear */
5218	ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, data: &data);
5219	if (ret_val)
5220	return ret_val;
5221	/* and again to get new status */
5222	ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, data: &data);
5223	if (ret_val)
5224	return ret_val;
5225
5226	/* check for PCS lock */
5227	if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5228	return 0;
5229
5230	/* Issue PHY reset */
5231	e1000_phy_hw_reset(hw);
5232	mdelay(5);
5233	}
5234	/* Disable GigE link negotiation */
5235	phy_ctrl = er32(PHY_CTRL);
5236	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5237	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5238	ew32(PHY_CTRL, phy_ctrl);
5239
5240	/* Call gig speed drop workaround on Gig disable before accessing
5241	* any PHY registers
5242	*/
5243	e1000e_gig_downshift_workaround_ich8lan(hw);
5244
5245	/* unable to acquire PCS lock */
5246	return -E1000_ERR_PHY;
5247	}
5248
5249	/**
5250	* e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5251	* @hw: pointer to the HW structure
5252	* @state: boolean value used to set the current Kumeran workaround state
5253	*
5254	* If ICH8, set the current Kumeran workaround state (enabled - true
5255	* /disabled - false).
5256	**/
5257	void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5258	bool state)
5259	{
5260	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5261
5262	if (hw->mac.type != e1000_ich8lan) {
5263	e_dbg("Workaround applies to ICH8 only.\n");
5264	return;
5265	}
5266
5267	dev_spec->kmrn_lock_loss_workaround_enabled = state;
5268	}
5269
5270	/**
5271	* e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5272	* @hw: pointer to the HW structure
5273	*
5274	* Workaround for 82566 power-down on D3 entry:
5275	* 1) disable gigabit link
5276	* 2) write VR power-down enable
5277	* 3) read it back
5278	* Continue if successful, else issue LCD reset and repeat
5279	**/
5280	void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5281	{
5282	u32 reg;
5283	u16 data;
5284	u8 retry = 0;
5285
5286	if (hw->phy.type != e1000_phy_igp_3)
5287	return;
5288
5289	/* Try the workaround twice (if needed) */
5290	do {
5291	/* Disable link */
5292	reg = er32(PHY_CTRL);
5293	reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5294	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5295	ew32(PHY_CTRL, reg);
5296
5297	/* Call gig speed drop workaround on Gig disable before
5298	* accessing any PHY registers
5299	*/
5300	if (hw->mac.type == e1000_ich8lan)
5301	e1000e_gig_downshift_workaround_ich8lan(hw);
5302
5303	/* Write VR power-down enable */
5304	e1e_rphy(hw, IGP3_VR_CTRL, data: &data);
5305	data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5306	e1e_wphy(hw, IGP3_VR_CTRL, data: data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5307
5308	/* Read it back and test */
5309	e1e_rphy(hw, IGP3_VR_CTRL, data: &data);
5310	data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5311	if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5312	break;
5313
5314	/* Issue PHY reset and repeat at most one more time */
5315	reg = er32(CTRL);
5316	ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5317	retry++;
5318	} while (retry);
5319	}
5320
5321	/**
5322	* e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5323	* @hw: pointer to the HW structure
5324	*
5325	* Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5326	* LPLU, Gig disable, MDIC PHY reset):
5327	* 1) Set Kumeran Near-end loopback
5328	* 2) Clear Kumeran Near-end loopback
5329	* Should only be called for ICH8[m] devices with any 1G Phy.
5330	**/
5331	void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5332	{
5333	s32 ret_val;
5334	u16 reg_data;
5335
5336	if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5337	return;
5338
5339	ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5340	data: &reg_data);
5341	if (ret_val)
5342	return;
5343	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5344	ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5345	data: reg_data);
5346	if (ret_val)
5347	return;
5348	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5349	e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, data: reg_data);
5350	}
5351
5352	/**
5353	* e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5354	* @hw: pointer to the HW structure
5355	*
5356	* During S0 to Sx transition, it is possible the link remains at gig
5357	* instead of negotiating to a lower speed. Before going to Sx, set
5358	* 'Gig Disable' to force link speed negotiation to a lower speed based on
5359	* the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5360	* the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5361	* needs to be written.
5362	* Parts that support (and are linked to a partner which support) EEE in
5363	* 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5364	* than 10Mbps w/o EEE.
5365	**/
5366	void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5367	{
5368	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5369	u32 phy_ctrl;
5370	s32 ret_val;
5371
5372	phy_ctrl = er32(PHY_CTRL);
5373	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5374
5375	if (hw->phy.type == e1000_phy_i217) {
5376	u16 phy_reg, device_id = hw->adapter->pdev->device;
5377
5378	if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5379	(device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5380	(device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5381	(device_id == E1000_DEV_ID_PCH_I218_V3) ||
5382	(hw->mac.type >= e1000_pch_spt)) {
5383	u32 fextnvm6 = er32(FEXTNVM6);
5384
5385	ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5386	}
5387
5388	ret_val = hw->phy.ops.acquire(hw);
5389	if (ret_val)
5390	goto out;
5391
5392	if (!dev_spec->eee_disable) {
5393	u16 eee_advert;
5394
5395	ret_val =
5396	e1000_read_emi_reg_locked(hw,
5397	I217_EEE_ADVERTISEMENT,
5398	data: &eee_advert);
5399	if (ret_val)
5400	goto release;
5401
5402	/* Disable LPLU if both link partners support 100BaseT
5403	* EEE and 100Full is advertised on both ends of the
5404	* link, and enable Auto Enable LPI since there will
5405	* be no driver to enable LPI while in Sx.
5406	*/
5407	if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5408	(dev_spec->eee_lp_ability &
5409	I82579_EEE_100_SUPPORTED) &&
5410	(hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5411	phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5412	E1000_PHY_CTRL_NOND0A_LPLU);
5413
5414	/* Set Auto Enable LPI after link up */
5415	e1e_rphy_locked(hw,
5416	I217_LPI_GPIO_CTRL, data: &phy_reg);
5417	phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5418	e1e_wphy_locked(hw,
5419	I217_LPI_GPIO_CTRL, data: phy_reg);
5420	}
5421	}
5422
5423	/* For i217 Intel Rapid Start Technology support,
5424	* when the system is going into Sx and no manageability engine
5425	* is present, the driver must configure proxy to reset only on
5426	* power good. LPI (Low Power Idle) state must also reset only
5427	* on power good, as well as the MTA (Multicast table array).
5428	* The SMBus release must also be disabled on LCD reset.
5429	*/
5430	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5431	/* Enable proxy to reset only on power good. */
5432	e1e_rphy_locked(hw, I217_PROXY_CTRL, data: &phy_reg);
5433	phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5434	e1e_wphy_locked(hw, I217_PROXY_CTRL, data: phy_reg);
5435
5436	/* Set bit enable LPI (EEE) to reset only on
5437	* power good.
5438	*/
5439	e1e_rphy_locked(hw, I217_SxCTRL, data: &phy_reg);
5440	phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5441	e1e_wphy_locked(hw, I217_SxCTRL, data: phy_reg);
5442
5443	/* Disable the SMB release on LCD reset. */
5444	e1e_rphy_locked(hw, I217_MEMPWR, data: &phy_reg);
5445	phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5446	e1e_wphy_locked(hw, I217_MEMPWR, data: phy_reg);
5447	}
5448
5449	/* Enable MTA to reset for Intel Rapid Start Technology
5450	* Support
5451	*/
5452	e1e_rphy_locked(hw, I217_CGFREG, data: &phy_reg);
5453	phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5454	e1e_wphy_locked(hw, I217_CGFREG, data: phy_reg);
5455
5456	release:
5457	hw->phy.ops.release(hw);
5458	}
5459	out:
5460	ew32(PHY_CTRL, phy_ctrl);
5461
5462	if (hw->mac.type == e1000_ich8lan)
5463	e1000e_gig_downshift_workaround_ich8lan(hw);
5464
5465	if (hw->mac.type >= e1000_pchlan) {
5466	e1000_oem_bits_config_ich8lan(hw, d0_state: false);
5467
5468	/* Reset PHY to activate OEM bits on 82577/8 */
5469	if (hw->mac.type == e1000_pchlan)
5470	e1000e_phy_hw_reset_generic(hw);
5471
5472	ret_val = hw->phy.ops.acquire(hw);
5473	if (ret_val)
5474	return;
5475	e1000_write_smbus_addr(hw);
5476	hw->phy.ops.release(hw);
5477	}
5478	}
5479
5480	/**
5481	* e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5482	* @hw: pointer to the HW structure
5483	*
5484	* During Sx to S0 transitions on non-managed devices or managed devices
5485	* on which PHY resets are not blocked, if the PHY registers cannot be
5486	* accessed properly by the s/w toggle the LANPHYPC value to power cycle
5487	* the PHY.
5488	* On i217, setup Intel Rapid Start Technology.
5489	**/
5490	void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5491	{
5492	s32 ret_val;
5493
5494	if (hw->mac.type < e1000_pch2lan)
5495	return;
5496
5497	ret_val = e1000_init_phy_workarounds_pchlan(hw);
5498	if (ret_val) {
5499	e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5500	return;
5501	}
5502
5503	/* For i217 Intel Rapid Start Technology support when the system
5504	* is transitioning from Sx and no manageability engine is present
5505	* configure SMBus to restore on reset, disable proxy, and enable
5506	* the reset on MTA (Multicast table array).
5507	*/
5508	if (hw->phy.type == e1000_phy_i217) {
5509	u16 phy_reg;
5510
5511	ret_val = hw->phy.ops.acquire(hw);
5512	if (ret_val) {
5513	e_dbg("Failed to setup iRST\n");
5514	return;
5515	}
5516
5517	/* Clear Auto Enable LPI after link up */
5518	e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, data: &phy_reg);
5519	phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5520	e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, data: phy_reg);
5521
5522	if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5523	/* Restore clear on SMB if no manageability engine
5524	* is present
5525	*/
5526	ret_val = e1e_rphy_locked(hw, I217_MEMPWR, data: &phy_reg);
5527	if (ret_val)
5528	goto release;
5529	phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5530	e1e_wphy_locked(hw, I217_MEMPWR, data: phy_reg);
5531
5532	/* Disable Proxy */
5533	e1e_wphy_locked(hw, I217_PROXY_CTRL, data: 0);
5534	}
5535	/* Enable reset on MTA */
5536	ret_val = e1e_rphy_locked(hw, I217_CGFREG, data: &phy_reg);
5537	if (ret_val)
5538	goto release;
5539	phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5540	e1e_wphy_locked(hw, I217_CGFREG, data: phy_reg);
5541	release:
5542	if (ret_val)
5543	e_dbg("Error %d in resume workarounds\n", ret_val);
5544	hw->phy.ops.release(hw);
5545	}
5546	}
5547
5548	/**
5549	* e1000_cleanup_led_ich8lan - Restore the default LED operation
5550	* @hw: pointer to the HW structure
5551	*
5552	* Return the LED back to the default configuration.
5553	**/
5554	static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5555	{
5556	if (hw->phy.type == e1000_phy_ife)
5557	return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, data: 0);
5558
5559	ew32(LEDCTL, hw->mac.ledctl_default);
5560	return 0;
5561	}
5562
5563	/**
5564	* e1000_led_on_ich8lan - Turn LEDs on
5565	* @hw: pointer to the HW structure
5566	*
5567	* Turn on the LEDs.
5568	**/
5569	static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5570	{
5571	if (hw->phy.type == e1000_phy_ife)
5572	return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5573	data: (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5574
5575	ew32(LEDCTL, hw->mac.ledctl_mode2);
5576	return 0;
5577	}
5578
5579	/**
5580	* e1000_led_off_ich8lan - Turn LEDs off
5581	* @hw: pointer to the HW structure
5582	*
5583	* Turn off the LEDs.
5584	**/
5585	static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5586	{
5587	if (hw->phy.type == e1000_phy_ife)
5588	return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5589	data: (IFE_PSCL_PROBE_MODE |
5590	IFE_PSCL_PROBE_LEDS_OFF));
5591
5592	ew32(LEDCTL, hw->mac.ledctl_mode1);
5593	return 0;
5594	}
5595
5596	/**
5597	* e1000_setup_led_pchlan - Configures SW controllable LED
5598	* @hw: pointer to the HW structure
5599	*
5600	* This prepares the SW controllable LED for use.
5601	**/
5602	static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5603	{
5604	return e1e_wphy(hw, HV_LED_CONFIG, data: (u16)hw->mac.ledctl_mode1);
5605	}
5606
5607	/**
5608	* e1000_cleanup_led_pchlan - Restore the default LED operation
5609	* @hw: pointer to the HW structure
5610	*
5611	* Return the LED back to the default configuration.
5612	**/
5613	static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5614	{
5615	return e1e_wphy(hw, HV_LED_CONFIG, data: (u16)hw->mac.ledctl_default);
5616	}
5617
5618	/**
5619	* e1000_led_on_pchlan - Turn LEDs on
5620	* @hw: pointer to the HW structure
5621	*
5622	* Turn on the LEDs.
5623	**/
5624	static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5625	{
5626	u16 data = (u16)hw->mac.ledctl_mode2;
5627	u32 i, led;
5628
5629	/* If no link, then turn LED on by setting the invert bit
5630	* for each LED that's mode is "link_up" in ledctl_mode2.
5631	*/
5632	if (!(er32(STATUS) & E1000_STATUS_LU)) {
5633	for (i = 0; i < 3; i++) {
5634	led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5635	if ((led & E1000_PHY_LED0_MODE_MASK) !=
5636	E1000_LEDCTL_MODE_LINK_UP)
5637	continue;
5638	if (led & E1000_PHY_LED0_IVRT)
5639	data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5640	else
5641	data |= (E1000_PHY_LED0_IVRT << (i * 5));
5642	}
5643	}
5644
5645	return e1e_wphy(hw, HV_LED_CONFIG, data);
5646	}
5647
5648	/**
5649	* e1000_led_off_pchlan - Turn LEDs off
5650	* @hw: pointer to the HW structure
5651	*
5652	* Turn off the LEDs.
5653	**/
5654	static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5655	{
5656	u16 data = (u16)hw->mac.ledctl_mode1;
5657	u32 i, led;
5658
5659	/* If no link, then turn LED off by clearing the invert bit
5660	* for each LED that's mode is "link_up" in ledctl_mode1.
5661	*/
5662	if (!(er32(STATUS) & E1000_STATUS_LU)) {
5663	for (i = 0; i < 3; i++) {
5664	led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5665	if ((led & E1000_PHY_LED0_MODE_MASK) !=
5666	E1000_LEDCTL_MODE_LINK_UP)
5667	continue;
5668	if (led & E1000_PHY_LED0_IVRT)
5669	data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5670	else
5671	data |= (E1000_PHY_LED0_IVRT << (i * 5));
5672	}
5673	}
5674
5675	return e1e_wphy(hw, HV_LED_CONFIG, data);
5676	}
5677
5678	/**
5679	* e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5680	* @hw: pointer to the HW structure
5681	*
5682	* Read appropriate register for the config done bit for completion status
5683	* and configure the PHY through s/w for EEPROM-less parts.
5684	*
5685	* NOTE: some silicon which is EEPROM-less will fail trying to read the
5686	* config done bit, so only an error is logged and continues. If we were
5687	* to return with error, EEPROM-less silicon would not be able to be reset
5688	* or change link.
5689	**/
5690	static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5691	{
5692	s32 ret_val = 0;
5693	u32 bank = 0;
5694	u32 status;
5695
5696	e1000e_get_cfg_done_generic(hw);
5697
5698	/* Wait for indication from h/w that it has completed basic config */
5699	if (hw->mac.type >= e1000_ich10lan) {
5700	e1000_lan_init_done_ich8lan(hw);
5701	} else {
5702	ret_val = e1000e_get_auto_rd_done(hw);
5703	if (ret_val) {
5704	/* When auto config read does not complete, do not
5705	* return with an error. This can happen in situations
5706	* where there is no eeprom and prevents getting link.
5707	*/
5708	e_dbg("Auto Read Done did not complete\n");
5709	ret_val = 0;
5710	}
5711	}
5712
5713	/* Clear PHY Reset Asserted bit */
5714	status = er32(STATUS);
5715	if (status & E1000_STATUS_PHYRA)
5716	ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5717	else
5718	e_dbg("PHY Reset Asserted not set - needs delay\n");
5719
5720	/* If EEPROM is not marked present, init the IGP 3 PHY manually */
5721	if (hw->mac.type <= e1000_ich9lan) {
5722	if (!(er32(EECD) & E1000_EECD_PRES) &&
5723	(hw->phy.type == e1000_phy_igp_3)) {
5724	e1000e_phy_init_script_igp3(hw);
5725	}
5726	} else {
5727	if (e1000_valid_nvm_bank_detect_ich8lan(hw, bank: &bank)) {
5728	/* Maybe we should do a basic PHY config */
5729	e_dbg("EEPROM not present\n");
5730	ret_val = -E1000_ERR_CONFIG;
5731	}
5732	}
5733
5734	return ret_val;
5735	}
5736
5737	/**
5738	* e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5739	* @hw: pointer to the HW structure
5740	*
5741	* In the case of a PHY power down to save power, or to turn off link during a
5742	* driver unload, or wake on lan is not enabled, remove the link.
5743	**/
5744	static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5745	{
5746	/* If the management interface is not enabled, then power down */
5747	if (!(hw->mac.ops.check_mng_mode(hw) ||
5748	hw->phy.ops.check_reset_block(hw)))
5749	e1000_power_down_phy_copper(hw);
5750	}
5751
5752	/**
5753	* e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5754	* @hw: pointer to the HW structure
5755	*
5756	* Clears hardware counters specific to the silicon family and calls
5757	* clear_hw_cntrs_generic to clear all general purpose counters.
5758	**/
5759	static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5760	{
5761	u16 phy_data;
5762	s32 ret_val;
5763
5764	e1000e_clear_hw_cntrs_base(hw);
5765
5766	er32(ALGNERRC);
5767	er32(RXERRC);
5768	er32(TNCRS);
5769	er32(CEXTERR);
5770	er32(TSCTC);
5771	er32(TSCTFC);
5772
5773	er32(MGTPRC);
5774	er32(MGTPDC);
5775	er32(MGTPTC);
5776
5777	er32(IAC);
5778	er32(ICRXOC);
5779
5780	/* Clear PHY statistics registers */
5781	if ((hw->phy.type == e1000_phy_82578) ||
5782	(hw->phy.type == e1000_phy_82579) ||
5783	(hw->phy.type == e1000_phy_i217) ||
5784	(hw->phy.type == e1000_phy_82577)) {
5785	ret_val = hw->phy.ops.acquire(hw);
5786	if (ret_val)
5787	return;
5788	ret_val = hw->phy.ops.set_page(hw,
5789	HV_STATS_PAGE << IGP_PAGE_SHIFT);
5790	if (ret_val)
5791	goto release;
5792	hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5793	hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5794	hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5795	hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5796	hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5797	hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5798	hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5799	hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5800	hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5801	hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5802	hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5803	hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5804	hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5805	hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5806	release:
5807	hw->phy.ops.release(hw);
5808	}
5809	}
5810
5811	static const struct e1000_mac_operations ich8_mac_ops = {
5812	/* check_mng_mode dependent on mac type */
5813	.check_for_link = e1000_check_for_copper_link_ich8lan,
5814	/* cleanup_led dependent on mac type */
5815	.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5816	.get_bus_info = e1000_get_bus_info_ich8lan,
5817	.set_lan_id = e1000_set_lan_id_single_port,
5818	.get_link_up_info = e1000_get_link_up_info_ich8lan,
5819	/* led_on dependent on mac type */
5820	/* led_off dependent on mac type */
5821	.update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5822	.reset_hw = e1000_reset_hw_ich8lan,
5823	.init_hw = e1000_init_hw_ich8lan,
5824	.setup_link = e1000_setup_link_ich8lan,
5825	.setup_physical_interface = e1000_setup_copper_link_ich8lan,
5826	/* id_led_init dependent on mac type */
5827	.config_collision_dist = e1000e_config_collision_dist_generic,
5828	.rar_set = e1000e_rar_set_generic,
5829	.rar_get_count = e1000e_rar_get_count_generic,
5830	};
5831
5832	static const struct e1000_phy_operations ich8_phy_ops = {
5833	.acquire = e1000_acquire_swflag_ich8lan,
5834	.check_reset_block = e1000_check_reset_block_ich8lan,
5835	.commit = NULL,
5836	.get_cfg_done = e1000_get_cfg_done_ich8lan,
5837	.get_cable_length = e1000e_get_cable_length_igp_2,
5838	.read_reg = e1000e_read_phy_reg_igp,
5839	.release = e1000_release_swflag_ich8lan,
5840	.reset = e1000_phy_hw_reset_ich8lan,
5841	.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5842	.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5843	.write_reg = e1000e_write_phy_reg_igp,
5844	};
5845
5846	static const struct e1000_nvm_operations ich8_nvm_ops = {
5847	.acquire = e1000_acquire_nvm_ich8lan,
5848	.read = e1000_read_nvm_ich8lan,
5849	.release = e1000_release_nvm_ich8lan,
5850	.reload = e1000e_reload_nvm_generic,
5851	.update = e1000_update_nvm_checksum_ich8lan,
5852	.valid_led_default = e1000_valid_led_default_ich8lan,
5853	.validate = e1000_validate_nvm_checksum_ich8lan,
5854	.write = e1000_write_nvm_ich8lan,
5855	};
5856
5857	static const struct e1000_nvm_operations spt_nvm_ops = {
5858	.acquire = e1000_acquire_nvm_ich8lan,
5859	.release = e1000_release_nvm_ich8lan,
5860	.read = e1000_read_nvm_spt,
5861	.update = e1000_update_nvm_checksum_spt,
5862	.reload = e1000e_reload_nvm_generic,
5863	.valid_led_default = e1000_valid_led_default_ich8lan,
5864	.validate = e1000_validate_nvm_checksum_ich8lan,
5865	.write = e1000_write_nvm_ich8lan,
5866	};
5867
5868	const struct e1000_info e1000_ich8_info = {
5869	.mac = e1000_ich8lan,
5870	.flags = FLAG_HAS_WOL
5871	| FLAG_IS_ICH
5872	| FLAG_HAS_CTRLEXT_ON_LOAD
5873	| FLAG_HAS_AMT
5874	| FLAG_HAS_FLASH
5875	| FLAG_APME_IN_WUC,
5876	.pba = 8,
5877	.max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5878	.get_variants = e1000_get_variants_ich8lan,
5879	.mac_ops = &ich8_mac_ops,
5880	.phy_ops = &ich8_phy_ops,
5881	.nvm_ops = &ich8_nvm_ops,
5882	};
5883
5884	const struct e1000_info e1000_ich9_info = {
5885	.mac = e1000_ich9lan,
5886	.flags = FLAG_HAS_JUMBO_FRAMES
5887	| FLAG_IS_ICH
5888	| FLAG_HAS_WOL
5889	| FLAG_HAS_CTRLEXT_ON_LOAD
5890	| FLAG_HAS_AMT
5891	| FLAG_HAS_FLASH
5892	| FLAG_APME_IN_WUC,
5893	.pba = 18,
5894	.max_hw_frame_size = DEFAULT_JUMBO,
5895	.get_variants = e1000_get_variants_ich8lan,
5896	.mac_ops = &ich8_mac_ops,
5897	.phy_ops = &ich8_phy_ops,
5898	.nvm_ops = &ich8_nvm_ops,
5899	};
5900
5901	const struct e1000_info e1000_ich10_info = {
5902	.mac = e1000_ich10lan,
5903	.flags = FLAG_HAS_JUMBO_FRAMES
5904	| FLAG_IS_ICH
5905	| FLAG_HAS_WOL
5906	| FLAG_HAS_CTRLEXT_ON_LOAD
5907	| FLAG_HAS_AMT
5908	| FLAG_HAS_FLASH
5909	| FLAG_APME_IN_WUC,
5910	.pba = 18,
5911	.max_hw_frame_size = DEFAULT_JUMBO,
5912	.get_variants = e1000_get_variants_ich8lan,
5913	.mac_ops = &ich8_mac_ops,
5914	.phy_ops = &ich8_phy_ops,
5915	.nvm_ops = &ich8_nvm_ops,
5916	};
5917
5918	const struct e1000_info e1000_pch_info = {
5919	.mac = e1000_pchlan,
5920	.flags = FLAG_IS_ICH
5921	| FLAG_HAS_WOL
5922	| FLAG_HAS_CTRLEXT_ON_LOAD
5923	| FLAG_HAS_AMT
5924	| FLAG_HAS_FLASH
5925	| FLAG_HAS_JUMBO_FRAMES
5926	| FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5927	| FLAG_APME_IN_WUC,
5928	.flags2 = FLAG2_HAS_PHY_STATS,
5929	.pba = 26,
5930	.max_hw_frame_size = 4096,
5931	.get_variants = e1000_get_variants_ich8lan,
5932	.mac_ops = &ich8_mac_ops,
5933	.phy_ops = &ich8_phy_ops,
5934	.nvm_ops = &ich8_nvm_ops,
5935	};
5936
5937	const struct e1000_info e1000_pch2_info = {
5938	.mac = e1000_pch2lan,
5939	.flags = FLAG_IS_ICH
5940	| FLAG_HAS_WOL
5941	| FLAG_HAS_HW_TIMESTAMP
5942	| FLAG_HAS_CTRLEXT_ON_LOAD
5943	| FLAG_HAS_AMT
5944	| FLAG_HAS_FLASH
5945	| FLAG_HAS_JUMBO_FRAMES
5946	| FLAG_APME_IN_WUC,
5947	.flags2 = FLAG2_HAS_PHY_STATS
5948	| FLAG2_HAS_EEE
5949	| FLAG2_CHECK_SYSTIM_OVERFLOW,
5950	.pba = 26,
5951	.max_hw_frame_size = 9022,
5952	.get_variants = e1000_get_variants_ich8lan,
5953	.mac_ops = &ich8_mac_ops,
5954	.phy_ops = &ich8_phy_ops,
5955	.nvm_ops = &ich8_nvm_ops,
5956	};
5957
5958	const struct e1000_info e1000_pch_lpt_info = {
5959	.mac = e1000_pch_lpt,
5960	.flags = FLAG_IS_ICH
5961	| FLAG_HAS_WOL
5962	| FLAG_HAS_HW_TIMESTAMP
5963	| FLAG_HAS_CTRLEXT_ON_LOAD
5964	| FLAG_HAS_AMT
5965	| FLAG_HAS_FLASH
5966	| FLAG_HAS_JUMBO_FRAMES
5967	| FLAG_APME_IN_WUC,
5968	.flags2 = FLAG2_HAS_PHY_STATS
5969	| FLAG2_HAS_EEE
5970	| FLAG2_CHECK_SYSTIM_OVERFLOW,
5971	.pba = 26,
5972	.max_hw_frame_size = 9022,
5973	.get_variants = e1000_get_variants_ich8lan,
5974	.mac_ops = &ich8_mac_ops,
5975	.phy_ops = &ich8_phy_ops,
5976	.nvm_ops = &ich8_nvm_ops,
5977	};
5978
5979	const struct e1000_info e1000_pch_spt_info = {
5980	.mac = e1000_pch_spt,
5981	.flags = FLAG_IS_ICH
5982	| FLAG_HAS_WOL
5983	| FLAG_HAS_HW_TIMESTAMP
5984	| FLAG_HAS_CTRLEXT_ON_LOAD
5985	| FLAG_HAS_AMT
5986	| FLAG_HAS_FLASH
5987	| FLAG_HAS_JUMBO_FRAMES
5988	| FLAG_APME_IN_WUC,
5989	.flags2 = FLAG2_HAS_PHY_STATS
5990	| FLAG2_HAS_EEE,
5991	.pba = 26,
5992	.max_hw_frame_size = 9022,
5993	.get_variants = e1000_get_variants_ich8lan,
5994	.mac_ops = &ich8_mac_ops,
5995	.phy_ops = &ich8_phy_ops,
5996	.nvm_ops = &spt_nvm_ops,
5997	};
5998
5999	const struct e1000_info e1000_pch_cnp_info = {
6000	.mac = e1000_pch_cnp,
6001	.flags = FLAG_IS_ICH
6002	| FLAG_HAS_WOL
6003	| FLAG_HAS_HW_TIMESTAMP
6004	| FLAG_HAS_CTRLEXT_ON_LOAD
6005	| FLAG_HAS_AMT
6006	| FLAG_HAS_FLASH
6007	| FLAG_HAS_JUMBO_FRAMES
6008	| FLAG_APME_IN_WUC,
6009	.flags2 = FLAG2_HAS_PHY_STATS
6010	| FLAG2_HAS_EEE,
6011	.pba = 26,
6012	.max_hw_frame_size = 9022,
6013	.get_variants = e1000_get_variants_ich8lan,
6014	.mac_ops = &ich8_mac_ops,
6015	.phy_ops = &ich8_phy_ops,
6016	.nvm_ops = &spt_nvm_ops,
6017	};
6018
6019	const struct e1000_info e1000_pch_tgp_info = {
6020	.mac = e1000_pch_tgp,
6021	.flags = FLAG_IS_ICH
6022	| FLAG_HAS_WOL
6023	| FLAG_HAS_HW_TIMESTAMP
6024	| FLAG_HAS_CTRLEXT_ON_LOAD
6025	| FLAG_HAS_AMT
6026	| FLAG_HAS_FLASH
6027	| FLAG_HAS_JUMBO_FRAMES
6028	| FLAG_APME_IN_WUC,
6029	.flags2 = FLAG2_HAS_PHY_STATS
6030	| FLAG2_HAS_EEE,
6031	.pba = 26,
6032	.max_hw_frame_size = 9022,
6033	.get_variants = e1000_get_variants_ich8lan,
6034	.mac_ops = &ich8_mac_ops,
6035	.phy_ops = &ich8_phy_ops,
6036	.nvm_ops = &spt_nvm_ops,
6037	};
6038
6039	const struct e1000_info e1000_pch_adp_info = {
6040	.mac = e1000_pch_adp,
6041	.flags = FLAG_IS_ICH
6042	| FLAG_HAS_WOL
6043	| FLAG_HAS_HW_TIMESTAMP
6044	| FLAG_HAS_CTRLEXT_ON_LOAD
6045	| FLAG_HAS_AMT
6046	| FLAG_HAS_FLASH
6047	| FLAG_HAS_JUMBO_FRAMES
6048	| FLAG_APME_IN_WUC,
6049	.flags2 = FLAG2_HAS_PHY_STATS
6050	| FLAG2_HAS_EEE,
6051	.pba = 26,
6052	.max_hw_frame_size = 9022,
6053	.get_variants = e1000_get_variants_ich8lan,
6054	.mac_ops = &ich8_mac_ops,
6055	.phy_ops = &ich8_phy_ops,
6056	.nvm_ops = &spt_nvm_ops,
6057	};
6058
6059	const struct e1000_info e1000_pch_mtp_info = {
6060	.mac = e1000_pch_mtp,
6061	.flags = FLAG_IS_ICH
6062	| FLAG_HAS_WOL
6063	| FLAG_HAS_HW_TIMESTAMP
6064	| FLAG_HAS_CTRLEXT_ON_LOAD
6065	| FLAG_HAS_AMT
6066	| FLAG_HAS_FLASH
6067	| FLAG_HAS_JUMBO_FRAMES
6068	| FLAG_APME_IN_WUC,
6069	.flags2 = FLAG2_HAS_PHY_STATS
6070	| FLAG2_HAS_EEE,
6071	.pba = 26,
6072	.max_hw_frame_size = 9022,
6073	.get_variants = e1000_get_variants_ich8lan,
6074	.mac_ops = &ich8_mac_ops,
6075	.phy_ops = &ich8_phy_ops,
6076	.nvm_ops = &spt_nvm_ops,
6077	};
6078