1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* Copyright (C) 2018 Microchip Technology Inc. */ |
3 | |
4 | #ifndef _LAN743X_H |
5 | #define _LAN743X_H |
6 | |
7 | #include <linux/phy.h> |
8 | #include "lan743x_ptp.h" |
9 | |
10 | #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" |
11 | #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" |
12 | #define DRIVER_NAME "lan743x" |
13 | |
14 | /* Register Definitions */ |
15 | #define ID_REV (0x00) |
16 | #define ID_REV_ID_MASK_ (0xFFFF0000) |
17 | #define ID_REV_ID_LAN7430_ (0x74300000) |
18 | #define ID_REV_ID_LAN7431_ (0x74310000) |
19 | #define ID_REV_ID_LAN743X_ (0x74300000) |
20 | #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 |
21 | #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 |
22 | #define ID_REV_ID_A0X1_ (0xA0010000) |
23 | #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ |
24 | ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ |
25 | (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) |
26 | #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) |
27 | #define ID_REV_CHIP_REV_A0_ (0x00000000) |
28 | #define ID_REV_CHIP_REV_B0_ (0x00000010) |
29 | #define ID_REV_CHIP_REV_PCI11X1X_B0_ (0x000000B0) |
30 | |
31 | #define FPGA_REV (0x04) |
32 | #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) |
33 | #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) |
34 | #define FPGA_SGMII_OP BIT(24) |
35 | |
36 | #define STRAP_READ (0x0C) |
37 | #define STRAP_READ_USE_SGMII_EN_ BIT(22) |
38 | #define STRAP_READ_SGMII_EN_ BIT(6) |
39 | #define STRAP_READ_SGMII_REFCLK_ BIT(5) |
40 | #define STRAP_READ_SGMII_2_5G_ BIT(4) |
41 | #define STRAP_READ_BASE_X_ BIT(3) |
42 | #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2) |
43 | #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1) |
44 | #define STRAP_READ_ADV_PM_DISABLE_ BIT(0) |
45 | |
46 | #define HW_CFG (0x010) |
47 | #define HW_CFG_RST_PROTECT_PCIE_ BIT(19) |
48 | #define HW_CFG_HOT_RESET_DIS_ BIT(15) |
49 | #define HW_CFG_D3_VAUX_OVR_ BIT(14) |
50 | #define HW_CFG_D3_RESET_DIS_ BIT(13) |
51 | #define HW_CFG_RST_PROTECT_ BIT(12) |
52 | #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) |
53 | #define HW_CFG_EE_OTP_RELOAD_ BIT(4) |
54 | #define HW_CFG_LRST_ BIT(1) |
55 | |
56 | #define PMT_CTL (0x014) |
57 | #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) |
58 | #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) |
59 | #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) |
60 | #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) |
61 | #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) |
62 | #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) |
63 | #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) |
64 | #define PMT_CTL_READY_ BIT(7) |
65 | #define PMT_CTL_ETH_PHY_RST_ BIT(4) |
66 | #define PMT_CTL_WOL_EN_ BIT(3) |
67 | #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) |
68 | #define PMT_CTL_WUPS_MASK_ (0x00000003) |
69 | |
70 | #define DP_SEL (0x024) |
71 | #define DP_SEL_DPRDY_ BIT(31) |
72 | #define DP_SEL_MASK_ (0x0000001F) |
73 | #define DP_SEL_RFE_RAM (0x00000001) |
74 | |
75 | #define DP_SEL_VHF_HASH_LEN (16) |
76 | #define DP_SEL_VHF_VLAN_LEN (128) |
77 | |
78 | #define DP_CMD (0x028) |
79 | #define DP_CMD_WRITE_ (0x00000001) |
80 | |
81 | #define DP_ADDR (0x02C) |
82 | |
83 | #define DP_DATA_0 (0x030) |
84 | |
85 | #define E2P_CMD (0x040) |
86 | #define E2P_CMD_EPC_BUSY_ BIT(31) |
87 | #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) |
88 | #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) |
89 | #define E2P_CMD_EPC_CMD_READ_ (0x00000000) |
90 | #define E2P_CMD_EPC_TIMEOUT_ BIT(10) |
91 | #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) |
92 | |
93 | #define E2P_DATA (0x044) |
94 | |
95 | /* Hearthstone top level & System Reg Addresses */ |
96 | #define ETH_CTRL_REG_ADDR_BASE (0x0000) |
97 | #define ETH_SYS_REG_ADDR_BASE (0x4000) |
98 | #define CONFIG_REG_ADDR_BASE (0x0000) |
99 | #define ETH_EEPROM_REG_ADDR_BASE (0x0E00) |
100 | #define ETH_OTP_REG_ADDR_BASE (0x1000) |
101 | #define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078) |
102 | #define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \ |
103 | CONFIG_REG_ADDR_BASE + \ |
104 | GEN_SYS_CONFIG_LOAD_STARTED_REG) |
105 | #define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4) |
106 | #define SYS_LOCK_REG (0x00A0) |
107 | #define SYS_LOCK_REG_MAIN_LOCK_ BIT(7) |
108 | #define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5) |
109 | #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4) |
110 | #define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3) |
111 | #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2) |
112 | #define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1) |
113 | #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0) |
114 | #define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \ |
115 | CONFIG_REG_ADDR_BASE + \ |
116 | SYS_LOCK_REG) |
117 | #define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \ |
118 | ETH_EEPROM_REG_ADDR_BASE) |
119 | #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000) |
120 | #define HS_E2P_CMD_EPC_BUSY_ BIT(31) |
121 | #define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28) |
122 | #define HS_E2P_CMD_EPC_CMD_READ_ (0x0) |
123 | #define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17) |
124 | #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0) |
125 | #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004) |
126 | #define HS_E2P_DATA_MASK_ GENMASK(7, 0) |
127 | #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008) |
128 | #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16) |
129 | #define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12) |
130 | #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8) |
131 | #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0) |
132 | #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C) |
133 | |
134 | #define GPIO_CFG0 (0x050) |
135 | #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) |
136 | #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) |
137 | |
138 | #define GPIO_CFG1 (0x054) |
139 | #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) |
140 | #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) |
141 | |
142 | #define GPIO_CFG2 (0x058) |
143 | #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) |
144 | |
145 | #define GPIO_CFG3 (0x05C) |
146 | #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) |
147 | #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) |
148 | |
149 | #define FCT_RX_CTL (0xAC) |
150 | #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) |
151 | #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) |
152 | #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) |
153 | |
154 | #define FCT_TX_CTL (0xC4) |
155 | #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) |
156 | #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) |
157 | #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) |
158 | |
159 | #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) |
160 | #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) |
161 | #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ |
162 | ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) |
163 | #define FCT_FLOW_CTL_REQ_EN_ BIT(7) |
164 | #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) |
165 | #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ |
166 | ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) |
167 | |
168 | #define MAC_CR (0x100) |
169 | #define MAC_CR_MII_EN_ BIT(19) |
170 | #define MAC_CR_EEE_EN_ BIT(17) |
171 | #define MAC_CR_ADD_ BIT(12) |
172 | #define MAC_CR_ASD_ BIT(11) |
173 | #define MAC_CR_CNTR_RST_ BIT(5) |
174 | #define MAC_CR_DPX_ BIT(3) |
175 | #define MAC_CR_CFG_H_ BIT(2) |
176 | #define MAC_CR_CFG_L_ BIT(1) |
177 | #define MAC_CR_RST_ BIT(0) |
178 | |
179 | #define MAC_RX (0x104) |
180 | #define MAC_RX_MAX_SIZE_SHIFT_ (16) |
181 | #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) |
182 | #define MAC_RX_RXD_ BIT(1) |
183 | #define MAC_RX_RXEN_ BIT(0) |
184 | |
185 | #define MAC_TX (0x108) |
186 | #define MAC_TX_TXD_ BIT(1) |
187 | #define MAC_TX_TXEN_ BIT(0) |
188 | |
189 | #define MAC_FLOW (0x10C) |
190 | #define MAC_FLOW_CR_TX_FCEN_ BIT(30) |
191 | #define MAC_FLOW_CR_RX_FCEN_ BIT(29) |
192 | #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) |
193 | |
194 | #define MAC_RX_ADDRH (0x118) |
195 | |
196 | #define MAC_RX_ADDRL (0x11C) |
197 | |
198 | #define MAC_MII_ACC (0x120) |
199 | #define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16) |
200 | #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000) |
201 | #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0) |
202 | #define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1) |
203 | #define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2) |
204 | #define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3) |
205 | #define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4) |
206 | #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) |
207 | #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) |
208 | #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) |
209 | #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) |
210 | #define MAC_MII_ACC_MII_READ_ (0x00000000) |
211 | #define MAC_MII_ACC_MII_WRITE_ (0x00000002) |
212 | #define MAC_MII_ACC_MII_BUSY_ BIT(0) |
213 | |
214 | #define MAC_MII_ACC_MIIMMD_SHIFT_ (6) |
215 | #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0) |
216 | #define MAC_MII_ACC_MIICL45_ BIT(3) |
217 | #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006) |
218 | #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000) |
219 | #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002) |
220 | #define MAC_MII_ACC_MIICMD_READ_ (0x00000004) |
221 | #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006) |
222 | |
223 | #define MAC_MII_DATA (0x124) |
224 | |
225 | #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) |
226 | |
227 | #define MAC_WUCSR (0x140) |
228 | #define MAC_MP_SO_EN_ BIT(21) |
229 | #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) |
230 | #define MAC_WUCSR_PFDA_EN_ BIT(3) |
231 | #define MAC_WUCSR_WAKE_EN_ BIT(2) |
232 | #define MAC_WUCSR_MPEN_ BIT(1) |
233 | #define MAC_WUCSR_BCST_EN_ BIT(0) |
234 | |
235 | #define MAC_WK_SRC (0x144) |
236 | #define MAC_MP_SO_HI (0x148) |
237 | #define MAC_MP_SO_LO (0x14C) |
238 | |
239 | #define MAC_WUF_CFG0 (0x150) |
240 | #define MAC_NUM_OF_WUF_CFG (32) |
241 | #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) |
242 | #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) |
243 | #define MAC_WUF_CFG_EN_ BIT(31) |
244 | #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) |
245 | #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) |
246 | #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) |
247 | #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) |
248 | |
249 | #define MAC_WUF_MASK0_0 (0x200) |
250 | #define MAC_WUF_MASK0_1 (0x204) |
251 | #define MAC_WUF_MASK0_2 (0x208) |
252 | #define MAC_WUF_MASK0_3 (0x20C) |
253 | #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) |
254 | #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) |
255 | #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) |
256 | #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) |
257 | #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) |
258 | #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) |
259 | #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) |
260 | #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) |
261 | |
262 | /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ |
263 | #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) |
264 | #define RFE_ADDR_FILT_HI_VALID_ BIT(31) |
265 | |
266 | /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ |
267 | #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) |
268 | |
269 | #define RFE_CTL (0x508) |
270 | #define RFE_CTL_TCP_UDP_COE_ BIT(12) |
271 | #define RFE_CTL_IP_COE_ BIT(11) |
272 | #define RFE_CTL_AB_ BIT(10) |
273 | #define RFE_CTL_AM_ BIT(9) |
274 | #define RFE_CTL_AU_ BIT(8) |
275 | #define RFE_CTL_MCAST_HASH_ BIT(3) |
276 | #define RFE_CTL_DA_PERFECT_ BIT(1) |
277 | |
278 | #define (0x554) |
279 | #define BIT(16) |
280 | #define BIT(15) |
281 | #define BIT(14) |
282 | #define BIT(13) |
283 | #define BIT(12) |
284 | #define BIT(11) |
285 | #define BIT(10) |
286 | #define BIT(9) |
287 | #define BIT(8) |
288 | #define (0x000000E0) |
289 | #define BIT(2) |
290 | #define BIT(1) |
291 | #define BIT(0) |
292 | |
293 | #define RFE_HASH_KEY(index) (0x558 + (index << 2)) |
294 | |
295 | #define RFE_INDX(index) (0x580 + (index << 2)) |
296 | |
297 | #define MAC_WUCSR2 (0x600) |
298 | |
299 | #define SGMII_ACC (0x720) |
300 | #define SGMII_ACC_SGMII_BZY_ BIT(31) |
301 | #define SGMII_ACC_SGMII_WR_ BIT(30) |
302 | #define SGMII_ACC_SGMII_MMD_SHIFT_ (16) |
303 | #define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16) |
304 | #define SGMII_ACC_SGMII_MMD_VSR_ BIT(15) |
305 | #define SGMII_ACC_SGMII_ADDR_SHIFT_ (0) |
306 | #define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0) |
307 | #define SGMII_DATA (0x724) |
308 | #define SGMII_DATA_SHIFT_ (0) |
309 | #define SGMII_DATA_MASK_ GENMASK(15, 0) |
310 | #define SGMII_CTL (0x728) |
311 | #define SGMII_CTL_SGMII_ENABLE_ BIT(31) |
312 | #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8) |
313 | #define SGMII_CTL_SGMII_POWER_DN_ BIT(1) |
314 | |
315 | #define MISC_CTL_0 (0x920) |
316 | #define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4) |
317 | |
318 | /* Vendor Specific SGMII MMD details */ |
319 | #define SR_VSMMD_PCS_ID1 0x0004 |
320 | #define SR_VSMMD_PCS_ID2 0x0005 |
321 | #define SR_VSMMD_STS 0x0008 |
322 | #define SR_VSMMD_CTRL 0x0009 |
323 | |
324 | #define VR_MII_DIG_CTRL1 0x8000 |
325 | #define VR_MII_DIG_CTRL1_VR_RST_ BIT(15) |
326 | #define VR_MII_DIG_CTRL1_R2TLBE_ BIT(14) |
327 | #define VR_MII_DIG_CTRL1_EN_VSMMD1_ BIT(13) |
328 | #define VR_MII_DIG_CTRL1_CS_EN_ BIT(10) |
329 | #define VR_MII_DIG_CTRL1_MAC_AUTO_SW_ BIT(9) |
330 | #define VR_MII_DIG_CTRL1_INIT_ BIT(8) |
331 | #define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4) |
332 | #define VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_ BIT(3) |
333 | #define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2) |
334 | #define VR_MII_DIG_CTRL1_BYP_PWRUP_ BIT(1) |
335 | #define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0) |
336 | #define VR_MII_AN_CTRL 0x8001 |
337 | #define VR_MII_AN_CTRL_MII_CTRL_ BIT(8) |
338 | #define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4) |
339 | #define VR_MII_AN_CTRL_TX_CONFIG_ BIT(3) |
340 | #define VR_MII_AN_CTRL_1000BASE_X_ (0) |
341 | #define VR_MII_AN_CTRL_SGMII_MODE_ (2) |
342 | #define VR_MII_AN_CTRL_QSGMII_MODE_ (3) |
343 | #define VR_MII_AN_CTRL_PCS_MODE_SHIFT_ (1) |
344 | #define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1) |
345 | #define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0) |
346 | #define VR_MII_AN_INTR_STS 0x8002 |
347 | #define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4) |
348 | #define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2) |
349 | #define VR_MII_AN_INTR_STS_1000_MBPS_ BIT(3) |
350 | #define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2) |
351 | #define VR_MII_AN_INTR_STS_10_MBPS_ (0) |
352 | #define VR_MII_AN_INTR_STS_FDX_ BIT(1) |
353 | #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0) |
354 | |
355 | #define VR_MII_LINK_TIMER_CTRL 0x800A |
356 | #define VR_MII_DIG_STS 0x8010 |
357 | #define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2) |
358 | #define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2) |
359 | #define VR_MII_GEN2_4_MPLL_CTRL0 0x8078 |
360 | #define VR_MII_MPLL_CTRL0_REF_CLK_DIV2_ BIT(12) |
361 | #define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4) |
362 | #define VR_MII_GEN2_4_MPLL_CTRL1 0x8079 |
363 | #define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0) |
364 | #define VR_MII_BAUD_RATE_3P125GBPS (3125) |
365 | #define VR_MII_BAUD_RATE_1P25GBPS (1250) |
366 | #define VR_MII_MPLL_MULTIPLIER_125 (125) |
367 | #define VR_MII_MPLL_MULTIPLIER_100 (100) |
368 | #define VR_MII_MPLL_MULTIPLIER_50 (50) |
369 | #define VR_MII_MPLL_MULTIPLIER_40 (40) |
370 | #define VR_MII_GEN2_4_MISC_CTRL1 0x809A |
371 | #define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2) |
372 | #define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2) |
373 | #define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0) |
374 | #define VR_MII_MPLL_BAUD_CLK (0) |
375 | #define VR_MII_MPLL_BAUD_CLK_DIV_2 (1) |
376 | #define VR_MII_MPLL_BAUD_CLK_DIV_4 (2) |
377 | |
378 | #define INT_STS (0x780) |
379 | #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) |
380 | #define INT_BIT_ALL_RX_ (0x0F000000) |
381 | #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) |
382 | #define INT_BIT_ALL_TX_ (0x000F0000) |
383 | #define INT_BIT_SW_GP_ BIT(9) |
384 | #define INT_BIT_1588_ BIT(7) |
385 | #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) |
386 | #define INT_BIT_MAS_ BIT(0) |
387 | |
388 | #define INT_SET (0x784) |
389 | |
390 | #define INT_EN_SET (0x788) |
391 | |
392 | #define INT_EN_CLR (0x78C) |
393 | |
394 | #define INT_STS_R2C (0x790) |
395 | |
396 | #define INT_VEC_EN_SET (0x794) |
397 | #define INT_VEC_EN_CLR (0x798) |
398 | #define INT_VEC_EN_AUTO_CLR (0x79C) |
399 | #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) |
400 | |
401 | #define INT_VEC_MAP0 (0x7A0) |
402 | #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ |
403 | (((u32)(vector)) << ((channel) << 2)) |
404 | |
405 | #define INT_VEC_MAP1 (0x7A4) |
406 | #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ |
407 | (((u32)(vector)) << ((channel) << 2)) |
408 | |
409 | #define INT_VEC_MAP2 (0x7A8) |
410 | |
411 | #define INT_MOD_MAP0 (0x7B0) |
412 | |
413 | #define INT_MOD_MAP1 (0x7B4) |
414 | |
415 | #define INT_MOD_MAP2 (0x7B8) |
416 | |
417 | #define INT_MOD_CFG0 (0x7C0) |
418 | #define INT_MOD_CFG1 (0x7C4) |
419 | #define INT_MOD_CFG2 (0x7C8) |
420 | #define INT_MOD_CFG3 (0x7CC) |
421 | #define INT_MOD_CFG4 (0x7D0) |
422 | #define INT_MOD_CFG5 (0x7D4) |
423 | #define INT_MOD_CFG6 (0x7D8) |
424 | #define INT_MOD_CFG7 (0x7DC) |
425 | #define INT_MOD_CFG8 (0x7E0) |
426 | #define INT_MOD_CFG9 (0x7E4) |
427 | |
428 | #define PTP_CMD_CTL (0x0A00) |
429 | #define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13) |
430 | #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) |
431 | #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) |
432 | #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) |
433 | #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) |
434 | #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) |
435 | #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) |
436 | #define PTP_CMD_CTL_PTP_RESET_ BIT(0) |
437 | #define PTP_GENERAL_CONFIG (0x0A04) |
438 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ |
439 | (0x7 << (1 + ((channel) << 2))) |
440 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) |
441 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) |
442 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) |
443 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) |
444 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) |
445 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) |
446 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) |
447 | #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ |
448 | (((value) & 0x7) << (1 + ((channel) << 2))) |
449 | #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) |
450 | |
451 | #define HS_PTP_GENERAL_CONFIG (0x0A04) |
452 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ |
453 | (0xf << (4 + ((channel) << 2))) |
454 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) |
455 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1) |
456 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2) |
457 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3) |
458 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4) |
459 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5) |
460 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6) |
461 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7) |
462 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8) |
463 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9) |
464 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10) |
465 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11) |
466 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12) |
467 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13) |
468 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14) |
469 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15) |
470 | #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ |
471 | (((value) & 0xf) << (4 + ((channel) << 2))) |
472 | #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) |
473 | #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) |
474 | |
475 | #define PTP_INT_STS (0x0A08) |
476 | #define PTP_INT_IO_FE_MASK_ GENMASK(31, 24) |
477 | #define PTP_INT_IO_FE_SHIFT_ (24) |
478 | #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) |
479 | #define PTP_INT_IO_RE_MASK_ GENMASK(23, 16) |
480 | #define PTP_INT_IO_RE_SHIFT_ (16) |
481 | #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) |
482 | #define PTP_INT_TX_TS_OVRFL_INT_ BIT(14) |
483 | #define PTP_INT_TX_SWTS_ERR_INT_ BIT(13) |
484 | #define PTP_INT_TX_TS_INT_ BIT(12) |
485 | #define PTP_INT_RX_TS_OVRFL_INT_ BIT(9) |
486 | #define PTP_INT_RX_TS_INT_ BIT(8) |
487 | #define PTP_INT_TIMER_INT_B_ BIT(1) |
488 | #define PTP_INT_TIMER_INT_A_ BIT(0) |
489 | #define PTP_INT_EN_SET (0x0A0C) |
490 | #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) |
491 | #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) |
492 | #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) |
493 | #define PTP_INT_EN_CLR (0x0A10) |
494 | #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) |
495 | #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) |
496 | #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) |
497 | #define PTP_INT_BIT_TX_TS_ BIT(12) |
498 | #define PTP_INT_BIT_TIMER_B_ BIT(1) |
499 | #define PTP_INT_BIT_TIMER_A_ BIT(0) |
500 | |
501 | #define PTP_CLOCK_SEC (0x0A14) |
502 | #define PTP_CLOCK_NS (0x0A18) |
503 | #define PTP_CLOCK_SUBNS (0x0A1C) |
504 | #define PTP_CLOCK_RATE_ADJ (0x0A20) |
505 | #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) |
506 | #define PTP_CLOCK_STEP_ADJ (0x0A2C) |
507 | #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) |
508 | #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) |
509 | #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) |
510 | #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) |
511 | #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) |
512 | #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) |
513 | #define PTP_LTC_SET_SEC_HI (0x0A50) |
514 | #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) |
515 | #define PTP_VERSION (0x0A54) |
516 | #define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24) |
517 | #define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16) |
518 | #define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8) |
519 | #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0) |
520 | #define PTP_IO_SEL (0x0A58) |
521 | #define PTP_IO_SEL_MASK_ GENMASK(10, 8) |
522 | #define PTP_IO_SEL_SHIFT_ (8) |
523 | #define PTP_LATENCY (0x0A5C) |
524 | #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) |
525 | #define PTP_LATENCY_RX_SET_(rx_latency) \ |
526 | (((u32)(rx_latency)) & 0x0000FFFF) |
527 | #define PTP_CAP_INFO (0x0A60) |
528 | #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) |
529 | #define PTP_RX_TS_CFG (0x0A68) |
530 | #define PTP_RX_TS_CFG_EVENT_MSGS_ GENMASK(3, 0) |
531 | |
532 | #define PTP_TX_MOD (0x0AA4) |
533 | #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) |
534 | |
535 | #define PTP_TX_MOD2 (0x0AA8) |
536 | #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) |
537 | |
538 | #define PTP_TX_EGRESS_SEC (0x0AAC) |
539 | #define PTP_TX_EGRESS_NS (0x0AB0) |
540 | #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) |
541 | #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) |
542 | #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) |
543 | #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) |
544 | |
545 | #define (0x0AB4) |
546 | #define (0x000F0000) |
547 | #define (0x00000000) |
548 | |
549 | #define PTP_TX_CAP_INFO (0x0AB8) |
550 | #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0) |
551 | #define PTP_TX_DOMAIN (0x0ABC) |
552 | #define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16) |
553 | #define PTP_TX_DOMAIN_RANGE_EN_ BIT(15) |
554 | #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0) |
555 | #define PTP_TX_SDOID (0x0AC0) |
556 | #define PTP_TX_SDOID_MASK_ GENMASK(23, 16) |
557 | #define PTP_TX_SDOID_RANGE_EN_ BIT(15) |
558 | #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0) |
559 | #define PTP_IO_CAP_CONFIG (0x0AC4) |
560 | #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) |
561 | #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) |
562 | #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) |
563 | #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) |
564 | #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8) |
565 | #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC) |
566 | #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0) |
567 | #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4) |
568 | #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8) |
569 | #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) |
570 | #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) |
571 | #define PTP_IO_PIN_CFG (0x0ADC) |
572 | #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) |
573 | #define PTP_LTC_RD_SEC_HI (0x0AF0) |
574 | #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) |
575 | #define PTP_LTC_RD_SEC_LO (0x0AF4) |
576 | #define PTP_LTC_RD_NS (0x0AF8) |
577 | #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0) |
578 | #define PTP_LTC_RD_SUBNS (0x0AFC) |
579 | #define PTP_RX_USER_MAC_HI (0x0B00) |
580 | #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) |
581 | #define PTP_RX_USER_MAC_LO (0x0B04) |
582 | #define PTP_RX_USER_IP_ADDR_0 (0x0B20) |
583 | #define PTP_RX_USER_IP_ADDR_1 (0x0B24) |
584 | #define PTP_RX_USER_IP_ADDR_2 (0x0B28) |
585 | #define PTP_RX_USER_IP_ADDR_3 (0x0B2C) |
586 | #define PTP_RX_USER_IP_MASK_0 (0x0B30) |
587 | #define PTP_RX_USER_IP_MASK_1 (0x0B34) |
588 | #define PTP_RX_USER_IP_MASK_2 (0x0B38) |
589 | #define PTP_RX_USER_IP_MASK_3 (0x0B3C) |
590 | #define PTP_TX_USER_MAC_HI (0x0B40) |
591 | #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) |
592 | #define PTP_TX_USER_MAC_LO (0x0B44) |
593 | #define PTP_TX_USER_IP_ADDR_0 (0x0B60) |
594 | #define PTP_TX_USER_IP_ADDR_1 (0x0B64) |
595 | #define PTP_TX_USER_IP_ADDR_2 (0x0B68) |
596 | #define PTP_TX_USER_IP_ADDR_3 (0x0B6C) |
597 | #define PTP_TX_USER_IP_MASK_0 (0x0B70) |
598 | #define PTP_TX_USER_IP_MASK_1 (0x0B74) |
599 | #define PTP_TX_USER_IP_MASK_2 (0x0B78) |
600 | #define PTP_TX_USER_IP_MASK_3 (0x0B7C) |
601 | |
602 | #define DMAC_CFG (0xC00) |
603 | #define DMAC_CFG_COAL_EN_ BIT(16) |
604 | #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) |
605 | #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) |
606 | #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ |
607 | ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) |
608 | #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) |
609 | #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) |
610 | #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) |
611 | #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) |
612 | |
613 | #define DMAC_COAL_CFG (0xC04) |
614 | #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) |
615 | #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ |
616 | ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) |
617 | #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) |
618 | #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) |
619 | #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) |
620 | #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) |
621 | #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) |
622 | #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ |
623 | ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) |
624 | #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) |
625 | #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ |
626 | (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) |
627 | |
628 | #define DMAC_OBFF_CFG (0xC08) |
629 | #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) |
630 | #define DMAC_OBFF_TX_THRES_SET_(val) \ |
631 | ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) |
632 | #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) |
633 | #define DMAC_OBFF_RX_THRES_SET_(val) \ |
634 | (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) |
635 | |
636 | #define DMAC_CMD (0xC0C) |
637 | #define DMAC_CMD_SWR_ BIT(31) |
638 | #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) |
639 | #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) |
640 | #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) |
641 | #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) |
642 | #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) |
643 | #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) |
644 | |
645 | #define DMAC_INT_STS (0xC10) |
646 | #define DMAC_INT_EN_SET (0xC14) |
647 | #define DMAC_INT_EN_CLR (0xC18) |
648 | #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) |
649 | #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) |
650 | |
651 | #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) |
652 | #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) |
653 | #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) |
654 | #define RX_CFG_A_RX_WB_THRES_SET_(val) \ |
655 | ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) |
656 | #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) |
657 | #define RX_CFG_A_RX_PF_THRES_SET_(val) \ |
658 | ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) |
659 | #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) |
660 | #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ |
661 | ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) |
662 | #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) |
663 | |
664 | #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) |
665 | #define RX_CFG_B_TS_ALL_RX_ BIT(29) |
666 | #define RX_CFG_B_TS_DESCR_EN_ BIT(28) |
667 | #define RX_CFG_B_TS_NONE_ 0 |
668 | #define RX_CFG_B_TS_MASK_ (0xCFFFFFFF) |
669 | #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) |
670 | #define RX_CFG_B_RX_PAD_0_ (0x00000000) |
671 | #define RX_CFG_B_RX_PAD_2_ (0x02000000) |
672 | #define RX_CFG_B_RDMABL_512_ (0x00040000) |
673 | #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) |
674 | |
675 | #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) |
676 | |
677 | #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) |
678 | |
679 | #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) |
680 | |
681 | #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) |
682 | |
683 | #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) |
684 | |
685 | #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) |
686 | #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) |
687 | #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) |
688 | |
689 | #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) |
690 | #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) |
691 | #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) |
692 | #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) |
693 | #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) |
694 | |
695 | #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) |
696 | #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) |
697 | #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) |
698 | #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) |
699 | #define TX_CFG_A_TX_PF_THRES_SET_(value) \ |
700 | ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) |
701 | #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) |
702 | #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ |
703 | ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) |
704 | #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) |
705 | #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) |
706 | #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ |
707 | (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) |
708 | |
709 | #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) |
710 | #define TX_CFG_B_TDMABL_512_ (0x00040000) |
711 | #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) |
712 | |
713 | #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) |
714 | |
715 | #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) |
716 | |
717 | #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) |
718 | |
719 | #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) |
720 | |
721 | #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) |
722 | |
723 | #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) |
724 | #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) |
725 | #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) |
726 | #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) |
727 | |
728 | #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) |
729 | #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) |
730 | #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) |
731 | #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) |
732 | #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) |
733 | #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) |
734 | |
735 | #define OTP_PWR_DN (0x1000) |
736 | #define OTP_PWR_DN_PWRDN_N_ BIT(0) |
737 | |
738 | #define OTP_ADDR_HIGH (0x1004) |
739 | #define OTP_ADDR_LOW (0x1008) |
740 | |
741 | #define OTP_PRGM_DATA (0x1010) |
742 | |
743 | #define OTP_PRGM_MODE (0x1014) |
744 | #define OTP_PRGM_MODE_BYTE_ BIT(0) |
745 | |
746 | #define OTP_READ_DATA (0x1018) |
747 | |
748 | #define OTP_FUNC_CMD (0x1020) |
749 | #define OTP_FUNC_CMD_READ_ BIT(0) |
750 | |
751 | #define OTP_TST_CMD (0x1024) |
752 | #define OTP_TST_CMD_PRGVRFY_ BIT(3) |
753 | |
754 | #define OTP_CMD_GO (0x1028) |
755 | #define OTP_CMD_GO_GO_ BIT(0) |
756 | |
757 | #define OTP_STATUS (0x1030) |
758 | #define OTP_STATUS_BUSY_ BIT(0) |
759 | |
760 | /* Hearthstone OTP block registers */ |
761 | #define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \ |
762 | ETH_OTP_REG_ADDR_BASE) |
763 | #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0) |
764 | #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4) |
765 | #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8) |
766 | #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10) |
767 | #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14) |
768 | #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18) |
769 | #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20) |
770 | #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24) |
771 | #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28) |
772 | #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30) |
773 | |
774 | /* MAC statistics registers */ |
775 | #define STAT_RX_FCS_ERRORS (0x1200) |
776 | #define STAT_RX_ALIGNMENT_ERRORS (0x1204) |
777 | #define STAT_RX_FRAGMENT_ERRORS (0x1208) |
778 | #define STAT_RX_JABBER_ERRORS (0x120C) |
779 | #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) |
780 | #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) |
781 | #define STAT_RX_DROPPED_FRAMES (0x1218) |
782 | #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) |
783 | #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) |
784 | #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) |
785 | #define STAT_RX_UNICAST_FRAMES (0x1228) |
786 | #define STAT_RX_BROADCAST_FRAMES (0x122C) |
787 | #define STAT_RX_MULTICAST_FRAMES (0x1230) |
788 | #define STAT_RX_PAUSE_FRAMES (0x1234) |
789 | #define STAT_RX_64_BYTE_FRAMES (0x1238) |
790 | #define STAT_RX_65_127_BYTE_FRAMES (0x123C) |
791 | #define STAT_RX_128_255_BYTE_FRAMES (0x1240) |
792 | #define STAT_RX_256_511_BYTES_FRAMES (0x1244) |
793 | #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) |
794 | #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) |
795 | #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) |
796 | #define STAT_RX_TOTAL_FRAMES (0x1254) |
797 | #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) |
798 | #define STAT_EEE_RX_LPI_TIME (0x125C) |
799 | #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) |
800 | |
801 | #define STAT_TX_FCS_ERRORS (0x1280) |
802 | #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) |
803 | #define STAT_TX_CARRIER_ERRORS (0x1288) |
804 | #define STAT_TX_BAD_BYTE_COUNT (0x128C) |
805 | #define STAT_TX_SINGLE_COLLISIONS (0x1290) |
806 | #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) |
807 | #define STAT_TX_EXCESSIVE_COLLISION (0x1298) |
808 | #define STAT_TX_LATE_COLLISIONS (0x129C) |
809 | #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) |
810 | #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) |
811 | #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) |
812 | #define STAT_TX_UNICAST_FRAMES (0x12AC) |
813 | #define STAT_TX_BROADCAST_FRAMES (0x12B0) |
814 | #define STAT_TX_MULTICAST_FRAMES (0x12B4) |
815 | #define STAT_TX_PAUSE_FRAMES (0x12B8) |
816 | #define STAT_TX_64_BYTE_FRAMES (0x12BC) |
817 | #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) |
818 | #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) |
819 | #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) |
820 | #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) |
821 | #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) |
822 | #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) |
823 | #define STAT_TX_TOTAL_FRAMES (0x12D8) |
824 | #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) |
825 | #define STAT_EEE_TX_LPI_TIME (0x12E0) |
826 | #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) |
827 | |
828 | /* End of Register definitions */ |
829 | |
830 | #define LAN743X_MAX_RX_CHANNELS (4) |
831 | #define LAN743X_MAX_TX_CHANNELS (1) |
832 | #define PCI11X1X_MAX_TX_CHANNELS (4) |
833 | struct lan743x_adapter; |
834 | |
835 | #define LAN743X_USED_RX_CHANNELS (4) |
836 | #define LAN743X_USED_TX_CHANNELS (1) |
837 | #define PCI11X1X_USED_TX_CHANNELS (4) |
838 | #define LAN743X_INT_MOD (400) |
839 | |
840 | #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) |
841 | #error Invalid LAN743X_USED_RX_CHANNELS |
842 | #endif |
843 | #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) |
844 | #error Invalid LAN743X_USED_TX_CHANNELS |
845 | #endif |
846 | #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) |
847 | #error Invalid PCI11X1X_USED_TX_CHANNELS |
848 | #endif |
849 | |
850 | /* PCI */ |
851 | /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ |
852 | #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR |
853 | #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) |
854 | #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) |
855 | #define PCI_DEVICE_ID_SMSC_A011 (0xA011) |
856 | #define PCI_DEVICE_ID_SMSC_A041 (0xA041) |
857 | |
858 | #define PCI_CONFIG_LENGTH (0x1000) |
859 | |
860 | /* CSR */ |
861 | #define CSR_LENGTH (0x2000) |
862 | |
863 | #define LAN743X_CSR_FLAG_IS_A0 BIT(0) |
864 | #define LAN743X_CSR_FLAG_IS_B0 BIT(1) |
865 | #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) |
866 | |
867 | struct lan743x_csr { |
868 | u32 flags; |
869 | u8 __iomem *csr_address; |
870 | u32 id_rev; |
871 | u32 fpga_rev; |
872 | }; |
873 | |
874 | /* INTERRUPTS */ |
875 | typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); |
876 | |
877 | #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) |
878 | #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) |
879 | #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) |
880 | #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) |
881 | #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) |
882 | #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) |
883 | #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) |
884 | #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) |
885 | #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) |
886 | #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) |
887 | #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) |
888 | #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) |
889 | #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) |
890 | #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) |
891 | #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) |
892 | #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) |
893 | |
894 | struct lan743x_vector { |
895 | int irq; |
896 | u32 flags; |
897 | struct lan743x_adapter *adapter; |
898 | int vector_index; |
899 | u32 int_mask; |
900 | lan743x_vector_handler handler; |
901 | void *context; |
902 | }; |
903 | |
904 | #define LAN743X_MAX_VECTOR_COUNT (8) |
905 | #define PCI11X1X_MAX_VECTOR_COUNT (16) |
906 | |
907 | struct lan743x_intr { |
908 | int flags; |
909 | |
910 | unsigned int irq; |
911 | |
912 | struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT]; |
913 | int number_of_vectors; |
914 | bool using_vectors; |
915 | |
916 | bool software_isr_flag; |
917 | wait_queue_head_t software_isr_wq; |
918 | }; |
919 | |
920 | #define LAN743X_MAX_FRAME_SIZE (9 * 1024) |
921 | |
922 | /* PHY */ |
923 | struct lan743x_phy { |
924 | bool fc_autoneg; |
925 | u8 fc_request_control; |
926 | }; |
927 | |
928 | /* TX */ |
929 | struct lan743x_tx_descriptor; |
930 | struct lan743x_tx_buffer_info; |
931 | |
932 | #define GPIO_QUEUE_STARTED (0) |
933 | #define GPIO_TX_FUNCTION (1) |
934 | #define GPIO_TX_COMPLETION (2) |
935 | #define GPIO_TX_FRAGMENT (3) |
936 | |
937 | #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) |
938 | |
939 | #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) |
940 | #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) |
941 | |
942 | struct lan743x_tx { |
943 | struct lan743x_adapter *adapter; |
944 | u32 ts_flags; |
945 | u32 vector_flags; |
946 | int channel_number; |
947 | |
948 | int ring_size; |
949 | size_t ring_allocation_size; |
950 | struct lan743x_tx_descriptor *ring_cpu_ptr; |
951 | dma_addr_t ring_dma_ptr; |
952 | /* ring_lock: used to prevent concurrent access to tx ring */ |
953 | spinlock_t ring_lock; |
954 | u32 frame_flags; |
955 | u32 frame_first; |
956 | u32 frame_data0; |
957 | u32 frame_tail; |
958 | |
959 | struct lan743x_tx_buffer_info *buffer_info; |
960 | |
961 | __le32 *head_cpu_ptr; |
962 | dma_addr_t head_dma_ptr; |
963 | int last_head; |
964 | int last_tail; |
965 | |
966 | struct napi_struct napi; |
967 | u32 frame_count; |
968 | u32 rqd_descriptors; |
969 | }; |
970 | |
971 | void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, |
972 | bool enable_timestamping, |
973 | bool enable_onestep_sync); |
974 | |
975 | /* RX */ |
976 | struct lan743x_rx_descriptor; |
977 | struct lan743x_rx_buffer_info; |
978 | |
979 | struct lan743x_rx { |
980 | struct lan743x_adapter *adapter; |
981 | u32 vector_flags; |
982 | int channel_number; |
983 | |
984 | int ring_size; |
985 | size_t ring_allocation_size; |
986 | struct lan743x_rx_descriptor *ring_cpu_ptr; |
987 | dma_addr_t ring_dma_ptr; |
988 | |
989 | struct lan743x_rx_buffer_info *buffer_info; |
990 | |
991 | __le32 *head_cpu_ptr; |
992 | dma_addr_t head_dma_ptr; |
993 | u32 last_head; |
994 | u32 last_tail; |
995 | |
996 | struct napi_struct napi; |
997 | |
998 | u32 frame_count; |
999 | |
1000 | struct sk_buff *skb_head, *skb_tail; |
1001 | }; |
1002 | |
1003 | int lan743x_rx_set_tstamp_mode(struct lan743x_adapter *adapter, |
1004 | int rx_filter); |
1005 | |
1006 | /* SGMII Link Speed Duplex status */ |
1007 | enum lan743x_sgmii_lsd { |
1008 | POWER_DOWN = 0, |
1009 | LINK_DOWN, |
1010 | ANEG_BUSY, |
1011 | LINK_10HD, |
1012 | LINK_10FD, |
1013 | LINK_100HD, |
1014 | LINK_100FD, |
1015 | LINK_1000_MASTER, |
1016 | LINK_1000_SLAVE, |
1017 | LINK_2500_MASTER, |
1018 | LINK_2500_SLAVE |
1019 | }; |
1020 | |
1021 | struct lan743x_adapter { |
1022 | struct net_device *netdev; |
1023 | struct mii_bus *mdiobus; |
1024 | int msg_enable; |
1025 | #ifdef CONFIG_PM |
1026 | u32 wolopts; |
1027 | u8 sopass[SOPASS_MAX]; |
1028 | #endif |
1029 | struct pci_dev *pdev; |
1030 | struct lan743x_csr csr; |
1031 | struct lan743x_intr intr; |
1032 | |
1033 | struct lan743x_gpio gpio; |
1034 | struct lan743x_ptp ptp; |
1035 | |
1036 | u8 mac_address[ETH_ALEN]; |
1037 | |
1038 | struct lan743x_phy phy; |
1039 | struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; |
1040 | struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; |
1041 | bool is_pci11x1x; |
1042 | bool is_sgmii_en; |
1043 | /* protect ethernet syslock */ |
1044 | spinlock_t eth_syslock_spinlock; |
1045 | bool eth_syslock_en; |
1046 | u32 eth_syslock_acquire_cnt; |
1047 | struct mutex sgmii_rw_lock; |
1048 | /* SGMII Link Speed & Duplex status */ |
1049 | enum lan743x_sgmii_lsd sgmii_lsd; |
1050 | u8 max_tx_channels; |
1051 | u8 used_tx_channels; |
1052 | u8 max_vector_count; |
1053 | |
1054 | #define LAN743X_ADAPTER_FLAG_OTP BIT(0) |
1055 | u32 flags; |
1056 | u32 hw_cfg; |
1057 | phy_interface_t phy_interface; |
1058 | }; |
1059 | |
1060 | #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) |
1061 | |
1062 | #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) |
1063 | #define INTR_FLAG_MSI_ENABLED BIT(8) |
1064 | #define INTR_FLAG_MSIX_ENABLED BIT(9) |
1065 | |
1066 | #define MAC_MII_READ 1 |
1067 | #define MAC_MII_WRITE 0 |
1068 | |
1069 | #define PHY_FLAG_OPENED BIT(0) |
1070 | #define PHY_FLAG_ATTACHED BIT(1) |
1071 | |
1072 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
1073 | #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) |
1074 | #else |
1075 | #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) |
1076 | #endif |
1077 | #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) |
1078 | #define DMA_DESCRIPTOR_SPACING_16 (16) |
1079 | #define DMA_DESCRIPTOR_SPACING_32 (32) |
1080 | #define DMA_DESCRIPTOR_SPACING_64 (64) |
1081 | #define DMA_DESCRIPTOR_SPACING_128 (128) |
1082 | #define DEFAULT_DMA_DESCRIPTOR_SPACING (DMA_DESCRIPTOR_SPACING_16) |
1083 | |
1084 | #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ |
1085 | (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) |
1086 | #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) |
1087 | #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) |
1088 | #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) |
1089 | #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) |
1090 | |
1091 | /* TX Descriptor bits */ |
1092 | #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) |
1093 | #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) |
1094 | #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) |
1095 | #define TX_DESC_DATA0_FS_ (0x20000000) |
1096 | #define TX_DESC_DATA0_LS_ (0x10000000) |
1097 | #define TX_DESC_DATA0_EXT_ (0x08000000) |
1098 | #define TX_DESC_DATA0_IOC_ (0x04000000) |
1099 | #define TX_DESC_DATA0_ICE_ (0x00400000) |
1100 | #define TX_DESC_DATA0_IPE_ (0x00200000) |
1101 | #define TX_DESC_DATA0_TPE_ (0x00100000) |
1102 | #define TX_DESC_DATA0_FCS_ (0x00020000) |
1103 | #define TX_DESC_DATA0_TSE_ (0x00010000) |
1104 | #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) |
1105 | #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) |
1106 | #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) |
1107 | #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) |
1108 | |
1109 | struct lan743x_tx_descriptor { |
1110 | __le32 data0; |
1111 | __le32 data1; |
1112 | __le32 data2; |
1113 | __le32 data3; |
1114 | } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); |
1115 | |
1116 | #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) |
1117 | #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) |
1118 | #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) |
1119 | #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) |
1120 | struct lan743x_tx_buffer_info { |
1121 | int flags; |
1122 | struct sk_buff *skb; |
1123 | dma_addr_t dma_ptr; |
1124 | unsigned int buffer_length; |
1125 | }; |
1126 | |
1127 | #define LAN743X_TX_RING_SIZE (128) |
1128 | |
1129 | /* OWN bit is set. ie, Descs are owned by RX DMAC */ |
1130 | #define RX_DESC_DATA0_OWN_ (0x00008000) |
1131 | /* OWN bit is clear. ie, Descs are owned by host */ |
1132 | #define RX_DESC_DATA0_FS_ (0x80000000) |
1133 | #define RX_DESC_DATA0_LS_ (0x40000000) |
1134 | #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) |
1135 | #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ |
1136 | (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) |
1137 | #define RX_DESC_DATA0_EXT_ (0x00004000) |
1138 | #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) |
1139 | #define RX_DESC_DATA1_STATUS_ICE_ (0x00020000) |
1140 | #define RX_DESC_DATA1_STATUS_TCE_ (0x00010000) |
1141 | #define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001) |
1142 | #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) |
1143 | |
1144 | #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) |
1145 | #error NET_IP_ALIGN must be 0 or 2 |
1146 | #endif |
1147 | |
1148 | #define RX_HEAD_PADDING NET_IP_ALIGN |
1149 | |
1150 | struct lan743x_rx_descriptor { |
1151 | __le32 data0; |
1152 | __le32 data1; |
1153 | __le32 data2; |
1154 | __le32 data3; |
1155 | } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); |
1156 | |
1157 | #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) |
1158 | struct lan743x_rx_buffer_info { |
1159 | int flags; |
1160 | struct sk_buff *skb; |
1161 | |
1162 | dma_addr_t dma_ptr; |
1163 | unsigned int buffer_length; |
1164 | }; |
1165 | |
1166 | #define LAN743X_RX_RING_SIZE (128) |
1167 | |
1168 | #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) |
1169 | #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) |
1170 | |
1171 | u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); |
1172 | void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); |
1173 | int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout); |
1174 | void lan743x_hs_syslock_release(struct lan743x_adapter *adapter); |
1175 | void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter, |
1176 | bool tx_enable, bool rx_enable); |
1177 | int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr); |
1178 | |
1179 | #endif /* _LAN743X_H */ |
1180 | |