1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7*******************************************************************************/
8
9#ifndef __STMMAC_H__
10#define __STMMAC_H__
11
12#define STMMAC_RESOURCE_NAME "stmmaceth"
13
14#include <linux/clk.h>
15#include <linux/hrtimer.h>
16#include <linux/if_vlan.h>
17#include <linux/stmmac.h>
18#include <linux/phylink.h>
19#include <linux/pci.h>
20#include "common.h"
21#include <linux/ptp_clock_kernel.h>
22#include <linux/net_tstamp.h>
23#include <linux/reset.h>
24#include <net/page_pool/types.h>
25#include <net/xdp.h>
26#include <uapi/linux/bpf.h>
27
28struct stmmac_resources {
29 void __iomem *addr;
30 u8 mac[ETH_ALEN];
31 int wol_irq;
32 int lpi_irq;
33 int irq;
34 int sfty_irq;
35 int sfty_ce_irq;
36 int sfty_ue_irq;
37 int rx_irq[MTL_MAX_RX_QUEUES];
38 int tx_irq[MTL_MAX_TX_QUEUES];
39};
40
41enum stmmac_txbuf_type {
42 STMMAC_TXBUF_T_SKB,
43 STMMAC_TXBUF_T_XDP_TX,
44 STMMAC_TXBUF_T_XDP_NDO,
45 STMMAC_TXBUF_T_XSK_TX,
46};
47
48struct stmmac_tx_info {
49 dma_addr_t buf;
50 bool map_as_page;
51 unsigned len;
52 bool last_segment;
53 bool is_jumbo;
54 enum stmmac_txbuf_type buf_type;
55 struct xsk_tx_metadata_compl xsk_meta;
56};
57
58#define STMMAC_TBS_AVAIL BIT(0)
59#define STMMAC_TBS_EN BIT(1)
60
61/* Frequently used values are kept adjacent for cache effect */
62struct stmmac_tx_queue {
63 u32 tx_count_frames;
64 int tbs;
65 struct hrtimer txtimer;
66 u32 queue_index;
67 struct stmmac_priv *priv_data;
68 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
69 struct dma_edesc *dma_entx;
70 struct dma_desc *dma_tx;
71 union {
72 struct sk_buff **tx_skbuff;
73 struct xdp_frame **xdpf;
74 };
75 struct stmmac_tx_info *tx_skbuff_dma;
76 struct xsk_buff_pool *xsk_pool;
77 u32 xsk_frames_done;
78 unsigned int cur_tx;
79 unsigned int dirty_tx;
80 dma_addr_t dma_tx_phy;
81 dma_addr_t tx_tail_addr;
82 u32 mss;
83};
84
85struct stmmac_rx_buffer {
86 union {
87 struct {
88 struct page *page;
89 dma_addr_t addr;
90 __u32 page_offset;
91 };
92 struct xdp_buff *xdp;
93 };
94 struct page *sec_page;
95 dma_addr_t sec_addr;
96};
97
98struct stmmac_xdp_buff {
99 struct xdp_buff xdp;
100 struct stmmac_priv *priv;
101 struct dma_desc *desc;
102 struct dma_desc *ndesc;
103};
104
105struct stmmac_metadata_request {
106 struct stmmac_priv *priv;
107 struct dma_desc *tx_desc;
108 bool *set_ic;
109 struct dma_edesc *edesc;
110 int tbs;
111};
112
113struct stmmac_xsk_tx_complete {
114 struct stmmac_priv *priv;
115 struct dma_desc *desc;
116};
117
118struct stmmac_rx_queue {
119 u32 rx_count_frames;
120 u32 queue_index;
121 struct xdp_rxq_info xdp_rxq;
122 struct xsk_buff_pool *xsk_pool;
123 struct page_pool *page_pool;
124 struct stmmac_rx_buffer *buf_pool;
125 struct stmmac_priv *priv_data;
126 struct dma_extended_desc *dma_erx;
127 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
128 unsigned int cur_rx;
129 unsigned int dirty_rx;
130 unsigned int buf_alloc_num;
131 unsigned int napi_skb_frag_size;
132 dma_addr_t dma_rx_phy;
133 u32 rx_tail_addr;
134 unsigned int state_saved;
135 struct {
136 struct sk_buff *skb;
137 unsigned int len;
138 unsigned int error;
139 } state;
140};
141
142struct stmmac_channel {
143 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
144 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
145 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
146 struct stmmac_priv *priv_data;
147 spinlock_t lock;
148 u32 index;
149};
150
151struct stmmac_fpe_cfg {
152 struct ethtool_mmsv mmsv;
153 const struct stmmac_fpe_reg *reg;
154 u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */
155};
156
157struct stmmac_tc_entry {
158 bool in_use;
159 bool in_hw;
160 bool is_last;
161 bool is_frag;
162 void *frag_ptr;
163 unsigned int table_pos;
164 u32 handle;
165 u32 prio;
166 struct {
167 u32 match_data;
168 u32 match_en;
169 u8 af:1;
170 u8 rf:1;
171 u8 im:1;
172 u8 nc:1;
173 u8 res1:4;
174 u8 frame_offset;
175 u8 ok_index;
176 u8 dma_ch_no;
177 u32 res2;
178 } __packed val;
179};
180
181#define STMMAC_PPS_MAX 4
182struct stmmac_pps_cfg {
183 bool available;
184 struct timespec64 start;
185 struct timespec64 period;
186};
187
188struct stmmac_rss {
189 int enable;
190 u8 key[STMMAC_RSS_HASH_KEY_SIZE];
191 u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
192};
193
194#define STMMAC_FLOW_ACTION_DROP BIT(0)
195struct stmmac_flow_entry {
196 unsigned long cookie;
197 unsigned long action;
198 u8 ip_proto;
199 int in_use;
200 int idx;
201 int is_l4;
202};
203
204/* Rx Frame Steering */
205enum stmmac_rfs_type {
206 STMMAC_RFS_T_VLAN,
207 STMMAC_RFS_T_LLDP,
208 STMMAC_RFS_T_1588,
209 STMMAC_RFS_T_MAX,
210};
211
212struct stmmac_rfs_entry {
213 unsigned long cookie;
214 u16 etype;
215 int in_use;
216 int type;
217 int tc;
218};
219
220struct stmmac_dma_conf {
221 unsigned int dma_buf_sz;
222
223 /* RX Queue */
224 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
225 unsigned int dma_rx_size;
226
227 /* TX Queue */
228 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
229 unsigned int dma_tx_size;
230};
231
232#define EST_GCL 1024
233struct stmmac_est {
234 int enable;
235 u32 btr_reserve[2];
236 u32 btr_offset[2];
237 u32 btr[2];
238 u32 ctr[2];
239 u32 ter;
240 u32 gcl_unaligned[EST_GCL];
241 u32 gcl[EST_GCL];
242 u32 gcl_size;
243 u32 max_sdu[MTL_MAX_TX_QUEUES];
244};
245
246struct stmmac_priv {
247 /* Frequently used values are kept adjacent for cache effect */
248 u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
249 u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
250 u32 rx_coal_frames[MTL_MAX_RX_QUEUES];
251
252 int hwts_tx_en;
253 bool tx_path_in_lpi_mode;
254 bool tso;
255 int sph;
256 int sph_cap;
257 u32 sarc_type;
258 u32 rx_riwt[MTL_MAX_RX_QUEUES];
259 int hwts_rx_en;
260
261 void __iomem *ioaddr;
262 struct net_device *dev;
263 struct device *device;
264 struct mac_device_info *hw;
265 int (*hwif_quirks)(struct stmmac_priv *priv);
266 struct mutex lock;
267
268 struct stmmac_dma_conf dma_conf;
269
270 /* Generic channel for NAPI */
271 struct stmmac_channel channel[STMMAC_CH_MAX];
272
273 unsigned int pause_time;
274 struct mii_bus *mii;
275
276 struct phylink_config phylink_config;
277 struct phylink *phylink;
278
279 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
280 struct stmmac_safety_stats sstats;
281 struct plat_stmmacenet_data *plat;
282 /* Protect est parameters */
283 struct mutex est_lock;
284 struct stmmac_est *est;
285 struct dma_features dma_cap;
286 struct stmmac_counters mmc;
287 int hw_cap_support;
288 int synopsys_id;
289 u32 msg_enable;
290 int wolopts;
291 int wol_irq;
292 bool wol_irq_disabled;
293 int clk_csr;
294 struct timer_list eee_ctrl_timer;
295 int lpi_irq;
296 u32 tx_lpi_timer;
297 bool tx_lpi_clk_stop;
298 bool eee_enabled;
299 bool eee_active;
300 bool eee_sw_timer_en;
301 unsigned int mode;
302 unsigned int chain_mode;
303 int extend_desc;
304 struct kernel_hwtstamp_config tstamp_config;
305 struct ptp_clock *ptp_clock;
306 struct ptp_clock_info ptp_clock_ops;
307 unsigned int default_addend;
308 u32 sub_second_inc;
309 u32 systime_flags;
310 u32 adv_ts;
311 int use_riwt;
312 int irq_wake;
313 rwlock_t ptp_lock;
314 /* Protects auxiliary snapshot registers from concurrent access. */
315 struct mutex aux_ts_lock;
316 wait_queue_head_t tstamp_busy_wait;
317
318 void __iomem *mmcaddr;
319 void __iomem *ptpaddr;
320 void __iomem *estaddr;
321 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
322 int sfty_irq;
323 int sfty_ce_irq;
324 int sfty_ue_irq;
325 int rx_irq[MTL_MAX_RX_QUEUES];
326 int tx_irq[MTL_MAX_TX_QUEUES];
327 /*irq name */
328 char int_name_mac[IFNAMSIZ + 9];
329 char int_name_wol[IFNAMSIZ + 9];
330 char int_name_lpi[IFNAMSIZ + 9];
331 char int_name_sfty[IFNAMSIZ + 10];
332 char int_name_sfty_ce[IFNAMSIZ + 10];
333 char int_name_sfty_ue[IFNAMSIZ + 10];
334 char int_name_rx_irq[MTL_MAX_RX_QUEUES][IFNAMSIZ + 14];
335 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
336
337#ifdef CONFIG_DEBUG_FS
338 struct dentry *dbgfs_dir;
339#endif
340
341 unsigned long state;
342 struct workqueue_struct *wq;
343 struct work_struct service_task;
344
345 /* Frame Preemption feature (FPE) */
346 struct stmmac_fpe_cfg fpe_cfg;
347
348 /* TC Handling */
349 unsigned int tc_entries_max;
350 unsigned int tc_off_max;
351 struct stmmac_tc_entry *tc_entries;
352 unsigned int flow_entries_max;
353 struct stmmac_flow_entry *flow_entries;
354 unsigned int rfs_entries_max[STMMAC_RFS_T_MAX];
355 unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX];
356 unsigned int rfs_entries_total;
357 struct stmmac_rfs_entry *rfs_entries;
358
359 /* Pulse Per Second output */
360 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
361
362 /* Receive Side Scaling */
363 struct stmmac_rss rss;
364
365 /* XDP BPF Program */
366 unsigned long *af_xdp_zc_qps;
367 struct bpf_prog *xdp_prog;
368};
369
370enum stmmac_state {
371 STMMAC_DOWN,
372 STMMAC_RESET_REQUESTED,
373 STMMAC_RESETING,
374 STMMAC_SERVICE_SCHED,
375};
376
377int stmmac_mdio_unregister(struct net_device *ndev);
378int stmmac_mdio_register(struct net_device *ndev);
379int stmmac_mdio_reset(struct mii_bus *mii);
380int stmmac_pcs_setup(struct net_device *ndev);
381void stmmac_pcs_clean(struct net_device *ndev);
382void stmmac_set_ethtool_ops(struct net_device *netdev);
383
384int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags);
385void stmmac_ptp_register(struct stmmac_priv *priv);
386void stmmac_ptp_unregister(struct stmmac_priv *priv);
387int stmmac_xdp_open(struct net_device *dev);
388void stmmac_xdp_release(struct net_device *dev);
389int stmmac_resume(struct device *dev);
390int stmmac_suspend(struct device *dev);
391void stmmac_dvr_remove(struct device *dev);
392int stmmac_dvr_probe(struct device *device,
393 struct plat_stmmacenet_data *plat_dat,
394 struct stmmac_resources *res);
395int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
396int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
397int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
398int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
399 phy_interface_t interface, int speed);
400
401static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
402{
403 return !!priv->xdp_prog;
404}
405
406void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
407void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
408void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
409void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
410int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
411struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
412 ktime_t current_time,
413 u64 cycle_time);
414
415#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
416void stmmac_selftest_run(struct net_device *dev,
417 struct ethtool_test *etest, u64 *buf);
418void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
419int stmmac_selftest_get_count(struct stmmac_priv *priv);
420#else
421static inline void stmmac_selftest_run(struct net_device *dev,
422 struct ethtool_test *etest, u64 *buf)
423{
424 /* Not enabled */
425}
426static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
427 u8 *data)
428{
429 /* Not enabled */
430}
431static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
432{
433 return -EOPNOTSUPP;
434}
435#endif /* CONFIG_STMMAC_SELFTESTS */
436
437#endif /* __STMMAC_H__ */
438

source code of linux/drivers/net/ethernet/stmicro/stmmac/stmmac.h