1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7*******************************************************************************/
8
9#ifndef __STMMAC_H__
10#define __STMMAC_H__
11
12#define STMMAC_RESOURCE_NAME "stmmaceth"
13
14#include <linux/clk.h>
15#include <linux/hrtimer.h>
16#include <linux/if_vlan.h>
17#include <linux/stmmac.h>
18#include <linux/phylink.h>
19#include <linux/pci.h>
20#include "common.h"
21#include <linux/ptp_clock_kernel.h>
22#include <linux/net_tstamp.h>
23#include <linux/reset.h>
24#include <net/page_pool/types.h>
25#include <net/xdp.h>
26#include <uapi/linux/bpf.h>
27
28struct stmmac_resources {
29 void __iomem *addr;
30 u8 mac[ETH_ALEN];
31 int wol_irq;
32 int lpi_irq;
33 int irq;
34 int sfty_irq;
35 int sfty_ce_irq;
36 int sfty_ue_irq;
37 int rx_irq[MTL_MAX_RX_QUEUES];
38 int tx_irq[MTL_MAX_TX_QUEUES];
39};
40
41enum stmmac_txbuf_type {
42 STMMAC_TXBUF_T_SKB,
43 STMMAC_TXBUF_T_XDP_TX,
44 STMMAC_TXBUF_T_XDP_NDO,
45 STMMAC_TXBUF_T_XSK_TX,
46};
47
48struct stmmac_tx_info {
49 dma_addr_t buf;
50 bool map_as_page;
51 unsigned len;
52 bool last_segment;
53 bool is_jumbo;
54 enum stmmac_txbuf_type buf_type;
55 struct xsk_tx_metadata_compl xsk_meta;
56};
57
58#define STMMAC_TBS_AVAIL BIT(0)
59#define STMMAC_TBS_EN BIT(1)
60
61/* Frequently used values are kept adjacent for cache effect */
62struct stmmac_tx_queue {
63 u32 tx_count_frames;
64 int tbs;
65 struct hrtimer txtimer;
66 u32 queue_index;
67 struct stmmac_priv *priv_data;
68 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
69 struct dma_edesc *dma_entx;
70 struct dma_desc *dma_tx;
71 union {
72 struct sk_buff **tx_skbuff;
73 struct xdp_frame **xdpf;
74 };
75 struct stmmac_tx_info *tx_skbuff_dma;
76 struct xsk_buff_pool *xsk_pool;
77 u32 xsk_frames_done;
78 unsigned int cur_tx;
79 unsigned int dirty_tx;
80 dma_addr_t dma_tx_phy;
81 dma_addr_t tx_tail_addr;
82 u32 mss;
83};
84
85struct stmmac_rx_buffer {
86 union {
87 struct {
88 struct page *page;
89 dma_addr_t addr;
90 __u32 page_offset;
91 };
92 struct xdp_buff *xdp;
93 };
94 struct page *sec_page;
95 dma_addr_t sec_addr;
96};
97
98struct stmmac_xdp_buff {
99 struct xdp_buff xdp;
100 struct stmmac_priv *priv;
101 struct dma_desc *desc;
102 struct dma_desc *ndesc;
103};
104
105struct stmmac_metadata_request {
106 struct stmmac_priv *priv;
107 struct dma_desc *tx_desc;
108 bool *set_ic;
109};
110
111struct stmmac_xsk_tx_complete {
112 struct stmmac_priv *priv;
113 struct dma_desc *desc;
114};
115
116struct stmmac_rx_queue {
117 u32 rx_count_frames;
118 u32 queue_index;
119 struct xdp_rxq_info xdp_rxq;
120 struct xsk_buff_pool *xsk_pool;
121 struct page_pool *page_pool;
122 struct stmmac_rx_buffer *buf_pool;
123 struct stmmac_priv *priv_data;
124 struct dma_extended_desc *dma_erx;
125 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
126 unsigned int cur_rx;
127 unsigned int dirty_rx;
128 unsigned int buf_alloc_num;
129 u32 rx_zeroc_thresh;
130 dma_addr_t dma_rx_phy;
131 u32 rx_tail_addr;
132 unsigned int state_saved;
133 struct {
134 struct sk_buff *skb;
135 unsigned int len;
136 unsigned int error;
137 } state;
138};
139
140struct stmmac_channel {
141 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
142 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
143 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
144 struct stmmac_priv *priv_data;
145 spinlock_t lock;
146 u32 index;
147};
148
149struct stmmac_tc_entry {
150 bool in_use;
151 bool in_hw;
152 bool is_last;
153 bool is_frag;
154 void *frag_ptr;
155 unsigned int table_pos;
156 u32 handle;
157 u32 prio;
158 struct {
159 u32 match_data;
160 u32 match_en;
161 u8 af:1;
162 u8 rf:1;
163 u8 im:1;
164 u8 nc:1;
165 u8 res1:4;
166 u8 frame_offset;
167 u8 ok_index;
168 u8 dma_ch_no;
169 u32 res2;
170 } __packed val;
171};
172
173#define STMMAC_PPS_MAX 4
174struct stmmac_pps_cfg {
175 bool available;
176 struct timespec64 start;
177 struct timespec64 period;
178};
179
180struct stmmac_rss {
181 int enable;
182 u8 key[STMMAC_RSS_HASH_KEY_SIZE];
183 u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
184};
185
186#define STMMAC_FLOW_ACTION_DROP BIT(0)
187struct stmmac_flow_entry {
188 unsigned long cookie;
189 unsigned long action;
190 u8 ip_proto;
191 int in_use;
192 int idx;
193 int is_l4;
194};
195
196/* Rx Frame Steering */
197enum stmmac_rfs_type {
198 STMMAC_RFS_T_VLAN,
199 STMMAC_RFS_T_LLDP,
200 STMMAC_RFS_T_1588,
201 STMMAC_RFS_T_MAX,
202};
203
204struct stmmac_rfs_entry {
205 unsigned long cookie;
206 u16 etype;
207 int in_use;
208 int type;
209 int tc;
210};
211
212struct stmmac_dma_conf {
213 unsigned int dma_buf_sz;
214
215 /* RX Queue */
216 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
217 unsigned int dma_rx_size;
218
219 /* TX Queue */
220 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
221 unsigned int dma_tx_size;
222};
223
224struct stmmac_priv {
225 /* Frequently used values are kept adjacent for cache effect */
226 u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
227 u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
228 u32 rx_coal_frames[MTL_MAX_TX_QUEUES];
229
230 int hwts_tx_en;
231 bool tx_path_in_lpi_mode;
232 bool tso;
233 int sph;
234 int sph_cap;
235 u32 sarc_type;
236
237 unsigned int rx_copybreak;
238 u32 rx_riwt[MTL_MAX_TX_QUEUES];
239 int hwts_rx_en;
240
241 void __iomem *ioaddr;
242 struct net_device *dev;
243 struct device *device;
244 struct mac_device_info *hw;
245 int (*hwif_quirks)(struct stmmac_priv *priv);
246 struct mutex lock;
247
248 struct stmmac_dma_conf dma_conf;
249
250 /* Generic channel for NAPI */
251 struct stmmac_channel channel[STMMAC_CH_MAX];
252
253 int speed;
254 unsigned int flow_ctrl;
255 unsigned int pause;
256 struct mii_bus *mii;
257
258 struct phylink_config phylink_config;
259 struct phylink *phylink;
260
261 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
262 struct stmmac_safety_stats sstats;
263 struct plat_stmmacenet_data *plat;
264 struct dma_features dma_cap;
265 struct stmmac_counters mmc;
266 int hw_cap_support;
267 int synopsys_id;
268 u32 msg_enable;
269 int wolopts;
270 int wol_irq;
271 bool wol_irq_disabled;
272 int clk_csr;
273 struct timer_list eee_ctrl_timer;
274 int lpi_irq;
275 int eee_enabled;
276 int eee_active;
277 int tx_lpi_timer;
278 int tx_lpi_enabled;
279 int eee_tw_timer;
280 bool eee_sw_timer_en;
281 unsigned int mode;
282 unsigned int chain_mode;
283 int extend_desc;
284 struct hwtstamp_config tstamp_config;
285 struct ptp_clock *ptp_clock;
286 struct ptp_clock_info ptp_clock_ops;
287 unsigned int default_addend;
288 u32 sub_second_inc;
289 u32 systime_flags;
290 u32 adv_ts;
291 int use_riwt;
292 int irq_wake;
293 rwlock_t ptp_lock;
294 /* Protects auxiliary snapshot registers from concurrent access. */
295 struct mutex aux_ts_lock;
296 wait_queue_head_t tstamp_busy_wait;
297
298 void __iomem *mmcaddr;
299 void __iomem *ptpaddr;
300 void __iomem *estaddr;
301 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
302 int sfty_irq;
303 int sfty_ce_irq;
304 int sfty_ue_irq;
305 int rx_irq[MTL_MAX_RX_QUEUES];
306 int tx_irq[MTL_MAX_TX_QUEUES];
307 /*irq name */
308 char int_name_mac[IFNAMSIZ + 9];
309 char int_name_wol[IFNAMSIZ + 9];
310 char int_name_lpi[IFNAMSIZ + 9];
311 char int_name_sfty[IFNAMSIZ + 10];
312 char int_name_sfty_ce[IFNAMSIZ + 10];
313 char int_name_sfty_ue[IFNAMSIZ + 10];
314 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14];
315 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
316
317#ifdef CONFIG_DEBUG_FS
318 struct dentry *dbgfs_dir;
319#endif
320
321 unsigned long state;
322 struct workqueue_struct *wq;
323 struct work_struct service_task;
324
325 /* Workqueue for handling FPE hand-shaking */
326 unsigned long fpe_task_state;
327 struct workqueue_struct *fpe_wq;
328 struct work_struct fpe_task;
329 char wq_name[IFNAMSIZ + 4];
330
331 /* TC Handling */
332 unsigned int tc_entries_max;
333 unsigned int tc_off_max;
334 struct stmmac_tc_entry *tc_entries;
335 unsigned int flow_entries_max;
336 struct stmmac_flow_entry *flow_entries;
337 unsigned int rfs_entries_max[STMMAC_RFS_T_MAX];
338 unsigned int rfs_entries_cnt[STMMAC_RFS_T_MAX];
339 unsigned int rfs_entries_total;
340 struct stmmac_rfs_entry *rfs_entries;
341
342 /* Pulse Per Second output */
343 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
344
345 /* Receive Side Scaling */
346 struct stmmac_rss rss;
347
348 /* XDP BPF Program */
349 unsigned long *af_xdp_zc_qps;
350 struct bpf_prog *xdp_prog;
351};
352
353enum stmmac_state {
354 STMMAC_DOWN,
355 STMMAC_RESET_REQUESTED,
356 STMMAC_RESETING,
357 STMMAC_SERVICE_SCHED,
358};
359
360int stmmac_mdio_unregister(struct net_device *ndev);
361int stmmac_mdio_register(struct net_device *ndev);
362int stmmac_mdio_reset(struct mii_bus *mii);
363int stmmac_xpcs_setup(struct mii_bus *mii);
364void stmmac_set_ethtool_ops(struct net_device *netdev);
365
366int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags);
367void stmmac_ptp_register(struct stmmac_priv *priv);
368void stmmac_ptp_unregister(struct stmmac_priv *priv);
369int stmmac_xdp_open(struct net_device *dev);
370void stmmac_xdp_release(struct net_device *dev);
371int stmmac_resume(struct device *dev);
372int stmmac_suspend(struct device *dev);
373void stmmac_dvr_remove(struct device *dev);
374int stmmac_dvr_probe(struct device *device,
375 struct plat_stmmacenet_data *plat_dat,
376 struct stmmac_resources *res);
377void stmmac_disable_eee_mode(struct stmmac_priv *priv);
378bool stmmac_eee_init(struct stmmac_priv *priv);
379int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
380int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
381int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
382void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable);
383
384static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
385{
386 return !!priv->xdp_prog;
387}
388
389static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv)
390{
391 if (stmmac_xdp_is_enabled(priv))
392 return XDP_PACKET_HEADROOM;
393
394 return 0;
395}
396
397void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
398void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
399void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
400void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
401int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
402struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
403 ktime_t current_time,
404 u64 cycle_time);
405
406#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
407void stmmac_selftest_run(struct net_device *dev,
408 struct ethtool_test *etest, u64 *buf);
409void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
410int stmmac_selftest_get_count(struct stmmac_priv *priv);
411#else
412static inline void stmmac_selftest_run(struct net_device *dev,
413 struct ethtool_test *etest, u64 *buf)
414{
415 /* Not enabled */
416}
417static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
418 u8 *data)
419{
420 /* Not enabled */
421}
422static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
423{
424 return -EOPNOTSUPP;
425}
426#endif /* CONFIG_STMMAC_SELFTESTS */
427
428#endif /* __STMMAC_H__ */
429

source code of linux/drivers/net/ethernet/stmicro/stmmac/stmmac.h