1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* $Id: sunbmac.h,v 1.7 2000/07/11 22:35:22 davem Exp $ |
3 | * sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards. |
4 | * |
5 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) |
6 | */ |
7 | |
8 | #ifndef _SUNBMAC_H |
9 | #define _SUNBMAC_H |
10 | |
11 | /* QEC global registers. */ |
12 | #define GLOB_CTRL 0x00UL /* Control */ |
13 | #define GLOB_STAT 0x04UL /* Status */ |
14 | #define GLOB_PSIZE 0x08UL /* Packet Size */ |
15 | #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */ |
16 | #define GLOB_RSIZE 0x10UL /* Receive partition size */ |
17 | #define GLOB_TSIZE 0x14UL /* Transmit partition size */ |
18 | #define GLOB_REG_SIZE 0x18UL |
19 | |
20 | #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */ |
21 | #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */ |
22 | #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */ |
23 | #define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */ |
24 | #define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */ |
25 | #define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */ |
26 | #define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */ |
27 | #define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */ |
28 | |
29 | #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */ |
30 | #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */ |
31 | #define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */ |
32 | #define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */ |
33 | |
34 | #define GLOB_PSIZE_2048 0x00 /* 2k packet size */ |
35 | #define GLOB_PSIZE_4096 0x01 /* 4k packet size */ |
36 | #define GLOB_PSIZE_6144 0x10 /* 6k packet size */ |
37 | #define GLOB_PSIZE_8192 0x11 /* 8k packet size */ |
38 | |
39 | /* QEC BigMAC channel registers. */ |
40 | #define CREG_CTRL 0x00UL /* Control */ |
41 | #define CREG_STAT 0x04UL /* Status */ |
42 | #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */ |
43 | #define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */ |
44 | #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */ |
45 | #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */ |
46 | #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */ |
47 | #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/ |
48 | #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */ |
49 | #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */ |
50 | #define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */ |
51 | #define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */ |
52 | #define CREG_CCNT 0x30UL /* Collision Counter */ |
53 | #define CREG_REG_SIZE 0x34UL |
54 | |
55 | #define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */ |
56 | |
57 | #define CREG_STAT_BERROR 0x80000000 /* BigMAC error */ |
58 | #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */ |
59 | #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */ |
60 | #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */ |
61 | #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */ |
62 | #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */ |
63 | #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */ |
64 | #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */ |
65 | #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */ |
66 | #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */ |
67 | #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */ |
68 | #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */ |
69 | |
70 | #define CREG_STAT_ERRORS (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR| \ |
71 | CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP| \ |
72 | CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR| \ |
73 | CREG_STAT_RXSERR) |
74 | |
75 | #define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */ |
76 | #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */ |
77 | #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */ |
78 | #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */ |
79 | #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */ |
80 | #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */ |
81 | #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */ |
82 | #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */ |
83 | #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */ |
84 | |
85 | /* BIGMAC core registers */ |
86 | #define BMAC_XIFCFG 0x000UL /* XIF config register */ |
87 | /* 0x004-->0x0fc, reserved */ |
88 | #define BMAC_STATUS 0x100UL /* Status register, clear on read */ |
89 | #define BMAC_IMASK 0x104UL /* Interrupt mask register */ |
90 | /* 0x108-->0x204, reserved */ |
91 | #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */ |
92 | #define BMAC_TXCFG 0x20cUL /* Transmitter config register */ |
93 | #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */ |
94 | #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */ |
95 | #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */ |
96 | #define BMAC_STIME 0x21cUL /* Transmit slot time */ |
97 | #define BMAC_PLEN 0x220UL /* Size of transmit preamble */ |
98 | #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */ |
99 | #define BMAC_TXDELIM 0x228UL /* Transmit delimiter */ |
100 | #define BMAC_JSIZE 0x22cUL /* Toe jam... */ |
101 | #define BMAC_TXPMAX 0x230UL /* Transmit max pkt size */ |
102 | #define BMAC_TXPMIN 0x234UL /* Transmit min pkt size */ |
103 | #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */ |
104 | #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */ |
105 | #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */ |
106 | #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */ |
107 | #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */ |
108 | #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */ |
109 | #define BMAC_RSEED 0x250UL /* Transmit random number seed */ |
110 | #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */ |
111 | /* 0x258-->0x304, reserved */ |
112 | #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */ |
113 | #define BMAC_RXCFG 0x30cUL /* Receiver config register */ |
114 | #define BMAC_RXPMAX 0x310UL /* Receive max pkt size */ |
115 | #define BMAC_RXPMIN 0x314UL /* Receive min pkt size */ |
116 | #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */ |
117 | #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */ |
118 | #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */ |
119 | #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */ |
120 | #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */ |
121 | #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */ |
122 | #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */ |
123 | #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */ |
124 | #define BMAC_RXCVALID 0x338UL /* Receiver code violation */ |
125 | /* 0x33c, reserved */ |
126 | #define BMAC_HTABLE3 0x340UL /* Hash table 3 */ |
127 | #define BMAC_HTABLE2 0x344UL /* Hash table 2 */ |
128 | #define BMAC_HTABLE1 0x348UL /* Hash table 1 */ |
129 | #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */ |
130 | #define BMAC_AFILTER2 0x350UL /* Address filter 2 */ |
131 | #define BMAC_AFILTER1 0x354UL /* Address filter 1 */ |
132 | #define BMAC_AFILTER0 0x358UL /* Address filter 0 */ |
133 | #define BMAC_AFMASK 0x35cUL /* Address filter mask */ |
134 | #define BMAC_REG_SIZE 0x360UL |
135 | |
136 | /* BigMac XIF config register. */ |
137 | #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */ |
138 | #define BIGMAC_XCFG_RESV 0x00000002 /* Reserved, write always as 1 */ |
139 | #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */ |
140 | #define BIGMAC_XCFG_SMODE 0x00000008 /* Enable serial mode */ |
141 | |
142 | /* BigMAC status register. */ |
143 | #define BIGMAC_STAT_GOTFRAME 0x00000001 /* Received a frame */ |
144 | #define BIGMAC_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */ |
145 | #define BIGMAC_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */ |
146 | #define BIGMAC_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */ |
147 | #define BIGMAC_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */ |
148 | #define BIGMAC_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */ |
149 | #define BIGMAC_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */ |
150 | #define BIGMAC_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */ |
151 | #define BIGMAC_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */ |
152 | #define BIGMAC_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */ |
153 | #define BIGMAC_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */ |
154 | #define BIGMAC_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */ |
155 | #define BIGMAC_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */ |
156 | #define BIGMAC_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */ |
157 | #define BIGMAC_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */ |
158 | |
159 | /* BigMAC interrupt mask register. */ |
160 | #define BIGMAC_IMASK_GOTFRAME 0x00000001 /* Received a frame */ |
161 | #define BIGMAC_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */ |
162 | #define BIGMAC_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */ |
163 | #define BIGMAC_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */ |
164 | #define BIGMAC_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */ |
165 | #define BIGMAC_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */ |
166 | #define BIGMAC_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */ |
167 | #define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */ |
168 | #define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */ |
169 | #define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */ |
170 | #define BIGMAC_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */ |
171 | #define BIGMAC_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */ |
172 | #define BIGMAC_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */ |
173 | #define BIGMAC_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */ |
174 | #define BIGMAC_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */ |
175 | |
176 | /* BigMac transmit config register. */ |
177 | #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */ |
178 | #define BIGMAC_TXCFG_FIFO 0x00000010 /* Default tx fthresh... */ |
179 | #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */ |
180 | #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */ |
181 | #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */ |
182 | #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */ |
183 | #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */ |
184 | |
185 | /* BigMac receive config register. */ |
186 | #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */ |
187 | #define BIGMAC_RXCFG_FIFO 0x0000000e /* Default rx fthresh... */ |
188 | #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */ |
189 | #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscuous mode */ |
190 | #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */ |
191 | #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */ |
192 | #define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */ |
193 | #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */ |
194 | #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */ |
195 | #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */ |
196 | |
197 | /* The BigMAC PHY transceiver. Not nearly as sophisticated as the happy meal |
198 | * one. But it does have the "bit banger", oh baby. |
199 | */ |
200 | #define TCVR_TPAL 0x00UL |
201 | #define TCVR_MPAL 0x04UL |
202 | #define TCVR_REG_SIZE 0x08UL |
203 | |
204 | /* Frame commands. */ |
205 | #define FRAME_WRITE 0x50020000 |
206 | #define FRAME_READ 0x60020000 |
207 | |
208 | /* Tranceiver registers. */ |
209 | #define TCVR_PAL_SERIAL 0x00000001 /* Enable serial mode */ |
210 | #define TCVR_PAL_EXTLBACK 0x00000002 /* Enable external loopback */ |
211 | #define TCVR_PAL_MSENSE 0x00000004 /* Media sense */ |
212 | #define TCVR_PAL_LTENABLE 0x00000008 /* Link test enable */ |
213 | #define TCVR_PAL_LTSTATUS 0x00000010 /* Link test status (P1 only) */ |
214 | |
215 | /* Management PAL. */ |
216 | #define MGMT_PAL_DCLOCK 0x00000001 /* Data clock */ |
217 | #define MGMT_PAL_OENAB 0x00000002 /* Output enabler */ |
218 | #define MGMT_PAL_MDIO 0x00000004 /* MDIO Data/attached */ |
219 | #define MGMT_PAL_TIMEO 0x00000008 /* Transmit enable timeout error */ |
220 | #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO |
221 | #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO |
222 | |
223 | /* Here are some PHY addresses. */ |
224 | #define BIGMAC_PHY_EXTERNAL 0 /* External transceiver */ |
225 | #define BIGMAC_PHY_INTERNAL 1 /* Internal transceiver */ |
226 | |
227 | /* Ring descriptors and such, same as Quad Ethernet. */ |
228 | struct be_rxd { |
229 | u32 rx_flags; |
230 | u32 rx_addr; |
231 | }; |
232 | |
233 | #define RXD_OWN 0x80000000 /* Ownership. */ |
234 | #define RXD_UPDATE 0x10000000 /* Being Updated? */ |
235 | #define RXD_LENGTH 0x000007ff /* Packet Length. */ |
236 | |
237 | struct be_txd { |
238 | u32 tx_flags; |
239 | u32 tx_addr; |
240 | }; |
241 | |
242 | #define TXD_OWN 0x80000000 /* Ownership. */ |
243 | #define TXD_SOP 0x40000000 /* Start Of Packet */ |
244 | #define TXD_EOP 0x20000000 /* End Of Packet */ |
245 | #define TXD_UPDATE 0x10000000 /* Being Updated? */ |
246 | #define TXD_LENGTH 0x000007ff /* Packet Length. */ |
247 | |
248 | #define TX_RING_MAXSIZE 256 |
249 | #define RX_RING_MAXSIZE 256 |
250 | |
251 | #define TX_RING_SIZE 256 |
252 | #define RX_RING_SIZE 256 |
253 | |
254 | #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1)) |
255 | #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1)) |
256 | #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1)) |
257 | #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1)) |
258 | |
259 | #define TX_BUFFS_AVAIL(bp) \ |
260 | (((bp)->tx_old <= (bp)->tx_new) ? \ |
261 | (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new : \ |
262 | (bp)->tx_old - (bp)->tx_new - 1) |
263 | |
264 | |
265 | #define RX_COPY_THRESHOLD 256 |
266 | #define RX_BUF_ALLOC_SIZE (ETH_FRAME_LEN + (64 * 3)) |
267 | |
268 | struct bmac_init_block { |
269 | struct be_rxd be_rxd[RX_RING_MAXSIZE]; |
270 | struct be_txd be_txd[TX_RING_MAXSIZE]; |
271 | }; |
272 | |
273 | #define bib_offset(mem, elem) \ |
274 | ((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem])))) |
275 | |
276 | /* Now software state stuff. */ |
277 | enum bigmac_transceiver { |
278 | external = 0, |
279 | internal = 1, |
280 | none = 2, |
281 | }; |
282 | |
283 | /* Timer state engine. */ |
284 | enum bigmac_timer_state { |
285 | ltrywait = 1, /* Forcing try of all modes, from fastest to slowest. */ |
286 | asleep = 2, /* Timer inactive. */ |
287 | }; |
288 | |
289 | struct bigmac { |
290 | void __iomem *gregs; /* QEC Global Registers */ |
291 | void __iomem *creg; /* QEC BigMAC Channel Registers */ |
292 | void __iomem *bregs; /* BigMAC Registers */ |
293 | void __iomem *tregs; /* BigMAC Transceiver */ |
294 | struct bmac_init_block *bmac_block; /* RX and TX descriptors */ |
295 | dma_addr_t bblock_dvma; /* RX and TX descriptors */ |
296 | |
297 | spinlock_t lock; |
298 | |
299 | struct sk_buff *rx_skbs[RX_RING_SIZE]; |
300 | struct sk_buff *tx_skbs[TX_RING_SIZE]; |
301 | |
302 | int rx_new, tx_new, rx_old, tx_old; |
303 | |
304 | int board_rev; /* BigMAC board revision. */ |
305 | |
306 | enum bigmac_transceiver tcvr_type; |
307 | unsigned int bigmac_bursts; |
308 | unsigned int paddr; |
309 | unsigned short sw_bmsr; /* SW copy of PHY BMSR */ |
310 | unsigned short sw_bmcr; /* SW copy of PHY BMCR */ |
311 | struct timer_list bigmac_timer; |
312 | enum bigmac_timer_state timer_state; |
313 | unsigned int timer_ticks; |
314 | |
315 | struct platform_device *qec_op; |
316 | struct platform_device *bigmac_op; |
317 | struct net_device *dev; |
318 | }; |
319 | |
320 | /* We use this to acquire receive skb's that we can DMA directly into. */ |
321 | #define ALIGNED_RX_SKB_ADDR(addr) \ |
322 | ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr)) |
323 | |
324 | static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, gfp_t gfp_flags) |
325 | { |
326 | struct sk_buff *skb; |
327 | |
328 | skb = alloc_skb(size: length + 64, priority: gfp_flags); |
329 | if(skb) { |
330 | int offset = ALIGNED_RX_SKB_ADDR(skb->data); |
331 | |
332 | if(offset) |
333 | skb_reserve(skb, len: offset); |
334 | } |
335 | return skb; |
336 | } |
337 | |
338 | #endif /* !(_SUNBMAC_H) */ |
339 | |