1/* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver
2 *
3 * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com)
4 *
5 * This program is dual-licensed; you may select either version 2 of
6 * the GNU General Public License ("GPL") or BSD license ("BSD").
7 *
8 * This Synopsys DWC XLGMAC software driver and associated documentation
9 * (hereinafter the "Software") is an unsupported proprietary work of
10 * Synopsys, Inc. unless otherwise expressly agreed to in writing between
11 * Synopsys and you. The Software IS NOT an item of Licensed Software or a
12 * Licensed Product under any End User Software License Agreement or
13 * Agreement for Licensed Products with Synopsys or any supplement thereto.
14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included
15 * in the SOFTWARE may be the trademarks of their respective owners.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20
21#include "dwc-xlgmac.h"
22#include "dwc-xlgmac-reg.h"
23
24static int debug = -1;
25module_param(debug, int, 0644);
26MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)");
27static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
28 NETIF_MSG_IFUP);
29
30static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7};
31
32static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata)
33{
34 struct net_device *netdev = pdata->netdev;
35
36 /* Currently it uses a static mac address for test */
37 memcpy(pdata->mac_addr, dev_addr, netdev->addr_len);
38}
39
40static void xlgmac_default_config(struct xlgmac_pdata *pdata)
41{
42 pdata->tx_osp_mode = DMA_OSP_ENABLE;
43 pdata->tx_sf_mode = MTL_TSF_ENABLE;
44 pdata->rx_sf_mode = MTL_RSF_DISABLE;
45 pdata->pblx8 = DMA_PBL_X8_ENABLE;
46 pdata->tx_pbl = DMA_PBL_32;
47 pdata->rx_pbl = DMA_PBL_32;
48 pdata->tx_threshold = MTL_TX_THRESHOLD_128;
49 pdata->rx_threshold = MTL_RX_THRESHOLD_128;
50 pdata->tx_pause = 1;
51 pdata->rx_pause = 1;
52 pdata->phy_speed = SPEED_25000;
53 pdata->sysclk_rate = XLGMAC_SYSCLOCK;
54
55 strscpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name));
56 strscpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver));
57}
58
59static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata)
60{
61 xlgmac_init_desc_ops(desc_ops: &pdata->desc_ops);
62 xlgmac_init_hw_ops(hw_ops: &pdata->hw_ops);
63}
64
65static int xlgmac_init(struct xlgmac_pdata *pdata)
66{
67 struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops;
68 struct net_device *netdev = pdata->netdev;
69 unsigned int i;
70 int ret;
71
72 /* Set default configuration data */
73 xlgmac_default_config(pdata);
74
75 /* Set irq, base_addr, MAC address, */
76 netdev->irq = pdata->dev_irq;
77 netdev->base_addr = (unsigned long)pdata->mac_regs;
78 xlgmac_read_mac_addr(pdata);
79 eth_hw_addr_set(dev: netdev, addr: pdata->mac_addr);
80
81 /* Set all the function pointers */
82 xlgmac_init_all_ops(pdata);
83
84 /* Issue software reset to device */
85 hw_ops->exit(pdata);
86
87 /* Populate the hardware features */
88 xlgmac_get_all_hw_features(pdata);
89 xlgmac_print_all_hw_features(pdata);
90
91 /* TODO: Set the PHY mode to XLGMII */
92
93 /* Set the DMA mask */
94 ret = dma_set_mask_and_coherent(dev: pdata->dev,
95 DMA_BIT_MASK(pdata->hw_feat.dma_width));
96 if (ret) {
97 dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n");
98 return ret;
99 }
100
101 /* Channel and ring params initializtion
102 * pdata->channel_count;
103 * pdata->tx_ring_count;
104 * pdata->rx_ring_count;
105 * pdata->tx_desc_count;
106 * pdata->rx_desc_count;
107 */
108 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT);
109 pdata->tx_desc_count = XLGMAC_TX_DESC_CNT;
110 if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
111 dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n",
112 pdata->tx_desc_count);
113 ret = -EINVAL;
114 return ret;
115 }
116 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT);
117 pdata->rx_desc_count = XLGMAC_RX_DESC_CNT;
118 if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
119 dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n",
120 pdata->rx_desc_count);
121 ret = -EINVAL;
122 return ret;
123 }
124
125 pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
126 pdata->hw_feat.tx_ch_cnt);
127 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
128 pdata->hw_feat.tx_q_cnt);
129 pdata->tx_q_count = pdata->tx_ring_count;
130 ret = netif_set_real_num_tx_queues(dev: netdev, txq: pdata->tx_q_count);
131 if (ret) {
132 dev_err(pdata->dev, "error setting real tx queue count\n");
133 return ret;
134 }
135
136 pdata->rx_ring_count = min_t(unsigned int,
137 netif_get_num_default_rss_queues(),
138 pdata->hw_feat.rx_ch_cnt);
139 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
140 pdata->hw_feat.rx_q_cnt);
141 pdata->rx_q_count = pdata->rx_ring_count;
142 ret = netif_set_real_num_rx_queues(dev: netdev, rxq: pdata->rx_q_count);
143 if (ret) {
144 dev_err(pdata->dev, "error setting real rx queue count\n");
145 return ret;
146 }
147
148 pdata->channel_count =
149 max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
150
151 /* Initialize RSS hash key and lookup table */
152 netdev_rss_key_fill(buffer: pdata->rss_key, len: sizeof(pdata->rss_key));
153
154 for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++)
155 pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
156 pdata->rss_table[i],
157 MAC_RSSDR_DMCH_POS,
158 MAC_RSSDR_DMCH_LEN,
159 i % pdata->rx_ring_count);
160
161 pdata->rss_options = XLGMAC_SET_REG_BITS(
162 pdata->rss_options,
163 MAC_RSSCR_IP2TE_POS,
164 MAC_RSSCR_IP2TE_LEN, 1);
165 pdata->rss_options = XLGMAC_SET_REG_BITS(
166 pdata->rss_options,
167 MAC_RSSCR_TCP4TE_POS,
168 MAC_RSSCR_TCP4TE_LEN, 1);
169 pdata->rss_options = XLGMAC_SET_REG_BITS(
170 pdata->rss_options,
171 MAC_RSSCR_UDP4TE_POS,
172 MAC_RSSCR_UDP4TE_LEN, 1);
173
174 /* Set device operations */
175 netdev->netdev_ops = xlgmac_get_netdev_ops();
176 netdev->ethtool_ops = xlgmac_get_ethtool_ops();
177
178 /* Set device features */
179 if (pdata->hw_feat.tso) {
180 netdev->hw_features = NETIF_F_TSO;
181 netdev->hw_features |= NETIF_F_TSO6;
182 netdev->hw_features |= NETIF_F_SG;
183 netdev->hw_features |= NETIF_F_IP_CSUM;
184 netdev->hw_features |= NETIF_F_IPV6_CSUM;
185 } else if (pdata->hw_feat.tx_coe) {
186 netdev->hw_features = NETIF_F_IP_CSUM;
187 netdev->hw_features |= NETIF_F_IPV6_CSUM;
188 }
189
190 if (pdata->hw_feat.rx_coe) {
191 netdev->hw_features |= NETIF_F_RXCSUM;
192 netdev->hw_features |= NETIF_F_GRO;
193 }
194
195 if (pdata->hw_feat.rss)
196 netdev->hw_features |= NETIF_F_RXHASH;
197
198 netdev->vlan_features |= netdev->hw_features;
199
200 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
201 if (pdata->hw_feat.sa_vlan_ins)
202 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
203 if (pdata->hw_feat.vlhash)
204 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
205
206 netdev->features |= netdev->hw_features;
207 pdata->netdev_features = netdev->features;
208
209 netdev->priv_flags |= IFF_UNICAST_FLT;
210
211 /* Use default watchdog timeout */
212 netdev->watchdog_timeo = 0;
213
214 /* Tx coalesce parameters initialization */
215 pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS;
216 pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES;
217
218 /* Rx coalesce parameters initialization */
219 pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS);
220 pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS;
221 pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES;
222
223 return 0;
224}
225
226int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res)
227{
228 struct xlgmac_pdata *pdata;
229 struct net_device *netdev;
230 int ret;
231
232 netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata),
233 XLGMAC_MAX_DMA_CHANNELS);
234
235 if (!netdev) {
236 dev_err(dev, "alloc_etherdev failed\n");
237 return -ENOMEM;
238 }
239
240 SET_NETDEV_DEV(netdev, dev);
241 dev_set_drvdata(dev, data: netdev);
242 pdata = netdev_priv(dev: netdev);
243 pdata->dev = dev;
244 pdata->netdev = netdev;
245
246 pdata->dev_irq = res->irq;
247 pdata->mac_regs = res->addr;
248
249 mutex_init(&pdata->rss_mutex);
250 pdata->msg_enable = netif_msg_init(debug_value: debug, default_msg_enable_bits: default_msg_level);
251
252 ret = xlgmac_init(pdata);
253 if (ret) {
254 dev_err(dev, "xlgmac init failed\n");
255 goto err_free_netdev;
256 }
257
258 ret = register_netdev(dev: netdev);
259 if (ret) {
260 dev_err(dev, "net device registration failed\n");
261 goto err_free_netdev;
262 }
263
264 return 0;
265
266err_free_netdev:
267 free_netdev(dev: netdev);
268
269 return ret;
270}
271
272int xlgmac_drv_remove(struct device *dev)
273{
274 struct net_device *netdev = dev_get_drvdata(dev);
275
276 unregister_netdev(dev: netdev);
277 free_netdev(dev: netdev);
278
279 return 0;
280}
281
282void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata,
283 struct xlgmac_ring *ring,
284 unsigned int idx,
285 unsigned int count,
286 unsigned int flag)
287{
288 struct xlgmac_desc_data *desc_data;
289 struct xlgmac_dma_desc *dma_desc;
290
291 while (count--) {
292 desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
293 dma_desc = desc_data->dma_desc;
294
295 netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n",
296 desc_data->dma_desc, &desc_data->dma_desc_addr);
297 netdev_dbg(pdata->netdev,
298 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
299 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
300 le32_to_cpu(dma_desc->desc0),
301 le32_to_cpu(dma_desc->desc1),
302 le32_to_cpu(dma_desc->desc2),
303 le32_to_cpu(dma_desc->desc3));
304
305 idx++;
306 }
307}
308
309void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata,
310 struct xlgmac_ring *ring,
311 unsigned int idx)
312{
313 struct xlgmac_desc_data *desc_data;
314 struct xlgmac_dma_desc *dma_desc;
315
316 desc_data = XLGMAC_GET_DESC_DATA(ring, idx);
317 dma_desc = desc_data->dma_desc;
318
319 netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n",
320 desc_data->dma_desc, &desc_data->dma_desc_addr);
321 netdev_dbg(pdata->netdev,
322 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
323 idx,
324 le32_to_cpu(dma_desc->desc0),
325 le32_to_cpu(dma_desc->desc1),
326 le32_to_cpu(dma_desc->desc2),
327 le32_to_cpu(dma_desc->desc3));
328}
329
330void xlgmac_print_pkt(struct net_device *netdev,
331 struct sk_buff *skb, bool tx_rx)
332{
333 struct ethhdr *eth = (struct ethhdr *)skb->data;
334 unsigned char buffer[128];
335 unsigned int i;
336
337 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
338
339 netdev_dbg(netdev, "%s packet of %d bytes\n",
340 (tx_rx ? "TX" : "RX"), skb->len);
341
342 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
343 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
344 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
345
346 for (i = 0; i < skb->len; i += 32) {
347 unsigned int len = min(skb->len - i, 32U);
348
349 hex_dump_to_buffer(buf: &skb->data[i], len, rowsize: 32, groupsize: 1,
350 linebuf: buffer, linebuflen: sizeof(buffer), ascii: false);
351 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
352 }
353
354 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
355}
356
357void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata)
358{
359 struct xlgmac_hw_features *hw_feat = &pdata->hw_feat;
360 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
361
362 mac_hfr0 = readl(addr: pdata->mac_regs + MAC_HWF0R);
363 mac_hfr1 = readl(addr: pdata->mac_regs + MAC_HWF1R);
364 mac_hfr2 = readl(addr: pdata->mac_regs + MAC_HWF2R);
365
366 memset(hw_feat, 0, sizeof(*hw_feat));
367
368 hw_feat->version = readl(addr: pdata->mac_regs + MAC_VR);
369
370 /* Hardware feature register 0 */
371 hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0,
372 MAC_HWF0R_PHYIFSEL_POS,
373 MAC_HWF0R_PHYIFSEL_LEN);
374 hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0,
375 MAC_HWF0R_VLHASH_POS,
376 MAC_HWF0R_VLHASH_LEN);
377 hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0,
378 MAC_HWF0R_SMASEL_POS,
379 MAC_HWF0R_SMASEL_LEN);
380 hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0,
381 MAC_HWF0R_RWKSEL_POS,
382 MAC_HWF0R_RWKSEL_LEN);
383 hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0,
384 MAC_HWF0R_MGKSEL_POS,
385 MAC_HWF0R_MGKSEL_LEN);
386 hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0,
387 MAC_HWF0R_MMCSEL_POS,
388 MAC_HWF0R_MMCSEL_LEN);
389 hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0,
390 MAC_HWF0R_ARPOFFSEL_POS,
391 MAC_HWF0R_ARPOFFSEL_LEN);
392 hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0,
393 MAC_HWF0R_TSSEL_POS,
394 MAC_HWF0R_TSSEL_LEN);
395 hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0,
396 MAC_HWF0R_EEESEL_POS,
397 MAC_HWF0R_EEESEL_LEN);
398 hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
399 MAC_HWF0R_TXCOESEL_POS,
400 MAC_HWF0R_TXCOESEL_LEN);
401 hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0,
402 MAC_HWF0R_RXCOESEL_POS,
403 MAC_HWF0R_RXCOESEL_LEN);
404 hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0,
405 MAC_HWF0R_ADDMACADRSEL_POS,
406 MAC_HWF0R_ADDMACADRSEL_LEN);
407 hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0,
408 MAC_HWF0R_TSSTSSEL_POS,
409 MAC_HWF0R_TSSTSSEL_LEN);
410 hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0,
411 MAC_HWF0R_SAVLANINS_POS,
412 MAC_HWF0R_SAVLANINS_LEN);
413
414 /* Hardware feature register 1 */
415 hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
416 MAC_HWF1R_RXFIFOSIZE_POS,
417 MAC_HWF1R_RXFIFOSIZE_LEN);
418 hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1,
419 MAC_HWF1R_TXFIFOSIZE_POS,
420 MAC_HWF1R_TXFIFOSIZE_LEN);
421 hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1,
422 MAC_HWF1R_ADVTHWORD_POS,
423 MAC_HWF1R_ADVTHWORD_LEN);
424 hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1,
425 MAC_HWF1R_ADDR64_POS,
426 MAC_HWF1R_ADDR64_LEN);
427 hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1,
428 MAC_HWF1R_DCBEN_POS,
429 MAC_HWF1R_DCBEN_LEN);
430 hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1,
431 MAC_HWF1R_SPHEN_POS,
432 MAC_HWF1R_SPHEN_LEN);
433 hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1,
434 MAC_HWF1R_TSOEN_POS,
435 MAC_HWF1R_TSOEN_LEN);
436 hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1,
437 MAC_HWF1R_DBGMEMA_POS,
438 MAC_HWF1R_DBGMEMA_LEN);
439 hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1,
440 MAC_HWF1R_RSSEN_POS,
441 MAC_HWF1R_RSSEN_LEN);
442 hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1,
443 MAC_HWF1R_NUMTC_POS,
444 MAC_HWF1R_NUMTC_LEN);
445 hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1,
446 MAC_HWF1R_HASHTBLSZ_POS,
447 MAC_HWF1R_HASHTBLSZ_LEN);
448 hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1,
449 MAC_HWF1R_L3L4FNUM_POS,
450 MAC_HWF1R_L3L4FNUM_LEN);
451
452 /* Hardware feature register 2 */
453 hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
454 MAC_HWF2R_RXQCNT_POS,
455 MAC_HWF2R_RXQCNT_LEN);
456 hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
457 MAC_HWF2R_TXQCNT_POS,
458 MAC_HWF2R_TXQCNT_LEN);
459 hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
460 MAC_HWF2R_RXCHCNT_POS,
461 MAC_HWF2R_RXCHCNT_LEN);
462 hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2,
463 MAC_HWF2R_TXCHCNT_POS,
464 MAC_HWF2R_TXCHCNT_LEN);
465 hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2,
466 MAC_HWF2R_PPSOUTNUM_POS,
467 MAC_HWF2R_PPSOUTNUM_LEN);
468 hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2,
469 MAC_HWF2R_AUXSNAPNUM_POS,
470 MAC_HWF2R_AUXSNAPNUM_LEN);
471
472 /* Translate the Hash Table size into actual number */
473 switch (hw_feat->hash_table_size) {
474 case 0:
475 break;
476 case 1:
477 hw_feat->hash_table_size = 64;
478 break;
479 case 2:
480 hw_feat->hash_table_size = 128;
481 break;
482 case 3:
483 hw_feat->hash_table_size = 256;
484 break;
485 }
486
487 /* Translate the address width setting into actual number */
488 switch (hw_feat->dma_width) {
489 case 0:
490 hw_feat->dma_width = 32;
491 break;
492 case 1:
493 hw_feat->dma_width = 40;
494 break;
495 case 2:
496 hw_feat->dma_width = 48;
497 break;
498 default:
499 hw_feat->dma_width = 32;
500 }
501
502 /* The Queue, Channel and TC counts are zero based so increment them
503 * to get the actual number
504 */
505 hw_feat->rx_q_cnt++;
506 hw_feat->tx_q_cnt++;
507 hw_feat->rx_ch_cnt++;
508 hw_feat->tx_ch_cnt++;
509 hw_feat->tc_cnt++;
510}
511
512void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata)
513{
514 char __maybe_unused *str = NULL;
515
516 XLGMAC_PR("\n");
517 XLGMAC_PR("=====================================================\n");
518 XLGMAC_PR("\n");
519 XLGMAC_PR("HW support following features\n");
520 XLGMAC_PR("\n");
521 /* HW Feature Register0 */
522 XLGMAC_PR("VLAN Hash Filter Selected : %s\n",
523 pdata->hw_feat.vlhash ? "YES" : "NO");
524 XLGMAC_PR("SMA (MDIO) Interface : %s\n",
525 pdata->hw_feat.sma ? "YES" : "NO");
526 XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n",
527 pdata->hw_feat.rwk ? "YES" : "NO");
528 XLGMAC_PR("PMT Magic Packet Enable : %s\n",
529 pdata->hw_feat.mgk ? "YES" : "NO");
530 XLGMAC_PR("RMON/MMC Module Enable : %s\n",
531 pdata->hw_feat.mmc ? "YES" : "NO");
532 XLGMAC_PR("ARP Offload Enabled : %s\n",
533 pdata->hw_feat.aoe ? "YES" : "NO");
534 XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n",
535 pdata->hw_feat.ts ? "YES" : "NO");
536 XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n",
537 pdata->hw_feat.eee ? "YES" : "NO");
538 XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n",
539 pdata->hw_feat.tx_coe ? "YES" : "NO");
540 XLGMAC_PR("Receive Checksum Offload Enabled : %s\n",
541 pdata->hw_feat.rx_coe ? "YES" : "NO");
542 XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n",
543 pdata->hw_feat.addn_mac ? "YES" : "NO");
544
545 switch (pdata->hw_feat.ts_src) {
546 case 0:
547 str = "RESERVED";
548 break;
549 case 1:
550 str = "INTERNAL";
551 break;
552 case 2:
553 str = "EXTERNAL";
554 break;
555 case 3:
556 str = "BOTH";
557 break;
558 }
559 XLGMAC_PR("Timestamp System Time Source : %s\n", str);
560
561 XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n",
562 pdata->hw_feat.sa_vlan_ins ? "YES" : "NO");
563
564 /* HW Feature Register1 */
565 switch (pdata->hw_feat.rx_fifo_size) {
566 case 0:
567 str = "128 bytes";
568 break;
569 case 1:
570 str = "256 bytes";
571 break;
572 case 2:
573 str = "512 bytes";
574 break;
575 case 3:
576 str = "1 KBytes";
577 break;
578 case 4:
579 str = "2 KBytes";
580 break;
581 case 5:
582 str = "4 KBytes";
583 break;
584 case 6:
585 str = "8 KBytes";
586 break;
587 case 7:
588 str = "16 KBytes";
589 break;
590 case 8:
591 str = "32 kBytes";
592 break;
593 case 9:
594 str = "64 KBytes";
595 break;
596 case 10:
597 str = "128 KBytes";
598 break;
599 case 11:
600 str = "256 KBytes";
601 break;
602 default:
603 str = "RESERVED";
604 }
605 XLGMAC_PR("MTL Receive FIFO Size : %s\n", str);
606
607 switch (pdata->hw_feat.tx_fifo_size) {
608 case 0:
609 str = "128 bytes";
610 break;
611 case 1:
612 str = "256 bytes";
613 break;
614 case 2:
615 str = "512 bytes";
616 break;
617 case 3:
618 str = "1 KBytes";
619 break;
620 case 4:
621 str = "2 KBytes";
622 break;
623 case 5:
624 str = "4 KBytes";
625 break;
626 case 6:
627 str = "8 KBytes";
628 break;
629 case 7:
630 str = "16 KBytes";
631 break;
632 case 8:
633 str = "32 kBytes";
634 break;
635 case 9:
636 str = "64 KBytes";
637 break;
638 case 10:
639 str = "128 KBytes";
640 break;
641 case 11:
642 str = "256 KBytes";
643 break;
644 default:
645 str = "RESERVED";
646 }
647 XLGMAC_PR("MTL Transmit FIFO Size : %s\n", str);
648
649 XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n",
650 pdata->hw_feat.adv_ts_hi ? "YES" : "NO");
651 XLGMAC_PR("Address width : %u\n",
652 pdata->hw_feat.dma_width);
653 XLGMAC_PR("DCB Feature Enable : %s\n",
654 pdata->hw_feat.dcb ? "YES" : "NO");
655 XLGMAC_PR("Split Header Feature Enable : %s\n",
656 pdata->hw_feat.sph ? "YES" : "NO");
657 XLGMAC_PR("TCP Segmentation Offload Enable : %s\n",
658 pdata->hw_feat.tso ? "YES" : "NO");
659 XLGMAC_PR("DMA Debug Registers Enabled : %s\n",
660 pdata->hw_feat.dma_debug ? "YES" : "NO");
661 XLGMAC_PR("RSS Feature Enabled : %s\n",
662 pdata->hw_feat.rss ? "YES" : "NO");
663 XLGMAC_PR("Number of Traffic classes : %u\n",
664 (pdata->hw_feat.tc_cnt));
665 XLGMAC_PR("Hash Table Size : %u\n",
666 pdata->hw_feat.hash_table_size);
667 XLGMAC_PR("Total number of L3 or L4 Filters : %u\n",
668 pdata->hw_feat.l3l4_filter_num);
669
670 /* HW Feature Register2 */
671 XLGMAC_PR("Number of MTL Receive Queues : %u\n",
672 pdata->hw_feat.rx_q_cnt);
673 XLGMAC_PR("Number of MTL Transmit Queues : %u\n",
674 pdata->hw_feat.tx_q_cnt);
675 XLGMAC_PR("Number of DMA Receive Channels : %u\n",
676 pdata->hw_feat.rx_ch_cnt);
677 XLGMAC_PR("Number of DMA Transmit Channels : %u\n",
678 pdata->hw_feat.tx_ch_cnt);
679
680 switch (pdata->hw_feat.pps_out_num) {
681 case 0:
682 str = "No PPS output";
683 break;
684 case 1:
685 str = "1 PPS output";
686 break;
687 case 2:
688 str = "2 PPS output";
689 break;
690 case 3:
691 str = "3 PPS output";
692 break;
693 case 4:
694 str = "4 PPS output";
695 break;
696 default:
697 str = "RESERVED";
698 }
699 XLGMAC_PR("Number of PPS Outputs : %s\n", str);
700
701 switch (pdata->hw_feat.aux_snap_num) {
702 case 0:
703 str = "No auxiliary input";
704 break;
705 case 1:
706 str = "1 auxiliary input";
707 break;
708 case 2:
709 str = "2 auxiliary input";
710 break;
711 case 3:
712 str = "3 auxiliary input";
713 break;
714 case 4:
715 str = "4 auxiliary input";
716 break;
717 default:
718 str = "RESERVED";
719 }
720 XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s", str);
721
722 XLGMAC_PR("\n");
723 XLGMAC_PR("=====================================================\n");
724 XLGMAC_PR("\n");
725}
726
727MODULE_DESCRIPTION(XLGMAC_DRV_DESC);
728MODULE_VERSION(XLGMAC_DRV_VERSION);
729MODULE_AUTHOR("Jie Deng <jiedeng@synopsys.com>");
730MODULE_LICENSE("Dual BSD/GPL");
731

source code of linux/drivers/net/ethernet/synopsys/dwc-xlgmac-common.c