1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ |
3 | |
4 | #ifndef _WX_TYPE_H_ |
5 | #define _WX_TYPE_H_ |
6 | |
7 | #include <linux/bitfield.h> |
8 | #include <linux/netdevice.h> |
9 | #include <linux/if_vlan.h> |
10 | #include <linux/phylink.h> |
11 | #include <net/ip.h> |
12 | |
13 | #define WX_NCSI_SUP 0x8000 |
14 | #define WX_NCSI_MASK 0x8000 |
15 | #define WX_WOL_SUP 0x4000 |
16 | #define WX_WOL_MASK 0x4000 |
17 | |
18 | /* MSI-X capability fields masks */ |
19 | #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF |
20 | #define WX_PCI_LINK_STATUS 0xB2 |
21 | |
22 | /**************** Global Registers ****************************/ |
23 | /* chip control Registers */ |
24 | #define WX_MIS_PWR 0x10000 |
25 | #define WX_MIS_RST 0x1000C |
26 | #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1) |
27 | #define WX_MIS_RST_SW_RST BIT(0) |
28 | #define WX_MIS_ST 0x10028 |
29 | #define WX_MIS_ST_MNG_INIT_DN BIT(0) |
30 | #define WX_MIS_SWSM 0x1002C |
31 | #define WX_MIS_SWSM_SMBI BIT(0) |
32 | #define WX_MIS_RST_ST 0x10030 |
33 | #define WX_MIS_RST_ST_RST_INI_SHIFT 8 |
34 | #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT) |
35 | |
36 | /* FMGR Registers */ |
37 | #define WX_SPI_CMD 0x10104 |
38 | #define WX_SPI_CMD_READ_DWORD 0x1 |
39 | #define WX_SPI_CLK_DIV 0x3 |
40 | #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v) |
41 | #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v) |
42 | #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v) |
43 | #define WX_SPI_DATA 0x10108 |
44 | #define WX_SPI_DATA_BYPASS BIT(31) |
45 | #define WX_SPI_DATA_OP_DONE BIT(0) |
46 | #define WX_SPI_STATUS 0x1010C |
47 | #define WX_SPI_STATUS_OPDONE BIT(0) |
48 | #define WX_SPI_STATUS_FLASH_BYPASS BIT(31) |
49 | #define WX_SPI_ILDR_STATUS 0x10120 |
50 | |
51 | /* Sensors for PVT(Process Voltage Temperature) */ |
52 | #define WX_TS_EN 0x10304 |
53 | #define WX_TS_EN_ENA BIT(0) |
54 | #define WX_TS_ALARM_THRE 0x1030C |
55 | #define WX_TS_DALARM_THRE 0x10310 |
56 | #define WX_TS_INT_EN 0x10314 |
57 | #define WX_TS_INT_EN_DALARM_INT_EN BIT(1) |
58 | #define WX_TS_INT_EN_ALARM_INT_EN BIT(0) |
59 | #define WX_TS_ALARM_ST 0x10318 |
60 | #define WX_TS_ALARM_ST_DALARM BIT(1) |
61 | #define WX_TS_ALARM_ST_ALARM BIT(0) |
62 | |
63 | /* statistic */ |
64 | #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C |
65 | #define WX_TX_BC_FRAMES_GOOD_L 0x11824 |
66 | #define WX_TX_MC_FRAMES_GOOD_L 0x1182C |
67 | #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900 |
68 | #define WX_RX_BC_FRAMES_GOOD_L 0x11918 |
69 | #define WX_RX_MC_FRAMES_GOOD_L 0x11920 |
70 | #define WX_RX_CRC_ERROR_FRAMES_L 0x11928 |
71 | #define WX_RX_LEN_ERROR_FRAMES_L 0x11978 |
72 | #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938 |
73 | #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C |
74 | #define WX_MAC_LXONOFFRXC 0x11E0C |
75 | |
76 | /*********************** Receive DMA registers **************************/ |
77 | #define WX_RDM_DRP_PKT 0x12500 |
78 | #define WX_RDM_PKT_CNT 0x12504 |
79 | #define WX_RDM_BYTE_CNT_LSB 0x12508 |
80 | #define WX_RDM_BMC2OS_CNT 0x12510 |
81 | |
82 | /************************* Port Registers ************************************/ |
83 | /* port cfg Registers */ |
84 | #define WX_CFG_PORT_CTL 0x14400 |
85 | #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3) |
86 | #define WX_CFG_PORT_CTL_QINQ BIT(2) |
87 | #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/ |
88 | #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4)) |
89 | #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */ |
90 | |
91 | |
92 | /* GPIO Registers */ |
93 | #define WX_GPIO_DR 0x14800 |
94 | #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */ |
95 | #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */ |
96 | #define WX_GPIO_DDR 0x14804 |
97 | #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */ |
98 | #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */ |
99 | #define WX_GPIO_CTL 0x14808 |
100 | #define WX_GPIO_INTEN 0x14830 |
101 | #define WX_GPIO_INTEN_0 BIT(0) |
102 | #define WX_GPIO_INTEN_1 BIT(1) |
103 | #define WX_GPIO_INTMASK 0x14834 |
104 | #define WX_GPIO_INTTYPE_LEVEL 0x14838 |
105 | #define WX_GPIO_POLARITY 0x1483C |
106 | #define WX_GPIO_INTSTATUS 0x14844 |
107 | #define WX_GPIO_EOI 0x1484C |
108 | #define WX_GPIO_EXT 0x14850 |
109 | |
110 | /*********************** Transmit DMA registers **************************/ |
111 | /* transmit global control */ |
112 | #define WX_TDM_CTL 0x18000 |
113 | /* TDM CTL BIT */ |
114 | #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */ |
115 | #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4)) |
116 | #define WX_TDM_RP_IDX 0x1820C |
117 | #define WX_TDM_PKT_CNT 0x18308 |
118 | #define WX_TDM_BYTE_CNT_LSB 0x1830C |
119 | #define WX_TDM_OS2BMC_CNT 0x18314 |
120 | #define WX_TDM_RP_RATE 0x18404 |
121 | |
122 | /***************************** RDB registers *********************************/ |
123 | /* receive packet buffer */ |
124 | #define WX_RDB_PB_CTL 0x19000 |
125 | #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */ |
126 | #define WX_RDB_PB_CTL_DISABLED BIT(0) |
127 | #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4)) |
128 | #define WX_RDB_PB_SZ_SHIFT 10 |
129 | /* statistic */ |
130 | #define WX_RDB_PFCMACDAL 0x19210 |
131 | #define WX_RDB_PFCMACDAH 0x19214 |
132 | #define WX_RDB_LXOFFTXC 0x19218 |
133 | #define WX_RDB_LXONTXC 0x1921C |
134 | /* Flow Control Registers */ |
135 | #define WX_RDB_RFCV 0x19200 |
136 | #define WX_RDB_RFCL 0x19220 |
137 | #define WX_RDB_RFCL_XONE BIT(31) |
138 | #define WX_RDB_RFCH 0x19260 |
139 | #define WX_RDB_RFCH_XOFFE BIT(31) |
140 | #define WX_RDB_RFCRT 0x192A0 |
141 | #define WX_RDB_RFCC 0x192A4 |
142 | #define WX_RDB_RFCC_RFCE_802_3X BIT(3) |
143 | /* ring assignment */ |
144 | #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4)) |
145 | #define WX_RDB_PL_CFG_L4HDR BIT(1) |
146 | #define WX_RDB_PL_CFG_L3HDR BIT(2) |
147 | #define WX_RDB_PL_CFG_L2HDR BIT(3) |
148 | #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4) |
149 | #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5) |
150 | #define (_i) (0x19400 + ((_i) * 4)) |
151 | #define (_i) (0x19480 + ((_i) * 4)) |
152 | #define WX_RDB_RA_CTL 0x194F4 |
153 | #define BIT(2) /* RSS Enable */ |
154 | #define BIT(16) |
155 | #define BIT(17) |
156 | #define BIT(20) |
157 | #define BIT(21) |
158 | #define BIT(22) |
159 | #define BIT(23) |
160 | |
161 | /******************************* PSR Registers *******************************/ |
162 | /* psr control */ |
163 | #define WX_PSR_CTL 0x15000 |
164 | /* Header split receive */ |
165 | #define WX_PSR_CTL_SW_EN BIT(18) |
166 | #define WX_PSR_CTL_RSC_ACK BIT(17) |
167 | #define WX_PSR_CTL_RSC_DIS BIT(16) |
168 | #define WX_PSR_CTL_PCSD BIT(13) |
169 | #define WX_PSR_CTL_IPPCSE BIT(12) |
170 | #define WX_PSR_CTL_BAM BIT(10) |
171 | #define WX_PSR_CTL_UPE BIT(9) |
172 | #define WX_PSR_CTL_MPE BIT(8) |
173 | #define WX_PSR_CTL_MFE BIT(7) |
174 | #define WX_PSR_CTL_MO_SHIFT 5 |
175 | #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT) |
176 | #define WX_PSR_CTL_TPE BIT(4) |
177 | #define WX_PSR_MAX_SZ 0x15020 |
178 | #define WX_PSR_VLAN_CTL 0x15088 |
179 | #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */ |
180 | #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */ |
181 | /* mcasst/ucast overflow tbl */ |
182 | #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4)) |
183 | #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4)) |
184 | |
185 | /* VM L2 contorl */ |
186 | #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4)) |
187 | #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */ |
188 | #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */ |
189 | #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */ |
190 | #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */ |
191 | #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */ |
192 | #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */ |
193 | #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */ |
194 | |
195 | /* Management */ |
196 | #define WX_PSR_MNG_FLEX_SEL 0x1582C |
197 | #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16)) |
198 | #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16)) |
199 | #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16)) |
200 | #define WX_PSR_LAN_FLEX_SEL 0x15B8C |
201 | #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16)) |
202 | #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16)) |
203 | #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16)) |
204 | |
205 | #define WX_PSR_WKUP_CTL 0x15B80 |
206 | /* Wake Up Filter Control Bit */ |
207 | #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */ |
208 | |
209 | /* vlan tbl */ |
210 | #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4)) |
211 | |
212 | /* mac switcher */ |
213 | #define WX_PSR_MAC_SWC_AD_L 0x16200 |
214 | #define WX_PSR_MAC_SWC_AD_H 0x16204 |
215 | #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v) |
216 | #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v) |
217 | #define WX_PSR_MAC_SWC_AD_H_AV BIT(31) |
218 | #define WX_PSR_MAC_SWC_VM_L 0x16208 |
219 | #define WX_PSR_MAC_SWC_VM_H 0x1620C |
220 | #define WX_PSR_MAC_SWC_IDX 0x16210 |
221 | #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU |
222 | |
223 | /* vlan switch */ |
224 | #define WX_PSR_VLAN_SWC 0x16220 |
225 | #define WX_PSR_VLAN_SWC_VM_L 0x16224 |
226 | #define WX_PSR_VLAN_SWC_VM_H 0x16228 |
227 | #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */ |
228 | /* VLAN pool filtering masks */ |
229 | #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */ |
230 | #define WX_PSR_VLAN_SWC_ENTRIES 64 |
231 | |
232 | /********************************* RSEC **************************************/ |
233 | /* general rsec */ |
234 | #define WX_RSC_CTL 0x17000 |
235 | #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6) |
236 | #define WX_RSC_CTL_CRC_STRIP BIT(2) |
237 | #define WX_RSC_CTL_RX_DIS BIT(1) |
238 | #define WX_RSC_ST 0x17004 |
239 | #define WX_RSC_ST_RSEC_RDY BIT(0) |
240 | |
241 | /****************************** TDB ******************************************/ |
242 | #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4)) |
243 | #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ |
244 | |
245 | /****************************** TSEC *****************************************/ |
246 | /* Security Control Registers */ |
247 | #define WX_TSC_CTL 0x1D000 |
248 | #define WX_TSC_CTL_TX_DIS BIT(1) |
249 | #define WX_TSC_CTL_TSEC_DIS BIT(0) |
250 | #define WX_TSC_ST 0x1D004 |
251 | #define WX_TSC_ST_SECTX_RDY BIT(0) |
252 | #define WX_TSC_BUF_AE 0x1D00C |
253 | #define WX_TSC_BUF_AE_THR GENMASK(9, 0) |
254 | |
255 | /************************************** MNG ********************************/ |
256 | #define WX_MNG_SWFW_SYNC 0x1E008 |
257 | #define WX_MNG_SWFW_SYNC_SW_MB BIT(2) |
258 | #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3) |
259 | #define WX_MNG_MBOX 0x1E100 |
260 | #define WX_MNG_MBOX_CTL 0x1E044 |
261 | #define WX_MNG_MBOX_CTL_SWRDY BIT(0) |
262 | #define WX_MNG_MBOX_CTL_FWRDY BIT(2) |
263 | #define WX_MNG_BMC2OS_CNT 0x1E090 |
264 | #define WX_MNG_OS2BMC_CNT 0x1E094 |
265 | |
266 | /************************************* ETH MAC *****************************/ |
267 | #define WX_MAC_TX_CFG 0x11000 |
268 | #define WX_MAC_TX_CFG_TE BIT(0) |
269 | #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29) |
270 | #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0) |
271 | #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3) |
272 | #define WX_MAC_RX_CFG 0x11004 |
273 | #define WX_MAC_RX_CFG_RE BIT(0) |
274 | #define WX_MAC_RX_CFG_JE BIT(8) |
275 | #define WX_MAC_PKT_FLT 0x11008 |
276 | #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */ |
277 | #define WX_MAC_WDG_TIMEOUT 0x1100C |
278 | #define WX_MAC_RX_FLOW_CTRL 0x11090 |
279 | #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */ |
280 | /* MDIO Registers */ |
281 | #define WX_MSCA 0x11200 |
282 | #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v) |
283 | #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v) |
284 | #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v) |
285 | #define WX_MSCC 0x11204 |
286 | #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v) |
287 | |
288 | enum WX_MSCA_CMD_value { |
289 | WX_MSCA_CMD_RSV = 0, |
290 | WX_MSCA_CMD_WRITE, |
291 | WX_MSCA_CMD_POST_READ, |
292 | WX_MSCA_CMD_READ, |
293 | }; |
294 | |
295 | #define WX_MSCC_SADDR BIT(18) |
296 | #define WX_MSCC_BUSY BIT(22) |
297 | #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v) |
298 | #define WX_MDIO_CLAUSE_SELECT 0x11220 |
299 | #define WX_MMC_CONTROL 0x11800 |
300 | #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */ |
301 | |
302 | /********************************* BAR registers ***************************/ |
303 | /* Interrupt Registers */ |
304 | #define WX_BME_CTL 0x12020 |
305 | #define WX_PX_MISC_IC 0x100 |
306 | #define WX_PX_MISC_ICS 0x104 |
307 | #define WX_PX_MISC_IEN 0x108 |
308 | #define WX_PX_INTA 0x110 |
309 | #define WX_PX_GPIE 0x118 |
310 | #define WX_PX_GPIE_MODEL BIT(0) |
311 | #define WX_PX_IC(_i) (0x120 + (_i) * 4) |
312 | #define WX_PX_IMS(_i) (0x140 + (_i) * 4) |
313 | #define WX_PX_IMC(_i) (0x150 + (_i) * 4) |
314 | #define WX_PX_ISB_ADDR_L 0x160 |
315 | #define WX_PX_ISB_ADDR_H 0x164 |
316 | #define WX_PX_TRANSACTION_PENDING 0x168 |
317 | #define WX_PX_ITRSEL 0x180 |
318 | #define WX_PX_ITR(_i) (0x200 + (_i) * 4) |
319 | #define WX_PX_ITR_CNT_WDIS BIT(31) |
320 | #define WX_PX_MISC_IVAR 0x4FC |
321 | #define WX_PX_IVAR(_i) (0x500 + (_i) * 4) |
322 | |
323 | #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ |
324 | #define WX_7K_ITR 595 |
325 | #define WX_12K_ITR 336 |
326 | #define WX_20K_ITR 200 |
327 | #define WX_SP_MAX_EITR 0x00000FF8U |
328 | #define WX_EM_MAX_EITR 0x00007FFCU |
329 | |
330 | /* transmit DMA Registers */ |
331 | #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40)) |
332 | #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40)) |
333 | #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40)) |
334 | #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40)) |
335 | #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40)) |
336 | /* Transmit Config masks */ |
337 | #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */ |
338 | #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */ |
339 | #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */ |
340 | #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ |
341 | #define WX_PX_TR_CFG_THRE_SHIFT 8 |
342 | |
343 | /* Receive DMA Registers */ |
344 | #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40)) |
345 | #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40)) |
346 | #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40)) |
347 | #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40)) |
348 | #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40)) |
349 | #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40)) |
350 | /* PX_RR_CFG bit definitions */ |
351 | #define WX_PX_RR_CFG_VLAN BIT(31) |
352 | #define WX_PX_RR_CFG_DROP_EN BIT(30) |
353 | #define WX_PX_RR_CFG_SPLIT_MODE BIT(26) |
354 | #define WX_PX_RR_CFG_RR_THER_SHIFT 16 |
355 | #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12) |
356 | #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8) |
357 | #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6) |
358 | * + at bit 8 offset (<< 12) |
359 | * = (<< 6) |
360 | */ |
361 | #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */ |
362 | #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1 |
363 | #define WX_PX_RR_CFG_RR_EN BIT(0) |
364 | |
365 | /* Number of 80 microseconds we wait for PCI Express master disable */ |
366 | #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000 |
367 | |
368 | /****************** Manageablility Host Interface defines ********************/ |
369 | #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */ |
370 | #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */ |
371 | |
372 | #define FW_READ_SHADOW_RAM_CMD 0x31 |
373 | #define FW_READ_SHADOW_RAM_LEN 0x6 |
374 | #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ |
375 | #define FW_NVM_DATA_OFFSET 3 |
376 | #define FW_MAX_READ_BUFFER_SIZE 244 |
377 | #define FW_RESET_CMD 0xDF |
378 | #define FW_RESET_LEN 0x2 |
379 | #define FW_CEM_HDR_LEN 0x4 |
380 | #define FW_CEM_CMD_RESERVED 0X0 |
381 | #define FW_CEM_MAX_RETRIES 3 |
382 | #define FW_CEM_RESP_STATUS_SUCCESS 0x1 |
383 | |
384 | #define WX_SW_REGION_PTR 0x1C |
385 | |
386 | #define WX_MAC_STATE_DEFAULT 0x1 |
387 | #define WX_MAC_STATE_MODIFIED 0x2 |
388 | #define WX_MAC_STATE_IN_USE 0x4 |
389 | |
390 | /* BitTimes (BT) conversion */ |
391 | #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024)) |
392 | #define WX_B2BT(BT) ((BT) * 8) |
393 | |
394 | /* Calculate Delay to respond to PFC */ |
395 | #define WX_PFC_D 672 |
396 | /* Calculate Cable Delay */ |
397 | #define WX_CABLE_DC 5556 /* Delay Copper */ |
398 | /* Calculate Delay incurred from higher layer */ |
399 | #define WX_HD 6144 |
400 | |
401 | /* Calculate Interface Delay */ |
402 | #define WX_PHY_D 12800 |
403 | #define WX_MAC_D 4096 |
404 | #define WX_XAUI_D (2 * 1024) |
405 | #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D) |
406 | /* Calculate PCI Bus delay for low thresholds */ |
407 | #define WX_PCI_DELAY 10000 |
408 | |
409 | /* Calculate delay value in bit times */ |
410 | #define WX_DV(_max_frame_link, _max_frame_tc) \ |
411 | ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \ |
412 | (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \ |
413 | 2 * WX_B2BT(_max_frame_tc)) |
414 | |
415 | /* Calculate low threshold delay values */ |
416 | #define WX_LOW_DV(_max_frame_tc) \ |
417 | (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1)) |
418 | |
419 | /* flow control */ |
420 | #define WX_DEFAULT_FCPAUSE 0xFFFF |
421 | |
422 | #define WX_MAX_RXD 8192 |
423 | #define WX_MAX_TXD 8192 |
424 | #define WX_MIN_RXD 128 |
425 | #define WX_MIN_TXD 128 |
426 | |
427 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ |
428 | #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 8 |
429 | #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 8 |
430 | |
431 | #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */ |
432 | #define VMDQ_P(p) p |
433 | |
434 | /* Supported Rx Buffer Sizes */ |
435 | #define WX_RXBUFFER_256 256 /* Used for skb receive header */ |
436 | #define WX_RXBUFFER_2K 2048 |
437 | #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */ |
438 | |
439 | #if MAX_SKB_FRAGS < 8 |
440 | #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024) |
441 | #else |
442 | #define WX_RX_BUFSZ WX_RXBUFFER_2K |
443 | #endif |
444 | |
445 | #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
446 | |
447 | #define WX_MAX_DATA_PER_TXD BIT(14) |
448 | /* Tx Descriptors needed, worst case */ |
449 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD) |
450 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
451 | |
452 | #define WX_CFG_PORT_ST 0x14404 |
453 | |
454 | /******************* Receive Descriptor bit definitions **********************/ |
455 | #define WX_RXD_STAT_DD BIT(0) /* Done */ |
456 | #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */ |
457 | #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */ |
458 | #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */ |
459 | #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */ |
460 | #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/ |
461 | |
462 | #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */ |
463 | #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */ |
464 | #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */ |
465 | #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */ |
466 | |
467 | /* RSS Hash results */ |
468 | #define GENMASK(3, 0) |
469 | #define 0x00000001U |
470 | #define 0x00000003U |
471 | #define 0x00000004U |
472 | #define 0x00000006U |
473 | #define 0x00000007U |
474 | #define 0x00000008U |
475 | |
476 | #define \ |
477 | ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \ |
478 | (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \ |
479 | (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \ |
480 | (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \ |
481 | (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \ |
482 | (1ul << WX_RXD_RSSTYPE_IPV6_SCTP)) |
483 | /* TUN */ |
484 | #define WX_PTYPE_TUN_IPV4 0x80 |
485 | #define WX_PTYPE_TUN_IPV6 0xC0 |
486 | |
487 | /* PKT for TUN */ |
488 | #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */ |
489 | #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */ |
490 | #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */ |
491 | #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */ |
492 | /* PKT for !TUN */ |
493 | #define WX_PTYPE_PKT_MAC 0x10 |
494 | #define WX_PTYPE_PKT_IP 0x20 |
495 | |
496 | /* TYP for PKT=mac */ |
497 | #define WX_PTYPE_TYP_MAC 0x01 |
498 | /* TYP for PKT=ip */ |
499 | #define WX_PTYPE_PKT_IPV6 0x08 |
500 | #define WX_PTYPE_TYP_IPFRAG 0x01 |
501 | #define WX_PTYPE_TYP_IP 0x02 |
502 | #define WX_PTYPE_TYP_UDP 0x03 |
503 | #define WX_PTYPE_TYP_TCP 0x04 |
504 | #define WX_PTYPE_TYP_SCTP 0x05 |
505 | |
506 | #define WX_RXD_PKTTYPE(_rxd) \ |
507 | ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF) |
508 | #define WX_RXD_IPV6EX(_rxd) \ |
509 | ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 6) & 0x1) |
510 | /*********************** Transmit Descriptor Config Masks ****************/ |
511 | #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */ |
512 | #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */ |
513 | #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */ |
514 | #define WX_TXD_EOP BIT(24) /* End of Packet */ |
515 | #define WX_TXD_IFCS BIT(25) /* Insert FCS */ |
516 | #define WX_TXD_RS BIT(27) /* Report Status */ |
517 | |
518 | /*********************** Adv Transmit Descriptor Config Masks ****************/ |
519 | #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */ |
520 | #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */ |
521 | #define WX_TXD_LINKSEC BIT(26) /* enable linksec */ |
522 | #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */ |
523 | #define WX_TXD_TSE BIT(31) /* TCP Seg enable */ |
524 | #define WX_TXD_CC BIT(7) /* Check Context */ |
525 | #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */ |
526 | #define WX_TXD_L4CS BIT(9) |
527 | #define WX_TXD_IIPCS BIT(10) |
528 | #define WX_TXD_EIPCS BIT(11) |
529 | #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */ |
530 | #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ |
531 | #define WX_TXD_TAG_TPID_SEL_SHIFT 11 |
532 | |
533 | #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ |
534 | #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ |
535 | |
536 | #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */ |
537 | #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */ |
538 | #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */ |
539 | #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0) |
540 | #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1) |
541 | |
542 | enum wx_tx_flags { |
543 | /* cmd_type flags */ |
544 | WX_TX_FLAGS_HW_VLAN = 0x01, |
545 | WX_TX_FLAGS_TSO = 0x02, |
546 | WX_TX_FLAGS_TSTAMP = 0x04, |
547 | |
548 | /* olinfo flags */ |
549 | WX_TX_FLAGS_CC = 0x08, |
550 | WX_TX_FLAGS_IPV4 = 0x10, |
551 | WX_TX_FLAGS_CSUM = 0x20, |
552 | WX_TX_FLAGS_OUTER_IPV4 = 0x100, |
553 | WX_TX_FLAGS_LINKSEC = 0x200, |
554 | WX_TX_FLAGS_IPSEC = 0x400, |
555 | }; |
556 | |
557 | /* VLAN info */ |
558 | #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16) |
559 | #define WX_TX_FLAGS_VLAN_SHIFT 16 |
560 | |
561 | /* wx_dec_ptype.mac: outer mac */ |
562 | enum wx_dec_ptype_mac { |
563 | WX_DEC_PTYPE_MAC_IP = 0, |
564 | WX_DEC_PTYPE_MAC_L2 = 2, |
565 | WX_DEC_PTYPE_MAC_FCOE = 3, |
566 | }; |
567 | |
568 | /* wx_dec_ptype.[e]ip: outer&encaped ip */ |
569 | #define WX_DEC_PTYPE_IP_FRAG 0x4 |
570 | enum wx_dec_ptype_ip { |
571 | WX_DEC_PTYPE_IP_NONE = 0, |
572 | WX_DEC_PTYPE_IP_IPV4 = 1, |
573 | WX_DEC_PTYPE_IP_IPV6 = 2, |
574 | WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4, |
575 | WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6, |
576 | }; |
577 | |
578 | /* wx_dec_ptype.etype: encaped type */ |
579 | enum wx_dec_ptype_etype { |
580 | WX_DEC_PTYPE_ETYPE_NONE = 0, |
581 | WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */ |
582 | WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */ |
583 | WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */ |
584 | WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */ |
585 | }; |
586 | |
587 | /* wx_dec_ptype.proto: payload proto */ |
588 | enum wx_dec_ptype_prot { |
589 | WX_DEC_PTYPE_PROT_NONE = 0, |
590 | WX_DEC_PTYPE_PROT_UDP = 1, |
591 | WX_DEC_PTYPE_PROT_TCP = 2, |
592 | WX_DEC_PTYPE_PROT_SCTP = 3, |
593 | WX_DEC_PTYPE_PROT_ICMP = 4, |
594 | WX_DEC_PTYPE_PROT_TS = 5, /* time sync */ |
595 | }; |
596 | |
597 | /* wx_dec_ptype.layer: payload layer */ |
598 | enum wx_dec_ptype_layer { |
599 | WX_DEC_PTYPE_LAYER_NONE = 0, |
600 | WX_DEC_PTYPE_LAYER_PAY2 = 1, |
601 | WX_DEC_PTYPE_LAYER_PAY3 = 2, |
602 | WX_DEC_PTYPE_LAYER_PAY4 = 3, |
603 | }; |
604 | |
605 | struct wx_dec_ptype { |
606 | u32 known:1; |
607 | u32 mac:2; /* outer mac */ |
608 | u32 ip:3; /* outer ip*/ |
609 | u32 etype:3; /* encaped type */ |
610 | u32 eip:3; /* encaped ip */ |
611 | u32 prot:4; /* payload proto */ |
612 | u32 layer:3; /* payload layer */ |
613 | }; |
614 | |
615 | /* macro to make the table lines short */ |
616 | #define WX_PTT(mac, ip, etype, eip, proto, layer)\ |
617 | {1, \ |
618 | WX_DEC_PTYPE_MAC_##mac, /* mac */\ |
619 | WX_DEC_PTYPE_IP_##ip, /* ip */ \ |
620 | WX_DEC_PTYPE_ETYPE_##etype, /* etype */\ |
621 | WX_DEC_PTYPE_IP_##eip, /* eip */\ |
622 | WX_DEC_PTYPE_PROT_##proto, /* proto */\ |
623 | WX_DEC_PTYPE_LAYER_##layer /* layer */} |
624 | |
625 | /* Host Interface Command Structures */ |
626 | struct wx_hic_hdr { |
627 | u8 cmd; |
628 | u8 buf_len; |
629 | union { |
630 | u8 cmd_resv; |
631 | u8 ret_status; |
632 | } cmd_or_resp; |
633 | u8 checksum; |
634 | }; |
635 | |
636 | struct wx_hic_hdr2_req { |
637 | u8 cmd; |
638 | u8 buf_lenh; |
639 | u8 buf_lenl; |
640 | u8 checksum; |
641 | }; |
642 | |
643 | struct wx_hic_hdr2_rsp { |
644 | u8 cmd; |
645 | u8 buf_lenl; |
646 | u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ |
647 | u8 checksum; |
648 | }; |
649 | |
650 | union wx_hic_hdr2 { |
651 | struct wx_hic_hdr2_req req; |
652 | struct wx_hic_hdr2_rsp rsp; |
653 | }; |
654 | |
655 | /* These need to be dword aligned */ |
656 | struct wx_hic_read_shadow_ram { |
657 | union wx_hic_hdr2 hdr; |
658 | u32 address; |
659 | u16 length; |
660 | u16 pad2; |
661 | u16 data; |
662 | u16 pad3; |
663 | }; |
664 | |
665 | struct wx_hic_reset { |
666 | struct wx_hic_hdr hdr; |
667 | u16 lan_id; |
668 | u16 reset_type; |
669 | }; |
670 | |
671 | /* Bus parameters */ |
672 | struct wx_bus_info { |
673 | u8 func; |
674 | u16 device; |
675 | }; |
676 | |
677 | struct wx_thermal_sensor_data { |
678 | s16 temp; |
679 | s16 alarm_thresh; |
680 | s16 dalarm_thresh; |
681 | }; |
682 | |
683 | enum wx_mac_type { |
684 | wx_mac_unknown = 0, |
685 | wx_mac_sp, |
686 | wx_mac_em |
687 | }; |
688 | |
689 | enum sp_media_type { |
690 | sp_media_unknown = 0, |
691 | sp_media_fiber, |
692 | sp_media_copper, |
693 | sp_media_backplane |
694 | }; |
695 | |
696 | enum em_mac_type { |
697 | em_mac_type_unknown = 0, |
698 | em_mac_type_mdi, |
699 | em_mac_type_rgmii |
700 | }; |
701 | |
702 | struct wx_mac_info { |
703 | enum wx_mac_type type; |
704 | bool set_lben; |
705 | u8 addr[ETH_ALEN]; |
706 | u8 perm_addr[ETH_ALEN]; |
707 | u32 mta_shadow[128]; |
708 | s32 mc_filter_type; |
709 | u32 mcft_size; |
710 | u32 vft_shadow[128]; |
711 | u32 vft_size; |
712 | u32 num_rar_entries; |
713 | u32 rx_pb_size; |
714 | u32 tx_pb_size; |
715 | u32 max_tx_queues; |
716 | u32 max_rx_queues; |
717 | |
718 | u16 max_msix_vectors; |
719 | struct wx_thermal_sensor_data sensor; |
720 | }; |
721 | |
722 | enum wx_eeprom_type { |
723 | wx_eeprom_uninitialized = 0, |
724 | wx_eeprom_spi, |
725 | wx_flash, |
726 | wx_eeprom_none /* No NVM support */ |
727 | }; |
728 | |
729 | struct wx_eeprom_info { |
730 | enum wx_eeprom_type type; |
731 | u32 semaphore_delay; |
732 | u16 word_size; |
733 | u16 sw_region_offset; |
734 | }; |
735 | |
736 | struct wx_addr_filter_info { |
737 | u32 num_mc_addrs; |
738 | u32 mta_in_use; |
739 | bool user_set_promisc; |
740 | }; |
741 | |
742 | struct wx_mac_addr { |
743 | u8 addr[ETH_ALEN]; |
744 | u16 state; /* bitmask */ |
745 | u64 pools; |
746 | }; |
747 | |
748 | enum wx_reset_type { |
749 | WX_LAN_RESET = 0, |
750 | WX_SW_RESET, |
751 | WX_GLOBAL_RESET |
752 | }; |
753 | |
754 | struct wx_cb { |
755 | dma_addr_t dma; |
756 | u16 append_cnt; /* number of skb's appended */ |
757 | bool page_released; |
758 | bool dma_released; |
759 | }; |
760 | |
761 | #define WX_CB(skb) ((struct wx_cb *)(skb)->cb) |
762 | |
763 | /* Transmit Descriptor */ |
764 | union wx_tx_desc { |
765 | struct { |
766 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
767 | __le32 cmd_type_len; |
768 | __le32 olinfo_status; |
769 | } read; |
770 | struct { |
771 | __le64 rsvd; /* Reserved */ |
772 | __le32 nxtseq_seed; |
773 | __le32 status; |
774 | } wb; |
775 | }; |
776 | |
777 | /* Receive Descriptor */ |
778 | union wx_rx_desc { |
779 | struct { |
780 | __le64 pkt_addr; /* Packet buffer address */ |
781 | __le64 hdr_addr; /* Header buffer address */ |
782 | } read; |
783 | struct { |
784 | struct { |
785 | union { |
786 | __le32 data; |
787 | struct { |
788 | __le16 pkt_info; /* RSS, Pkt type */ |
789 | __le16 hdr_info; /* Splithdr, hdrlen */ |
790 | } ; |
791 | } lo_dword; |
792 | union { |
793 | __le32 ; /* RSS Hash */ |
794 | struct { |
795 | __le16 ip_id; /* IP id */ |
796 | __le16 csum; /* Packet Checksum */ |
797 | } csum_ip; |
798 | } hi_dword; |
799 | } lower; |
800 | struct { |
801 | __le32 status_error; /* ext status/error */ |
802 | __le16 length; /* Packet length */ |
803 | __le16 vlan; /* VLAN tag */ |
804 | } upper; |
805 | } wb; /* writeback */ |
806 | }; |
807 | |
808 | struct wx_tx_context_desc { |
809 | __le32 vlan_macip_lens; |
810 | __le32 seqnum_seed; |
811 | __le32 type_tucmd_mlhl; |
812 | __le32 mss_l4len_idx; |
813 | }; |
814 | |
815 | /* if _flag is in _input, return _result */ |
816 | #define WX_SET_FLAG(_input, _flag, _result) \ |
817 | (((_flag) <= (_result)) ? \ |
818 | ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \ |
819 | ((u32)((_input) & (_flag)) / ((_flag) / (_result)))) |
820 | |
821 | #define WX_RX_DESC(R, i) \ |
822 | (&(((union wx_rx_desc *)((R)->desc))[i])) |
823 | #define WX_TX_DESC(R, i) \ |
824 | (&(((union wx_tx_desc *)((R)->desc))[i])) |
825 | #define WX_TX_CTXTDESC(R, i) \ |
826 | (&(((struct wx_tx_context_desc *)((R)->desc))[i])) |
827 | |
828 | /* wrapper around a pointer to a socket buffer, |
829 | * so a DMA handle can be stored along with the buffer |
830 | */ |
831 | struct wx_tx_buffer { |
832 | union wx_tx_desc *next_to_watch; |
833 | struct sk_buff *skb; |
834 | unsigned int bytecount; |
835 | unsigned short gso_segs; |
836 | DEFINE_DMA_UNMAP_ADDR(dma); |
837 | DEFINE_DMA_UNMAP_LEN(len); |
838 | __be16 protocol; |
839 | u32 tx_flags; |
840 | }; |
841 | |
842 | struct wx_rx_buffer { |
843 | struct sk_buff *skb; |
844 | dma_addr_t dma; |
845 | dma_addr_t page_dma; |
846 | struct page *page; |
847 | unsigned int page_offset; |
848 | }; |
849 | |
850 | struct wx_queue_stats { |
851 | u64 packets; |
852 | u64 bytes; |
853 | }; |
854 | |
855 | struct wx_tx_queue_stats { |
856 | u64 restart_queue; |
857 | u64 tx_busy; |
858 | }; |
859 | |
860 | struct wx_rx_queue_stats { |
861 | u64 non_eop_descs; |
862 | u64 csum_good_cnt; |
863 | u64 csum_err; |
864 | u64 alloc_rx_buff_failed; |
865 | }; |
866 | |
867 | /* iterator for handling rings in ring container */ |
868 | #define wx_for_each_ring(posm, headm) \ |
869 | for (posm = (headm).ring; posm; posm = posm->next) |
870 | |
871 | struct wx_ring_container { |
872 | struct wx_ring *ring; /* pointer to linked list of rings */ |
873 | unsigned int total_bytes; /* total bytes processed this int */ |
874 | unsigned int total_packets; /* total packets processed this int */ |
875 | u8 count; /* total number of rings in vector */ |
876 | u8 itr; /* current ITR setting for ring */ |
877 | }; |
878 | struct wx_ring { |
879 | struct wx_ring *next; /* pointer to next ring in q_vector */ |
880 | struct wx_q_vector *q_vector; /* backpointer to host q_vector */ |
881 | struct net_device *netdev; /* netdev ring belongs to */ |
882 | struct device *dev; /* device for DMA mapping */ |
883 | struct page_pool *page_pool; |
884 | void *desc; /* descriptor ring memory */ |
885 | union { |
886 | struct wx_tx_buffer *tx_buffer_info; |
887 | struct wx_rx_buffer *rx_buffer_info; |
888 | }; |
889 | u8 __iomem *tail; |
890 | dma_addr_t dma; /* phys. address of descriptor ring */ |
891 | unsigned int size; /* length in bytes */ |
892 | |
893 | u16 count; /* amount of descriptors */ |
894 | |
895 | u8 queue_index; /* needed for multiqueue queue management */ |
896 | u8 reg_idx; /* holds the special value that gets |
897 | * the hardware register offset |
898 | * associated with this ring, which is |
899 | * different for DCB and RSS modes |
900 | */ |
901 | u16 next_to_use; |
902 | u16 next_to_clean; |
903 | u16 next_to_alloc; |
904 | |
905 | struct wx_queue_stats stats; |
906 | struct u64_stats_sync syncp; |
907 | union { |
908 | struct wx_tx_queue_stats tx_stats; |
909 | struct wx_rx_queue_stats rx_stats; |
910 | }; |
911 | } ____cacheline_internodealigned_in_smp; |
912 | |
913 | struct wx_q_vector { |
914 | struct wx *wx; |
915 | int cpu; /* CPU for DCA */ |
916 | int numa_node; |
917 | u16 v_idx; /* index of q_vector within array, also used for |
918 | * finding the bit in EICR and friends that |
919 | * represents the vector for this ring |
920 | */ |
921 | u16 itr; /* Interrupt throttle rate written to EITR */ |
922 | struct wx_ring_container rx, tx; |
923 | struct napi_struct napi; |
924 | struct rcu_head rcu; /* to avoid race with update stats on free */ |
925 | |
926 | char name[IFNAMSIZ + 17]; |
927 | |
928 | /* for dynamic allocation of rings associated with this q_vector */ |
929 | struct wx_ring ring[] ____cacheline_internodealigned_in_smp; |
930 | }; |
931 | |
932 | struct wx_ring_feature { |
933 | u16 limit; /* upper limit on feature indices */ |
934 | u16 indices; /* current value of indices */ |
935 | u16 mask; /* Mask used for feature to ring mapping */ |
936 | u16 offset; /* offset to start of feature */ |
937 | }; |
938 | |
939 | enum wx_ring_f_enum { |
940 | RING_F_NONE = 0, |
941 | , |
942 | RING_F_ARRAY_SIZE /* must be last in enum set */ |
943 | }; |
944 | |
945 | enum wx_isb_idx { |
946 | , |
947 | WX_ISB_MISC, |
948 | WX_ISB_VEC0, |
949 | WX_ISB_VEC1, |
950 | WX_ISB_MAX |
951 | }; |
952 | |
953 | struct wx_fc_info { |
954 | u32 high_water; /* Flow Ctrl High-water */ |
955 | u32 low_water; /* Flow Ctrl Low-water */ |
956 | }; |
957 | |
958 | /* Statistics counters collected by the MAC */ |
959 | struct wx_hw_stats { |
960 | u64 gprc; |
961 | u64 gptc; |
962 | u64 gorc; |
963 | u64 gotc; |
964 | u64 tpr; |
965 | u64 tpt; |
966 | u64 bprc; |
967 | u64 bptc; |
968 | u64 mprc; |
969 | u64 mptc; |
970 | u64 roc; |
971 | u64 ruc; |
972 | u64 lxonoffrxc; |
973 | u64 lxontxc; |
974 | u64 lxofftxc; |
975 | u64 o2bgptc; |
976 | u64 b2ospc; |
977 | u64 o2bspc; |
978 | u64 b2ogprc; |
979 | u64 rdmdrop; |
980 | u64 crcerrs; |
981 | u64 rlec; |
982 | u64 qmprc; |
983 | }; |
984 | |
985 | struct wx { |
986 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
987 | |
988 | void *priv; |
989 | u8 __iomem *hw_addr; |
990 | struct pci_dev *pdev; |
991 | struct net_device *netdev; |
992 | struct wx_bus_info bus; |
993 | struct wx_mac_info mac; |
994 | enum em_mac_type mac_type; |
995 | enum sp_media_type media_type; |
996 | struct wx_eeprom_info eeprom; |
997 | struct wx_addr_filter_info addr_ctrl; |
998 | struct wx_fc_info fc; |
999 | struct wx_mac_addr *mac_table; |
1000 | u16 device_id; |
1001 | u16 vendor_id; |
1002 | u16 subsystem_device_id; |
1003 | u16 subsystem_vendor_id; |
1004 | u8 revision_id; |
1005 | u16 oem_ssid; |
1006 | u16 oem_svid; |
1007 | u16 msg_enable; |
1008 | bool adapter_stopped; |
1009 | u16 tpid[8]; |
1010 | char eeprom_id[32]; |
1011 | char *driver_name; |
1012 | enum wx_reset_type reset_type; |
1013 | |
1014 | /* PHY stuff */ |
1015 | unsigned int link; |
1016 | int speed; |
1017 | int duplex; |
1018 | struct phy_device *phydev; |
1019 | struct phylink *phylink; |
1020 | struct phylink_config phylink_config; |
1021 | |
1022 | bool wol_hw_supported; |
1023 | bool ncsi_enabled; |
1024 | bool gpio_ctrl; |
1025 | raw_spinlock_t gpio_lock; |
1026 | |
1027 | /* Tx fast path data */ |
1028 | int num_tx_queues; |
1029 | u16 tx_itr_setting; |
1030 | u16 tx_work_limit; |
1031 | |
1032 | /* Rx fast path data */ |
1033 | int num_rx_queues; |
1034 | u16 rx_itr_setting; |
1035 | u16 rx_work_limit; |
1036 | |
1037 | int num_q_vectors; /* current number of q_vectors for device */ |
1038 | int max_q_vectors; /* upper limit of q_vectors for device */ |
1039 | |
1040 | u32 tx_ring_count; |
1041 | u32 rx_ring_count; |
1042 | |
1043 | struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp; |
1044 | struct wx_ring *rx_ring[64]; |
1045 | struct wx_q_vector *q_vector[64]; |
1046 | |
1047 | unsigned int queues_per_pool; |
1048 | struct msix_entry *msix_q_entries; |
1049 | struct msix_entry *msix_entry; |
1050 | struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
1051 | |
1052 | /* misc interrupt status block */ |
1053 | dma_addr_t isb_dma; |
1054 | u32 *isb_mem; |
1055 | u32 isb_tag[WX_ISB_MAX]; |
1056 | |
1057 | #define WX_MAX_RETA_ENTRIES 128 |
1058 | #define 64 |
1059 | u8 [WX_MAX_RETA_ENTRIES]; |
1060 | bool ; |
1061 | #define 40 /* size of RSS Hash Key in bytes */ |
1062 | u32 *; |
1063 | u32 wol; |
1064 | |
1065 | u16 bd_number; |
1066 | |
1067 | struct wx_hw_stats stats; |
1068 | u64 tx_busy; |
1069 | u64 non_eop_descs; |
1070 | u64 restart_queue; |
1071 | u64 hw_csum_rx_good; |
1072 | u64 hw_csum_rx_error; |
1073 | u64 alloc_rx_buff_failed; |
1074 | }; |
1075 | |
1076 | #define WX_INTR_ALL (~0ULL) |
1077 | #define WX_INTR_Q(i) BIT((i) + 1) |
1078 | |
1079 | /* register operations */ |
1080 | #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) |
1081 | #define rd32(a, reg) readl((a)->hw_addr + (reg)) |
1082 | #define rd32a(a, reg, offset) ( \ |
1083 | rd32((a), (reg) + ((offset) << 2))) |
1084 | #define wr32a(a, reg, off, val) \ |
1085 | wr32((a), (reg) + ((off) << 2), (val)) |
1086 | |
1087 | static inline u32 |
1088 | rd32m(struct wx *wx, u32 reg, u32 mask) |
1089 | { |
1090 | u32 val; |
1091 | |
1092 | val = rd32(wx, reg); |
1093 | return val & mask; |
1094 | } |
1095 | |
1096 | static inline void |
1097 | wr32m(struct wx *wx, u32 reg, u32 mask, u32 field) |
1098 | { |
1099 | u32 val; |
1100 | |
1101 | val = rd32(wx, reg); |
1102 | val = ((val & ~mask) | (field & mask)); |
1103 | |
1104 | wr32(wx, reg, val); |
1105 | } |
1106 | |
1107 | static inline u64 |
1108 | rd64(struct wx *wx, u32 reg) |
1109 | { |
1110 | u64 lsb, msb; |
1111 | |
1112 | lsb = rd32(wx, reg); |
1113 | msb = rd32(wx, reg + 4); |
1114 | |
1115 | return (lsb | msb << 32); |
1116 | } |
1117 | |
1118 | /* On some domestic CPU platforms, sometimes IO is not synchronized with |
1119 | * flushing memory, here use readl() to flush PCI read and write. |
1120 | */ |
1121 | #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR) |
1122 | |
1123 | #define wx_err(wx, fmt, arg...) \ |
1124 | dev_err(&(wx)->pdev->dev, fmt, ##arg) |
1125 | |
1126 | #define wx_dbg(wx, fmt, arg...) \ |
1127 | dev_dbg(&(wx)->pdev->dev, fmt, ##arg) |
1128 | |
1129 | static inline struct wx *phylink_to_wx(struct phylink_config *config) |
1130 | { |
1131 | return container_of(config, struct wx, phylink_config); |
1132 | } |
1133 | |
1134 | #endif /* _WX_TYPE_H_ */ |
1135 | |