1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10#include <linux/phy.h>
11#include <linux/module.h>
12#include <linux/string.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/ethtool_netlink.h>
16#include <linux/bitfield.h>
17#include <linux/regulator/of_regulator.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of.h>
21#include <linux/phylink.h>
22#include <linux/sfp.h>
23#include <dt-bindings/net/qca-ar803x.h>
24
25#include "qcom.h"
26
27#define AT803X_LED_CONTROL 0x18
28
29#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
30#define AT803X_WOL_EN BIT(5)
31
32#define AT803X_REG_CHIP_CONFIG 0x1f
33#define AT803X_BT_BX_REG_SEL 0x8000
34
35#define AT803X_MODE_CFG_MASK 0x0F
36#define AT803X_MODE_CFG_BASET_RGMII 0x00
37#define AT803X_MODE_CFG_BASET_SGMII 0x01
38#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
39#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
40#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
41#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
42#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
43#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
44#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
45#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
46#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
47
48#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
49#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
50
51#define AT803X_DEBUG_REG_1F 0x1F
52#define AT803X_DEBUG_PLL_ON BIT(2)
53#define AT803X_DEBUG_RGMII_1V8 BIT(3)
54
55/* AT803x supports either the XTAL input pad, an internal PLL or the
56 * DSP as clock reference for the clock output pad. The XTAL reference
57 * is only used for 25 MHz output, all other frequencies need the PLL.
58 * The DSP as a clock reference is used in synchronous ethernet
59 * applications.
60 *
61 * By default the PLL is only enabled if there is a link. Otherwise
62 * the PHY will go into low power state and disabled the PLL. You can
63 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
64 * enabled.
65 */
66#define AT803X_MMD7_CLK25M 0x8016
67#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
68#define AT803X_CLK_OUT_25MHZ_XTAL 0
69#define AT803X_CLK_OUT_25MHZ_DSP 1
70#define AT803X_CLK_OUT_50MHZ_PLL 2
71#define AT803X_CLK_OUT_50MHZ_DSP 3
72#define AT803X_CLK_OUT_62_5MHZ_PLL 4
73#define AT803X_CLK_OUT_62_5MHZ_DSP 5
74#define AT803X_CLK_OUT_125MHZ_PLL 6
75#define AT803X_CLK_OUT_125MHZ_DSP 7
76
77/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
78 * but doesn't support choosing between XTAL/PLL and DSP.
79 */
80#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
81
82#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
83#define AT803X_CLK_OUT_STRENGTH_FULL 0
84#define AT803X_CLK_OUT_STRENGTH_HALF 1
85#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
86
87#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
88#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
89#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
90#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
91
92#define ATH9331_PHY_ID 0x004dd041
93#define ATH8030_PHY_ID 0x004dd076
94#define ATH8031_PHY_ID 0x004dd074
95#define ATH8032_PHY_ID 0x004dd023
96#define ATH8035_PHY_ID 0x004dd072
97#define AT8030_PHY_ID_MASK 0xffffffef
98
99#define QCA9561_PHY_ID 0x004dd042
100
101#define AT803X_PAGE_FIBER 0
102#define AT803X_PAGE_COPPER 1
103
104/* don't turn off internal PLL */
105#define AT803X_KEEP_PLL_ENABLED BIT(0)
106#define AT803X_DISABLE_SMARTEEE BIT(1)
107
108/* disable hibernation mode */
109#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
110
111MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
112MODULE_AUTHOR("Matus Ujhelyi");
113MODULE_LICENSE("GPL");
114
115struct at803x_priv {
116 int flags;
117 u16 clk_25m_reg;
118 u16 clk_25m_mask;
119 u8 smarteee_lpi_tw_1g;
120 u8 smarteee_lpi_tw_100m;
121 bool is_fiber;
122 bool is_1000basex;
123 struct regulator_dev *vddio_rdev;
124 struct regulator_dev *vddh_rdev;
125};
126
127struct at803x_context {
128 u16 bmcr;
129 u16 advertise;
130 u16 control1000;
131 u16 int_enable;
132 u16 smart_speed;
133 u16 led_control;
134};
135
136static int at803x_write_page(struct phy_device *phydev, int page)
137{
138 int mask;
139 int set;
140
141 if (page == AT803X_PAGE_COPPER) {
142 set = AT803X_BT_BX_REG_SEL;
143 mask = 0;
144 } else {
145 set = 0;
146 mask = AT803X_BT_BX_REG_SEL;
147 }
148
149 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
150}
151
152static int at803x_read_page(struct phy_device *phydev)
153{
154 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
155
156 if (ccr < 0)
157 return ccr;
158
159 if (ccr & AT803X_BT_BX_REG_SEL)
160 return AT803X_PAGE_COPPER;
161
162 return AT803X_PAGE_FIBER;
163}
164
165static int at803x_enable_rx_delay(struct phy_device *phydev)
166{
167 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, clear: 0,
168 AT803X_DEBUG_RX_CLK_DLY_EN);
169}
170
171static int at803x_enable_tx_delay(struct phy_device *phydev)
172{
173 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, clear: 0,
174 AT803X_DEBUG_TX_CLK_DLY_EN);
175}
176
177static int at803x_disable_rx_delay(struct phy_device *phydev)
178{
179 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
180 AT803X_DEBUG_RX_CLK_DLY_EN, set: 0);
181}
182
183static int at803x_disable_tx_delay(struct phy_device *phydev)
184{
185 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
186 AT803X_DEBUG_TX_CLK_DLY_EN, set: 0);
187}
188
189/* save relevant PHY registers to private copy */
190static void at803x_context_save(struct phy_device *phydev,
191 struct at803x_context *context)
192{
193 context->bmcr = phy_read(phydev, MII_BMCR);
194 context->advertise = phy_read(phydev, MII_ADVERTISE);
195 context->control1000 = phy_read(phydev, MII_CTRL1000);
196 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
197 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
198 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
199}
200
201/* restore relevant PHY registers from private copy */
202static void at803x_context_restore(struct phy_device *phydev,
203 const struct at803x_context *context)
204{
205 phy_write(phydev, MII_BMCR, val: context->bmcr);
206 phy_write(phydev, MII_ADVERTISE, val: context->advertise);
207 phy_write(phydev, MII_CTRL1000, val: context->control1000);
208 phy_write(phydev, AT803X_INTR_ENABLE, val: context->int_enable);
209 phy_write(phydev, AT803X_SMART_SPEED, val: context->smart_speed);
210 phy_write(phydev, AT803X_LED_CONTROL, val: context->led_control);
211}
212
213static int at803x_suspend(struct phy_device *phydev)
214{
215 int value;
216 int wol_enabled;
217
218 value = phy_read(phydev, AT803X_INTR_ENABLE);
219 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
220
221 if (wol_enabled)
222 value = BMCR_ISOLATE;
223 else
224 value = BMCR_PDOWN;
225
226 phy_modify(phydev, MII_BMCR, mask: 0, set: value);
227
228 return 0;
229}
230
231static int at803x_resume(struct phy_device *phydev)
232{
233 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, set: 0);
234}
235
236static int at803x_parse_dt(struct phy_device *phydev)
237{
238 struct device_node *node = phydev->mdio.dev.of_node;
239 struct at803x_priv *priv = phydev->priv;
240 u32 freq, strength, tw;
241 unsigned int sel;
242 int ret;
243
244 if (!IS_ENABLED(CONFIG_OF_MDIO))
245 return 0;
246
247 if (of_property_read_bool(np: node, propname: "qca,disable-smarteee"))
248 priv->flags |= AT803X_DISABLE_SMARTEEE;
249
250 if (of_property_read_bool(np: node, propname: "qca,disable-hibernation-mode"))
251 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
252
253 if (!of_property_read_u32(np: node, propname: "qca,smarteee-tw-us-1g", out_value: &tw)) {
254 if (!tw || tw > 255) {
255 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
256 return -EINVAL;
257 }
258 priv->smarteee_lpi_tw_1g = tw;
259 }
260
261 if (!of_property_read_u32(np: node, propname: "qca,smarteee-tw-us-100m", out_value: &tw)) {
262 if (!tw || tw > 255) {
263 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
264 return -EINVAL;
265 }
266 priv->smarteee_lpi_tw_100m = tw;
267 }
268
269 ret = of_property_read_u32(np: node, propname: "qca,clk-out-frequency", out_value: &freq);
270 if (!ret) {
271 switch (freq) {
272 case 25000000:
273 sel = AT803X_CLK_OUT_25MHZ_XTAL;
274 break;
275 case 50000000:
276 sel = AT803X_CLK_OUT_50MHZ_PLL;
277 break;
278 case 62500000:
279 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
280 break;
281 case 125000000:
282 sel = AT803X_CLK_OUT_125MHZ_PLL;
283 break;
284 default:
285 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
286 return -EINVAL;
287 }
288
289 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
290 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
291 }
292
293 ret = of_property_read_u32(np: node, propname: "qca,clk-out-strength", out_value: &strength);
294 if (!ret) {
295 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
296 switch (strength) {
297 case AR803X_STRENGTH_FULL:
298 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
299 break;
300 case AR803X_STRENGTH_HALF:
301 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
302 break;
303 case AR803X_STRENGTH_QUARTER:
304 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
305 break;
306 default:
307 phydev_err(phydev, "invalid qca,clk-out-strength\n");
308 return -EINVAL;
309 }
310 }
311
312 return 0;
313}
314
315static int at803x_probe(struct phy_device *phydev)
316{
317 struct device *dev = &phydev->mdio.dev;
318 struct at803x_priv *priv;
319 int ret;
320
321 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
322 if (!priv)
323 return -ENOMEM;
324
325 phydev->priv = priv;
326
327 ret = at803x_parse_dt(phydev);
328 if (ret)
329 return ret;
330
331 return 0;
332}
333
334static int at803x_get_features(struct phy_device *phydev)
335{
336 struct at803x_priv *priv = phydev->priv;
337 int err;
338
339 err = genphy_read_abilities(phydev);
340 if (err)
341 return err;
342
343 if (phydev->drv->phy_id != ATH8031_PHY_ID)
344 return 0;
345
346 /* AR8031/AR8033 have different status registers
347 * for copper and fiber operation. However, the
348 * extended status register is the same for both
349 * operation modes.
350 *
351 * As a result of that, ESTATUS_1000_XFULL is set
352 * to 1 even when operating in copper TP mode.
353 *
354 * Remove this mode from the supported link modes
355 * when not operating in 1000BaseX mode.
356 */
357 if (!priv->is_1000basex)
358 linkmode_clear_bit(nr: ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
359 addr: phydev->supported);
360
361 return 0;
362}
363
364static int at803x_smarteee_config(struct phy_device *phydev)
365{
366 struct at803x_priv *priv = phydev->priv;
367 u16 mask = 0, val = 0;
368 int ret;
369
370 if (priv->flags & AT803X_DISABLE_SMARTEEE)
371 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
372 AT803X_MMD3_SMARTEEE_CTL3,
373 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, set: 0);
374
375 if (priv->smarteee_lpi_tw_1g) {
376 mask |= 0xff00;
377 val |= priv->smarteee_lpi_tw_1g << 8;
378 }
379 if (priv->smarteee_lpi_tw_100m) {
380 mask |= 0x00ff;
381 val |= priv->smarteee_lpi_tw_100m;
382 }
383 if (!mask)
384 return 0;
385
386 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
387 mask, set: val);
388 if (ret)
389 return ret;
390
391 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
392 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
393 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
394}
395
396static int at803x_clk_out_config(struct phy_device *phydev)
397{
398 struct at803x_priv *priv = phydev->priv;
399
400 if (!priv->clk_25m_mask)
401 return 0;
402
403 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
404 mask: priv->clk_25m_mask, set: priv->clk_25m_reg);
405}
406
407static int at8031_pll_config(struct phy_device *phydev)
408{
409 struct at803x_priv *priv = phydev->priv;
410
411 /* The default after hardware reset is PLL OFF. After a soft reset, the
412 * values are retained.
413 */
414 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
415 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
416 clear: 0, AT803X_DEBUG_PLL_ON);
417 else
418 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
419 AT803X_DEBUG_PLL_ON, set: 0);
420}
421
422static int at803x_hibernation_mode_config(struct phy_device *phydev)
423{
424 struct at803x_priv *priv = phydev->priv;
425
426 /* The default after hardware reset is hibernation mode enabled. After
427 * software reset, the value is retained.
428 */
429 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
430 return 0;
431
432 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
433 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, set: 0);
434}
435
436static int at803x_config_init(struct phy_device *phydev)
437{
438 int ret;
439
440 /* The RX and TX delay default is:
441 * after HW reset: RX delay enabled and TX delay disabled
442 * after SW reset: RX delay enabled, while TX delay retains the
443 * value before reset.
444 */
445 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
446 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
447 ret = at803x_enable_rx_delay(phydev);
448 else
449 ret = at803x_disable_rx_delay(phydev);
450 if (ret < 0)
451 return ret;
452
453 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
454 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
455 ret = at803x_enable_tx_delay(phydev);
456 else
457 ret = at803x_disable_tx_delay(phydev);
458 if (ret < 0)
459 return ret;
460
461 ret = at803x_smarteee_config(phydev);
462 if (ret < 0)
463 return ret;
464
465 ret = at803x_clk_out_config(phydev);
466 if (ret < 0)
467 return ret;
468
469 ret = at803x_hibernation_mode_config(phydev);
470 if (ret < 0)
471 return ret;
472
473 /* Ar803x extended next page bit is enabled by default. Cisco
474 * multigig switches read this bit and attempt to negotiate 10Gbps
475 * rates even if the next page bit is disabled. This is incorrect
476 * behaviour but we still need to accommodate it. XNP is only needed
477 * for 10Gbps support, so disable XNP.
478 */
479 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, set: 0);
480}
481
482static void at803x_link_change_notify(struct phy_device *phydev)
483{
484 /*
485 * Conduct a hardware reset for AT8030 every time a link loss is
486 * signalled. This is necessary to circumvent a hardware bug that
487 * occurs when the cable is unplugged while TX packets are pending
488 * in the FIFO. In such cases, the FIFO enters an error mode it
489 * cannot recover from by software.
490 */
491 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
492 struct at803x_context context;
493
494 at803x_context_save(phydev, context: &context);
495
496 phy_device_reset(phydev, value: 1);
497 usleep_range(min: 1000, max: 2000);
498 phy_device_reset(phydev, value: 0);
499 usleep_range(min: 1000, max: 2000);
500
501 at803x_context_restore(phydev, context: &context);
502
503 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
504 }
505}
506
507static int at803x_config_aneg(struct phy_device *phydev)
508{
509 struct at803x_priv *priv = phydev->priv;
510 int ret;
511
512 ret = at803x_prepare_config_aneg(phydev);
513 if (ret)
514 return ret;
515
516 if (priv->is_1000basex)
517 return genphy_c37_config_aneg(phydev);
518
519 return genphy_config_aneg(phydev);
520}
521
522static int at803x_cable_test_result_trans(u16 status)
523{
524 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
525 case AT803X_CDT_STATUS_STAT_NORMAL:
526 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
527 case AT803X_CDT_STATUS_STAT_SHORT:
528 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
529 case AT803X_CDT_STATUS_STAT_OPEN:
530 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
531 case AT803X_CDT_STATUS_STAT_FAIL:
532 default:
533 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
534 }
535}
536
537static bool at803x_cdt_test_failed(u16 status)
538{
539 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
540 AT803X_CDT_STATUS_STAT_FAIL;
541}
542
543static bool at803x_cdt_fault_length_valid(u16 status)
544{
545 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
546 case AT803X_CDT_STATUS_STAT_OPEN:
547 case AT803X_CDT_STATUS_STAT_SHORT:
548 return true;
549 }
550 return false;
551}
552
553static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
554{
555 static const int ethtool_pair[] = {
556 ETHTOOL_A_CABLE_PAIR_A,
557 ETHTOOL_A_CABLE_PAIR_B,
558 ETHTOOL_A_CABLE_PAIR_C,
559 ETHTOOL_A_CABLE_PAIR_D,
560 };
561 int ret, val;
562
563 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
564 AT803X_CDT_ENABLE_TEST;
565 ret = at803x_cdt_start(phydev, cdt_start: val);
566 if (ret)
567 return ret;
568
569 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
570 if (ret)
571 return ret;
572
573 val = phy_read(phydev, AT803X_CDT_STATUS);
574 if (val < 0)
575 return val;
576
577 if (at803x_cdt_test_failed(status: val))
578 return 0;
579
580 ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
581 result: at803x_cable_test_result_trans(status: val));
582
583 if (at803x_cdt_fault_length_valid(status: val)) {
584 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
585 ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair],
586 cm: at803x_cdt_fault_length(dt: val));
587 }
588
589 return 1;
590}
591
592static int at803x_cable_test_get_status(struct phy_device *phydev,
593 bool *finished, unsigned long pair_mask)
594{
595 int retries = 20;
596 int pair, ret;
597
598 *finished = false;
599
600 /* According to the datasheet the CDT can be performed when
601 * there is no link partner or when the link partner is
602 * auto-negotiating. Starting the test will restart the AN
603 * automatically. It seems that doing this repeatedly we will
604 * get a slot where our link partner won't disturb our
605 * measurement.
606 */
607 while (pair_mask && retries--) {
608 for_each_set_bit(pair, &pair_mask, 4) {
609 ret = at803x_cable_test_one_pair(phydev, pair);
610 if (ret < 0)
611 return ret;
612 if (ret)
613 clear_bit(nr: pair, addr: &pair_mask);
614 }
615 if (pair_mask)
616 msleep(msecs: 250);
617 }
618
619 *finished = true;
620
621 return 0;
622}
623
624static void at803x_cable_test_autoneg(struct phy_device *phydev)
625{
626 /* Enable auto-negotiation, but advertise no capabilities, no link
627 * will be established. A restart of the auto-negotiation is not
628 * required, because the cable test will automatically break the link.
629 */
630 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
631 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
632}
633
634static int at803x_cable_test_start(struct phy_device *phydev)
635{
636 at803x_cable_test_autoneg(phydev);
637 /* we do all the (time consuming) work later */
638 return 0;
639}
640
641static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
642 unsigned int selector)
643{
644 struct phy_device *phydev = rdev_get_drvdata(rdev);
645
646 if (selector)
647 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
648 clear: 0, AT803X_DEBUG_RGMII_1V8);
649 else
650 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
651 AT803X_DEBUG_RGMII_1V8, set: 0);
652}
653
654static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
655{
656 struct phy_device *phydev = rdev_get_drvdata(rdev);
657 int val;
658
659 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
660 if (val < 0)
661 return val;
662
663 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
664}
665
666static const struct regulator_ops vddio_regulator_ops = {
667 .list_voltage = regulator_list_voltage_table,
668 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
669 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
670};
671
672static const unsigned int vddio_voltage_table[] = {
673 1500000,
674 1800000,
675};
676
677static const struct regulator_desc vddio_desc = {
678 .name = "vddio",
679 .of_match = of_match_ptr("vddio-regulator"),
680 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
681 .volt_table = vddio_voltage_table,
682 .ops = &vddio_regulator_ops,
683 .type = REGULATOR_VOLTAGE,
684 .owner = THIS_MODULE,
685};
686
687static const struct regulator_ops vddh_regulator_ops = {
688};
689
690static const struct regulator_desc vddh_desc = {
691 .name = "vddh",
692 .of_match = of_match_ptr("vddh-regulator"),
693 .n_voltages = 1,
694 .fixed_uV = 2500000,
695 .ops = &vddh_regulator_ops,
696 .type = REGULATOR_VOLTAGE,
697 .owner = THIS_MODULE,
698};
699
700static int at8031_register_regulators(struct phy_device *phydev)
701{
702 struct at803x_priv *priv = phydev->priv;
703 struct device *dev = &phydev->mdio.dev;
704 struct regulator_config config = { };
705
706 config.dev = dev;
707 config.driver_data = phydev;
708
709 priv->vddio_rdev = devm_regulator_register(dev, regulator_desc: &vddio_desc, config: &config);
710 if (IS_ERR(ptr: priv->vddio_rdev)) {
711 phydev_err(phydev, "failed to register VDDIO regulator\n");
712 return PTR_ERR(ptr: priv->vddio_rdev);
713 }
714
715 priv->vddh_rdev = devm_regulator_register(dev, regulator_desc: &vddh_desc, config: &config);
716 if (IS_ERR(ptr: priv->vddh_rdev)) {
717 phydev_err(phydev, "failed to register VDDH regulator\n");
718 return PTR_ERR(ptr: priv->vddh_rdev);
719 }
720
721 return 0;
722}
723
724static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
725{
726 struct phy_device *phydev = upstream;
727 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
728 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
729 DECLARE_PHY_INTERFACE_MASK(interfaces);
730 phy_interface_t iface;
731
732 linkmode_zero(dst: phy_support);
733 phylink_set(phy_support, 1000baseX_Full);
734 phylink_set(phy_support, 1000baseT_Full);
735 phylink_set(phy_support, Autoneg);
736 phylink_set(phy_support, Pause);
737 phylink_set(phy_support, Asym_Pause);
738
739 linkmode_zero(dst: sfp_support);
740 sfp_parse_support(bus: phydev->sfp_bus, id, support: sfp_support, interfaces);
741 /* Some modules support 10G modes as well as others we support.
742 * Mask out non-supported modes so the correct interface is picked.
743 */
744 linkmode_and(dst: sfp_support, a: phy_support, b: sfp_support);
745
746 if (linkmode_empty(src: sfp_support)) {
747 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
748 return -EINVAL;
749 }
750
751 iface = sfp_select_interface(bus: phydev->sfp_bus, link_modes: sfp_support);
752
753 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
754 * interface for use with SFP modules.
755 * However, some copper modules detected as having a preferred SGMII
756 * interface do default to and function in 1000Base-X mode, so just
757 * print a warning and allow such modules, as they may have some chance
758 * of working.
759 */
760 if (iface == PHY_INTERFACE_MODE_SGMII)
761 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
762 else if (iface != PHY_INTERFACE_MODE_1000BASEX)
763 return -EINVAL;
764
765 return 0;
766}
767
768static const struct sfp_upstream_ops at8031_sfp_ops = {
769 .attach = phy_sfp_attach,
770 .detach = phy_sfp_detach,
771 .module_insert = at8031_sfp_insert,
772};
773
774static int at8031_parse_dt(struct phy_device *phydev)
775{
776 struct device_node *node = phydev->mdio.dev.of_node;
777 struct at803x_priv *priv = phydev->priv;
778 int ret;
779
780 if (of_property_read_bool(np: node, propname: "qca,keep-pll-enabled"))
781 priv->flags |= AT803X_KEEP_PLL_ENABLED;
782
783 ret = at8031_register_regulators(phydev);
784 if (ret < 0)
785 return ret;
786
787 ret = devm_regulator_get_enable_optional(dev: &phydev->mdio.dev,
788 id: "vddio");
789 if (ret) {
790 phydev_err(phydev, "failed to get VDDIO regulator\n");
791 return ret;
792 }
793
794 /* Only AR8031/8033 support 1000Base-X for SFP modules */
795 return phy_sfp_probe(phydev, ops: &at8031_sfp_ops);
796}
797
798static int at8031_probe(struct phy_device *phydev)
799{
800 struct at803x_priv *priv;
801 int mode_cfg;
802 int ccr;
803 int ret;
804
805 ret = at803x_probe(phydev);
806 if (ret)
807 return ret;
808
809 priv = phydev->priv;
810
811 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
812 * options.
813 */
814 ret = at8031_parse_dt(phydev);
815 if (ret)
816 return ret;
817
818 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
819 if (ccr < 0)
820 return ccr;
821 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
822
823 switch (mode_cfg) {
824 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
825 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
826 priv->is_1000basex = true;
827 fallthrough;
828 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
829 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
830 priv->is_fiber = true;
831 break;
832 }
833
834 /* Disable WoL in 1588 register which is enabled
835 * by default
836 */
837 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
838 AT803X_PHY_MMD3_WOL_CTRL,
839 AT803X_WOL_EN, set: 0);
840}
841
842static int at8031_config_init(struct phy_device *phydev)
843{
844 struct at803x_priv *priv = phydev->priv;
845 int ret;
846
847 /* Some bootloaders leave the fiber page selected.
848 * Switch to the appropriate page (fiber or copper), as otherwise we
849 * read the PHY capabilities from the wrong page.
850 */
851 phy_lock_mdio_bus(phydev);
852 ret = at803x_write_page(phydev,
853 page: priv->is_fiber ? AT803X_PAGE_FIBER :
854 AT803X_PAGE_COPPER);
855 phy_unlock_mdio_bus(phydev);
856 if (ret)
857 return ret;
858
859 ret = at8031_pll_config(phydev);
860 if (ret < 0)
861 return ret;
862
863 return at803x_config_init(phydev);
864}
865
866static int at8031_set_wol(struct phy_device *phydev,
867 struct ethtool_wolinfo *wol)
868{
869 int ret;
870
871 /* First setup MAC address and enable WOL interrupt */
872 ret = at803x_set_wol(phydev, wol);
873 if (ret)
874 return ret;
875
876 if (wol->wolopts & WAKE_MAGIC)
877 /* Enable WOL function for 1588 */
878 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
879 AT803X_PHY_MMD3_WOL_CTRL,
880 mask: 0, AT803X_WOL_EN);
881 else
882 /* Disable WoL function for 1588 */
883 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
884 AT803X_PHY_MMD3_WOL_CTRL,
885 AT803X_WOL_EN, set: 0);
886
887 return ret;
888}
889
890static int at8031_config_intr(struct phy_device *phydev)
891{
892 struct at803x_priv *priv = phydev->priv;
893 int err, value = 0;
894
895 if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
896 priv->is_fiber) {
897 /* Clear any pending interrupts */
898 err = at803x_ack_interrupt(phydev);
899 if (err)
900 return err;
901
902 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
903 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
904
905 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, val: value);
906 if (err)
907 return err;
908 }
909
910 return at803x_config_intr(phydev);
911}
912
913/* AR8031 and AR8033 share the same read status logic */
914static int at8031_read_status(struct phy_device *phydev)
915{
916 struct at803x_priv *priv = phydev->priv;
917 bool changed;
918
919 if (priv->is_1000basex)
920 return genphy_c37_read_status(phydev, changed: &changed);
921
922 return at803x_read_status(phydev);
923}
924
925/* AR8031 and AR8035 share the same cable test get status reg */
926static int at8031_cable_test_get_status(struct phy_device *phydev,
927 bool *finished)
928{
929 return at803x_cable_test_get_status(phydev, finished, pair_mask: 0xf);
930}
931
932/* AR8031 and AR8035 share the same cable test start logic */
933static int at8031_cable_test_start(struct phy_device *phydev)
934{
935 at803x_cable_test_autoneg(phydev);
936 phy_write(phydev, MII_CTRL1000, val: 0);
937 /* we do all the (time consuming) work later */
938 return 0;
939}
940
941/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
942static int at8032_cable_test_get_status(struct phy_device *phydev,
943 bool *finished)
944{
945 return at803x_cable_test_get_status(phydev, finished, pair_mask: 0x3);
946}
947
948static int at8035_parse_dt(struct phy_device *phydev)
949{
950 struct at803x_priv *priv = phydev->priv;
951
952 /* Mask is set by the generic at803x_parse_dt
953 * if property is set. Assume property is set
954 * with the mask not zero.
955 */
956 if (priv->clk_25m_mask) {
957 /* Fixup for the AR8030/AR8035. This chip has another mask and
958 * doesn't support the DSP reference. Eg. the lowest bit of the
959 * mask. The upper two bits select the same frequencies. Mask
960 * the lowest bit here.
961 *
962 * Warning:
963 * There was no datasheet for the AR8030 available so this is
964 * just a guess. But the AR8035 is listed as pin compatible
965 * to the AR8030 so there might be a good chance it works on
966 * the AR8030 too.
967 */
968 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
969 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
970 }
971
972 return 0;
973}
974
975/* AR8030 and AR8035 shared the same special mask for clk_25m */
976static int at8035_probe(struct phy_device *phydev)
977{
978 int ret;
979
980 ret = at803x_probe(phydev);
981 if (ret)
982 return ret;
983
984 return at8035_parse_dt(phydev);
985}
986
987static struct phy_driver at803x_driver[] = {
988{
989 /* Qualcomm Atheros AR8035 */
990 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
991 .name = "Qualcomm Atheros AR8035",
992 .flags = PHY_POLL_CABLE_TEST,
993 .probe = at8035_probe,
994 .config_aneg = at803x_config_aneg,
995 .config_init = at803x_config_init,
996 .soft_reset = genphy_soft_reset,
997 .set_wol = at803x_set_wol,
998 .get_wol = at803x_get_wol,
999 .suspend = at803x_suspend,
1000 .resume = at803x_resume,
1001 /* PHY_GBIT_FEATURES */
1002 .read_status = at803x_read_status,
1003 .config_intr = at803x_config_intr,
1004 .handle_interrupt = at803x_handle_interrupt,
1005 .get_tunable = at803x_get_tunable,
1006 .set_tunable = at803x_set_tunable,
1007 .cable_test_start = at8031_cable_test_start,
1008 .cable_test_get_status = at8031_cable_test_get_status,
1009}, {
1010 /* Qualcomm Atheros AR8030 */
1011 .phy_id = ATH8030_PHY_ID,
1012 .name = "Qualcomm Atheros AR8030",
1013 .phy_id_mask = AT8030_PHY_ID_MASK,
1014 .probe = at8035_probe,
1015 .config_init = at803x_config_init,
1016 .link_change_notify = at803x_link_change_notify,
1017 .set_wol = at803x_set_wol,
1018 .get_wol = at803x_get_wol,
1019 .suspend = at803x_suspend,
1020 .resume = at803x_resume,
1021 /* PHY_BASIC_FEATURES */
1022 .config_intr = at803x_config_intr,
1023 .handle_interrupt = at803x_handle_interrupt,
1024}, {
1025 /* Qualcomm Atheros AR8031/AR8033 */
1026 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1027 .name = "Qualcomm Atheros AR8031/AR8033",
1028 .flags = PHY_POLL_CABLE_TEST,
1029 .probe = at8031_probe,
1030 .config_init = at8031_config_init,
1031 .config_aneg = at803x_config_aneg,
1032 .soft_reset = genphy_soft_reset,
1033 .set_wol = at8031_set_wol,
1034 .get_wol = at803x_get_wol,
1035 .suspend = at803x_suspend,
1036 .resume = at803x_resume,
1037 .read_page = at803x_read_page,
1038 .write_page = at803x_write_page,
1039 .get_features = at803x_get_features,
1040 .read_status = at8031_read_status,
1041 .config_intr = at8031_config_intr,
1042 .handle_interrupt = at803x_handle_interrupt,
1043 .get_tunable = at803x_get_tunable,
1044 .set_tunable = at803x_set_tunable,
1045 .cable_test_start = at8031_cable_test_start,
1046 .cable_test_get_status = at8031_cable_test_get_status,
1047}, {
1048 /* Qualcomm Atheros AR8032 */
1049 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1050 .name = "Qualcomm Atheros AR8032",
1051 .probe = at803x_probe,
1052 .flags = PHY_POLL_CABLE_TEST,
1053 .config_init = at803x_config_init,
1054 .link_change_notify = at803x_link_change_notify,
1055 .suspend = at803x_suspend,
1056 .resume = at803x_resume,
1057 /* PHY_BASIC_FEATURES */
1058 .config_intr = at803x_config_intr,
1059 .handle_interrupt = at803x_handle_interrupt,
1060 .cable_test_start = at803x_cable_test_start,
1061 .cable_test_get_status = at8032_cable_test_get_status,
1062}, {
1063 /* ATHEROS AR9331 */
1064 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1065 .name = "Qualcomm Atheros AR9331 built-in PHY",
1066 .probe = at803x_probe,
1067 .suspend = at803x_suspend,
1068 .resume = at803x_resume,
1069 .flags = PHY_POLL_CABLE_TEST,
1070 /* PHY_BASIC_FEATURES */
1071 .config_intr = at803x_config_intr,
1072 .handle_interrupt = at803x_handle_interrupt,
1073 .cable_test_start = at803x_cable_test_start,
1074 .cable_test_get_status = at8032_cable_test_get_status,
1075 .read_status = at803x_read_status,
1076 .soft_reset = genphy_soft_reset,
1077 .config_aneg = at803x_config_aneg,
1078}, {
1079 /* Qualcomm Atheros QCA9561 */
1080 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
1081 .name = "Qualcomm Atheros QCA9561 built-in PHY",
1082 .probe = at803x_probe,
1083 .suspend = at803x_suspend,
1084 .resume = at803x_resume,
1085 .flags = PHY_POLL_CABLE_TEST,
1086 /* PHY_BASIC_FEATURES */
1087 .config_intr = at803x_config_intr,
1088 .handle_interrupt = at803x_handle_interrupt,
1089 .cable_test_start = at803x_cable_test_start,
1090 .cable_test_get_status = at8032_cable_test_get_status,
1091 .read_status = at803x_read_status,
1092 .soft_reset = genphy_soft_reset,
1093 .config_aneg = at803x_config_aneg,
1094}, };
1095
1096module_phy_driver(at803x_driver);
1097
1098static struct mdio_device_id __maybe_unused atheros_tbl[] = {
1099 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1100 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1101 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1102 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1103 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1104 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
1105 { }
1106};
1107
1108MODULE_DEVICE_TABLE(mdio, atheros_tbl);
1109

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source code of linux/drivers/net/phy/qcom/at803x.c