1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10#include <linux/phy.h>
11#include <linux/module.h>
12#include <linux/string.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/ethtool_netlink.h>
16#include <linux/bitfield.h>
17#include <linux/regulator/of_regulator.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of.h>
21#include <linux/phylink.h>
22#include <linux/sfp.h>
23#include <dt-bindings/net/qca-ar803x.h>
24
25#include "qcom.h"
26
27#define AT803X_LED_CONTROL 0x18
28
29#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
30#define AT803X_WOL_EN BIT(5)
31
32#define AT803X_REG_CHIP_CONFIG 0x1f
33#define AT803X_BT_BX_REG_SEL 0x8000
34
35#define AT803X_MODE_CFG_MASK 0x0F
36#define AT803X_MODE_CFG_BASET_RGMII 0x00
37#define AT803X_MODE_CFG_BASET_SGMII 0x01
38#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
39#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
40#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
41#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
42#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
43#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
44#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
45#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
46#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
47
48#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
49#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
50
51#define AT803X_DEBUG_REG_1F 0x1F
52#define AT803X_DEBUG_PLL_ON BIT(2)
53#define AT803X_DEBUG_RGMII_1V8 BIT(3)
54
55/* AT803x supports either the XTAL input pad, an internal PLL or the
56 * DSP as clock reference for the clock output pad. The XTAL reference
57 * is only used for 25 MHz output, all other frequencies need the PLL.
58 * The DSP as a clock reference is used in synchronous ethernet
59 * applications.
60 *
61 * By default the PLL is only enabled if there is a link. Otherwise
62 * the PHY will go into low power state and disabled the PLL. You can
63 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
64 * enabled.
65 */
66#define AT803X_MMD7_CLK25M 0x8016
67#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
68#define AT803X_CLK_OUT_25MHZ_XTAL 0
69#define AT803X_CLK_OUT_25MHZ_DSP 1
70#define AT803X_CLK_OUT_50MHZ_PLL 2
71#define AT803X_CLK_OUT_50MHZ_DSP 3
72#define AT803X_CLK_OUT_62_5MHZ_PLL 4
73#define AT803X_CLK_OUT_62_5MHZ_DSP 5
74#define AT803X_CLK_OUT_125MHZ_PLL 6
75#define AT803X_CLK_OUT_125MHZ_DSP 7
76
77/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
78 * but doesn't support choosing between XTAL/PLL and DSP.
79 */
80#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
81
82#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
83#define AT803X_CLK_OUT_STRENGTH_FULL 0
84#define AT803X_CLK_OUT_STRENGTH_HALF 1
85#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
86
87#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
88#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
89#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
90#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
91
92#define ATH9331_PHY_ID 0x004dd041
93#define ATH8030_PHY_ID 0x004dd076
94#define ATH8031_PHY_ID 0x004dd074
95#define ATH8032_PHY_ID 0x004dd023
96#define ATH8035_PHY_ID 0x004dd072
97#define AT8030_PHY_ID_MASK 0xffffffef
98
99#define QCA9561_PHY_ID 0x004dd042
100
101#define AT803X_PAGE_FIBER 0
102#define AT803X_PAGE_COPPER 1
103
104/* don't turn off internal PLL */
105#define AT803X_KEEP_PLL_ENABLED BIT(0)
106#define AT803X_DISABLE_SMARTEEE BIT(1)
107
108/* disable hibernation mode */
109#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
110
111MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
112MODULE_AUTHOR("Matus Ujhelyi");
113MODULE_LICENSE("GPL");
114
115struct at803x_priv {
116 int flags;
117 u16 clk_25m_reg;
118 u16 clk_25m_mask;
119 u8 smarteee_lpi_tw_1g;
120 u8 smarteee_lpi_tw_100m;
121 bool is_fiber;
122 bool is_1000basex;
123 struct regulator_dev *vddio_rdev;
124 struct regulator_dev *vddh_rdev;
125};
126
127struct at803x_context {
128 u16 bmcr;
129 u16 advertise;
130 u16 control1000;
131 u16 int_enable;
132 u16 smart_speed;
133 u16 led_control;
134};
135
136static int at803x_write_page(struct phy_device *phydev, int page)
137{
138 int mask;
139 int set;
140
141 if (page == AT803X_PAGE_COPPER) {
142 set = AT803X_BT_BX_REG_SEL;
143 mask = 0;
144 } else {
145 set = 0;
146 mask = AT803X_BT_BX_REG_SEL;
147 }
148
149 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
150}
151
152static int at803x_read_page(struct phy_device *phydev)
153{
154 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
155
156 if (ccr < 0)
157 return ccr;
158
159 if (ccr & AT803X_BT_BX_REG_SEL)
160 return AT803X_PAGE_COPPER;
161
162 return AT803X_PAGE_FIBER;
163}
164
165static int at803x_enable_rx_delay(struct phy_device *phydev)
166{
167 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, clear: 0,
168 AT803X_DEBUG_RX_CLK_DLY_EN);
169}
170
171static int at803x_enable_tx_delay(struct phy_device *phydev)
172{
173 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, clear: 0,
174 AT803X_DEBUG_TX_CLK_DLY_EN);
175}
176
177static int at803x_disable_rx_delay(struct phy_device *phydev)
178{
179 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
180 AT803X_DEBUG_RX_CLK_DLY_EN, set: 0);
181}
182
183static int at803x_disable_tx_delay(struct phy_device *phydev)
184{
185 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
186 AT803X_DEBUG_TX_CLK_DLY_EN, set: 0);
187}
188
189/* save relevant PHY registers to private copy */
190static void at803x_context_save(struct phy_device *phydev,
191 struct at803x_context *context)
192{
193 context->bmcr = phy_read(phydev, MII_BMCR);
194 context->advertise = phy_read(phydev, MII_ADVERTISE);
195 context->control1000 = phy_read(phydev, MII_CTRL1000);
196 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
197 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
198 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
199}
200
201/* restore relevant PHY registers from private copy */
202static void at803x_context_restore(struct phy_device *phydev,
203 const struct at803x_context *context)
204{
205 phy_write(phydev, MII_BMCR, val: context->bmcr);
206 phy_write(phydev, MII_ADVERTISE, val: context->advertise);
207 phy_write(phydev, MII_CTRL1000, val: context->control1000);
208 phy_write(phydev, AT803X_INTR_ENABLE, val: context->int_enable);
209 phy_write(phydev, AT803X_SMART_SPEED, val: context->smart_speed);
210 phy_write(phydev, AT803X_LED_CONTROL, val: context->led_control);
211}
212
213static int at803x_suspend(struct phy_device *phydev)
214{
215 int value;
216 int wol_enabled;
217
218 value = phy_read(phydev, AT803X_INTR_ENABLE);
219 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
220
221 if (wol_enabled)
222 value = BMCR_ISOLATE;
223 else
224 value = BMCR_PDOWN;
225
226 phy_modify(phydev, MII_BMCR, mask: 0, set: value);
227
228 return 0;
229}
230
231static int at803x_resume(struct phy_device *phydev)
232{
233 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, set: 0);
234}
235
236static int at803x_parse_dt(struct phy_device *phydev)
237{
238 struct device_node *node = phydev->mdio.dev.of_node;
239 struct at803x_priv *priv = phydev->priv;
240 u32 freq, strength, tw;
241 unsigned int sel;
242 int ret;
243
244 if (!IS_ENABLED(CONFIG_OF_MDIO))
245 return 0;
246
247 if (of_property_read_bool(np: node, propname: "qca,disable-smarteee"))
248 priv->flags |= AT803X_DISABLE_SMARTEEE;
249
250 if (of_property_read_bool(np: node, propname: "qca,disable-hibernation-mode"))
251 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
252
253 if (!of_property_read_u32(np: node, propname: "qca,smarteee-tw-us-1g", out_value: &tw)) {
254 if (!tw || tw > 255) {
255 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
256 return -EINVAL;
257 }
258 priv->smarteee_lpi_tw_1g = tw;
259 }
260
261 if (!of_property_read_u32(np: node, propname: "qca,smarteee-tw-us-100m", out_value: &tw)) {
262 if (!tw || tw > 255) {
263 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
264 return -EINVAL;
265 }
266 priv->smarteee_lpi_tw_100m = tw;
267 }
268
269 ret = of_property_read_u32(np: node, propname: "qca,clk-out-frequency", out_value: &freq);
270 if (!ret) {
271 switch (freq) {
272 case 25000000:
273 sel = AT803X_CLK_OUT_25MHZ_XTAL;
274 break;
275 case 50000000:
276 sel = AT803X_CLK_OUT_50MHZ_PLL;
277 break;
278 case 62500000:
279 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
280 break;
281 case 125000000:
282 sel = AT803X_CLK_OUT_125MHZ_PLL;
283 break;
284 default:
285 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
286 return -EINVAL;
287 }
288
289 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
290 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
291 }
292
293 ret = of_property_read_u32(np: node, propname: "qca,clk-out-strength", out_value: &strength);
294 if (!ret) {
295 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
296 switch (strength) {
297 case AR803X_STRENGTH_FULL:
298 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
299 break;
300 case AR803X_STRENGTH_HALF:
301 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
302 break;
303 case AR803X_STRENGTH_QUARTER:
304 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
305 break;
306 default:
307 phydev_err(phydev, "invalid qca,clk-out-strength\n");
308 return -EINVAL;
309 }
310 }
311
312 return 0;
313}
314
315static int at803x_probe(struct phy_device *phydev)
316{
317 struct device *dev = &phydev->mdio.dev;
318 struct at803x_priv *priv;
319 int ret;
320
321 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
322 if (!priv)
323 return -ENOMEM;
324
325 phydev->priv = priv;
326
327 ret = at803x_parse_dt(phydev);
328 if (ret)
329 return ret;
330
331 return 0;
332}
333
334static int at803x_get_features(struct phy_device *phydev)
335{
336 struct at803x_priv *priv = phydev->priv;
337 int err;
338
339 err = genphy_read_abilities(phydev);
340 if (err)
341 return err;
342
343 if (phydev->drv->phy_id != ATH8031_PHY_ID)
344 return 0;
345
346 /* AR8031/AR8033 have different status registers
347 * for copper and fiber operation. However, the
348 * extended status register is the same for both
349 * operation modes.
350 *
351 * As a result of that, ESTATUS_1000_XFULL is set
352 * to 1 even when operating in copper TP mode.
353 *
354 * Remove this mode from the supported link modes
355 * when not operating in 1000BaseX mode.
356 */
357 if (!priv->is_1000basex)
358 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
359 phydev->supported);
360
361 return 0;
362}
363
364static int at803x_smarteee_config(struct phy_device *phydev)
365{
366 struct at803x_priv *priv = phydev->priv;
367 u16 mask = 0, val = 0;
368 int ret;
369
370 if (priv->flags & AT803X_DISABLE_SMARTEEE)
371 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
372 AT803X_MMD3_SMARTEEE_CTL3,
373 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, set: 0);
374
375 if (priv->smarteee_lpi_tw_1g) {
376 mask |= 0xff00;
377 val |= priv->smarteee_lpi_tw_1g << 8;
378 }
379 if (priv->smarteee_lpi_tw_100m) {
380 mask |= 0x00ff;
381 val |= priv->smarteee_lpi_tw_100m;
382 }
383 if (!mask)
384 return 0;
385
386 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
387 mask, set: val);
388 if (ret)
389 return ret;
390
391 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
392 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
393 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
394}
395
396static int at803x_clk_out_config(struct phy_device *phydev)
397{
398 struct at803x_priv *priv = phydev->priv;
399
400 if (!priv->clk_25m_mask)
401 return 0;
402
403 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
404 mask: priv->clk_25m_mask, set: priv->clk_25m_reg);
405}
406
407static int at8031_pll_config(struct phy_device *phydev)
408{
409 struct at803x_priv *priv = phydev->priv;
410
411 /* The default after hardware reset is PLL OFF. After a soft reset, the
412 * values are retained.
413 */
414 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
415 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
416 clear: 0, AT803X_DEBUG_PLL_ON);
417 else
418 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
419 AT803X_DEBUG_PLL_ON, set: 0);
420}
421
422static int at803x_hibernation_mode_config(struct phy_device *phydev)
423{
424 struct at803x_priv *priv = phydev->priv;
425
426 /* The default after hardware reset is hibernation mode enabled. After
427 * software reset, the value is retained.
428 */
429 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) &&
430 !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON))
431 return 0;
432
433 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
434 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, set: 0);
435}
436
437static int at803x_config_init(struct phy_device *phydev)
438{
439 int ret;
440
441 /* The RX and TX delay default is:
442 * after HW reset: RX delay enabled and TX delay disabled
443 * after SW reset: RX delay enabled, while TX delay retains the
444 * value before reset.
445 */
446 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
447 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
448 ret = at803x_enable_rx_delay(phydev);
449 else
450 ret = at803x_disable_rx_delay(phydev);
451 if (ret < 0)
452 return ret;
453
454 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
455 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
456 ret = at803x_enable_tx_delay(phydev);
457 else
458 ret = at803x_disable_tx_delay(phydev);
459 if (ret < 0)
460 return ret;
461
462 ret = at803x_smarteee_config(phydev);
463 if (ret < 0)
464 return ret;
465
466 ret = at803x_clk_out_config(phydev);
467 if (ret < 0)
468 return ret;
469
470 ret = at803x_hibernation_mode_config(phydev);
471 if (ret < 0)
472 return ret;
473
474 /* Ar803x extended next page bit is enabled by default. Cisco
475 * multigig switches read this bit and attempt to negotiate 10Gbps
476 * rates even if the next page bit is disabled. This is incorrect
477 * behaviour but we still need to accommodate it. XNP is only needed
478 * for 10Gbps support, so disable XNP.
479 */
480 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, set: 0);
481}
482
483static void at803x_link_change_notify(struct phy_device *phydev)
484{
485 /*
486 * Conduct a hardware reset for AT8030 every time a link loss is
487 * signalled. This is necessary to circumvent a hardware bug that
488 * occurs when the cable is unplugged while TX packets are pending
489 * in the FIFO. In such cases, the FIFO enters an error mode it
490 * cannot recover from by software.
491 */
492 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
493 struct at803x_context context;
494
495 at803x_context_save(phydev, context: &context);
496
497 phy_device_reset(phydev, value: 1);
498 usleep_range(min: 1000, max: 2000);
499 phy_device_reset(phydev, value: 0);
500 usleep_range(min: 1000, max: 2000);
501
502 at803x_context_restore(phydev, context: &context);
503
504 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
505 }
506}
507
508static int at803x_config_aneg(struct phy_device *phydev)
509{
510 struct at803x_priv *priv = phydev->priv;
511 int ret;
512
513 ret = at803x_prepare_config_aneg(phydev);
514 if (ret)
515 return ret;
516
517 if (priv->is_1000basex)
518 return genphy_c37_config_aneg(phydev);
519
520 return genphy_config_aneg(phydev);
521}
522
523static int at803x_cable_test_result_trans(u16 status)
524{
525 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
526 case AT803X_CDT_STATUS_STAT_NORMAL:
527 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
528 case AT803X_CDT_STATUS_STAT_SHORT:
529 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
530 case AT803X_CDT_STATUS_STAT_OPEN:
531 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
532 case AT803X_CDT_STATUS_STAT_FAIL:
533 default:
534 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
535 }
536}
537
538static bool at803x_cdt_test_failed(u16 status)
539{
540 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
541 AT803X_CDT_STATUS_STAT_FAIL;
542}
543
544static bool at803x_cdt_fault_length_valid(u16 status)
545{
546 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
547 case AT803X_CDT_STATUS_STAT_OPEN:
548 case AT803X_CDT_STATUS_STAT_SHORT:
549 return true;
550 }
551 return false;
552}
553
554static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
555{
556 static const int ethtool_pair[] = {
557 ETHTOOL_A_CABLE_PAIR_A,
558 ETHTOOL_A_CABLE_PAIR_B,
559 ETHTOOL_A_CABLE_PAIR_C,
560 ETHTOOL_A_CABLE_PAIR_D,
561 };
562 int ret, val;
563
564 val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
565 AT803X_CDT_ENABLE_TEST;
566 ret = at803x_cdt_start(phydev, cdt_start: val);
567 if (ret)
568 return ret;
569
570 ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
571 if (ret)
572 return ret;
573
574 val = phy_read(phydev, AT803X_CDT_STATUS);
575 if (val < 0)
576 return val;
577
578 if (at803x_cdt_test_failed(status: val))
579 return 0;
580
581 ethnl_cable_test_result(phydev, pair: ethtool_pair[pair],
582 result: at803x_cable_test_result_trans(status: val));
583
584 if (at803x_cdt_fault_length_valid(status: val)) {
585 val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
586 ethnl_cable_test_fault_length(phydev, pair: ethtool_pair[pair],
587 cm: at803x_cdt_fault_length(dt: val));
588 }
589
590 return 1;
591}
592
593static int at803x_cable_test_get_status(struct phy_device *phydev,
594 bool *finished, unsigned long pair_mask)
595{
596 int retries = 20;
597 int pair, ret;
598
599 *finished = false;
600
601 /* According to the datasheet the CDT can be performed when
602 * there is no link partner or when the link partner is
603 * auto-negotiating. Starting the test will restart the AN
604 * automatically. It seems that doing this repeatedly we will
605 * get a slot where our link partner won't disturb our
606 * measurement.
607 */
608 while (pair_mask && retries--) {
609 for_each_set_bit(pair, &pair_mask, 4) {
610 ret = at803x_cable_test_one_pair(phydev, pair);
611 if (ret < 0)
612 return ret;
613 if (ret)
614 clear_bit(nr: pair, addr: &pair_mask);
615 }
616 if (pair_mask)
617 msleep(msecs: 250);
618 }
619
620 *finished = true;
621
622 return 0;
623}
624
625static void at803x_cable_test_autoneg(struct phy_device *phydev)
626{
627 /* Enable auto-negotiation, but advertise no capabilities, no link
628 * will be established. A restart of the auto-negotiation is not
629 * required, because the cable test will automatically break the link.
630 */
631 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
632 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
633}
634
635static int at803x_cable_test_start(struct phy_device *phydev)
636{
637 at803x_cable_test_autoneg(phydev);
638 /* we do all the (time consuming) work later */
639 return 0;
640}
641
642static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
643 unsigned int selector)
644{
645 struct phy_device *phydev = rdev_get_drvdata(rdev);
646
647 if (selector)
648 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
649 clear: 0, AT803X_DEBUG_RGMII_1V8);
650 else
651 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
652 AT803X_DEBUG_RGMII_1V8, set: 0);
653}
654
655static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
656{
657 struct phy_device *phydev = rdev_get_drvdata(rdev);
658 int val;
659
660 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
661 if (val < 0)
662 return val;
663
664 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
665}
666
667static const struct regulator_ops vddio_regulator_ops = {
668 .list_voltage = regulator_list_voltage_table,
669 .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
670 .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
671};
672
673static const unsigned int vddio_voltage_table[] = {
674 1500000,
675 1800000,
676};
677
678static const struct regulator_desc vddio_desc = {
679 .name = "vddio",
680 .of_match = of_match_ptr("vddio-regulator"),
681 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
682 .volt_table = vddio_voltage_table,
683 .ops = &vddio_regulator_ops,
684 .type = REGULATOR_VOLTAGE,
685 .owner = THIS_MODULE,
686};
687
688static const struct regulator_ops vddh_regulator_ops = {
689};
690
691static const struct regulator_desc vddh_desc = {
692 .name = "vddh",
693 .of_match = of_match_ptr("vddh-regulator"),
694 .n_voltages = 1,
695 .fixed_uV = 2500000,
696 .ops = &vddh_regulator_ops,
697 .type = REGULATOR_VOLTAGE,
698 .owner = THIS_MODULE,
699};
700
701static int at8031_register_regulators(struct phy_device *phydev)
702{
703 struct at803x_priv *priv = phydev->priv;
704 struct device *dev = &phydev->mdio.dev;
705 struct regulator_config config = { };
706
707 config.dev = dev;
708 config.driver_data = phydev;
709
710 priv->vddio_rdev = devm_regulator_register(dev, regulator_desc: &vddio_desc, config: &config);
711 if (IS_ERR(ptr: priv->vddio_rdev)) {
712 phydev_err(phydev, "failed to register VDDIO regulator\n");
713 return PTR_ERR(ptr: priv->vddio_rdev);
714 }
715
716 priv->vddh_rdev = devm_regulator_register(dev, regulator_desc: &vddh_desc, config: &config);
717 if (IS_ERR(ptr: priv->vddh_rdev)) {
718 phydev_err(phydev, "failed to register VDDH regulator\n");
719 return PTR_ERR(ptr: priv->vddh_rdev);
720 }
721
722 return 0;
723}
724
725static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
726{
727 struct phy_device *phydev = upstream;
728 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
729 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
730 DECLARE_PHY_INTERFACE_MASK(interfaces);
731 phy_interface_t iface;
732
733 linkmode_zero(dst: phy_support);
734 phylink_set(phy_support, 1000baseX_Full);
735 phylink_set(phy_support, 1000baseT_Full);
736 phylink_set(phy_support, Autoneg);
737 phylink_set(phy_support, Pause);
738 phylink_set(phy_support, Asym_Pause);
739
740 linkmode_zero(dst: sfp_support);
741 sfp_parse_support(bus: phydev->sfp_bus, id, support: sfp_support, interfaces);
742 /* Some modules support 10G modes as well as others we support.
743 * Mask out non-supported modes so the correct interface is picked.
744 */
745 linkmode_and(dst: sfp_support, a: phy_support, b: sfp_support);
746
747 if (linkmode_empty(src: sfp_support)) {
748 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
749 return -EINVAL;
750 }
751
752 iface = sfp_select_interface(bus: phydev->sfp_bus, link_modes: sfp_support);
753
754 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
755 * interface for use with SFP modules.
756 * However, some copper modules detected as having a preferred SGMII
757 * interface do default to and function in 1000Base-X mode, so just
758 * print a warning and allow such modules, as they may have some chance
759 * of working.
760 */
761 if (iface == PHY_INTERFACE_MODE_SGMII)
762 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
763 else if (iface != PHY_INTERFACE_MODE_1000BASEX)
764 return -EINVAL;
765
766 return 0;
767}
768
769static const struct sfp_upstream_ops at8031_sfp_ops = {
770 .attach = phy_sfp_attach,
771 .detach = phy_sfp_detach,
772 .module_insert = at8031_sfp_insert,
773 .connect_phy = phy_sfp_connect_phy,
774 .disconnect_phy = phy_sfp_disconnect_phy,
775};
776
777static int at8031_parse_dt(struct phy_device *phydev)
778{
779 struct device_node *node = phydev->mdio.dev.of_node;
780 struct at803x_priv *priv = phydev->priv;
781 int ret;
782
783 if (of_property_read_bool(np: node, propname: "qca,keep-pll-enabled"))
784 priv->flags |= AT803X_KEEP_PLL_ENABLED;
785
786 ret = at8031_register_regulators(phydev);
787 if (ret < 0)
788 return ret;
789
790 ret = devm_regulator_get_enable_optional(dev: &phydev->mdio.dev,
791 id: "vddio");
792 if (ret) {
793 phydev_err(phydev, "failed to get VDDIO regulator\n");
794 return ret;
795 }
796
797 /* Only AR8031/8033 support 1000Base-X for SFP modules */
798 return phy_sfp_probe(phydev, ops: &at8031_sfp_ops);
799}
800
801static int at8031_probe(struct phy_device *phydev)
802{
803 struct at803x_priv *priv;
804 int mode_cfg;
805 int ccr;
806 int ret;
807
808 ret = at803x_probe(phydev);
809 if (ret)
810 return ret;
811
812 priv = phydev->priv;
813
814 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
815 * options.
816 */
817 ret = at8031_parse_dt(phydev);
818 if (ret)
819 return ret;
820
821 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
822 if (ccr < 0)
823 return ccr;
824 mode_cfg = ccr & AT803X_MODE_CFG_MASK;
825
826 switch (mode_cfg) {
827 case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
828 case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
829 priv->is_1000basex = true;
830 fallthrough;
831 case AT803X_MODE_CFG_FX100_RGMII_50OHM:
832 case AT803X_MODE_CFG_FX100_RGMII_75OHM:
833 priv->is_fiber = true;
834 break;
835 }
836
837 /* Disable WoL in 1588 register which is enabled
838 * by default
839 */
840 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
841 AT803X_PHY_MMD3_WOL_CTRL,
842 AT803X_WOL_EN, set: 0);
843}
844
845static int at8031_config_init(struct phy_device *phydev)
846{
847 struct at803x_priv *priv = phydev->priv;
848 int ret;
849
850 /* Some bootloaders leave the fiber page selected.
851 * Switch to the appropriate page (fiber or copper), as otherwise we
852 * read the PHY capabilities from the wrong page.
853 */
854 phy_lock_mdio_bus(phydev);
855 ret = at803x_write_page(phydev,
856 page: priv->is_fiber ? AT803X_PAGE_FIBER :
857 AT803X_PAGE_COPPER);
858 phy_unlock_mdio_bus(phydev);
859 if (ret)
860 return ret;
861
862 ret = at8031_pll_config(phydev);
863 if (ret < 0)
864 return ret;
865
866 return at803x_config_init(phydev);
867}
868
869static int at8031_set_wol(struct phy_device *phydev,
870 struct ethtool_wolinfo *wol)
871{
872 int ret;
873
874 /* First setup MAC address and enable WOL interrupt */
875 ret = at803x_set_wol(phydev, wol);
876 if (ret)
877 return ret;
878
879 if (wol->wolopts & WAKE_MAGIC)
880 /* Enable WOL function for 1588 */
881 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
882 AT803X_PHY_MMD3_WOL_CTRL,
883 mask: 0, AT803X_WOL_EN);
884 else
885 /* Disable WoL function for 1588 */
886 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
887 AT803X_PHY_MMD3_WOL_CTRL,
888 AT803X_WOL_EN, set: 0);
889
890 return ret;
891}
892
893static int at8031_config_intr(struct phy_device *phydev)
894{
895 struct at803x_priv *priv = phydev->priv;
896 int err, value = 0;
897
898 if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
899 priv->is_fiber) {
900 /* Clear any pending interrupts */
901 err = at803x_ack_interrupt(phydev);
902 if (err)
903 return err;
904
905 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
906 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
907
908 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, val: value);
909 if (err)
910 return err;
911 }
912
913 return at803x_config_intr(phydev);
914}
915
916/* AR8031 and AR8033 share the same read status logic */
917static int at8031_read_status(struct phy_device *phydev)
918{
919 struct at803x_priv *priv = phydev->priv;
920 bool changed;
921
922 if (priv->is_1000basex)
923 return genphy_c37_read_status(phydev, changed: &changed);
924
925 return at803x_read_status(phydev);
926}
927
928/* AR8031 and AR8035 share the same cable test get status reg */
929static int at8031_cable_test_get_status(struct phy_device *phydev,
930 bool *finished)
931{
932 return at803x_cable_test_get_status(phydev, finished, pair_mask: 0xf);
933}
934
935/* AR8031 and AR8035 share the same cable test start logic */
936static int at8031_cable_test_start(struct phy_device *phydev)
937{
938 at803x_cable_test_autoneg(phydev);
939 phy_write(phydev, MII_CTRL1000, val: 0);
940 /* we do all the (time consuming) work later */
941 return 0;
942}
943
944/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
945static int at8032_cable_test_get_status(struct phy_device *phydev,
946 bool *finished)
947{
948 return at803x_cable_test_get_status(phydev, finished, pair_mask: 0x3);
949}
950
951static int at8035_parse_dt(struct phy_device *phydev)
952{
953 struct at803x_priv *priv = phydev->priv;
954
955 /* Mask is set by the generic at803x_parse_dt
956 * if property is set. Assume property is set
957 * with the mask not zero.
958 */
959 if (priv->clk_25m_mask) {
960 /* Fixup for the AR8030/AR8035. This chip has another mask and
961 * doesn't support the DSP reference. Eg. the lowest bit of the
962 * mask. The upper two bits select the same frequencies. Mask
963 * the lowest bit here.
964 *
965 * Warning:
966 * There was no datasheet for the AR8030 available so this is
967 * just a guess. But the AR8035 is listed as pin compatible
968 * to the AR8030 so there might be a good chance it works on
969 * the AR8030 too.
970 */
971 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
972 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
973 }
974
975 return 0;
976}
977
978/* AR8030 and AR8035 shared the same special mask for clk_25m */
979static int at8035_probe(struct phy_device *phydev)
980{
981 int ret;
982
983 ret = at803x_probe(phydev);
984 if (ret)
985 return ret;
986
987 return at8035_parse_dt(phydev);
988}
989
990static struct phy_driver at803x_driver[] = {
991{
992 /* Qualcomm Atheros AR8035 */
993 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
994 .name = "Qualcomm Atheros AR8035",
995 .flags = PHY_POLL_CABLE_TEST,
996 .probe = at8035_probe,
997 .config_aneg = at803x_config_aneg,
998 .config_init = at803x_config_init,
999 .soft_reset = genphy_soft_reset,
1000 .set_wol = at803x_set_wol,
1001 .get_wol = at803x_get_wol,
1002 .suspend = at803x_suspend,
1003 .resume = at803x_resume,
1004 /* PHY_GBIT_FEATURES */
1005 .read_status = at803x_read_status,
1006 .config_intr = at803x_config_intr,
1007 .handle_interrupt = at803x_handle_interrupt,
1008 .get_tunable = at803x_get_tunable,
1009 .set_tunable = at803x_set_tunable,
1010 .cable_test_start = at8031_cable_test_start,
1011 .cable_test_get_status = at8031_cable_test_get_status,
1012}, {
1013 /* Qualcomm Atheros AR8030 */
1014 .phy_id = ATH8030_PHY_ID,
1015 .name = "Qualcomm Atheros AR8030",
1016 .phy_id_mask = AT8030_PHY_ID_MASK,
1017 .probe = at8035_probe,
1018 .config_init = at803x_config_init,
1019 .link_change_notify = at803x_link_change_notify,
1020 .set_wol = at803x_set_wol,
1021 .get_wol = at803x_get_wol,
1022 .suspend = at803x_suspend,
1023 .resume = at803x_resume,
1024 /* PHY_BASIC_FEATURES */
1025 .config_intr = at803x_config_intr,
1026 .handle_interrupt = at803x_handle_interrupt,
1027}, {
1028 /* Qualcomm Atheros AR8031/AR8033 */
1029 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1030 .name = "Qualcomm Atheros AR8031/AR8033",
1031 .flags = PHY_POLL_CABLE_TEST,
1032 .probe = at8031_probe,
1033 .config_init = at8031_config_init,
1034 .config_aneg = at803x_config_aneg,
1035 .soft_reset = genphy_soft_reset,
1036 .set_wol = at8031_set_wol,
1037 .get_wol = at803x_get_wol,
1038 .suspend = at803x_suspend,
1039 .resume = at803x_resume,
1040 .read_page = at803x_read_page,
1041 .write_page = at803x_write_page,
1042 .get_features = at803x_get_features,
1043 .read_status = at8031_read_status,
1044 .config_intr = at8031_config_intr,
1045 .handle_interrupt = at803x_handle_interrupt,
1046 .get_tunable = at803x_get_tunable,
1047 .set_tunable = at803x_set_tunable,
1048 .cable_test_start = at8031_cable_test_start,
1049 .cable_test_get_status = at8031_cable_test_get_status,
1050}, {
1051 /* Qualcomm Atheros AR8032 */
1052 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1053 .name = "Qualcomm Atheros AR8032",
1054 .probe = at803x_probe,
1055 .flags = PHY_POLL_CABLE_TEST,
1056 .config_init = at803x_config_init,
1057 .link_change_notify = at803x_link_change_notify,
1058 .suspend = at803x_suspend,
1059 .resume = at803x_resume,
1060 /* PHY_BASIC_FEATURES */
1061 .config_intr = at803x_config_intr,
1062 .handle_interrupt = at803x_handle_interrupt,
1063 .cable_test_start = at803x_cable_test_start,
1064 .cable_test_get_status = at8032_cable_test_get_status,
1065}, {
1066 /* ATHEROS AR9331 */
1067 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1068 .name = "Qualcomm Atheros AR9331 built-in PHY",
1069 .probe = at803x_probe,
1070 .suspend = at803x_suspend,
1071 .resume = at803x_resume,
1072 .flags = PHY_POLL_CABLE_TEST,
1073 /* PHY_BASIC_FEATURES */
1074 .config_intr = at803x_config_intr,
1075 .handle_interrupt = at803x_handle_interrupt,
1076 .cable_test_start = at803x_cable_test_start,
1077 .cable_test_get_status = at8032_cable_test_get_status,
1078 .read_status = at803x_read_status,
1079 .soft_reset = genphy_soft_reset,
1080 .config_aneg = at803x_config_aneg,
1081}, {
1082 /* Qualcomm Atheros QCA9561 */
1083 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
1084 .name = "Qualcomm Atheros QCA9561 built-in PHY",
1085 .probe = at803x_probe,
1086 .suspend = at803x_suspend,
1087 .resume = at803x_resume,
1088 .flags = PHY_POLL_CABLE_TEST,
1089 /* PHY_BASIC_FEATURES */
1090 .config_intr = at803x_config_intr,
1091 .handle_interrupt = at803x_handle_interrupt,
1092 .cable_test_start = at803x_cable_test_start,
1093 .cable_test_get_status = at8032_cable_test_get_status,
1094 .read_status = at803x_read_status,
1095 .soft_reset = genphy_soft_reset,
1096 .config_aneg = at803x_config_aneg,
1097}, };
1098
1099module_phy_driver(at803x_driver);
1100
1101static const struct mdio_device_id __maybe_unused atheros_tbl[] = {
1102 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1103 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1104 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1105 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1106 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1107 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
1108 { }
1109};
1110
1111MODULE_DEVICE_TABLE(mdio, atheros_tbl);
1112

source code of linux/drivers/net/phy/qcom/at803x.c