1// SPDX-License-Identifier: GPL-2.0+
2/* drivers/net/phy/realtek.c
3 *
4 * Driver for Realtek PHYs
5 *
6 * Author: Johnson Leung <r58129@freescale.com>
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 */
10#include <linux/bitops.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/of.h>
13#include <linux/phy.h>
14#include <linux/pm_wakeirq.h>
15#include <linux/netdevice.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/string_choices.h>
20
21#include "realtek.h"
22
23#define RTL8201F_IER 0x13
24
25#define RTL8201F_ISR 0x1e
26#define RTL8201F_ISR_ANERR BIT(15)
27#define RTL8201F_ISR_DUPLEX BIT(13)
28#define RTL8201F_ISR_LINK BIT(11)
29#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
30 RTL8201F_ISR_DUPLEX | \
31 RTL8201F_ISR_LINK)
32
33#define RTL821x_INER 0x12
34#define RTL8211B_INER_INIT 0x6400
35#define RTL8211E_INER_LINK_STATUS BIT(10)
36#define RTL8211F_INER_PME BIT(7)
37#define RTL8211F_INER_LINK_STATUS BIT(4)
38
39#define RTL821x_INSR 0x13
40
41#define RTL821x_EXT_PAGE_SELECT 0x1e
42
43#define RTL821x_PAGE_SELECT 0x1f
44#define RTL821x_SET_EXT_PAGE 0x07
45
46/* RTL8211E extension page 44/0x2c */
47#define RTL8211E_LEDCR_EXT_PAGE 0x2c
48#define RTL8211E_LEDCR1 0x1a
49#define RTL8211E_LEDCR1_ACT_TXRX BIT(4)
50#define RTL8211E_LEDCR1_MASK BIT(4)
51#define RTL8211E_LEDCR1_SHIFT 1
52
53#define RTL8211E_LEDCR2 0x1c
54#define RTL8211E_LEDCR2_LINK_1000 BIT(2)
55#define RTL8211E_LEDCR2_LINK_100 BIT(1)
56#define RTL8211E_LEDCR2_LINK_10 BIT(0)
57#define RTL8211E_LEDCR2_MASK GENMASK(2, 0)
58#define RTL8211E_LEDCR2_SHIFT 4
59
60/* RTL8211E extension page 164/0xa4 */
61#define RTL8211E_RGMII_EXT_PAGE 0xa4
62#define RTL8211E_RGMII_DELAY 0x1c
63#define RTL8211E_CTRL_DELAY BIT(13)
64#define RTL8211E_TX_DELAY BIT(12)
65#define RTL8211E_RX_DELAY BIT(11)
66#define RTL8211E_DELAY_MASK GENMASK(13, 11)
67
68/* RTL8211F PHY configuration */
69#define RTL8211F_PHYCR_PAGE 0xa43
70#define RTL8211F_PHYCR1 0x18
71#define RTL8211F_ALDPS_PLL_OFF BIT(1)
72#define RTL8211F_ALDPS_ENABLE BIT(2)
73#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
74
75#define RTL8211F_PHYCR2 0x19
76#define RTL8211F_CLKOUT_EN BIT(0)
77#define RTL8211F_PHYCR2_PHY_EEE_ENABLE BIT(5)
78
79#define RTL8211F_INSR_PAGE 0xa43
80#define RTL8211F_INSR 0x1d
81
82/* RTL8211F LED configuration */
83#define RTL8211F_LEDCR_PAGE 0xd04
84#define RTL8211F_LEDCR 0x10
85#define RTL8211F_LEDCR_MODE BIT(15)
86#define RTL8211F_LEDCR_ACT_TXRX BIT(4)
87#define RTL8211F_LEDCR_LINK_1000 BIT(3)
88#define RTL8211F_LEDCR_LINK_100 BIT(1)
89#define RTL8211F_LEDCR_LINK_10 BIT(0)
90#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
91#define RTL8211F_LEDCR_SHIFT 5
92
93/* RTL8211F(D)(I)-VD-CG CLKOUT configuration is specified via magic values
94 * to undocumented register pages. The names here do not reflect the datasheet.
95 * Unlike other PHY models, CLKOUT configuration does not go through PHYCR2.
96 */
97#define RTL8211FVD_CLKOUT_PAGE 0xd05
98#define RTL8211FVD_CLKOUT_REG 0x11
99#define RTL8211FVD_CLKOUT_EN BIT(8)
100
101/* RTL8211F RGMII configuration */
102#define RTL8211F_RGMII_PAGE 0xd08
103
104#define RTL8211F_TXCR 0x11
105#define RTL8211F_TX_DELAY BIT(8)
106
107#define RTL8211F_RXCR 0x15
108#define RTL8211F_RX_DELAY BIT(3)
109
110/* RTL8211F WOL settings */
111#define RTL8211F_WOL_PAGE 0xd8a
112#define RTL8211F_WOL_SETTINGS_EVENTS 16
113#define RTL8211F_WOL_EVENT_MAGIC BIT(12)
114#define RTL8211F_WOL_RST_RMSQ 17
115#define RTL8211F_WOL_RG_RSTB BIT(15)
116#define RTL8211F_WOL_RMSQ 0x1fff
117
118/* RTL8211F Unique phyiscal and multicast address (WOL) */
119#define RTL8211F_PHYSICAL_ADDR_PAGE 0xd8c
120#define RTL8211F_PHYSICAL_ADDR_WORD0 16
121#define RTL8211F_PHYSICAL_ADDR_WORD1 17
122#define RTL8211F_PHYSICAL_ADDR_WORD2 18
123
124#define RTL822X_VND1_SERDES_OPTION 0x697a
125#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
126#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
127#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
128
129#define RTL822X_VND1_SERDES_CTRL3 0x7580
130#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
131#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
132#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
133
134/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
135 * is set, they cannot be accessed by C45-over-C22.
136 */
137#define RTL822X_VND2_C22_REG(reg) (0xa400 + 2 * (reg))
138
139#define RTL8221B_VND2_INER 0xa4d2
140#define RTL8221B_VND2_INER_LINK_STATUS BIT(4)
141
142#define RTL8221B_VND2_INSR 0xa4d4
143
144#define RTL8224_MII_RTCT 0x11
145#define RTL8224_MII_RTCT_ENABLE BIT(0)
146#define RTL8224_MII_RTCT_PAIR_A BIT(4)
147#define RTL8224_MII_RTCT_PAIR_B BIT(5)
148#define RTL8224_MII_RTCT_PAIR_C BIT(6)
149#define RTL8224_MII_RTCT_PAIR_D BIT(7)
150#define RTL8224_MII_RTCT_DONE BIT(15)
151
152#define RTL8224_MII_SRAM_ADDR 0x1b
153#define RTL8224_MII_SRAM_DATA 0x1c
154
155#define RTL8224_SRAM_RTCT_FAULT(pair) (0x8026 + (pair) * 4)
156#define RTL8224_SRAM_RTCT_FAULT_BUSY BIT(0)
157#define RTL8224_SRAM_RTCT_FAULT_OPEN BIT(3)
158#define RTL8224_SRAM_RTCT_FAULT_SAME_SHORT BIT(4)
159#define RTL8224_SRAM_RTCT_FAULT_OK BIT(5)
160#define RTL8224_SRAM_RTCT_FAULT_DONE BIT(6)
161#define RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT BIT(7)
162
163#define RTL8224_SRAM_RTCT_LEN(pair) (0x8028 + (pair) * 4)
164
165#define RTL8366RB_POWER_SAVE 0x15
166#define RTL8366RB_POWER_SAVE_ON BIT(12)
167
168#define RTL9000A_GINMR 0x14
169#define RTL9000A_GINMR_LINK_STATUS BIT(4)
170
171#define RTL_VND2_PHYSR 0xa434
172#define RTL_VND2_PHYSR_DUPLEX BIT(3)
173#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
174#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
175#define RTL_VND2_PHYSR_MASTER BIT(11)
176#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
177
178#define RTL_MDIO_PCS_EEE_ABLE 0xa5c4
179#define RTL_MDIO_AN_EEE_ADV 0xa5d0
180#define RTL_MDIO_AN_EEE_LPABLE 0xa5d2
181#define RTL_MDIO_AN_10GBT_CTRL 0xa5d4
182#define RTL_MDIO_AN_10GBT_STAT 0xa5d6
183#define RTL_MDIO_PMA_SPEED 0xa616
184#define RTL_MDIO_AN_EEE_LPABLE2 0xa6d0
185#define RTL_MDIO_AN_EEE_ADV2 0xa6d4
186#define RTL_MDIO_PCS_EEE_ABLE2 0xa6ec
187
188#define RTL_GENERIC_PHYID 0x001cc800
189#define RTL_8211FVD_PHYID 0x001cc878
190#define RTL_8221B 0x001cc840
191#define RTL_8221B_VB_CG 0x001cc849
192#define RTL_8221B_VM_CG 0x001cc84a
193#define RTL_8251B 0x001cc862
194#define RTL_8261C 0x001cc890
195
196/* RTL8211E and RTL8211F support up to three LEDs */
197#define RTL8211x_LED_COUNT 3
198
199MODULE_DESCRIPTION("Realtek PHY driver");
200MODULE_AUTHOR("Johnson Leung");
201MODULE_LICENSE("GPL");
202
203struct rtl821x_priv {
204 bool enable_aldps;
205 bool disable_clk_out;
206 struct clk *clk;
207 /* rtl8211f */
208 u16 iner;
209};
210
211static int rtl821x_read_page(struct phy_device *phydev)
212{
213 return __phy_read(phydev, RTL821x_PAGE_SELECT);
214}
215
216static int rtl821x_write_page(struct phy_device *phydev, int page)
217{
218 return __phy_write(phydev, RTL821x_PAGE_SELECT, val: page);
219}
220
221static int rtl821x_read_ext_page(struct phy_device *phydev, u16 ext_page,
222 u32 regnum)
223{
224 int oldpage, ret = 0;
225
226 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
227 if (oldpage >= 0) {
228 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, val: ext_page);
229 if (ret == 0)
230 ret = __phy_read(phydev, regnum);
231 }
232
233 return phy_restore_page(phydev, oldpage, ret);
234}
235
236static int rtl821x_modify_ext_page(struct phy_device *phydev, u16 ext_page,
237 u32 regnum, u16 mask, u16 set)
238{
239 int oldpage, ret = 0;
240
241 oldpage = phy_select_page(phydev, RTL821x_SET_EXT_PAGE);
242 if (oldpage >= 0) {
243 ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, val: ext_page);
244 if (ret == 0)
245 ret = __phy_modify(phydev, regnum, mask, set);
246 }
247
248 return phy_restore_page(phydev, oldpage, ret);
249}
250
251static int rtl821x_probe(struct phy_device *phydev)
252{
253 struct device *dev = &phydev->mdio.dev;
254 struct rtl821x_priv *priv;
255
256 priv = devm_kzalloc(dev, size: sizeof(*priv), GFP_KERNEL);
257 if (!priv)
258 return -ENOMEM;
259
260 priv->clk = devm_clk_get_optional_enabled(dev, NULL);
261 if (IS_ERR(ptr: priv->clk))
262 return dev_err_probe(dev, err: PTR_ERR(ptr: priv->clk),
263 fmt: "failed to get phy clock\n");
264
265 priv->enable_aldps = of_property_read_bool(np: dev->of_node,
266 propname: "realtek,aldps-enable");
267 priv->disable_clk_out = of_property_read_bool(np: dev->of_node,
268 propname: "realtek,clkout-disable");
269
270 phydev->priv = priv;
271
272 return 0;
273}
274
275static int rtl8211f_probe(struct phy_device *phydev)
276{
277 struct device *dev = &phydev->mdio.dev;
278 int ret;
279
280 ret = rtl821x_probe(phydev);
281 if (ret < 0)
282 return ret;
283
284 /* Disable all PME events */
285 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE,
286 RTL8211F_WOL_SETTINGS_EVENTS, val: 0);
287 if (ret < 0)
288 return ret;
289
290 /* Mark this PHY as wakeup capable and register the interrupt as a
291 * wakeup IRQ if the PHY is marked as a wakeup source in firmware,
292 * and the interrupt is valid.
293 */
294 if (device_property_read_bool(dev, propname: "wakeup-source") &&
295 phy_interrupt_is_valid(phydev)) {
296 device_set_wakeup_capable(dev, capable: true);
297 devm_pm_set_wake_irq(dev, irq: phydev->irq);
298 }
299
300 return ret;
301}
302
303static int rtl8201_ack_interrupt(struct phy_device *phydev)
304{
305 int err;
306
307 err = phy_read(phydev, RTL8201F_ISR);
308
309 return (err < 0) ? err : 0;
310}
311
312static int rtl821x_ack_interrupt(struct phy_device *phydev)
313{
314 int err;
315
316 err = phy_read(phydev, RTL821x_INSR);
317
318 return (err < 0) ? err : 0;
319}
320
321static int rtl8211f_ack_interrupt(struct phy_device *phydev)
322{
323 int err;
324
325 err = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
326
327 return (err < 0) ? err : 0;
328}
329
330static int rtl8201_config_intr(struct phy_device *phydev)
331{
332 u16 val;
333 int err;
334
335 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
336 err = rtl8201_ack_interrupt(phydev);
337 if (err)
338 return err;
339
340 val = BIT(13) | BIT(12) | BIT(11);
341 err = phy_write_paged(phydev, page: 0x7, RTL8201F_IER, val);
342 } else {
343 val = 0;
344 err = phy_write_paged(phydev, page: 0x7, RTL8201F_IER, val);
345 if (err)
346 return err;
347
348 err = rtl8201_ack_interrupt(phydev);
349 }
350
351 return err;
352}
353
354static int rtl8211b_config_intr(struct phy_device *phydev)
355{
356 int err;
357
358 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
359 err = rtl821x_ack_interrupt(phydev);
360 if (err)
361 return err;
362
363 err = phy_write(phydev, RTL821x_INER,
364 RTL8211B_INER_INIT);
365 } else {
366 err = phy_write(phydev, RTL821x_INER, val: 0);
367 if (err)
368 return err;
369
370 err = rtl821x_ack_interrupt(phydev);
371 }
372
373 return err;
374}
375
376static int rtl8211e_config_intr(struct phy_device *phydev)
377{
378 int err;
379
380 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
381 err = rtl821x_ack_interrupt(phydev);
382 if (err)
383 return err;
384
385 err = phy_write(phydev, RTL821x_INER,
386 RTL8211E_INER_LINK_STATUS);
387 } else {
388 err = phy_write(phydev, RTL821x_INER, val: 0);
389 if (err)
390 return err;
391
392 err = rtl821x_ack_interrupt(phydev);
393 }
394
395 return err;
396}
397
398static int rtl8211f_config_intr(struct phy_device *phydev)
399{
400 struct rtl821x_priv *priv = phydev->priv;
401 u16 val;
402 int err;
403
404 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
405 err = rtl8211f_ack_interrupt(phydev);
406 if (err)
407 return err;
408
409 val = RTL8211F_INER_LINK_STATUS;
410 err = phy_write_paged(phydev, page: 0xa42, RTL821x_INER, val);
411 if (err == 0)
412 priv->iner = val;
413 } else {
414 priv->iner = val = 0;
415 err = phy_write_paged(phydev, page: 0xa42, RTL821x_INER, val);
416 if (err)
417 return err;
418
419 err = rtl8211f_ack_interrupt(phydev);
420 }
421
422 return err;
423}
424
425static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
426{
427 int irq_status;
428
429 irq_status = phy_read(phydev, RTL8201F_ISR);
430 if (irq_status < 0) {
431 phy_error(phydev);
432 return IRQ_NONE;
433 }
434
435 if (!(irq_status & RTL8201F_ISR_MASK))
436 return IRQ_NONE;
437
438 phy_trigger_machine(phydev);
439
440 return IRQ_HANDLED;
441}
442
443static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
444{
445 int irq_status, irq_enabled;
446
447 irq_status = phy_read(phydev, RTL821x_INSR);
448 if (irq_status < 0) {
449 phy_error(phydev);
450 return IRQ_NONE;
451 }
452
453 irq_enabled = phy_read(phydev, RTL821x_INER);
454 if (irq_enabled < 0) {
455 phy_error(phydev);
456 return IRQ_NONE;
457 }
458
459 if (!(irq_status & irq_enabled))
460 return IRQ_NONE;
461
462 phy_trigger_machine(phydev);
463
464 return IRQ_HANDLED;
465}
466
467static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
468{
469 int irq_status;
470
471 irq_status = phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
472 if (irq_status < 0) {
473 phy_error(phydev);
474 return IRQ_NONE;
475 }
476
477 if (irq_status & RTL8211F_INER_LINK_STATUS) {
478 phy_trigger_machine(phydev);
479 return IRQ_HANDLED;
480 }
481
482 if (irq_status & RTL8211F_INER_PME) {
483 pm_wakeup_event(dev: &phydev->mdio.dev, msec: 0);
484 return IRQ_HANDLED;
485 }
486
487 return IRQ_NONE;
488}
489
490static void rtl8211f_get_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
491{
492 int wol_events;
493
494 /* If the PHY is not capable of waking the system, then WoL can not
495 * be supported.
496 */
497 if (!device_can_wakeup(dev: &dev->mdio.dev)) {
498 wol->supported = 0;
499 return;
500 }
501
502 wol->supported = WAKE_MAGIC;
503
504 wol_events = phy_read_paged(phydev: dev, RTL8211F_WOL_PAGE, RTL8211F_WOL_SETTINGS_EVENTS);
505 if (wol_events < 0)
506 return;
507
508 if (wol_events & RTL8211F_WOL_EVENT_MAGIC)
509 wol->wolopts = WAKE_MAGIC;
510}
511
512static int rtl8211f_set_wol(struct phy_device *dev, struct ethtool_wolinfo *wol)
513{
514 const u8 *mac_addr = dev->attached_dev->dev_addr;
515 int oldpage;
516
517 if (!device_can_wakeup(dev: &dev->mdio.dev))
518 return -EOPNOTSUPP;
519
520 oldpage = phy_save_page(phydev: dev);
521 if (oldpage < 0)
522 goto err;
523
524 if (wol->wolopts & WAKE_MAGIC) {
525 /* Store the device address for the magic packet */
526 rtl821x_write_page(phydev: dev, RTL8211F_PHYSICAL_ADDR_PAGE);
527 __phy_write(phydev: dev, RTL8211F_PHYSICAL_ADDR_WORD0, val: mac_addr[1] << 8 | (mac_addr[0]));
528 __phy_write(phydev: dev, RTL8211F_PHYSICAL_ADDR_WORD1, val: mac_addr[3] << 8 | (mac_addr[2]));
529 __phy_write(phydev: dev, RTL8211F_PHYSICAL_ADDR_WORD2, val: mac_addr[5] << 8 | (mac_addr[4]));
530
531 /* Enable magic packet matching */
532 rtl821x_write_page(phydev: dev, RTL8211F_WOL_PAGE);
533 __phy_write(phydev: dev, RTL8211F_WOL_SETTINGS_EVENTS, RTL8211F_WOL_EVENT_MAGIC);
534 /* Set the maximum packet size, and assert WoL reset */
535 __phy_write(phydev: dev, RTL8211F_WOL_RST_RMSQ, RTL8211F_WOL_RMSQ);
536 } else {
537 /* Disable magic packet matching */
538 rtl821x_write_page(phydev: dev, RTL8211F_WOL_PAGE);
539 __phy_write(phydev: dev, RTL8211F_WOL_SETTINGS_EVENTS, val: 0);
540
541 /* Place WoL in reset */
542 __phy_clear_bits(phydev: dev, RTL8211F_WOL_RST_RMSQ,
543 RTL8211F_WOL_RG_RSTB);
544 }
545
546 device_set_wakeup_enable(dev: &dev->mdio.dev, enable: !!(wol->wolopts & WAKE_MAGIC));
547
548err:
549 return phy_restore_page(phydev: dev, oldpage, ret: 0);
550}
551
552static int rtl8211_config_aneg(struct phy_device *phydev)
553{
554 int ret;
555
556 ret = genphy_config_aneg(phydev);
557 if (ret < 0)
558 return ret;
559
560 /* Quirk was copied from vendor driver. Unfortunately it includes no
561 * description of the magic numbers.
562 */
563 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
564 phy_write(phydev, regnum: 0x17, val: 0x2138);
565 phy_write(phydev, regnum: 0x0e, val: 0x0260);
566 } else {
567 phy_write(phydev, regnum: 0x17, val: 0x2108);
568 phy_write(phydev, regnum: 0x0e, val: 0x0000);
569 }
570
571 return 0;
572}
573
574static int rtl8211c_config_init(struct phy_device *phydev)
575{
576 /* RTL8211C has an issue when operating in Gigabit slave mode */
577 return phy_set_bits(phydev, MII_CTRL1000,
578 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
579}
580
581static int rtl8211f_config_rgmii_delay(struct phy_device *phydev)
582{
583 u16 val_txdly, val_rxdly;
584 int ret;
585
586 switch (phydev->interface) {
587 case PHY_INTERFACE_MODE_RGMII:
588 val_txdly = 0;
589 val_rxdly = 0;
590 break;
591
592 case PHY_INTERFACE_MODE_RGMII_RXID:
593 val_txdly = 0;
594 val_rxdly = RTL8211F_RX_DELAY;
595 break;
596
597 case PHY_INTERFACE_MODE_RGMII_TXID:
598 val_txdly = RTL8211F_TX_DELAY;
599 val_rxdly = 0;
600 break;
601
602 case PHY_INTERFACE_MODE_RGMII_ID:
603 val_txdly = RTL8211F_TX_DELAY;
604 val_rxdly = RTL8211F_RX_DELAY;
605 break;
606
607 default: /* the rest of the modes imply leaving delay as is. */
608 return 0;
609 }
610
611 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
612 RTL8211F_TXCR, RTL8211F_TX_DELAY,
613 set: val_txdly);
614 if (ret < 0) {
615 phydev_err(phydev, "Failed to update the TX delay register: %pe\n",
616 ERR_PTR(ret));
617 return ret;
618 } else if (ret) {
619 phydev_dbg(phydev,
620 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
621 str_enable_disable(val_txdly));
622 } else {
623 phydev_dbg(phydev,
624 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
625 str_enabled_disabled(val_txdly));
626 }
627
628 ret = phy_modify_paged_changed(phydev, RTL8211F_RGMII_PAGE,
629 RTL8211F_RXCR, RTL8211F_RX_DELAY,
630 set: val_rxdly);
631 if (ret < 0) {
632 phydev_err(phydev, "Failed to update the RX delay register: %pe\n",
633 ERR_PTR(ret));
634 return ret;
635 } else if (ret) {
636 phydev_dbg(phydev,
637 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
638 str_enable_disable(val_rxdly));
639 } else {
640 phydev_dbg(phydev,
641 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
642 str_enabled_disabled(val_rxdly));
643 }
644
645 return 0;
646}
647
648static int rtl8211f_config_clk_out(struct phy_device *phydev)
649{
650 struct rtl821x_priv *priv = phydev->priv;
651 int ret;
652
653 /* The value is preserved if the device tree property is absent */
654 if (!priv->disable_clk_out)
655 return 0;
656
657 if (phydev->drv->phy_id == RTL_8211FVD_PHYID)
658 ret = phy_modify_paged(phydev, RTL8211FVD_CLKOUT_PAGE,
659 RTL8211FVD_CLKOUT_REG,
660 RTL8211FVD_CLKOUT_EN, set: 0);
661 else
662 ret = phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE,
663 RTL8211F_PHYCR2, RTL8211F_CLKOUT_EN, set: 0);
664 if (ret)
665 return ret;
666
667 return genphy_soft_reset(phydev);
668}
669
670/* Advance Link Down Power Saving (ALDPS) mode changes crystal/clock behaviour,
671 * which causes the RXC clock signal to stop for tens to hundreds of
672 * milliseconds.
673 *
674 * Some MACs need the RXC clock to support their internal RX logic, so ALDPS is
675 * only enabled based on an opt-in device tree property.
676 */
677static int rtl8211f_config_aldps(struct phy_device *phydev)
678{
679 struct rtl821x_priv *priv = phydev->priv;
680 u16 mask = RTL8211F_ALDPS_PLL_OFF |
681 RTL8211F_ALDPS_ENABLE |
682 RTL8211F_ALDPS_XTAL_OFF;
683
684 /* The value is preserved if the device tree property is absent */
685 if (!priv->enable_aldps)
686 return 0;
687
688 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR1,
689 mask, set: mask);
690}
691
692static int rtl8211f_config_phy_eee(struct phy_device *phydev)
693{
694 /* Disable PHY-mode EEE so LPI is passed to the MAC */
695 return phy_modify_paged(phydev, RTL8211F_PHYCR_PAGE, RTL8211F_PHYCR2,
696 RTL8211F_PHYCR2_PHY_EEE_ENABLE, set: 0);
697}
698
699static int rtl8211f_config_init(struct phy_device *phydev)
700{
701 struct device *dev = &phydev->mdio.dev;
702 int ret;
703
704 ret = rtl8211f_config_aldps(phydev);
705 if (ret) {
706 dev_err(dev, "aldps mode configuration failed: %pe\n",
707 ERR_PTR(ret));
708 return ret;
709 }
710
711 ret = rtl8211f_config_rgmii_delay(phydev);
712 if (ret)
713 return ret;
714
715 ret = rtl8211f_config_clk_out(phydev);
716 if (ret) {
717 dev_err(dev, "clkout configuration failed: %pe\n",
718 ERR_PTR(ret));
719 return ret;
720 }
721
722 return rtl8211f_config_phy_eee(phydev);
723}
724
725static int rtl821x_suspend(struct phy_device *phydev)
726{
727 struct rtl821x_priv *priv = phydev->priv;
728 int ret = 0;
729
730 if (!phydev->wol_enabled) {
731 ret = genphy_suspend(phydev);
732
733 if (ret)
734 return ret;
735
736 clk_disable_unprepare(clk: priv->clk);
737 }
738
739 return ret;
740}
741
742static int rtl8211f_suspend(struct phy_device *phydev)
743{
744 u16 wol_rst;
745 int ret;
746
747 ret = rtl821x_suspend(phydev);
748 if (ret < 0)
749 return ret;
750
751 /* If a PME event is enabled, then configure the interrupt for
752 * PME events only, disabling link interrupt. We avoid switching
753 * to PMEB mode as we don't have a status bit for that.
754 */
755 if (device_may_wakeup(dev: &phydev->mdio.dev)) {
756 ret = phy_write_paged(phydev, page: 0xa42, RTL821x_INER,
757 RTL8211F_INER_PME);
758 if (ret < 0)
759 goto err;
760
761 /* Read the INSR to clear any pending interrupt */
762 phy_read_paged(phydev, RTL8211F_INSR_PAGE, RTL8211F_INSR);
763
764 /* Reset the WoL to ensure that an event is picked up.
765 * Unless we do this, even if we receive another packet,
766 * we may not have a PME interrupt raised.
767 */
768 ret = phy_read_paged(phydev, RTL8211F_WOL_PAGE,
769 RTL8211F_WOL_RST_RMSQ);
770 if (ret < 0)
771 goto err;
772
773 wol_rst = ret & ~RTL8211F_WOL_RG_RSTB;
774 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE,
775 RTL8211F_WOL_RST_RMSQ, val: wol_rst);
776 if (ret < 0)
777 goto err;
778
779 wol_rst |= RTL8211F_WOL_RG_RSTB;
780 ret = phy_write_paged(phydev, RTL8211F_WOL_PAGE,
781 RTL8211F_WOL_RST_RMSQ, val: wol_rst);
782 }
783
784err:
785 return ret;
786}
787
788static int rtl821x_resume(struct phy_device *phydev)
789{
790 struct rtl821x_priv *priv = phydev->priv;
791 int ret;
792
793 if (!phydev->wol_enabled)
794 clk_prepare_enable(clk: priv->clk);
795
796 ret = genphy_resume(phydev);
797 if (ret < 0)
798 return ret;
799
800 msleep(msecs: 20);
801
802 return 0;
803}
804
805static int rtl8211f_resume(struct phy_device *phydev)
806{
807 struct rtl821x_priv *priv = phydev->priv;
808 int ret;
809
810 ret = rtl821x_resume(phydev);
811 if (ret < 0)
812 return ret;
813
814 /* If the device was programmed for a PME event, restore the interrupt
815 * enable so phylib can receive link state interrupts.
816 */
817 if (device_may_wakeup(dev: &phydev->mdio.dev))
818 ret = phy_write_paged(phydev, page: 0xa42, RTL821x_INER, val: priv->iner);
819
820 return ret;
821}
822
823static int rtl8211x_led_hw_is_supported(struct phy_device *phydev, u8 index,
824 unsigned long rules)
825{
826 const unsigned long mask = BIT(TRIGGER_NETDEV_LINK) |
827 BIT(TRIGGER_NETDEV_LINK_10) |
828 BIT(TRIGGER_NETDEV_LINK_100) |
829 BIT(TRIGGER_NETDEV_LINK_1000) |
830 BIT(TRIGGER_NETDEV_RX) |
831 BIT(TRIGGER_NETDEV_TX);
832
833 /* The RTL8211F PHY supports these LED settings on up to three LEDs:
834 * - Link: Configurable subset of 10/100/1000 link rates
835 * - Active: Blink on activity, RX or TX is not differentiated
836 * The Active option has two modes, A and B:
837 * - A: Link and Active indication at configurable, but matching,
838 * subset of 10/100/1000 link rates
839 * - B: Link indication at configurable subset of 10/100/1000 link
840 * rates and Active indication always at all three 10+100+1000
841 * link rates.
842 * This code currently uses mode B only.
843 *
844 * RTL8211E PHY LED has one mode, which works like RTL8211F mode B.
845 */
846
847 if (index >= RTL8211x_LED_COUNT)
848 return -EINVAL;
849
850 /* Filter out any other unsupported triggers. */
851 if (rules & ~mask)
852 return -EOPNOTSUPP;
853
854 /* RX and TX are not differentiated, either both are set or not set. */
855 if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
856 return -EOPNOTSUPP;
857
858 return 0;
859}
860
861static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
862 unsigned long *rules)
863{
864 int val;
865
866 if (index >= RTL8211x_LED_COUNT)
867 return -EINVAL;
868
869 val = phy_read_paged(phydev, page: 0xd04, RTL8211F_LEDCR);
870 if (val < 0)
871 return val;
872
873 val >>= RTL8211F_LEDCR_SHIFT * index;
874 val &= RTL8211F_LEDCR_MASK;
875
876 if (val & RTL8211F_LEDCR_LINK_10)
877 __set_bit(TRIGGER_NETDEV_LINK_10, rules);
878
879 if (val & RTL8211F_LEDCR_LINK_100)
880 __set_bit(TRIGGER_NETDEV_LINK_100, rules);
881
882 if (val & RTL8211F_LEDCR_LINK_1000)
883 __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
884
885 if ((val & RTL8211F_LEDCR_LINK_10) &&
886 (val & RTL8211F_LEDCR_LINK_100) &&
887 (val & RTL8211F_LEDCR_LINK_1000)) {
888 __set_bit(TRIGGER_NETDEV_LINK, rules);
889 }
890
891 if (val & RTL8211F_LEDCR_ACT_TXRX) {
892 __set_bit(TRIGGER_NETDEV_RX, rules);
893 __set_bit(TRIGGER_NETDEV_TX, rules);
894 }
895
896 return 0;
897}
898
899static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
900 unsigned long rules)
901{
902 const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
903 u16 reg = 0;
904
905 if (index >= RTL8211x_LED_COUNT)
906 return -EINVAL;
907
908 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
909 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) {
910 reg |= RTL8211F_LEDCR_LINK_10;
911 }
912
913 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
914 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) {
915 reg |= RTL8211F_LEDCR_LINK_100;
916 }
917
918 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
919 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) {
920 reg |= RTL8211F_LEDCR_LINK_1000;
921 }
922
923 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
924 test_bit(TRIGGER_NETDEV_TX, &rules)) {
925 reg |= RTL8211F_LEDCR_ACT_TXRX;
926 }
927
928 reg <<= RTL8211F_LEDCR_SHIFT * index;
929 reg |= RTL8211F_LEDCR_MODE; /* Mode B */
930
931 return phy_modify_paged(phydev, page: 0xd04, RTL8211F_LEDCR, mask, set: reg);
932}
933
934static int rtl8211e_led_hw_control_get(struct phy_device *phydev, u8 index,
935 unsigned long *rules)
936{
937 int ret;
938 u16 cr1, cr2;
939
940 if (index >= RTL8211x_LED_COUNT)
941 return -EINVAL;
942
943 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
944 RTL8211E_LEDCR1);
945 if (ret < 0)
946 return ret;
947
948 cr1 = ret >> RTL8211E_LEDCR1_SHIFT * index;
949 if (cr1 & RTL8211E_LEDCR1_ACT_TXRX) {
950 __set_bit(TRIGGER_NETDEV_RX, rules);
951 __set_bit(TRIGGER_NETDEV_TX, rules);
952 }
953
954 ret = rtl821x_read_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
955 RTL8211E_LEDCR2);
956 if (ret < 0)
957 return ret;
958
959 cr2 = ret >> RTL8211E_LEDCR2_SHIFT * index;
960 if (cr2 & RTL8211E_LEDCR2_LINK_10)
961 __set_bit(TRIGGER_NETDEV_LINK_10, rules);
962
963 if (cr2 & RTL8211E_LEDCR2_LINK_100)
964 __set_bit(TRIGGER_NETDEV_LINK_100, rules);
965
966 if (cr2 & RTL8211E_LEDCR2_LINK_1000)
967 __set_bit(TRIGGER_NETDEV_LINK_1000, rules);
968
969 if ((cr2 & RTL8211E_LEDCR2_LINK_10) &&
970 (cr2 & RTL8211E_LEDCR2_LINK_100) &&
971 (cr2 & RTL8211E_LEDCR2_LINK_1000)) {
972 __set_bit(TRIGGER_NETDEV_LINK, rules);
973 }
974
975 return ret;
976}
977
978static int rtl8211e_led_hw_control_set(struct phy_device *phydev, u8 index,
979 unsigned long rules)
980{
981 const u16 cr1mask =
982 RTL8211E_LEDCR1_MASK << (RTL8211E_LEDCR1_SHIFT * index);
983 const u16 cr2mask =
984 RTL8211E_LEDCR2_MASK << (RTL8211E_LEDCR2_SHIFT * index);
985 u16 cr1 = 0, cr2 = 0;
986 int ret;
987
988 if (index >= RTL8211x_LED_COUNT)
989 return -EINVAL;
990
991 if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
992 test_bit(TRIGGER_NETDEV_TX, &rules)) {
993 cr1 |= RTL8211E_LEDCR1_ACT_TXRX;
994 }
995
996 cr1 <<= RTL8211E_LEDCR1_SHIFT * index;
997 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
998 RTL8211E_LEDCR1, mask: cr1mask, set: cr1);
999 if (ret < 0)
1000 return ret;
1001
1002 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
1003 test_bit(TRIGGER_NETDEV_LINK_10, &rules)) {
1004 cr2 |= RTL8211E_LEDCR2_LINK_10;
1005 }
1006
1007 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
1008 test_bit(TRIGGER_NETDEV_LINK_100, &rules)) {
1009 cr2 |= RTL8211E_LEDCR2_LINK_100;
1010 }
1011
1012 if (test_bit(TRIGGER_NETDEV_LINK, &rules) ||
1013 test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) {
1014 cr2 |= RTL8211E_LEDCR2_LINK_1000;
1015 }
1016
1017 cr2 <<= RTL8211E_LEDCR2_SHIFT * index;
1018 ret = rtl821x_modify_ext_page(phydev, RTL8211E_LEDCR_EXT_PAGE,
1019 RTL8211E_LEDCR2, mask: cr2mask, set: cr2);
1020
1021 return ret;
1022}
1023
1024static int rtl8211e_config_init(struct phy_device *phydev)
1025{
1026 u16 val;
1027
1028 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
1029 switch (phydev->interface) {
1030 case PHY_INTERFACE_MODE_RGMII:
1031 val = RTL8211E_CTRL_DELAY | 0;
1032 break;
1033 case PHY_INTERFACE_MODE_RGMII_ID:
1034 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
1035 break;
1036 case PHY_INTERFACE_MODE_RGMII_RXID:
1037 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
1038 break;
1039 case PHY_INTERFACE_MODE_RGMII_TXID:
1040 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
1041 break;
1042 default: /* the rest of the modes imply leaving delays as is. */
1043 return 0;
1044 }
1045
1046 /* According to a sample driver there is a 0x1c config register on the
1047 * 0xa4 extension page (0x7) layout. It can be used to disable/enable
1048 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
1049 * The configuration register definition:
1050 * 14 = reserved
1051 * 13 = Force Tx RX Delay controlled by bit12 bit11,
1052 * 12 = RX Delay, 11 = TX Delay
1053 * 10:0 = Test && debug settings reserved by realtek
1054 */
1055 return rtl821x_modify_ext_page(phydev, RTL8211E_RGMII_EXT_PAGE,
1056 RTL8211E_RGMII_DELAY,
1057 RTL8211E_DELAY_MASK, set: val);
1058}
1059
1060static int rtl8211b_suspend(struct phy_device *phydev)
1061{
1062 phy_write(phydev, MII_MMD_DATA, BIT(9));
1063
1064 return genphy_suspend(phydev);
1065}
1066
1067static int rtl8211b_resume(struct phy_device *phydev)
1068{
1069 phy_write(phydev, MII_MMD_DATA, val: 0);
1070
1071 return genphy_resume(phydev);
1072}
1073
1074static int rtl8366rb_config_init(struct phy_device *phydev)
1075{
1076 int ret;
1077
1078 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
1079 RTL8366RB_POWER_SAVE_ON);
1080 if (ret) {
1081 dev_err(&phydev->mdio.dev,
1082 "error enabling power management\n");
1083 }
1084
1085 return ret;
1086}
1087
1088/* get actual speed to cover the downshift case */
1089static void rtlgen_decode_physr(struct phy_device *phydev, int val)
1090{
1091 /* bit 3
1092 * 0: Half Duplex
1093 * 1: Full Duplex
1094 */
1095 if (val & RTL_VND2_PHYSR_DUPLEX)
1096 phydev->duplex = DUPLEX_FULL;
1097 else
1098 phydev->duplex = DUPLEX_HALF;
1099
1100 switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
1101 case 0x0000:
1102 phydev->speed = SPEED_10;
1103 break;
1104 case 0x0010:
1105 phydev->speed = SPEED_100;
1106 break;
1107 case 0x0020:
1108 phydev->speed = SPEED_1000;
1109 break;
1110 case 0x0200:
1111 phydev->speed = SPEED_10000;
1112 break;
1113 case 0x0210:
1114 phydev->speed = SPEED_2500;
1115 break;
1116 case 0x0220:
1117 phydev->speed = SPEED_5000;
1118 break;
1119 default:
1120 break;
1121 }
1122
1123 /* bit 11
1124 * 0: Slave Mode
1125 * 1: Master Mode
1126 */
1127 if (phydev->speed >= 1000) {
1128 if (val & RTL_VND2_PHYSR_MASTER)
1129 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1130 else
1131 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1132 } else {
1133 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
1134 }
1135}
1136
1137static int rtlgen_read_status(struct phy_device *phydev)
1138{
1139 int ret, val;
1140
1141 ret = genphy_read_status(phydev);
1142 if (ret < 0)
1143 return ret;
1144
1145 if (!phydev->link)
1146 return 0;
1147
1148 val = phy_read_paged(phydev, page: 0xa43, regnum: 0x12);
1149 if (val < 0)
1150 return val;
1151
1152 rtlgen_decode_physr(phydev, val);
1153
1154 return 0;
1155}
1156
1157static int rtlgen_read_vend2(struct phy_device *phydev, int regnum)
1158{
1159 return __mdiobus_c45_read(bus: phydev->mdio.bus, addr: 0, MDIO_MMD_VEND2, regnum);
1160}
1161
1162static int rtlgen_write_vend2(struct phy_device *phydev, int regnum, u16 val)
1163{
1164 return __mdiobus_c45_write(bus: phydev->mdio.bus, addr: 0, MDIO_MMD_VEND2, regnum,
1165 val);
1166}
1167
1168static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
1169{
1170 int ret;
1171
1172 if (devnum == MDIO_MMD_VEND2)
1173 ret = rtlgen_read_vend2(phydev, regnum);
1174 else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE)
1175 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE);
1176 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
1177 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV);
1178 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE)
1179 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE);
1180 else
1181 ret = -EOPNOTSUPP;
1182
1183 return ret;
1184}
1185
1186static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
1187 u16 val)
1188{
1189 int ret;
1190
1191 if (devnum == MDIO_MMD_VEND2)
1192 ret = rtlgen_write_vend2(phydev, regnum, val);
1193 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV)
1194 ret = rtlgen_write_vend2(phydev, regnum, RTL_MDIO_AN_EEE_ADV);
1195 else
1196 ret = -EOPNOTSUPP;
1197
1198 return ret;
1199}
1200
1201static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
1202{
1203 int ret = rtlgen_read_mmd(phydev, devnum, regnum);
1204
1205 if (ret != -EOPNOTSUPP)
1206 return ret;
1207
1208 if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2)
1209 ret = rtlgen_read_vend2(phydev, RTL_MDIO_PCS_EEE_ABLE2);
1210 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
1211 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_ADV2);
1212 else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2)
1213 ret = rtlgen_read_vend2(phydev, RTL_MDIO_AN_EEE_LPABLE2);
1214
1215 return ret;
1216}
1217
1218static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
1219 u16 val)
1220{
1221 int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
1222
1223 if (ret != -EOPNOTSUPP)
1224 return ret;
1225
1226 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2)
1227 ret = rtlgen_write_vend2(phydev, RTL_MDIO_AN_EEE_ADV2, val);
1228
1229 return ret;
1230}
1231
1232static int rtl822x_probe(struct phy_device *phydev)
1233{
1234 if (IS_ENABLED(CONFIG_REALTEK_PHY_HWMON) &&
1235 phydev->phy_id != RTL_GENERIC_PHYID)
1236 return rtl822x_hwmon_init(phydev);
1237
1238 return 0;
1239}
1240
1241static int rtl822x_set_serdes_option_mode(struct phy_device *phydev, bool gen1)
1242{
1243 bool has_2500, has_sgmii;
1244 u16 mode;
1245 int ret;
1246
1247 has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
1248 phydev->host_interfaces) ||
1249 phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
1250
1251 has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
1252 phydev->host_interfaces) ||
1253 phydev->interface == PHY_INTERFACE_MODE_SGMII;
1254
1255 /* fill in possible interfaces */
1256 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
1257 has_2500);
1258 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
1259 has_sgmii);
1260
1261 if (!has_2500 && !has_sgmii)
1262 return 0;
1263
1264 /* determine SerDes option mode */
1265 if (has_2500 && !has_sgmii) {
1266 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
1267 phydev->rate_matching = RATE_MATCH_PAUSE;
1268 } else {
1269 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
1270 phydev->rate_matching = RATE_MATCH_NONE;
1271 }
1272
1273 /* the following sequence with magic numbers sets up the SerDes
1274 * option mode
1275 */
1276
1277 if (!gen1) {
1278 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: 0x75f3, val: 0);
1279 if (ret < 0)
1280 return ret;
1281 }
1282
1283 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
1284 RTL822X_VND1_SERDES_OPTION,
1285 RTL822X_VND1_SERDES_OPTION_MODE_MASK,
1286 set: mode);
1287 if (gen1 || ret < 0)
1288 return ret;
1289
1290 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: 0x6a04, val: 0x0503);
1291 if (ret < 0)
1292 return ret;
1293
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: 0x6f10, val: 0xd455);
1295 if (ret < 0)
1296 return ret;
1297
1298 return phy_write_mmd(phydev, MDIO_MMD_VEND1, regnum: 0x6f11, val: 0x8020);
1299}
1300
1301static int rtl822x_config_init(struct phy_device *phydev)
1302{
1303 return rtl822x_set_serdes_option_mode(phydev, gen1: true);
1304}
1305
1306static int rtl822xb_config_init(struct phy_device *phydev)
1307{
1308 return rtl822x_set_serdes_option_mode(phydev, gen1: false);
1309}
1310
1311static int rtl822xb_get_rate_matching(struct phy_device *phydev,
1312 phy_interface_t iface)
1313{
1314 int val;
1315
1316 /* Only rate matching at 2500base-x */
1317 if (iface != PHY_INTERFACE_MODE_2500BASEX)
1318 return RATE_MATCH_NONE;
1319
1320 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
1321 if (val < 0)
1322 return val;
1323
1324 if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
1325 RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
1326 return RATE_MATCH_PAUSE;
1327
1328 /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
1329 return RATE_MATCH_NONE;
1330}
1331
1332static int rtl822x_get_features(struct phy_device *phydev)
1333{
1334 int val;
1335
1336 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_PMA_SPEED);
1337 if (val < 0)
1338 return val;
1339
1340 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1341 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
1342 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1343 phydev->supported, val & MDIO_PMA_SPEED_5G);
1344 linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1345 phydev->supported, val & MDIO_SPEED_10G);
1346
1347 return genphy_read_abilities(phydev);
1348}
1349
1350static int rtl822x_config_aneg(struct phy_device *phydev)
1351{
1352 int ret = 0;
1353
1354 if (phydev->autoneg == AUTONEG_ENABLE) {
1355 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(advertising: phydev->advertising);
1356
1357 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
1358 RTL_MDIO_AN_10GBT_CTRL,
1359 MDIO_AN_10GBT_CTRL_ADV2_5G |
1360 MDIO_AN_10GBT_CTRL_ADV5G, set: adv);
1361 if (ret < 0)
1362 return ret;
1363 }
1364
1365 return __genphy_config_aneg(phydev, changed: ret);
1366}
1367
1368static void rtl822xb_update_interface(struct phy_device *phydev)
1369{
1370 int val;
1371
1372 if (!phydev->link)
1373 return;
1374
1375 /* Change interface according to serdes mode */
1376 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
1377 if (val < 0)
1378 return;
1379
1380 switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
1381 case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
1382 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1383 break;
1384 case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
1385 phydev->interface = PHY_INTERFACE_MODE_SGMII;
1386 break;
1387 }
1388}
1389
1390static int rtl822x_read_status(struct phy_device *phydev)
1391{
1392 int lpadv, ret;
1393
1394 mii_10gbt_stat_mod_linkmode_lpa_t(advertising: phydev->lp_advertising, lpa: 0);
1395
1396 ret = rtlgen_read_status(phydev);
1397 if (ret < 0)
1398 return ret;
1399
1400 if (phydev->autoneg == AUTONEG_DISABLE ||
1401 !phydev->autoneg_complete)
1402 return 0;
1403
1404 lpadv = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_MDIO_AN_10GBT_STAT);
1405 if (lpadv < 0)
1406 return lpadv;
1407
1408 mii_10gbt_stat_mod_linkmode_lpa_t(advertising: phydev->lp_advertising, lpa: lpadv);
1409
1410 return 0;
1411}
1412
1413static int rtl822xb_read_status(struct phy_device *phydev)
1414{
1415 int ret;
1416
1417 ret = rtl822x_read_status(phydev);
1418 if (ret < 0)
1419 return ret;
1420
1421 rtl822xb_update_interface(phydev);
1422
1423 return 0;
1424}
1425
1426static int rtl822x_c45_get_features(struct phy_device *phydev)
1427{
1428 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
1429 phydev->supported);
1430
1431 return genphy_c45_pma_read_abilities(phydev);
1432}
1433
1434static int rtl822x_c45_config_aneg(struct phy_device *phydev)
1435{
1436 bool changed = false;
1437 int ret, val;
1438
1439 if (phydev->autoneg == AUTONEG_DISABLE)
1440 return genphy_c45_pma_setup_forced(phydev);
1441
1442 ret = genphy_c45_an_config_aneg(phydev);
1443 if (ret < 0)
1444 return ret;
1445 if (ret > 0)
1446 changed = true;
1447
1448 val = linkmode_adv_to_mii_ctrl1000_t(advertising: phydev->advertising);
1449
1450 /* Vendor register as C45 has no standardized support for 1000BaseT */
1451 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2,
1452 RTL822X_VND2_C22_REG(MII_CTRL1000),
1453 ADVERTISE_1000FULL, set: val);
1454 if (ret < 0)
1455 return ret;
1456 if (ret > 0)
1457 changed = true;
1458
1459 return genphy_c45_check_and_restart_aneg(phydev, restart: changed);
1460}
1461
1462static int rtl822x_c45_read_status(struct phy_device *phydev)
1463{
1464 int ret, val;
1465
1466 /* Vendor register as C45 has no standardized support for 1000BaseT */
1467 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) {
1468 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1469 RTL822X_VND2_C22_REG(MII_STAT1000));
1470 if (val < 0)
1471 return val;
1472 } else {
1473 val = 0;
1474 }
1475 mii_stat1000_mod_linkmode_lpa_t(advertising: phydev->lp_advertising, lpa: val);
1476
1477 ret = genphy_c45_read_status(phydev);
1478 if (ret < 0)
1479 return ret;
1480
1481 if (!phydev->link) {
1482 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1483 return 0;
1484 }
1485
1486 /* Read actual speed from vendor register. */
1487 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1488 if (val < 0)
1489 return val;
1490
1491 rtlgen_decode_physr(phydev, val);
1492
1493 return 0;
1494}
1495
1496static int rtl822x_c45_soft_reset(struct phy_device *phydev)
1497{
1498 int ret, val;
1499
1500 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
1501 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
1502 if (ret < 0)
1503 return ret;
1504
1505 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
1506 MDIO_CTRL1, val,
1507 !(val & MDIO_CTRL1_RESET),
1508 5000, 100000, true);
1509}
1510
1511static int rtl822xb_c45_read_status(struct phy_device *phydev)
1512{
1513 int ret;
1514
1515 ret = rtl822x_c45_read_status(phydev);
1516 if (ret < 0)
1517 return ret;
1518
1519 rtl822xb_update_interface(phydev);
1520
1521 return 0;
1522}
1523
1524static int rtl8224_cable_test_start(struct phy_device *phydev)
1525{
1526 u32 val;
1527 int ret;
1528
1529 /* disable auto-negotiation and force 1000/Full */
1530 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1531 RTL822X_VND2_C22_REG(MII_BMCR),
1532 BMCR_ANENABLE | BMCR_SPEED100 | BMCR_SPEED10,
1533 BMCR_SPEED1000 | BMCR_FULLDPLX);
1534 if (ret)
1535 return ret;
1536
1537 mdelay(500);
1538
1539 /* trigger cable test */
1540 val = RTL8224_MII_RTCT_ENABLE;
1541 val |= RTL8224_MII_RTCT_PAIR_A;
1542 val |= RTL8224_MII_RTCT_PAIR_B;
1543 val |= RTL8224_MII_RTCT_PAIR_C;
1544 val |= RTL8224_MII_RTCT_PAIR_D;
1545
1546 return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1547 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT),
1548 RTL8224_MII_RTCT_DONE, set: val);
1549}
1550
1551static int rtl8224_sram_read(struct phy_device *phydev, u32 reg)
1552{
1553 int ret;
1554
1555 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1556 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_ADDR),
1557 val: reg);
1558 if (ret)
1559 return ret;
1560
1561 return phy_read_mmd(phydev, MDIO_MMD_VEND2,
1562 RTL822X_VND2_C22_REG(RTL8224_MII_SRAM_DATA));
1563}
1564
1565static int rtl8224_pair_len_get(struct phy_device *phydev, u32 pair)
1566{
1567 int cable_len;
1568 u32 reg_len;
1569 int ret;
1570 u32 cm;
1571
1572 reg_len = RTL8224_SRAM_RTCT_LEN(pair);
1573
1574 ret = rtl8224_sram_read(phydev, reg: reg_len);
1575 if (ret < 0)
1576 return ret;
1577
1578 cable_len = ret & 0xff00;
1579
1580 ret = rtl8224_sram_read(phydev, reg: reg_len + 1);
1581 if (ret < 0)
1582 return ret;
1583
1584 cable_len |= (ret & 0xff00) >> 8;
1585
1586 cable_len -= 620;
1587 cable_len = max(cable_len, 0);
1588
1589 cm = cable_len * 100 / 78;
1590
1591 return cm;
1592}
1593
1594static int rtl8224_cable_test_result_trans(u32 result)
1595{
1596 if (!(result & RTL8224_SRAM_RTCT_FAULT_DONE))
1597 return -EBUSY;
1598
1599 if (result & RTL8224_SRAM_RTCT_FAULT_OK)
1600 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1601
1602 if (result & RTL8224_SRAM_RTCT_FAULT_OPEN)
1603 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1604
1605 if (result & RTL8224_SRAM_RTCT_FAULT_SAME_SHORT)
1606 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1607
1608 if (result & RTL8224_SRAM_RTCT_FAULT_BUSY)
1609 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1610
1611 if (result & RTL8224_SRAM_RTCT_FAULT_CROSS_SHORT)
1612 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
1613
1614 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1615}
1616
1617static int rtl8224_cable_test_report_pair(struct phy_device *phydev, unsigned int pair)
1618{
1619 int fault_rslt;
1620 int ret;
1621
1622 ret = rtl8224_sram_read(phydev, RTL8224_SRAM_RTCT_FAULT(pair));
1623 if (ret < 0)
1624 return ret;
1625
1626 fault_rslt = rtl8224_cable_test_result_trans(result: ret);
1627 if (fault_rslt < 0)
1628 return 0;
1629
1630 ret = ethnl_cable_test_result(phydev, pair, result: fault_rslt);
1631 if (ret < 0)
1632 return ret;
1633
1634 switch (fault_rslt) {
1635 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
1636 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
1637 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
1638 ret = rtl8224_pair_len_get(phydev, pair);
1639 if (ret < 0)
1640 return ret;
1641
1642 return ethnl_cable_test_fault_length(phydev, pair, cm: ret);
1643 default:
1644 return 0;
1645 }
1646}
1647
1648static int rtl8224_cable_test_report(struct phy_device *phydev, bool *finished)
1649{
1650 unsigned int pair;
1651 int ret;
1652
1653 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) {
1654 ret = rtl8224_cable_test_report_pair(phydev, pair);
1655 if (ret == -EBUSY) {
1656 *finished = false;
1657 return 0;
1658 }
1659
1660 if (ret < 0)
1661 return ret;
1662 }
1663
1664 return 0;
1665}
1666
1667static int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished)
1668{
1669 int ret;
1670
1671 *finished = false;
1672
1673 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1674 RTL822X_VND2_C22_REG(RTL8224_MII_RTCT));
1675 if (ret < 0)
1676 return ret;
1677
1678 if (!(ret & RTL8224_MII_RTCT_DONE))
1679 return 0;
1680
1681 *finished = true;
1682
1683 return rtl8224_cable_test_report(phydev, finished);
1684}
1685
1686static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1687{
1688 int val;
1689
1690 phy_write(phydev, RTL821x_PAGE_SELECT, val: 0xa61);
1691 val = phy_read(phydev, regnum: 0x13);
1692 phy_write(phydev, RTL821x_PAGE_SELECT, val: 0);
1693
1694 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1695}
1696
1697/* On internal PHY's MMD reads over C22 always return 0.
1698 * Check a MMD register which is known to be non-zero.
1699 */
1700static bool rtlgen_supports_mmd(struct phy_device *phydev)
1701{
1702 int val;
1703
1704 phy_lock_mdio_bus(phydev);
1705 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1706 __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1707 __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1708 val = __phy_read(phydev, MII_MMD_DATA);
1709 phy_unlock_mdio_bus(phydev);
1710
1711 return val > 0;
1712}
1713
1714static int rtlgen_match_phy_device(struct phy_device *phydev,
1715 const struct phy_driver *phydrv)
1716{
1717 return phydev->phy_id == RTL_GENERIC_PHYID &&
1718 !rtlgen_supports_2_5gbps(phydev);
1719}
1720
1721static int rtl8226_match_phy_device(struct phy_device *phydev,
1722 const struct phy_driver *phydrv)
1723{
1724 return phydev->phy_id == RTL_GENERIC_PHYID &&
1725 rtlgen_supports_2_5gbps(phydev) &&
1726 rtlgen_supports_mmd(phydev);
1727}
1728
1729static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1730 bool is_c45)
1731{
1732 if (phydev->is_c45)
1733 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1734 else
1735 return !is_c45 && (id == phydev->phy_id);
1736}
1737
1738static int rtl8221b_match_phy_device(struct phy_device *phydev,
1739 const struct phy_driver *phydrv)
1740{
1741 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1742}
1743
1744static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev,
1745 const struct phy_driver *phydrv)
1746{
1747 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, is_c45: false);
1748}
1749
1750static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev,
1751 const struct phy_driver *phydrv)
1752{
1753 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, is_c45: true);
1754}
1755
1756static int rtl8221b_vm_cg_c22_match_phy_device(struct phy_device *phydev,
1757 const struct phy_driver *phydrv)
1758{
1759 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, is_c45: false);
1760}
1761
1762static int rtl8221b_vm_cg_c45_match_phy_device(struct phy_device *phydev,
1763 const struct phy_driver *phydrv)
1764{
1765 return rtlgen_is_c45_match(phydev, RTL_8221B_VM_CG, is_c45: true);
1766}
1767
1768static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev,
1769 const struct phy_driver *phydrv)
1770{
1771 if (phydev->is_c45)
1772 return false;
1773
1774 switch (phydev->phy_id) {
1775 case RTL_GENERIC_PHYID:
1776 case RTL_8221B:
1777 case RTL_8251B:
1778 case RTL_8261C:
1779 case 0x001cc841:
1780 break;
1781 default:
1782 return false;
1783 }
1784
1785 return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1786}
1787
1788static int rtl8251b_c45_match_phy_device(struct phy_device *phydev,
1789 const struct phy_driver *phydrv)
1790{
1791 return rtlgen_is_c45_match(phydev, RTL_8251B, is_c45: true);
1792}
1793
1794static int rtlgen_resume(struct phy_device *phydev)
1795{
1796 int ret = genphy_resume(phydev);
1797
1798 /* Internal PHY's from RTL8168h up may not be instantly ready */
1799 msleep(msecs: 20);
1800
1801 return ret;
1802}
1803
1804static int rtlgen_c45_resume(struct phy_device *phydev)
1805{
1806 int ret = genphy_c45_pma_resume(phydev);
1807
1808 msleep(msecs: 20);
1809
1810 return ret;
1811}
1812
1813static int rtl9000a_config_init(struct phy_device *phydev)
1814{
1815 phydev->autoneg = AUTONEG_DISABLE;
1816 phydev->speed = SPEED_100;
1817 phydev->duplex = DUPLEX_FULL;
1818
1819 return 0;
1820}
1821
1822static int rtl9000a_config_aneg(struct phy_device *phydev)
1823{
1824 int ret;
1825 u16 ctl = 0;
1826
1827 switch (phydev->master_slave_set) {
1828 case MASTER_SLAVE_CFG_MASTER_FORCE:
1829 ctl |= CTL1000_AS_MASTER;
1830 break;
1831 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1832 break;
1833 case MASTER_SLAVE_CFG_UNKNOWN:
1834 case MASTER_SLAVE_CFG_UNSUPPORTED:
1835 return 0;
1836 default:
1837 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1838 return -EOPNOTSUPP;
1839 }
1840
1841 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, set: ctl);
1842 if (ret == 1)
1843 ret = genphy_soft_reset(phydev);
1844
1845 return ret;
1846}
1847
1848static int rtl9000a_read_status(struct phy_device *phydev)
1849{
1850 int ret;
1851
1852 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1853 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1854
1855 ret = genphy_update_link(phydev);
1856 if (ret)
1857 return ret;
1858
1859 ret = phy_read(phydev, MII_CTRL1000);
1860 if (ret < 0)
1861 return ret;
1862 if (ret & CTL1000_AS_MASTER)
1863 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1864 else
1865 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1866
1867 ret = phy_read(phydev, MII_STAT1000);
1868 if (ret < 0)
1869 return ret;
1870 if (ret & LPA_1000MSRES)
1871 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1872 else
1873 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1874
1875 return 0;
1876}
1877
1878static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1879{
1880 int err;
1881
1882 err = phy_read(phydev, RTL8211F_INSR);
1883
1884 return (err < 0) ? err : 0;
1885}
1886
1887static int rtl9000a_config_intr(struct phy_device *phydev)
1888{
1889 u16 val;
1890 int err;
1891
1892 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1893 err = rtl9000a_ack_interrupt(phydev);
1894 if (err)
1895 return err;
1896
1897 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1898 err = phy_write_paged(phydev, page: 0xa42, RTL9000A_GINMR, val);
1899 } else {
1900 val = ~0;
1901 err = phy_write_paged(phydev, page: 0xa42, RTL9000A_GINMR, val);
1902 if (err)
1903 return err;
1904
1905 err = rtl9000a_ack_interrupt(phydev);
1906 }
1907
1908 return phy_write_paged(phydev, page: 0xa42, RTL9000A_GINMR, val);
1909}
1910
1911static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1912{
1913 int irq_status;
1914
1915 irq_status = phy_read(phydev, RTL8211F_INSR);
1916 if (irq_status < 0) {
1917 phy_error(phydev);
1918 return IRQ_NONE;
1919 }
1920
1921 if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1922 return IRQ_NONE;
1923
1924 phy_trigger_machine(phydev);
1925
1926 return IRQ_HANDLED;
1927}
1928
1929static int rtl8221b_ack_interrupt(struct phy_device *phydev)
1930{
1931 int err;
1932
1933 err = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INSR);
1934
1935 return (err < 0) ? err : 0;
1936}
1937
1938static int rtl8221b_config_intr(struct phy_device *phydev)
1939{
1940 int err;
1941
1942 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1943 err = rtl8221b_ack_interrupt(phydev);
1944 if (err)
1945 return err;
1946
1947 err = phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_VND2_INER,
1948 RTL8221B_VND2_INER_LINK_STATUS);
1949 } else {
1950 err = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1951 RTL8221B_VND2_INER, val: 0);
1952 if (err)
1953 return err;
1954
1955 err = rtl8221b_ack_interrupt(phydev);
1956 }
1957
1958 return err;
1959}
1960
1961static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev)
1962{
1963 int err;
1964
1965 err = rtl8221b_ack_interrupt(phydev);
1966 if (err) {
1967 phy_error(phydev);
1968 return IRQ_NONE;
1969 }
1970
1971 phy_trigger_machine(phydev);
1972
1973 return IRQ_HANDLED;
1974}
1975
1976static struct phy_driver realtek_drvs[] = {
1977 {
1978 PHY_ID_MATCH_EXACT(0x00008201),
1979 .name = "RTL8201CP Ethernet",
1980 .read_page = rtl821x_read_page,
1981 .write_page = rtl821x_write_page,
1982 }, {
1983 PHY_ID_MATCH_EXACT(0x001cc816),
1984 .name = "RTL8201F Fast Ethernet",
1985 .config_intr = &rtl8201_config_intr,
1986 .handle_interrupt = rtl8201_handle_interrupt,
1987 .suspend = genphy_suspend,
1988 .resume = genphy_resume,
1989 .read_page = rtl821x_read_page,
1990 .write_page = rtl821x_write_page,
1991 }, {
1992 PHY_ID_MATCH_MODEL(0x001cc880),
1993 .name = "RTL8208 Fast Ethernet",
1994 .read_mmd = genphy_read_mmd_unsupported,
1995 .write_mmd = genphy_write_mmd_unsupported,
1996 .suspend = genphy_suspend,
1997 .resume = genphy_resume,
1998 .read_page = rtl821x_read_page,
1999 .write_page = rtl821x_write_page,
2000 }, {
2001 PHY_ID_MATCH_EXACT(0x001cc910),
2002 .name = "RTL8211 Gigabit Ethernet",
2003 .config_aneg = rtl8211_config_aneg,
2004 .read_mmd = &genphy_read_mmd_unsupported,
2005 .write_mmd = &genphy_write_mmd_unsupported,
2006 .read_page = rtl821x_read_page,
2007 .write_page = rtl821x_write_page,
2008 }, {
2009 PHY_ID_MATCH_EXACT(0x001cc912),
2010 .name = "RTL8211B Gigabit Ethernet",
2011 .config_intr = &rtl8211b_config_intr,
2012 .handle_interrupt = rtl821x_handle_interrupt,
2013 .read_mmd = &genphy_read_mmd_unsupported,
2014 .write_mmd = &genphy_write_mmd_unsupported,
2015 .suspend = rtl8211b_suspend,
2016 .resume = rtl8211b_resume,
2017 .read_page = rtl821x_read_page,
2018 .write_page = rtl821x_write_page,
2019 }, {
2020 PHY_ID_MATCH_EXACT(0x001cc913),
2021 .name = "RTL8211C Gigabit Ethernet",
2022 .config_init = rtl8211c_config_init,
2023 .read_mmd = &genphy_read_mmd_unsupported,
2024 .write_mmd = &genphy_write_mmd_unsupported,
2025 .read_page = rtl821x_read_page,
2026 .write_page = rtl821x_write_page,
2027 }, {
2028 PHY_ID_MATCH_EXACT(0x001cc914),
2029 .name = "RTL8211DN Gigabit Ethernet",
2030 .config_intr = rtl8211e_config_intr,
2031 .handle_interrupt = rtl821x_handle_interrupt,
2032 .suspend = genphy_suspend,
2033 .resume = genphy_resume,
2034 .read_page = rtl821x_read_page,
2035 .write_page = rtl821x_write_page,
2036 }, {
2037 PHY_ID_MATCH_EXACT(0x001cc915),
2038 .name = "RTL8211E Gigabit Ethernet",
2039 .config_init = &rtl8211e_config_init,
2040 .config_intr = &rtl8211e_config_intr,
2041 .handle_interrupt = rtl821x_handle_interrupt,
2042 .suspend = genphy_suspend,
2043 .resume = genphy_resume,
2044 .read_page = rtl821x_read_page,
2045 .write_page = rtl821x_write_page,
2046 .led_hw_is_supported = rtl8211x_led_hw_is_supported,
2047 .led_hw_control_get = rtl8211e_led_hw_control_get,
2048 .led_hw_control_set = rtl8211e_led_hw_control_set,
2049 }, {
2050 PHY_ID_MATCH_EXACT(0x001cc916),
2051 .name = "RTL8211F Gigabit Ethernet",
2052 .probe = rtl8211f_probe,
2053 .config_init = &rtl8211f_config_init,
2054 .read_status = rtlgen_read_status,
2055 .config_intr = &rtl8211f_config_intr,
2056 .handle_interrupt = rtl8211f_handle_interrupt,
2057 .set_wol = rtl8211f_set_wol,
2058 .get_wol = rtl8211f_get_wol,
2059 .suspend = rtl8211f_suspend,
2060 .resume = rtl8211f_resume,
2061 .read_page = rtl821x_read_page,
2062 .write_page = rtl821x_write_page,
2063 .flags = PHY_ALWAYS_CALL_SUSPEND,
2064 .led_hw_is_supported = rtl8211x_led_hw_is_supported,
2065 .led_hw_control_get = rtl8211f_led_hw_control_get,
2066 .led_hw_control_set = rtl8211f_led_hw_control_set,
2067 }, {
2068 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
2069 .name = "RTL8211F-VD Gigabit Ethernet",
2070 .probe = rtl821x_probe,
2071 .config_init = &rtl8211f_config_init,
2072 .read_status = rtlgen_read_status,
2073 .config_intr = &rtl8211f_config_intr,
2074 .handle_interrupt = rtl8211f_handle_interrupt,
2075 .suspend = rtl821x_suspend,
2076 .resume = rtl821x_resume,
2077 .read_page = rtl821x_read_page,
2078 .write_page = rtl821x_write_page,
2079 .flags = PHY_ALWAYS_CALL_SUSPEND,
2080 }, {
2081 .name = "Generic FE-GE Realtek PHY",
2082 .match_phy_device = rtlgen_match_phy_device,
2083 .read_status = rtlgen_read_status,
2084 .suspend = genphy_suspend,
2085 .resume = rtlgen_resume,
2086 .read_page = rtl821x_read_page,
2087 .write_page = rtl821x_write_page,
2088 .read_mmd = rtlgen_read_mmd,
2089 .write_mmd = rtlgen_write_mmd,
2090 }, {
2091 .name = "RTL8226 2.5Gbps PHY",
2092 .match_phy_device = rtl8226_match_phy_device,
2093 .get_features = rtl822x_get_features,
2094 .config_aneg = rtl822x_config_aneg,
2095 .read_status = rtl822x_read_status,
2096 .suspend = genphy_suspend,
2097 .resume = rtlgen_resume,
2098 .read_page = rtl821x_read_page,
2099 .write_page = rtl821x_write_page,
2100 }, {
2101 .match_phy_device = rtl8221b_match_phy_device,
2102 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
2103 .get_features = rtl822x_get_features,
2104 .config_aneg = rtl822x_config_aneg,
2105 .config_init = rtl822xb_config_init,
2106 .get_rate_matching = rtl822xb_get_rate_matching,
2107 .read_status = rtl822xb_read_status,
2108 .suspend = genphy_suspend,
2109 .resume = rtlgen_resume,
2110 .read_page = rtl821x_read_page,
2111 .write_page = rtl821x_write_page,
2112 }, {
2113 PHY_ID_MATCH_EXACT(0x001cc838),
2114 .name = "RTL8226-CG 2.5Gbps PHY",
2115 .soft_reset = rtl822x_c45_soft_reset,
2116 .get_features = rtl822x_c45_get_features,
2117 .config_aneg = rtl822x_c45_config_aneg,
2118 .config_init = rtl822x_config_init,
2119 .read_status = rtl822xb_c45_read_status,
2120 .suspend = genphy_c45_pma_suspend,
2121 .resume = rtlgen_c45_resume,
2122 }, {
2123 PHY_ID_MATCH_EXACT(0x001cc848),
2124 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
2125 .get_features = rtl822x_get_features,
2126 .config_aneg = rtl822x_config_aneg,
2127 .config_init = rtl822xb_config_init,
2128 .get_rate_matching = rtl822xb_get_rate_matching,
2129 .read_status = rtl822xb_read_status,
2130 .suspend = genphy_suspend,
2131 .resume = rtlgen_resume,
2132 .read_page = rtl821x_read_page,
2133 .write_page = rtl821x_write_page,
2134 }, {
2135 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
2136 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
2137 .probe = rtl822x_probe,
2138 .get_features = rtl822x_get_features,
2139 .config_aneg = rtl822x_config_aneg,
2140 .config_init = rtl822xb_config_init,
2141 .get_rate_matching = rtl822xb_get_rate_matching,
2142 .read_status = rtl822xb_read_status,
2143 .suspend = genphy_suspend,
2144 .resume = rtlgen_resume,
2145 .read_page = rtl821x_read_page,
2146 .write_page = rtl821x_write_page,
2147 }, {
2148 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
2149 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
2150 .config_intr = rtl8221b_config_intr,
2151 .handle_interrupt = rtl8221b_handle_interrupt,
2152 .probe = rtl822x_probe,
2153 .config_init = rtl822xb_config_init,
2154 .get_rate_matching = rtl822xb_get_rate_matching,
2155 .get_features = rtl822x_c45_get_features,
2156 .config_aneg = rtl822x_c45_config_aneg,
2157 .read_status = rtl822xb_c45_read_status,
2158 .suspend = genphy_c45_pma_suspend,
2159 .resume = rtlgen_c45_resume,
2160 }, {
2161 .match_phy_device = rtl8221b_vm_cg_c22_match_phy_device,
2162 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
2163 .probe = rtl822x_probe,
2164 .get_features = rtl822x_get_features,
2165 .config_aneg = rtl822x_config_aneg,
2166 .config_init = rtl822xb_config_init,
2167 .get_rate_matching = rtl822xb_get_rate_matching,
2168 .read_status = rtl822xb_read_status,
2169 .suspend = genphy_suspend,
2170 .resume = rtlgen_resume,
2171 .read_page = rtl821x_read_page,
2172 .write_page = rtl821x_write_page,
2173 }, {
2174 .match_phy_device = rtl8221b_vm_cg_c45_match_phy_device,
2175 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C45)",
2176 .config_intr = rtl8221b_config_intr,
2177 .handle_interrupt = rtl8221b_handle_interrupt,
2178 .probe = rtl822x_probe,
2179 .config_init = rtl822xb_config_init,
2180 .get_rate_matching = rtl822xb_get_rate_matching,
2181 .get_features = rtl822x_c45_get_features,
2182 .config_aneg = rtl822x_c45_config_aneg,
2183 .read_status = rtl822xb_c45_read_status,
2184 .suspend = genphy_c45_pma_suspend,
2185 .resume = rtlgen_c45_resume,
2186 }, {
2187 .match_phy_device = rtl8251b_c45_match_phy_device,
2188 .name = "RTL8251B 5Gbps PHY",
2189 .probe = rtl822x_probe,
2190 .get_features = rtl822x_get_features,
2191 .config_aneg = rtl822x_config_aneg,
2192 .read_status = rtl822x_read_status,
2193 .suspend = genphy_suspend,
2194 .resume = rtlgen_resume,
2195 .read_page = rtl821x_read_page,
2196 .write_page = rtl821x_write_page,
2197 }, {
2198 .match_phy_device = rtl_internal_nbaset_match_phy_device,
2199 .name = "Realtek Internal NBASE-T PHY",
2200 .flags = PHY_IS_INTERNAL,
2201 .probe = rtl822x_probe,
2202 .get_features = rtl822x_get_features,
2203 .config_aneg = rtl822x_config_aneg,
2204 .read_status = rtl822x_read_status,
2205 .suspend = genphy_suspend,
2206 .resume = rtlgen_resume,
2207 .read_page = rtl821x_read_page,
2208 .write_page = rtl821x_write_page,
2209 .read_mmd = rtl822x_read_mmd,
2210 .write_mmd = rtl822x_write_mmd,
2211 }, {
2212 PHY_ID_MATCH_EXACT(0x001ccad0),
2213 .name = "RTL8224 2.5Gbps PHY",
2214 .flags = PHY_POLL_CABLE_TEST,
2215 .get_features = rtl822x_c45_get_features,
2216 .config_aneg = rtl822x_c45_config_aneg,
2217 .read_status = rtl822x_c45_read_status,
2218 .suspend = genphy_c45_pma_suspend,
2219 .resume = rtlgen_c45_resume,
2220 .cable_test_start = rtl8224_cable_test_start,
2221 .cable_test_get_status = rtl8224_cable_test_get_status,
2222 }, {
2223 PHY_ID_MATCH_EXACT(0x001cc961),
2224 .name = "RTL8366RB Gigabit Ethernet",
2225 .config_init = &rtl8366rb_config_init,
2226 /* These interrupts are handled by the irq controller
2227 * embedded inside the RTL8366RB, they get unmasked when the
2228 * irq is requested and ACKed by reading the status register,
2229 * which is done by the irqchip code.
2230 */
2231 .config_intr = genphy_no_config_intr,
2232 .handle_interrupt = genphy_handle_interrupt_no_ack,
2233 .suspend = genphy_suspend,
2234 .resume = genphy_resume,
2235 }, {
2236 PHY_ID_MATCH_EXACT(0x001ccb00),
2237 .name = "RTL9000AA_RTL9000AN Ethernet",
2238 .features = PHY_BASIC_T1_FEATURES,
2239 .config_init = rtl9000a_config_init,
2240 .config_aneg = rtl9000a_config_aneg,
2241 .read_status = rtl9000a_read_status,
2242 .config_intr = rtl9000a_config_intr,
2243 .handle_interrupt = rtl9000a_handle_interrupt,
2244 .suspend = genphy_suspend,
2245 .resume = genphy_resume,
2246 .read_page = rtl821x_read_page,
2247 .write_page = rtl821x_write_page,
2248 }, {
2249 PHY_ID_MATCH_EXACT(0x001cc942),
2250 .name = "RTL8365MB-VC Gigabit Ethernet",
2251 /* Interrupt handling analogous to RTL8366RB */
2252 .config_intr = genphy_no_config_intr,
2253 .handle_interrupt = genphy_handle_interrupt_no_ack,
2254 .suspend = genphy_suspend,
2255 .resume = genphy_resume,
2256 }, {
2257 PHY_ID_MATCH_EXACT(0x001cc960),
2258 .name = "RTL8366S Gigabit Ethernet",
2259 .suspend = genphy_suspend,
2260 .resume = genphy_resume,
2261 .read_mmd = genphy_read_mmd_unsupported,
2262 .write_mmd = genphy_write_mmd_unsupported,
2263 },
2264};
2265
2266module_phy_driver(realtek_drvs);
2267
2268static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
2269 { PHY_ID_MATCH_VENDOR(0x001cc800) },
2270 { }
2271};
2272
2273MODULE_DEVICE_TABLE(mdio, realtek_tbl);
2274

source code of linux/drivers/net/phy/realtek/realtek_main.c