1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright Altera Corporation (C) 2013-2015. All rights reserved |
4 | * |
5 | * Author: Ley Foon Tan <lftan@altera.com> |
6 | * Description: Altera PCIe host controller driver |
7 | */ |
8 | |
9 | #include <linux/delay.h> |
10 | #include <linux/interrupt.h> |
11 | #include <linux/irqchip/chained_irq.h> |
12 | #include <linux/irqdomain.h> |
13 | #include <linux/init.h> |
14 | #include <linux/module.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_pci.h> |
17 | #include <linux/pci.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> |
20 | |
21 | #include "../pci.h" |
22 | |
23 | #define RP_TX_REG0 0x2000 |
24 | #define RP_TX_REG1 0x2004 |
25 | #define RP_TX_CNTRL 0x2008 |
26 | #define RP_TX_EOP 0x2 |
27 | #define RP_TX_SOP 0x1 |
28 | #define RP_RXCPL_STATUS 0x2010 |
29 | #define RP_RXCPL_EOP 0x2 |
30 | #define RP_RXCPL_SOP 0x1 |
31 | #define RP_RXCPL_REG0 0x2014 |
32 | #define RP_RXCPL_REG1 0x2018 |
33 | #define P2A_INT_STATUS 0x3060 |
34 | #define P2A_INT_STS_ALL 0xf |
35 | #define P2A_INT_ENABLE 0x3070 |
36 | #define P2A_INT_ENA_ALL 0xf |
37 | #define RP_LTSSM 0x3c64 |
38 | #define RP_LTSSM_MASK 0x1f |
39 | #define LTSSM_L0 0xf |
40 | |
41 | #define S10_RP_TX_CNTRL 0x2004 |
42 | #define S10_RP_RXCPL_REG 0x2008 |
43 | #define S10_RP_RXCPL_STATUS 0x200C |
44 | #define S10_RP_CFG_ADDR(pcie, reg) \ |
45 | (((pcie)->hip_base) + (reg) + (1 << 20)) |
46 | #define S10_RP_SECONDARY(pcie) \ |
47 | readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) |
48 | |
49 | /* TLP configuration type 0 and 1 */ |
50 | #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ |
51 | #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ |
52 | #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ |
53 | #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ |
54 | #define TLP_PAYLOAD_SIZE 0x01 |
55 | #define TLP_READ_TAG 0x1d |
56 | #define TLP_WRITE_TAG 0x10 |
57 | #define RP_DEVFN 0 |
58 | #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn)) |
59 | #define TLP_CFG_DW0(pcie, cfg) \ |
60 | (((cfg) << 24) | \ |
61 | TLP_PAYLOAD_SIZE) |
62 | #define TLP_CFG_DW1(pcie, tag, be) \ |
63 | (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be)) |
64 | #define TLP_CFG_DW2(bus, devfn, offset) \ |
65 | (((bus) << 24) | ((devfn) << 16) | (offset)) |
66 | #define TLP_COMP_STATUS(s) (((s) >> 13) & 7) |
67 | #define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) |
68 | #define TLP_HDR_SIZE 3 |
69 | #define TLP_LOOP 500 |
70 | |
71 | #define LINK_UP_TIMEOUT HZ |
72 | #define LINK_RETRAIN_TIMEOUT HZ |
73 | |
74 | #define DWORD_MASK 3 |
75 | |
76 | #define S10_TLP_FMTTYPE_CFGRD0 0x05 |
77 | #define S10_TLP_FMTTYPE_CFGRD1 0x04 |
78 | #define S10_TLP_FMTTYPE_CFGWR0 0x45 |
79 | #define S10_TLP_FMTTYPE_CFGWR1 0x44 |
80 | |
81 | enum altera_pcie_version { |
82 | ALTERA_PCIE_V1 = 0, |
83 | ALTERA_PCIE_V2, |
84 | }; |
85 | |
86 | struct altera_pcie { |
87 | struct platform_device *pdev; |
88 | void __iomem *cra_base; |
89 | void __iomem *hip_base; |
90 | int irq; |
91 | u8 root_bus_nr; |
92 | struct irq_domain *irq_domain; |
93 | struct resource bus_range; |
94 | const struct altera_pcie_data *pcie_data; |
95 | }; |
96 | |
97 | struct altera_pcie_ops { |
98 | int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value); |
99 | void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *, |
100 | u32 data, bool align); |
101 | bool (*get_link_status)(struct altera_pcie *pcie); |
102 | int (*rp_read_cfg)(struct altera_pcie *pcie, int where, |
103 | int size, u32 *value); |
104 | int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno, |
105 | int where, int size, u32 value); |
106 | }; |
107 | |
108 | struct altera_pcie_data { |
109 | const struct altera_pcie_ops *ops; |
110 | enum altera_pcie_version version; |
111 | u32 cap_offset; /* PCIe capability structure register offset */ |
112 | u32 cfgrd0; |
113 | u32 cfgrd1; |
114 | u32 cfgwr0; |
115 | u32 cfgwr1; |
116 | }; |
117 | |
118 | struct tlp_rp_regpair_t { |
119 | u32 ctrl; |
120 | u32 reg0; |
121 | u32 reg1; |
122 | }; |
123 | |
124 | static inline void cra_writel(struct altera_pcie *pcie, const u32 value, |
125 | const u32 reg) |
126 | { |
127 | writel_relaxed(value, pcie->cra_base + reg); |
128 | } |
129 | |
130 | static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) |
131 | { |
132 | return readl_relaxed(pcie->cra_base + reg); |
133 | } |
134 | |
135 | static bool altera_pcie_link_up(struct altera_pcie *pcie) |
136 | { |
137 | return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0); |
138 | } |
139 | |
140 | static bool s10_altera_pcie_link_up(struct altera_pcie *pcie) |
141 | { |
142 | void __iomem *addr = S10_RP_CFG_ADDR(pcie, |
143 | pcie->pcie_data->cap_offset + |
144 | PCI_EXP_LNKSTA); |
145 | |
146 | return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA); |
147 | } |
148 | |
149 | /* |
150 | * Altera PCIe port uses BAR0 of RC's configuration space as the translation |
151 | * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space |
152 | * using these registers, so it can be reached by DMA from EP devices. |
153 | * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt |
154 | * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge |
155 | * should be hidden during enumeration to avoid the sizing and resource |
156 | * allocation by PCIe core. |
157 | */ |
158 | static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, |
159 | int offset) |
160 | { |
161 | if (pci_is_root_bus(pbus: bus) && (devfn == 0) && |
162 | (offset == PCI_BASE_ADDRESS_0)) |
163 | return true; |
164 | |
165 | return false; |
166 | } |
167 | |
168 | static void tlp_write_tx(struct altera_pcie *pcie, |
169 | struct tlp_rp_regpair_t *tlp_rp_regdata) |
170 | { |
171 | cra_writel(pcie, value: tlp_rp_regdata->reg0, RP_TX_REG0); |
172 | cra_writel(pcie, value: tlp_rp_regdata->reg1, RP_TX_REG1); |
173 | cra_writel(pcie, value: tlp_rp_regdata->ctrl, RP_TX_CNTRL); |
174 | } |
175 | |
176 | static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl) |
177 | { |
178 | cra_writel(pcie, value: reg0, RP_TX_REG0); |
179 | cra_writel(pcie, value: ctrl, S10_RP_TX_CNTRL); |
180 | } |
181 | |
182 | static bool altera_pcie_valid_device(struct altera_pcie *pcie, |
183 | struct pci_bus *bus, int dev) |
184 | { |
185 | /* If there is no link, then there is no device */ |
186 | if (bus->number != pcie->root_bus_nr) { |
187 | if (!pcie->pcie_data->ops->get_link_status(pcie)) |
188 | return false; |
189 | } |
190 | |
191 | /* access only one slot on each root port */ |
192 | if (bus->number == pcie->root_bus_nr && dev > 0) |
193 | return false; |
194 | |
195 | return true; |
196 | } |
197 | |
198 | static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) |
199 | { |
200 | int i; |
201 | bool sop = false; |
202 | u32 ctrl; |
203 | u32 reg0, reg1; |
204 | u32 comp_status = 1; |
205 | |
206 | /* |
207 | * Minimum 2 loops to read TLP headers and 1 loop to read data |
208 | * payload. |
209 | */ |
210 | for (i = 0; i < TLP_LOOP; i++) { |
211 | ctrl = cra_readl(pcie, RP_RXCPL_STATUS); |
212 | if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { |
213 | reg0 = cra_readl(pcie, RP_RXCPL_REG0); |
214 | reg1 = cra_readl(pcie, RP_RXCPL_REG1); |
215 | |
216 | if (ctrl & RP_RXCPL_SOP) { |
217 | sop = true; |
218 | comp_status = TLP_COMP_STATUS(reg1); |
219 | } |
220 | |
221 | if (ctrl & RP_RXCPL_EOP) { |
222 | if (comp_status) |
223 | return PCIBIOS_DEVICE_NOT_FOUND; |
224 | |
225 | if (value) |
226 | *value = reg0; |
227 | |
228 | return PCIBIOS_SUCCESSFUL; |
229 | } |
230 | } |
231 | udelay(5); |
232 | } |
233 | |
234 | return PCIBIOS_DEVICE_NOT_FOUND; |
235 | } |
236 | |
237 | static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value) |
238 | { |
239 | u32 ctrl; |
240 | u32 comp_status; |
241 | u32 dw[4]; |
242 | u32 count; |
243 | struct device *dev = &pcie->pdev->dev; |
244 | |
245 | for (count = 0; count < TLP_LOOP; count++) { |
246 | ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); |
247 | if (ctrl & RP_RXCPL_SOP) { |
248 | /* Read first DW */ |
249 | dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG); |
250 | break; |
251 | } |
252 | |
253 | udelay(5); |
254 | } |
255 | |
256 | /* SOP detection failed, return error */ |
257 | if (count == TLP_LOOP) |
258 | return PCIBIOS_DEVICE_NOT_FOUND; |
259 | |
260 | count = 1; |
261 | |
262 | /* Poll for EOP */ |
263 | while (count < ARRAY_SIZE(dw)) { |
264 | ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); |
265 | dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG); |
266 | if (ctrl & RP_RXCPL_EOP) { |
267 | comp_status = TLP_COMP_STATUS(dw[1]); |
268 | if (comp_status) |
269 | return PCIBIOS_DEVICE_NOT_FOUND; |
270 | |
271 | if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) && |
272 | count == 4) |
273 | *value = dw[3]; |
274 | |
275 | return PCIBIOS_SUCCESSFUL; |
276 | } |
277 | } |
278 | |
279 | dev_warn(dev, "Malformed TLP packet\n" ); |
280 | |
281 | return PCIBIOS_DEVICE_NOT_FOUND; |
282 | } |
283 | |
284 | static void tlp_write_packet(struct altera_pcie *pcie, u32 *, |
285 | u32 data, bool align) |
286 | { |
287 | struct tlp_rp_regpair_t tlp_rp_regdata; |
288 | |
289 | tlp_rp_regdata.reg0 = headers[0]; |
290 | tlp_rp_regdata.reg1 = headers[1]; |
291 | tlp_rp_regdata.ctrl = RP_TX_SOP; |
292 | tlp_write_tx(pcie, tlp_rp_regdata: &tlp_rp_regdata); |
293 | |
294 | if (align) { |
295 | tlp_rp_regdata.reg0 = headers[2]; |
296 | tlp_rp_regdata.reg1 = 0; |
297 | tlp_rp_regdata.ctrl = 0; |
298 | tlp_write_tx(pcie, tlp_rp_regdata: &tlp_rp_regdata); |
299 | |
300 | tlp_rp_regdata.reg0 = data; |
301 | tlp_rp_regdata.reg1 = 0; |
302 | } else { |
303 | tlp_rp_regdata.reg0 = headers[2]; |
304 | tlp_rp_regdata.reg1 = data; |
305 | } |
306 | |
307 | tlp_rp_regdata.ctrl = RP_TX_EOP; |
308 | tlp_write_tx(pcie, tlp_rp_regdata: &tlp_rp_regdata); |
309 | } |
310 | |
311 | static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *, |
312 | u32 data, bool dummy) |
313 | { |
314 | s10_tlp_write_tx(pcie, reg0: headers[0], RP_TX_SOP); |
315 | s10_tlp_write_tx(pcie, reg0: headers[1], ctrl: 0); |
316 | s10_tlp_write_tx(pcie, reg0: headers[2], ctrl: 0); |
317 | s10_tlp_write_tx(pcie, reg0: data, RP_TX_EOP); |
318 | } |
319 | |
320 | static void (struct altera_pcie *pcie, u8 bus, u32 devfn, |
321 | int where, u8 byte_en, bool read, u32 *) |
322 | { |
323 | u8 cfg; |
324 | u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0; |
325 | u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1; |
326 | u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG; |
327 | |
328 | if (pcie->pcie_data->version == ALTERA_PCIE_V1) |
329 | cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; |
330 | else |
331 | cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; |
332 | |
333 | headers[0] = TLP_CFG_DW0(pcie, cfg); |
334 | headers[1] = TLP_CFG_DW1(pcie, tag, byte_en); |
335 | headers[2] = TLP_CFG_DW2(bus, devfn, where); |
336 | } |
337 | |
338 | static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, |
339 | int where, u8 byte_en, u32 *value) |
340 | { |
341 | u32 [TLP_HDR_SIZE]; |
342 | |
343 | get_tlp_header(pcie, bus, devfn, where, byte_en, read: true, |
344 | headers); |
345 | |
346 | pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false); |
347 | |
348 | return pcie->pcie_data->ops->tlp_read_pkt(pcie, value); |
349 | } |
350 | |
351 | static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, |
352 | int where, u8 byte_en, u32 value) |
353 | { |
354 | u32 [TLP_HDR_SIZE]; |
355 | int ret; |
356 | |
357 | get_tlp_header(pcie, bus, devfn, where, byte_en, read: false, |
358 | headers); |
359 | |
360 | /* check alignment to Qword */ |
361 | if ((where & 0x7) == 0) |
362 | pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, |
363 | value, true); |
364 | else |
365 | pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, |
366 | value, false); |
367 | |
368 | ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL); |
369 | if (ret != PCIBIOS_SUCCESSFUL) |
370 | return ret; |
371 | |
372 | /* |
373 | * Monitor changes to PCI_PRIMARY_BUS register on root port |
374 | * and update local copy of root bus number accordingly. |
375 | */ |
376 | if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) |
377 | pcie->root_bus_nr = (u8)(value); |
378 | |
379 | return PCIBIOS_SUCCESSFUL; |
380 | } |
381 | |
382 | static int s10_rp_read_cfg(struct altera_pcie *pcie, int where, |
383 | int size, u32 *value) |
384 | { |
385 | void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); |
386 | |
387 | switch (size) { |
388 | case 1: |
389 | *value = readb(addr); |
390 | break; |
391 | case 2: |
392 | *value = readw(addr); |
393 | break; |
394 | default: |
395 | *value = readl(addr); |
396 | break; |
397 | } |
398 | |
399 | return PCIBIOS_SUCCESSFUL; |
400 | } |
401 | |
402 | static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno, |
403 | int where, int size, u32 value) |
404 | { |
405 | void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); |
406 | |
407 | switch (size) { |
408 | case 1: |
409 | writeb(val: value, addr); |
410 | break; |
411 | case 2: |
412 | writew(val: value, addr); |
413 | break; |
414 | default: |
415 | writel(val: value, addr); |
416 | break; |
417 | } |
418 | |
419 | /* |
420 | * Monitor changes to PCI_PRIMARY_BUS register on root port |
421 | * and update local copy of root bus number accordingly. |
422 | */ |
423 | if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS) |
424 | pcie->root_bus_nr = value & 0xff; |
425 | |
426 | return PCIBIOS_SUCCESSFUL; |
427 | } |
428 | |
429 | static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno, |
430 | unsigned int devfn, int where, int size, |
431 | u32 *value) |
432 | { |
433 | int ret; |
434 | u32 data; |
435 | u8 byte_en; |
436 | |
437 | if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg) |
438 | return pcie->pcie_data->ops->rp_read_cfg(pcie, where, |
439 | size, value); |
440 | |
441 | switch (size) { |
442 | case 1: |
443 | byte_en = 1 << (where & 3); |
444 | break; |
445 | case 2: |
446 | byte_en = 3 << (where & 3); |
447 | break; |
448 | default: |
449 | byte_en = 0xf; |
450 | break; |
451 | } |
452 | |
453 | ret = tlp_cfg_dword_read(pcie, bus: busno, devfn, |
454 | where: (where & ~DWORD_MASK), byte_en, value: &data); |
455 | if (ret != PCIBIOS_SUCCESSFUL) |
456 | return ret; |
457 | |
458 | switch (size) { |
459 | case 1: |
460 | *value = (data >> (8 * (where & 0x3))) & 0xff; |
461 | break; |
462 | case 2: |
463 | *value = (data >> (8 * (where & 0x2))) & 0xffff; |
464 | break; |
465 | default: |
466 | *value = data; |
467 | break; |
468 | } |
469 | |
470 | return PCIBIOS_SUCCESSFUL; |
471 | } |
472 | |
473 | static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno, |
474 | unsigned int devfn, int where, int size, |
475 | u32 value) |
476 | { |
477 | u32 data32; |
478 | u32 shift = 8 * (where & 3); |
479 | u8 byte_en; |
480 | |
481 | if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg) |
482 | return pcie->pcie_data->ops->rp_write_cfg(pcie, busno, |
483 | where, size, value); |
484 | |
485 | switch (size) { |
486 | case 1: |
487 | data32 = (value & 0xff) << shift; |
488 | byte_en = 1 << (where & 3); |
489 | break; |
490 | case 2: |
491 | data32 = (value & 0xffff) << shift; |
492 | byte_en = 3 << (where & 3); |
493 | break; |
494 | default: |
495 | data32 = value; |
496 | byte_en = 0xf; |
497 | break; |
498 | } |
499 | |
500 | return tlp_cfg_dword_write(pcie, bus: busno, devfn, where: (where & ~DWORD_MASK), |
501 | byte_en, value: data32); |
502 | } |
503 | |
504 | static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, |
505 | int where, int size, u32 *value) |
506 | { |
507 | struct altera_pcie *pcie = bus->sysdata; |
508 | |
509 | if (altera_pcie_hide_rc_bar(bus, devfn, offset: where)) |
510 | return PCIBIOS_BAD_REGISTER_NUMBER; |
511 | |
512 | if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) |
513 | return PCIBIOS_DEVICE_NOT_FOUND; |
514 | |
515 | return _altera_pcie_cfg_read(pcie, busno: bus->number, devfn, where, size, |
516 | value); |
517 | } |
518 | |
519 | static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, |
520 | int where, int size, u32 value) |
521 | { |
522 | struct altera_pcie *pcie = bus->sysdata; |
523 | |
524 | if (altera_pcie_hide_rc_bar(bus, devfn, offset: where)) |
525 | return PCIBIOS_BAD_REGISTER_NUMBER; |
526 | |
527 | if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) |
528 | return PCIBIOS_DEVICE_NOT_FOUND; |
529 | |
530 | return _altera_pcie_cfg_write(pcie, busno: bus->number, devfn, where, size, |
531 | value); |
532 | } |
533 | |
534 | static struct pci_ops altera_pcie_ops = { |
535 | .read = altera_pcie_cfg_read, |
536 | .write = altera_pcie_cfg_write, |
537 | }; |
538 | |
539 | static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno, |
540 | unsigned int devfn, int offset, u16 *value) |
541 | { |
542 | u32 data; |
543 | int ret; |
544 | |
545 | ret = _altera_pcie_cfg_read(pcie, busno, devfn, |
546 | where: pcie->pcie_data->cap_offset + offset, |
547 | size: sizeof(*value), |
548 | value: &data); |
549 | *value = data; |
550 | return ret; |
551 | } |
552 | |
553 | static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno, |
554 | unsigned int devfn, int offset, u16 value) |
555 | { |
556 | return _altera_pcie_cfg_write(pcie, busno, devfn, |
557 | where: pcie->pcie_data->cap_offset + offset, |
558 | size: sizeof(value), |
559 | value); |
560 | } |
561 | |
562 | static void altera_wait_link_retrain(struct altera_pcie *pcie) |
563 | { |
564 | struct device *dev = &pcie->pdev->dev; |
565 | u16 reg16; |
566 | unsigned long start_jiffies; |
567 | |
568 | /* Wait for link training end. */ |
569 | start_jiffies = jiffies; |
570 | for (;;) { |
571 | altera_read_cap_word(pcie, busno: pcie->root_bus_nr, RP_DEVFN, |
572 | PCI_EXP_LNKSTA, value: ®16); |
573 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
574 | break; |
575 | |
576 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) { |
577 | dev_err(dev, "link retrain timeout\n" ); |
578 | break; |
579 | } |
580 | udelay(100); |
581 | } |
582 | |
583 | /* Wait for link is up */ |
584 | start_jiffies = jiffies; |
585 | for (;;) { |
586 | if (pcie->pcie_data->ops->get_link_status(pcie)) |
587 | break; |
588 | |
589 | if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) { |
590 | dev_err(dev, "link up timeout\n" ); |
591 | break; |
592 | } |
593 | udelay(100); |
594 | } |
595 | } |
596 | |
597 | static void altera_pcie_retrain(struct altera_pcie *pcie) |
598 | { |
599 | u16 linkcap, linkstat, linkctl; |
600 | |
601 | if (!pcie->pcie_data->ops->get_link_status(pcie)) |
602 | return; |
603 | |
604 | /* |
605 | * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but |
606 | * current speed is 2.5 GB/s. |
607 | */ |
608 | altera_read_cap_word(pcie, busno: pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP, |
609 | value: &linkcap); |
610 | if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) |
611 | return; |
612 | |
613 | altera_read_cap_word(pcie, busno: pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA, |
614 | value: &linkstat); |
615 | if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { |
616 | altera_read_cap_word(pcie, busno: pcie->root_bus_nr, RP_DEVFN, |
617 | PCI_EXP_LNKCTL, value: &linkctl); |
618 | linkctl |= PCI_EXP_LNKCTL_RL; |
619 | altera_write_cap_word(pcie, busno: pcie->root_bus_nr, RP_DEVFN, |
620 | PCI_EXP_LNKCTL, value: linkctl); |
621 | |
622 | altera_wait_link_retrain(pcie); |
623 | } |
624 | } |
625 | |
626 | static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, |
627 | irq_hw_number_t hwirq) |
628 | { |
629 | irq_set_chip_and_handler(irq, chip: &dummy_irq_chip, handle: handle_simple_irq); |
630 | irq_set_chip_data(irq, data: domain->host_data); |
631 | return 0; |
632 | } |
633 | |
634 | static const struct irq_domain_ops intx_domain_ops = { |
635 | .map = altera_pcie_intx_map, |
636 | .xlate = pci_irqd_intx_xlate, |
637 | }; |
638 | |
639 | static void altera_pcie_isr(struct irq_desc *desc) |
640 | { |
641 | struct irq_chip *chip = irq_desc_get_chip(desc); |
642 | struct altera_pcie *pcie; |
643 | struct device *dev; |
644 | unsigned long status; |
645 | u32 bit; |
646 | int ret; |
647 | |
648 | chained_irq_enter(chip, desc); |
649 | pcie = irq_desc_get_handler_data(desc); |
650 | dev = &pcie->pdev->dev; |
651 | |
652 | while ((status = cra_readl(pcie, P2A_INT_STATUS) |
653 | & P2A_INT_STS_ALL) != 0) { |
654 | for_each_set_bit(bit, &status, PCI_NUM_INTX) { |
655 | /* clear interrupts */ |
656 | cra_writel(pcie, value: 1 << bit, P2A_INT_STATUS); |
657 | |
658 | ret = generic_handle_domain_irq(domain: pcie->irq_domain, hwirq: bit); |
659 | if (ret) |
660 | dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n" , bit); |
661 | } |
662 | } |
663 | |
664 | chained_irq_exit(chip, desc); |
665 | } |
666 | |
667 | static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) |
668 | { |
669 | struct device *dev = &pcie->pdev->dev; |
670 | struct device_node *node = dev->of_node; |
671 | |
672 | /* Setup INTx */ |
673 | pcie->irq_domain = irq_domain_add_linear(of_node: node, PCI_NUM_INTX, |
674 | ops: &intx_domain_ops, host_data: pcie); |
675 | if (!pcie->irq_domain) { |
676 | dev_err(dev, "Failed to get a INTx IRQ domain\n" ); |
677 | return -ENOMEM; |
678 | } |
679 | |
680 | return 0; |
681 | } |
682 | |
683 | static void altera_pcie_irq_teardown(struct altera_pcie *pcie) |
684 | { |
685 | irq_set_chained_handler_and_data(irq: pcie->irq, NULL, NULL); |
686 | irq_domain_remove(host: pcie->irq_domain); |
687 | irq_dispose_mapping(virq: pcie->irq); |
688 | } |
689 | |
690 | static int altera_pcie_parse_dt(struct altera_pcie *pcie) |
691 | { |
692 | struct platform_device *pdev = pcie->pdev; |
693 | |
694 | pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, name: "Cra" ); |
695 | if (IS_ERR(ptr: pcie->cra_base)) |
696 | return PTR_ERR(ptr: pcie->cra_base); |
697 | |
698 | if (pcie->pcie_data->version == ALTERA_PCIE_V2) { |
699 | pcie->hip_base = |
700 | devm_platform_ioremap_resource_byname(pdev, name: "Hip" ); |
701 | if (IS_ERR(ptr: pcie->hip_base)) |
702 | return PTR_ERR(ptr: pcie->hip_base); |
703 | } |
704 | |
705 | /* setup IRQ */ |
706 | pcie->irq = platform_get_irq(pdev, 0); |
707 | if (pcie->irq < 0) |
708 | return pcie->irq; |
709 | |
710 | irq_set_chained_handler_and_data(irq: pcie->irq, handle: altera_pcie_isr, data: pcie); |
711 | return 0; |
712 | } |
713 | |
714 | static void altera_pcie_host_init(struct altera_pcie *pcie) |
715 | { |
716 | altera_pcie_retrain(pcie); |
717 | } |
718 | |
719 | static const struct altera_pcie_ops altera_pcie_ops_1_0 = { |
720 | .tlp_read_pkt = tlp_read_packet, |
721 | .tlp_write_pkt = tlp_write_packet, |
722 | .get_link_status = altera_pcie_link_up, |
723 | }; |
724 | |
725 | static const struct altera_pcie_ops altera_pcie_ops_2_0 = { |
726 | .tlp_read_pkt = s10_tlp_read_packet, |
727 | .tlp_write_pkt = s10_tlp_write_packet, |
728 | .get_link_status = s10_altera_pcie_link_up, |
729 | .rp_read_cfg = s10_rp_read_cfg, |
730 | .rp_write_cfg = s10_rp_write_cfg, |
731 | }; |
732 | |
733 | static const struct altera_pcie_data altera_pcie_1_0_data = { |
734 | .ops = &altera_pcie_ops_1_0, |
735 | .cap_offset = 0x80, |
736 | .version = ALTERA_PCIE_V1, |
737 | .cfgrd0 = TLP_FMTTYPE_CFGRD0, |
738 | .cfgrd1 = TLP_FMTTYPE_CFGRD1, |
739 | .cfgwr0 = TLP_FMTTYPE_CFGWR0, |
740 | .cfgwr1 = TLP_FMTTYPE_CFGWR1, |
741 | }; |
742 | |
743 | static const struct altera_pcie_data altera_pcie_2_0_data = { |
744 | .ops = &altera_pcie_ops_2_0, |
745 | .version = ALTERA_PCIE_V2, |
746 | .cap_offset = 0x70, |
747 | .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0, |
748 | .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1, |
749 | .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0, |
750 | .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1, |
751 | }; |
752 | |
753 | static const struct of_device_id altera_pcie_of_match[] = { |
754 | {.compatible = "altr,pcie-root-port-1.0" , |
755 | .data = &altera_pcie_1_0_data }, |
756 | {.compatible = "altr,pcie-root-port-2.0" , |
757 | .data = &altera_pcie_2_0_data }, |
758 | {}, |
759 | }; |
760 | |
761 | static int altera_pcie_probe(struct platform_device *pdev) |
762 | { |
763 | struct device *dev = &pdev->dev; |
764 | struct altera_pcie *pcie; |
765 | struct pci_host_bridge *bridge; |
766 | int ret; |
767 | const struct altera_pcie_data *data; |
768 | |
769 | bridge = devm_pci_alloc_host_bridge(dev, priv: sizeof(*pcie)); |
770 | if (!bridge) |
771 | return -ENOMEM; |
772 | |
773 | pcie = pci_host_bridge_priv(bridge); |
774 | pcie->pdev = pdev; |
775 | platform_set_drvdata(pdev, data: pcie); |
776 | |
777 | data = of_device_get_match_data(dev: &pdev->dev); |
778 | if (!data) |
779 | return -ENODEV; |
780 | |
781 | pcie->pcie_data = data; |
782 | |
783 | ret = altera_pcie_parse_dt(pcie); |
784 | if (ret) { |
785 | dev_err(dev, "Parsing DT failed\n" ); |
786 | return ret; |
787 | } |
788 | |
789 | ret = altera_pcie_init_irq_domain(pcie); |
790 | if (ret) { |
791 | dev_err(dev, "Failed creating IRQ Domain\n" ); |
792 | return ret; |
793 | } |
794 | |
795 | /* clear all interrupts */ |
796 | cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); |
797 | /* enable all interrupts */ |
798 | cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); |
799 | altera_pcie_host_init(pcie); |
800 | |
801 | bridge->sysdata = pcie; |
802 | bridge->busnr = pcie->root_bus_nr; |
803 | bridge->ops = &altera_pcie_ops; |
804 | |
805 | return pci_host_probe(bridge); |
806 | } |
807 | |
808 | static void altera_pcie_remove(struct platform_device *pdev) |
809 | { |
810 | struct altera_pcie *pcie = platform_get_drvdata(pdev); |
811 | struct pci_host_bridge *bridge = pci_host_bridge_from_priv(priv: pcie); |
812 | |
813 | pci_stop_root_bus(bus: bridge->bus); |
814 | pci_remove_root_bus(bus: bridge->bus); |
815 | altera_pcie_irq_teardown(pcie); |
816 | } |
817 | |
818 | static struct platform_driver altera_pcie_driver = { |
819 | .probe = altera_pcie_probe, |
820 | .remove_new = altera_pcie_remove, |
821 | .driver = { |
822 | .name = "altera-pcie" , |
823 | .of_match_table = altera_pcie_of_match, |
824 | }, |
825 | }; |
826 | |
827 | MODULE_DEVICE_TABLE(of, altera_pcie_of_match); |
828 | module_platform_driver(altera_pcie_driver); |
829 | MODULE_LICENSE("GPL v2" ); |
830 | |